WO2017166398A1 - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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Publication number
WO2017166398A1
WO2017166398A1 PCT/CN2016/082791 CN2016082791W WO2017166398A1 WO 2017166398 A1 WO2017166398 A1 WO 2017166398A1 CN 2016082791 W CN2016082791 W CN 2016082791W WO 2017166398 A1 WO2017166398 A1 WO 2017166398A1
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Prior art keywords
layer
forming
conductor layer
connection portion
pattern
Prior art date
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Ceased
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PCT/CN2016/082791
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English (en)
French (fr)
Inventor
宋博韬
林亮
马涛
王文龙
韩领
魏钰
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US15/531,294 priority Critical patent/US10372000B2/en
Publication of WO2017166398A1 publication Critical patent/WO2017166398A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134336—Matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
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    • G02F1/13685—Top gates
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to an array substrate, a method of fabricating the same, and a display device including the array substrate.
  • the common electrode may be disposed on the side of the color filter substrate or on the side of the array substrate.
  • the step difference of the common hole in the common electrode is substantially the sum of the thicknesses of the gate insulating layer, the etch barrier layer, and the passivation layer, so that the hole of the common hole Deeper and deeper, the difference between the inside of the hole and the outside of the hole is larger.
  • the inventors of the present invention have found that, in addition to increasing the coating manner of the PI liquid or the molten metal, it is possible to alleviate the occurrence of PI liquid or molten metal at the edge of the common hole or the connecting hole after reducing the step of the common hole or the connecting hole. Poor diffusion, which causes problems with screen stains.
  • the present invention provides an array substrate manufacturing method for reducing screen stains by reducing the step difference of the common holes/connection holes.
  • a method of fabricating an array substrate comprising the steps of forming a thin film transistor on a substrate, wherein the step of forming a thin film transistor on the substrate comprises: forming a first conductor on the substrate a layer; an insulator layer formed on the first conductor layer; at least one common hole formed on the insulator layer to be connected to the first conductor layer; and a second conductor layer formed on the insulator layer using a single process At least a portion of the common aperture in the at least one common aperture forms a first connection of the same material as the second conductor layer, the first connection being in electrical contact with the first conductor layer.
  • a first connection portion electrically connected to the first conductor layer is formed in the common hole, whereby the hole depth of the common hole is reduced by the thickness of the first connection portion, At the same time, the electrical communication with the first conductor layer is maintained, so that the step of the common hole can be reduced, and the problem of poor diffusion of the PI liquid or the molten metal at the edge of the common hole can be alleviated, thereby reducing the screen stain. Further, since the first connection portion can be formed in the common hole while forming the second conductor layer, an additional process step is not required, and the manufacturing cost is not increased.
  • the first conductor layer includes a common electrode pattern and a gate pattern of the thin film transistor
  • the second conductor layer includes a source and a drain pattern of the thin film transistor and a lead thereof, that is, the The array substrate is a bottom gate type array substrate.
  • the step of forming the first connecting portion of the same material as the second conductor layer in the at least one common hole while forming the second conductor layer on the insulator layer comprises: forming the metal material Simultaneously with the source and drain patterns of the thin film transistor and their leads, a first connection portion is formed in the at least one common hole using the metal material, the first connection portion being in electrical contact with the common electrode pattern.
  • the first conductor layer includes a source and drain pattern of the thin film transistor
  • the second conductor layer includes a gate pattern of the thin film transistor, that is, the array substrate is a top gate Type structure.
  • the step of forming the first connection portion of the same material as the second conductor layer in at least a portion of the common holes of the at least one common hole includes: Forming a first connection portion in at least a portion of the common holes of the at least one common hole using the metal material to form a gate pattern of the thin film transistor, the first connection portion and the film One of the source and drain patterns of the transistor is in electrical contact.
  • an array substrate having a thin film transistor including And a first conductor layer formed on the substrate; an insulator layer formed on the first conductor layer; at least one common hole formed on the insulator layer, the at least one common hole being connected to the first a conductor layer; and a second conductor layer formed on the insulator layer; wherein the first connection portion is formed in the at least one common hole with the same material while forming the second conductor layer using a single process The first connection portion is in electrical contact with the first conductor layer and has a thickness equal to the thickness of the second conductor layer.
  • a first connection portion electrically connected to the first conductor layer is formed in the common hole, whereby the hole depth of the common hole is reduced by the thickness of the first connection portion, and at the same time The electrical communication with the first conductor layer is maintained, so that the step of the common hole can be reduced, and the problem of poor diffusion of the PI liquid or the molten metal at the edge of the common hole can be alleviated, thereby reducing the screen stain. Furthermore, since the second conductor layer and the first connection portion in the common hole are formed in the same process so that the thicknesses of the two are related, no additional process steps are required and the manufacturing cost is not increased.
  • a display device including the array substrate as described above is provided.
  • FIG. 1(a) is a flow chart of a method of fabricating an array substrate in accordance with an embodiment of the present invention
  • 1(b) is a corresponding highly schematic structural view of an array substrate in the process of fabricating an array substrate according to an embodiment of the invention
  • 2(a)-(b) are a cross-sectional view and a plan view of a corresponding structure 1 of an array substrate in the process of fabricating an array substrate according to an embodiment of the present invention, wherein the array substrate is a bottom gate structure;
  • FIG 3 is a cross-sectional view of a corresponding structure 2 of an array substrate in the process of fabricating an array substrate according to an embodiment of the invention, wherein the array substrate is a bottom gate structure;
  • FIGS. 4(a)-(b) are cross-sectional and top views of a corresponding structure 3 of an array substrate in the process of fabricating an array substrate according to an embodiment of the present invention, wherein the array substrate is a bottom gate structure;
  • 5(a)-(b) are a cross-sectional view and a plan view of a corresponding structure 4 of an array substrate in the process of fabricating an array substrate according to an embodiment of the present invention, wherein in the top view for convenience of illustration The gate insulating layer and the etch barrier layer are not shown, wherein the array substrate is a bottom gate structure;
  • 6(a)-(b) are a cross-sectional view and a plan view of a corresponding structure 5 of an array substrate in the process of fabricating an array substrate according to an embodiment of the present invention, wherein the gate insulating layer and the engraving are not shown in a plan view for convenience of illustration.
  • FIG. 7 is a cross-sectional view of a corresponding structure 6 of an array substrate in the process of fabricating an array substrate according to an embodiment of the invention, wherein the array substrate is a bottom gate structure;
  • FIGS. 8(a)-(b) are a cross-sectional view and a plan view of a corresponding structure 7 of an array substrate in the process of fabricating an array substrate according to an embodiment of the present invention, wherein a gate insulating layer is not shown in a plan view for convenience of illustration.
  • 9(a)-(b) are a cross-sectional view and a plan view of a corresponding structure 8 of an array substrate in the process of fabricating an array substrate according to an embodiment of the present invention, wherein a gate insulating layer is not shown in a plan view for convenience of illustration.
  • FIG. 10 is a partially schematic cross-sectional view showing a top gate type array substrate formed by a method of manufacturing an array substrate according to an embodiment of the present invention.
  • a method of fabricating an array substrate according to an embodiment of the present invention includes forming a thin film transistor on a substrate, wherein the step of forming a thin film transistor on the substrate includes:
  • the first connection portion electrically connected to the first conductor layer is formed in the common hole, whereby the hole depth of the common hole is made by the thickness of the first connection portion It is reduced while maintaining electrical communication with the first conductor layer, so that the step of the common hole can be reduced, and the problem of poor diffusion of PI liquid or molten metal at the edge of the common hole can be alleviated, thereby reducing screen stains. Further, since the first connection portion can be formed in the common hole while forming the second conductor layer, an additional process step is not required, and the manufacturing cost is not increased.
  • the first conductor layer 11 includes a common electrode pattern 102 and a gate pattern 102a of a thin film transistor
  • the second conductor layer 14 includes source and drain patterns 100a and 100b of the thin film transistor and leads thereof
  • the layer 12 includes a gate insulating layer 103 or a gate insulating layer 103 and an etch barrier layer 104.
  • the step of forming the first connection portion 106 of the same material as the second conductor layer 13 in the at least one common hole 105 while forming the second conductor layer 13 on the insulator layer 12 includes: forming a source of the thin film transistor using a metal material, While the drain patterns 100a and 100b and their leads are formed, the first connection portion 106 is formed in the at least one common hole 105 using the metal material, and the first connection portion 106 is in electrical contact with the common electrode pattern 102.
  • the step of forming at least one common hole 105 on the gate insulating layer 103 or the gate insulating layer 103 and the etch barrier layer 104 to connect the first conductor layer 11 includes:
  • a common hole 105 is connected to the common electrode pattern 102.
  • the steps of forming a common aperture are:
  • a gate pattern 102a and a corresponding common electrode pattern 102 are formed on the substrate 101, as shown in FIGS. 2(a) and 2(b), wherein 102b is an ITO (Indium Tin Oxide) common electrode.
  • ITO Indium Tin Oxide
  • the active layer pattern 103a is formed at a portion of the gate insulating layer 103 corresponding to the gate pattern 102a, for example, as shown in FIG. 4(b).
  • At least one common hole 105 is formed at a portion of the etch barrier layer 104 corresponding to the plurality of common electrode patterns 102, and at least one common hole 105 is formed as a through hole to the common electrode pattern 102, as shown in FIG. 5(a) ) and 5(b).
  • S206 The source and drain electrodes 100a and 100b and their leads are formed on the active layer pattern 103a using a metal material as shown in FIG. 6(b).
  • the first connection portion 106 is formed by one process in at least one common electrode hole 105 using the same metal material, for example, As shown in FIG. 6(a), the first connection portion 106 is electrically connected to the common electrode pattern 102.
  • the common hole 105 is formed while forming the thin film transistor array, instead of forming a common hole after forming the passivation layer of the array substrate, in order to reduce The section difference of the public hole provides protection.
  • the etch stop layer 104 is retained, however, this is not essential, and after the formation of the common hole 105, the etch stop layer 104 may be removed to further reduce the step difference of the common electrode hole. Moreover, the various steps described above can be accomplished using any suitable process known in the art, for example, a common hole can be formed on the common electrode using wet etching.
  • the thickness of the source and drain electrodes 100a and 100b and their leads and the first connection portion 106 is the same as the thickness of the first connection portion 106.
  • the method for manufacturing an array substrate may further include the steps of:
  • each common electrode connection wire 108 is formed on the passivation layer 107, and each common electrode connection wire 108 is electrically connected to at least one common electrode pattern 102 as shown in FIG. 9(a).
  • the respective common electrodes in the figure may be electrically connected, and secondary electrical connection is achieved by connecting the respective common electrode extension wires on the passivation layer.
  • at least a portion of the common electrodes are not in electrical communication, and a common electrode hole is formed corresponding to each of at least a portion of the common electrodes, and the wires are connected through the first connection portion of the common electrode holes and the plurality of common electrodes. Electrical communication of the entire common electrode pattern forms a common electrode layer.
  • the above steps may be implemented by any suitable process known in the art.
  • a portion of the passivation layer corresponding to the first connection portion may be etched away using dry etching to expose the first connection portion.
  • the first conductor layer 11 includes source and drain patterns 100a and 100b of thin film transistors and their leads
  • the second conductor layer 13 includes a gate pattern 102a of a thin film transistor
  • the insulator layer 12 includes gate insulation.
  • Layer 103 the first conductor layer 11 includes source and drain patterns 100a and 100b of thin film transistors and their leads
  • the second conductor layer 13 includes a gate pattern 102a of a thin film transistor
  • the insulator layer 12 includes gate insulation.
  • the step of forming the first connecting portion 106 of the same material as the second conductor layer 13 in at least a part of the common holes of the at least one common hole 105 while forming the second conductor layer on the insulator layer 12 comprises: using metal The material forms a gate pattern 102a of the thin film transistor while using at least one metal material
  • a first connection portion 106 is formed in at least a portion of the common hole in the common hole 105, and the first connection portion 106 is in electrical contact with one of the source and drain patterns 100a and 100b of the thin film transistor.
  • the step of fabricating the top gate type array substrate further includes the steps of: forming a second conductor layer 13 on the 12 insulator layer while forming a second conductor in the remaining common holes in the at least one common hole 105
  • Layer 12 is a second connection 106a of the same material.
  • the step of forming the second connection portion 106a of the same material as the second conductor layer 13 in the remaining common holes in the at least one common hole 106 includes: While the metal material forms the gate pattern 102a of the thin film transistor, the second connection portion 106a is formed in the remaining common holes in the at least one common hole 105 using the metal material, and the second connection portion 106a and the source and drain patterns of the thin film transistor Another electrical contact.
  • the step of forming at least one common hole 105 on the insulator layer (gate insulating layer 103) to the first conductor layer (the source and drain patterns 100a and 100b of the thin film transistor) includes: the gate insulating layer 103 At least one common hole 105 is formed at a portion corresponding to the source and drain patterns to be connected to the source and drain patterns 100a and 100b of the thin film transistor.
  • the active layer pattern 103a and the source and drain patterns 100a and 100b are first formed on the substrate 101, and then the gate insulating layer 103 and the etch stop layer 104 are formed on the source and drain patterns 100a and 100b.
  • At least one common hole 105 is formed on the gate insulating layer 103 by etching the barrier layer 104.
  • the first connection portion 106 is formed in at least one common hole 105 while the gate pattern 102a is formed, and the material and thickness of the first connection portion 106 are the same as those of the gate pattern 102a.
  • the method for fabricating the top gate type array substrate further includes the steps of: forming a passivation layer (not shown) on the second conductor layer, the passivation layer covering the first connection portion 106; and the passivation layer 106: a portion corresponding to the first connection portion is etched away to expose the first connection portion 106; and a pixel electrode pattern and/or a data line pattern (not shown) is formed on the passivation layer, respectively passing through the common hole 105 and the common hole 105
  • the first connection portion 106 is electrically connected to the drain pattern 100b and/or the source pattern 100a.
  • a pixel electrode pattern and a data line pattern are formed on the passivation layer, respectively, through the first connection portion 106 and the second connection portion 106a and the drain in the common hole 105 and the common hole 105, respectively.
  • the pole pattern 100b and the source pattern 100a are electrically connected.
  • an embodiment of the present invention further provides an array substrate, including: a first conductor layer 11 formed on the substrate 101; an insulator layer 12 formed on the first conductor layer 11; At least one common hole 105 formed on the insulator layer 12, at least one common hole 105 is connected to the first conductor layer 11; and a second conductor layer 13 formed on the insulator layer 12; wherein the second conductor layer is formed using a single process
  • the first connection portion 106 is formed in at least one common 105 hole with the same material, and the first connection portion 106 is in electrical contact with the first conductor layer 11 and has the same thickness as the thickness of the second conductor layer 13 .
  • the first conductor layer 11 includes the common electrode pattern 102a and the gate pattern 102 of the thin film transistor
  • the second conductor layer 13 includes the source and drain patterns 100a of the thin film transistor and 100b and its leads.
  • the first connection portion is in electrical contact with the common electrode pattern of the first conductor layer.
  • the insulator layer 12 includes a gate insulating layer 103 or a gate insulating layer 103 and an etch barrier layer 104.
  • the array substrate further includes a passivation layer 107 formed on the insulator layer 13 (eg, the gate insulating layer 103 or the gate insulating layer 103 and the etch barrier layer 104), and the first connection of the passivation layer 107 The portion corresponding to the portion 106 is removed to expose the first connecting portion 106.
  • the array substrate further includes at least one common electrode connection wire 108 formed on the passivation layer 107, each common electrode connection wire 108 connecting the first connection portion 106 of the at least one common hole 105.
  • the first conductor layer 11 includes source and drain patterns 100a and 100b of thin film transistors and their leads
  • the second conductor layer 13 includes a gate pattern 102a of a thin film transistor.
  • the insulator layer 12 includes a gate insulating layer 103.
  • the array substrate further includes a passivation layer formed on the second conductor layer 13, and a portion of the passivation layer corresponding to the first connection portion 106 is removed to expose the first connection portion 106.
  • the array substrate further includes a pixel electrode pattern and/or a data line pattern formed on the passivation layer through the first connection portion 106 and the drain pattern 100b of the common hole 105 and the common hole 105, respectively.
  • the array substrate further includes a pixel electrode pattern and a data line pattern formed on the passivation layer, respectively passing through the first connection portion 106 and the second connection portion 106a and the drain in the common hole 105 and the common hole 105, respectively.
  • the pole pattern 100b and the source pattern 100a are electrically connected
  • the first connection portion electrically connected to the common electrode pattern is formed in the common hole, whereby the hole depth of the common hole is reduced by the thickness of the first connection portion, At the same time, the electrical connection with the common electrode pattern is maintained, so that the step difference of the common hole can be reduced, and the problem of poor diffusion of PI liquid or molten metal at the edge of the common hole can be alleviated. Thereby reducing screen stains.
  • the first connection portion can be formed in the common hole while forming the source and drain electrodes of the thin film transistor and the lead thereof, that is, the electrical connection portion in the source, the drain, and the common hole of the thin film transistor is formed by one process,
  • the first connection portion is electrically connected to the common electrode pattern and has the same thickness as the source and drain of the thin film transistor, and therefore, no additional process steps are required, and manufacturing cost and manufacturing time are not increased.
  • an embodiment of the present invention also provides a display device including the array substrate according to any of the above embodiments.
  • the display device may be a liquid crystal display device or an OLED display device.
  • the liquid crystal display device may be a product or a component having a display function, such as a liquid crystal display, a liquid crystal television, a mobile phone, a tablet computer, etc., which is not limited in this embodiment of the present invention. .

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Abstract

一种制造阵列基板的方法，包括在基板（101）上形成薄膜晶体管：在所述基板（101）上形成第一导体层（11）；在所述第一导体层（11）上形成绝缘体层（12）；在所述绝缘体层（12）上形成至少一个公共孔（105）连接至所述第一导体层（11）；在所述绝缘体层（12）上形成第二导体层（13）的同时，在所述至少一个公共孔（105）中的至少一部分公共孔中形成与所述第二导体层（13）相同材料的第一连接部（106），所述第一连接部（106）与所述第一导体层（11）电接触。一种通过上述制造方法制造的阵列基板以及包括该阵列基板的显示装置。

Description

阵列基板及其制造方法、显示装置
相关申请的交叉引用
本申请要求于2016年3月31日提交的、名称为“阵列基板及其制造方法、显示装置”的中国专利申请No.201610200608.8的优先权，该专利申请的公开内容通过引用方式整体并入本文。
技术领域
本发明涉及液晶显示技术领域，尤其涉及一种阵列基板及其制造方法和包括所述阵列基板的显示装置。
背景技术
在液晶显示技术中，公共电极可以设置在彩膜基板侧，也可以设置在阵列基板侧。在公共电极设置在阵列基板侧的情形中(底栅结构)，公共电极中的公共孔的段差基本上是栅绝缘层、刻蚀阻挡层和钝化层的厚度之和，使得公共孔的孔深较深，孔内与孔外的段差较大。结果，在后续的单元(Cell)装配过程中，在使用PI液形成导向膜的时候，会在公共电极孔的边缘处发生PI液扩散不良(诸如，不均匀)等问题，从而产生屏幕污渍(panel stain)。
同样的问题存在于顶栅结构的阵列基板上，在栅绝缘层上形成连接孔而电连接薄膜晶体管的源/漏电极和像素电极图案/数据线图案时，在连接孔周围也会发生金属液扩散不良(诸如，不均匀)等问题，从而产生屏幕污染。
发明内容
本发明的发明人发现，除了提高PI液或金属液的涂覆方式之外，在降低了公共孔或连接孔的段差之后，也能够缓解公共孔或连接孔的边缘处发生PI液或金属液扩散不良、从而导致屏幕污渍的问题。由此，本发明提供一种通过降低公共孔/连接孔的段差来减少屏幕污渍的阵列基板制造方法。
具体地，根据本发明的一方面，提供一种制造阵列基板的方法，包括步骤在基板上形成薄膜晶体管，其中所述在基板上形成薄膜晶体管的步骤包括：在所述基板上形成第一导体层；在所述第一导体层上形成绝缘体层；在所述绝缘体层上形成至少一个公共孔连接至所述第一导体层；使用一次工艺在所述绝缘体层上形成第二导体层的同时，在所述至少一个公共孔中的至少一部分公共孔形成与所述第二导体层相同材料的第一连接部，所述第一连接部与所述第一导体层电接触。
通过本发明提供的阵列基板制造方法，在公共孔中形成与第一导体层电连接的第一连接部，由此，藉由第一连接部的厚度，使得公共孔的孔深被减小、同时保持与第一导体层的电连通，从而能够减小公共孔的段差，缓解公共孔的边缘处发生PI液或金属液扩散不良的问题，进而减少屏幕污渍。此外，由于能够在形成第二导体层的同时在公共孔中形成第一连接部，因此不需要额外的工艺步骤，不会增加制造成本。
在一实施例中，所述第一导体层包括公共电极图案和所述薄膜晶体管的栅极图案，所述第二导体层包括所述薄膜晶体管的源、漏极图案及其引线，即，该阵列基板为底栅型阵列基板。其中，在所述绝缘体层上形成第二导体层的同时，在所述至少一个公共孔中形成与所述第二导体层相同材料的第一连接部的步骤包括：在使用金属材料形成所述薄膜晶体管的源、漏极图案及其引线的同时，使用所述金属材料在所述至少一个公共孔中形成第一连接部，所述第一连接部与所述公共电极图案电接触。
在另一实施例中，所述第一导体层包括所述薄膜晶体管的源、漏极图案，所述第二导体层包括所述薄膜晶体管的栅极图案，即，所述阵列基板是顶栅型结构。其中，在所述绝缘体层上形成第二导体层的同时，在所述至少一个公共孔中的至少一部分公共孔中形成与所述第二导体层相同材料的第一连接部的步骤包括：在使用金属材料形成所述薄膜晶体管的栅极图案的同时，使用所述金属材料在所述至少一个公共孔中的至少一部分公共孔中形成第一连接部，所述第一连接部与所述薄膜晶体管的源、漏极图案的其中之一电接触。
根据本发明的另一方面，提供一种具有薄膜晶体管的阵列基板，包 括：形成在基板上的第一导体层；形成在所述第一导体层上的绝缘体层；形成在所述绝缘体层上的至少一个公共孔，所述至少一个公共孔连接至所述第一导体层；和形成在所述绝缘体层上的第二导体层；其中使用一次工艺在形成所述第二导体层的同时，以相同材料在所述至少一个公共孔中形成第一连接部，所述第一连接部与所述第一导体层电接触且其厚度与所述第二导体层的厚度相同。
通过本发明提供的阵列基板，在公共孔中形成有与第一导体层电连接的第一连接部，由此，藉由第一连接部的厚度，使得公共孔的孔深被减小、同时保持与第一导体层的电连通，从而能够减小公共孔的段差，缓解公共孔的边缘处发生PI液或金属液扩散不良的问题，进而减少屏幕污渍。此外，由于第二导体层和公共孔中的第一连接部在同一工艺中形成，使得两者的厚度相关，因此不需要额外的工艺步骤，不会增加制造成本。
根据本发明的还一方面，提供一种显示装置，包括如上所述的阵列基板。
附图说明
下面将参照随附的示意性附图，仅以举例的方式，描述本发明的实施例，其中相同的附图标记表示结构相同或类似的结构或不见，其中：
图1(a)为根据本发明实施例的制造阵列基板的方法的流程图；
图1(b)为根据本发明实施例的制造阵列基板过程中的阵列基板的对应的高度示意性结构示图；
图2(a)-(b)是根据本发明实施例的制造阵列基板过程中的阵列基板的对应的结构一的剖视图和俯视图，其中阵列基板为底栅结构；
图3是根据本发明实施例的制造阵列基板过程中的阵列基板的对应的结构二的剖视图，其中阵列基板为底栅结构；
图4(a)-(b)是根据本发明实施例的制造阵列基板过程中的阵列基板的对应的结构三的剖视图和俯视图，其中阵列基板为底栅结构；
图5(a)-(b)是根据本发明实施例的制造阵列基板过程中的阵列基板的对应的结构四的剖视图和俯视图，其中为了方便图示，俯视图中 未示出栅绝缘层和刻蚀阻挡层，其中阵列基板为底栅结构；
图6(a)-(b)是根据本发明实施例的制造阵列基板过程中的阵列基板的对应的结构五的剖视图和俯视图，其中为了方便图示，俯视图中未示出栅绝缘层和刻蚀阻挡层，其中阵列基板为底栅结构；
图7是根据本发明实施例的制造阵列基板过程中的阵列基板的对应的结构六的剖视图，其中阵列基板为底栅结构；
图8(a)-(b)是根据本发明实施例的制造阵列基板过程中的阵列基板的对应的结构七的剖视图和俯视图，其中为了方便图示，俯视图中未示出栅绝缘层、刻蚀阻挡层和钝化层，其中阵列基板为底栅结构；
图9(a)-(b)是根据本发明实施例的制造阵列基板过程中的阵列基板的对应的结构八的剖视图和俯视图，其中为了方便图示，俯视图中未示出栅绝缘层、刻蚀阻挡层和钝化层，其中阵列基板为底栅结构；和
图10是通过本发明实施例的制造阵列基板的方法所形成的顶栅型阵列基板的局部示意结构剖视图。
具体实施方式
下面将参考附图详细描述各个实施例的其他特征和优点以及各个实施例的结构和操作。应该指出的是，本发明不限于本文中所描述的具体实施例。这些实施例呈现在本文中仅仅是为了图示的目的。基于本文中所包含的教导，附加的实施例对于本领域技术人员来说将是明显的。
应该指出的是，在说明书中提到的“一个实施例”、“实施例”、“示例实施例”等表明，所描述的实施例可以包括特定的特征、结构或特性，但是每个实施例不必包括特定的特征、结构或特性。而且，这些措辞不必表示同一实施例。此外，当结合实施例描述特定特征、结构或特性时，应该理解，结合不管是否被明确示出的其他实施例来实现这样的特征、结构或特性，是在本领域技术人员的知识范围内的。
如图1(a)和(b)所示，根据本发明实施例的制造阵列基板的方法包括在基板上形成薄膜晶体管，其中在基板上形成薄膜晶体管的步骤包括：
S10：在基板101上形成第一导体层11；
S20：在第一导体层11上形成绝缘体层12；
S30：在绝缘体层12上形成至少一个公共孔105连接至第一导体层11；
S40：在绝缘体层12上形成第二导体层13的同时，在至少一个公共孔105中的至少一部分公共孔中形成与第二导体层13相同材料的第一连接部106，第一连接部106与第一导体层11电接触。
通过本发明上述实施例提供的阵列基板的制造方法，在公共孔中形成与第一导体层电连接的第一连接部，由此，藉由第一连接部的厚度，使得公共孔的孔深被减小、同时保持与第一导体层的电连通，从而能够减小公共孔的段差，缓解公共孔的边缘处发生PI液或金属液扩散不良的问题，进而减少屏幕污渍。此外，由于能够在形成第二导体层的同时在公共孔中形成第一连接部，因此不需要额外的工艺步骤，不会增加制造成本。
示例1
下面将参考附图2(a)-9(b)，基于底栅型阵列基板结构，描述根据本发明实施例的制造阵列基板的具体方法。
在底栅型阵列基板结构中，第一导体层11包括公共电极图案102和薄膜晶体管的栅极图案102a，第二导体层14包括薄膜晶体管的源、漏极图案100a和100b及其引线，绝缘体层12包括栅绝缘层103或者栅绝缘层103和刻蚀阻挡层104。在绝缘体层12上形成第二导体层13的同时，在至少一个公共孔105中形成与第二导体层13相同材料的第一连接部106的步骤包括：在使用金属材料形成薄膜晶体管的源、漏极图案100a和100b及其引线的同时，使用所述金属材料在至少一个公共孔105中形成第一连接部106，第一连接部106与公共电极图案102电接触。
在一个实施例中，在栅绝缘层103或栅绝缘层103和刻蚀阻挡层104上形成至少一个公共孔105连接第一导体层11的步骤包括：
在栅绝缘层103上与栅极图案102a相对应的部位处形成有源层图案103a；
在所形成的基板上形成刻蚀阻挡层104；
在刻蚀阻挡层104的与公共电极图案102相对应的部位处形成至少 一个公共孔105连接至公共电极图案102。
在一具体实施例中，例如参考图2(a)-5(b)，形成公共孔的步骤为：
S201：在基板101上形成栅极图案102a和对应的公共电极图案102，如图2(a)和2(b)所示，其中102b是ITO(铟锡氧化物)共电极。
S202：在形成有栅极图案102a和对应的公共电极图案102的基板101上形成栅绝缘层103，如图3所示。
S203：在栅绝缘层103上与栅极图案102a相对应的部位处形成有源层图案103a，例如如图4(b)所示。
S204：在所形成的基板上形成刻蚀阻挡层104，如图4(a)所示；
S205：在刻蚀阻挡层104的与多个公共电极图案102相对应的部位处形成至少一个公共孔105，至少一个公共孔105形成为通至公共电极图案102的通孔，如图5(a)和5(b)所示。
S206：使用金属材料在有源层图案103a上形成源、漏电极100a和100b及其引线，如图6(b)所示。
期间，在使用金属材料形成有源层图案103a的源、漏电极100a和100b及其引线的同时，使用相同的金属材料在至少一个公共电极孔105中通过一次工艺形成第一连接部106，例如如图6(a)所示，第一连接部106与公共电极图案102电连接。
与现有技术相比，在上述实施例中，在制造阵列基板的过程中，形成薄膜晶体管阵列的同时形成公共孔105，而不是在形成阵列基板的钝化层之后再形成公共孔，为降低公共孔的段差提供保障。
应该指出的是，在上述实施例中，刻蚀阻挡层104被保留，然而这不是必须的，也可以在形成公共孔105之后，去除刻蚀阻挡层104，以便进一步减小公共电极孔的段差。此外，可以采用现有技术中已知的任何合适的工艺实现上述的各步骤，例如可以使用湿法蚀刻在公共电极上形成公共孔。
在一实施例中，由于使用一次工艺形成源、漏电极100a和100b及其引线和第一连接部106，因此源、漏电极的厚度与第一连接部106的厚度相同。
在一实施例中，参考图7-9(b)，制造阵列基板的方法还可以包括步骤：
S50：在公共孔105中形成有第一连接部106的基板101上形成钝化层107，钝化层107覆盖第一连接部106，如图7所示；
S60：将钝化层107的与第一连接部106对应的部位蚀刻去除，露出第一连接部106，并且在钝化层107上与各个漏电极100b对应的部位处刻蚀形成通孔107a，通至漏电极100b，如图8(a)和8(b)所示；
S70：通过通孔107a在钝化层107上形成与漏电极100b电连接的像素电极109，例如如图9(b)所示；和
S80：在钝化层107上形成至少一个公共电极连接导线108，每个公共电极连接导线108电连接至少一个公共电极图案102，如图9(a)所示。
应该指出的是，虽然未示出，然而，图中各个公共电极可以是电连接的，并且通过在钝化层上延伸的各个公共电极连接导线实现二次电连接。可选地，公共电极中的至少一部分不是电连通的，对应该至少一部分公共电极中的每一个形成公共电极孔，并通过公共电极孔中的第一连接部分以及多条公共电极连接导线，实现整个公共电极图案的电连通，从而形成公共电极层。
此外，可以采用现有技术中已知的任何合适的工艺实现上述的各步骤，例如可以使用干法蚀刻将钝化层的与第一连接部对应的部位蚀刻去除，露出第一连接部。
示例2
下面将参考附图10，基于顶栅型阵列基板结构，描述根据本发明实施例的制造阵列基板的具体方法。
在顶栅型阵列基板结构中，第一导体层11包括薄膜晶体管的源、漏极图案100a和100b及其引线，第二导体层13包括薄膜晶体管的栅极图案102a，绝缘体层12包括栅绝缘层103。其中，在绝缘体层12上形成第二导体层的同时，在至少一个公共孔105中的至少一部分公共孔中形成与第二导体层13相同材料的第一连接部106的步骤包括：在使用金属材料形成薄膜晶体管的栅极图案102a的同时，使用金属材料在至少一个 公共孔105中的至少一部分公共孔中形成第一连接部106，第一连接部106与薄膜晶体管的源、漏极图案100a和100b的其中之一电接触。
在还一实施例中，制造顶栅型阵列基板的步骤还包括步骤：在12绝缘体层上形成第二导体层13的同时，在至少一个公共孔105中的其余公共孔中形成与第二导体层12相同材料的第二连接部106a。进一步地，在绝缘体层12上形成第二导体层13的同时，在至少一个公共孔106中的其余公共孔中形成与第二导体层13相同材料的第二连接部106a的步骤包括：在使用金属材料形成薄膜晶体管的栅极图案102a的同时，使用金属材料在至少一个公共孔105中的其余公共孔中形成第二连接部106a，第二连接部106a与薄膜晶体管的源、漏极图案的另一个电接触。
在一实施例中，在绝缘体层(栅绝缘层103)上形成至少一个公共孔105连接至第一导体层(薄膜晶体管的源和漏极图案100a和100b)的步骤包括：在栅绝缘层103上与源、漏极图案相对应的部位处形成至少一个公共孔105连接至薄膜晶体管的源、漏极图案100a和100b。
在一个具体实施例中，首先在基板101上形成有源层图案103a和源、漏极图案100a和100b，之后在源、漏极图案100a和100b上形成栅绝缘层103和刻蚀阻挡层104，通过刻蚀阻挡层104在栅绝缘层103上形成至少一个公共孔105。去除刻蚀阻挡层104之后，在形成栅极图案102a的同时，在至少一个公共孔105中形成第一连接部106，第一连接部106的材料和厚度与栅极图案102a的相同。
在一实施例中，顶栅型阵列基板的制造方法还包括步骤：在第二导体层上形成钝化层(未示出)，钝化层覆盖第一连接部106；将钝化层的与106第一连接部对应的部位刻蚀去除，露出第一连接部106；和在钝化层上形成像素电极图案和/或数据线图案(未示出)，分别通过公共孔105和公共孔105中的第一连接部106与漏极图案100b和/或源极图案100a电连接。在一优选实施例中，在钝化层上形成像素电极图案和数据线图案(未示出)，分别通过公共孔105和公共孔105中的第一连接部106和第二连接部106a与漏极图案100b和源极图案100a电连接。
根据另一方面，本发明的实施例还提供一种阵列基板，包括：形成在基板101上的第一导体层11；形成在第一导体层11上的绝缘体层12； 形成在绝缘体层12上的至少一个公共孔105，至少一个公共孔105连接至第一导体层11；和形成在绝缘体层12上的第二导体层13；其中使用一次工艺在形成第二导体层13的同时，以相同材料在至少一个公共105孔中形成第一连接部106，第一连接部106与第一导体层11电接触且其厚度与第二导体层13的厚度相同。
在一实施例中，例如在底栅型阵列基板中，第一导体层11包括公共电极图案102a和薄膜晶体管的栅极图案102，第二导体层13包括薄膜晶体管的源、漏极图案100a和100b及其引线。第一连接部与所述第一导体层的所述公共电极图案电接触。绝缘体层12包括栅绝缘层103或者栅绝缘层103和刻蚀阻挡层104。在还一实施例中，阵列基板还包括形成在绝缘体层13(例如栅绝缘层103或者栅绝缘层103和刻蚀阻挡层104)上的钝化层107，钝化层107的与第一连接部106对应的部位被去除，露出第一连接部106。在另一实施例中，阵列基板还包括形成在钝化层107上的至少一个公共电极连接导线108，每个公共电极连接导线电108连接至少一个公共孔105中的第一连接部106。
在一实施例中，例如在顶栅型阵列基板上，第一导体层11包括薄膜晶体管的源、漏极图案100a和100b及其引线，第二导体层13包括薄膜晶体管的栅极图案102a。绝缘体层12包括栅绝缘层103。在还一实施例中，阵列基板还包括形成在第二导体层13上的钝化层，钝化层的与第一连接部106对应的部位被去除，露出第一连接部106。在另一实施例中，阵列基板还包括形成在钝化层上的像素电极图案和/或数据线图案，分别通过公共孔105和公共孔105中的第一连接部106与漏极图案100b和/或源极图案100a电连接。在一优选实施例中，阵列基板还包括形成在钝化层上的像素电极图案和数据线图案，分别通过公共孔105和公共孔105中的第一连接部106和第二连接部106a与漏极图案100b和源极图案100a电连接
通过本发明上述实施例提供的阵列基板，在公共孔中形成与公共电极图案电连接的第一连接部，由此，藉由第一连接部的厚度，使得公共孔的孔深被减小、同时保持与公共电极图案的电连通，从而能够减小公共孔的段差，缓解公共孔的边缘处发生PI液或金属液扩散不良的问题， 进而减少屏幕污渍。此外，由于能够在形成薄膜晶体管的源、漏电极及其引线的同时在公共孔中形成第一连接部，即，通过一次工艺形成薄膜晶体管的源、漏极和公共孔中的电连接部分，使得第一连接部与公共电极图案电连接且具有与薄膜晶体管的源、漏极的厚度相同的厚度，因此，不需要额外的工艺步骤，不会增加制造成本和制造时间。
根据还一方面，本发明的实施例还提供一种包括根据上述任意实施例的阵列基板的显示装置。该显示装置可以是液晶显示装置，也可以是OLED显示装置，其中液晶显示装置可以是液晶显示器、液晶电视、手机、平板电脑等具有显示功能的产品或者部件，本发明实施例对此不做限定。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种制造阵列基板的方法，包括步骤：在基板上形成薄膜晶体管，其中所述在基板上形成薄膜晶体管的步骤包括：
    在所述基板上形成第一导体层；
    在所述第一导体层上形成绝缘体层；
    在所述绝缘体层上形成至少一个公共孔连接至所述第一导体层；
    使用一次工艺在所述绝缘体层上形成第二导体层的同时，在所述至少一个公共孔中的至少一部分公共孔中形成与所述第二导体层相同材料的第一连接部，所述第一连接部与所述第一导体层电接触。
  2. 根据权利要求1所述的方法，其中，所述第一导体层包括公共电极图案和所述薄膜晶体管的栅极图案，所述第二导体层包括所述薄膜晶体管的源、漏极图案及其引线，
    在所述绝缘体层上形成第二导体层的同时，在所述至少一个公共孔中的至少一部分公共孔中形成与所述第二导体层相同材料的第一连接部的步骤包括：
    在使用金属材料形成所述薄膜晶体管的源、漏极图案及其引线的同时，使用所述金属材料在所述至少一个公共孔中形成第一连接部，所述第一连接部与所述公共电极图案电接触。
  3. 根据权利要求2所述的方法，其中，所述绝缘体层包括栅绝缘层或包括栅绝缘层和刻蚀阻挡层，
    在所述绝缘体层上形成至少一个公共孔连接至所述第一导体层的步骤包括：
    在所述栅绝缘层上与所述栅极图案相对应的部位处形成有源层图案；
    在所形成的基板上形成刻蚀阻挡层；
    在所述刻蚀阻挡层的与所述公共电极图案相对应的部位处形成所述至少一个公共孔连接至所述公共电极图案。
  4. 根据权利要求2或3所述的方法，其中还包括步骤：
    在所述第二导体层上形成钝化层，所述钝化层覆盖所述第一连接部；
    将所述钝化层的与所述第一连接部对应的部位刻蚀去除，露出所述第一连接部；和
    在所述钝化层上形成至少一个公共电极连接导线，每个公共电极连接导线电连接所述至少一个公共孔中的所述第一连接部。
  5. 根据权利要求1所述的方法，其中，所述第一导体层包括所述薄膜晶体管的源、漏极图案及其引线，所述第二导体层包括所述薄膜晶体管的栅极图案，
    在所述绝缘体层上形成第二导体层的同时，在所述至少一个公共孔中的至少一部分公共孔中形成与所述第二导体层相同材料的第一连接部的步骤包括：
    在使用金属材料形成所述薄膜晶体管的栅极图案的同时，使用所述金属材料在所述至少一个公共孔中的至少一部分公共孔中形成第一连接部，所述第一连接部与所述薄膜晶体管的源、漏极图案的其中之一电接触。
  6. 根据权利要求5所述的方法，其中还包括步骤：在所述绝缘体层上形成第二导体层的同时，在所述至少一个公共孔中的其余公共孔中形成与所述第二导体层相同材料的第二连接部。
  7. 根据权利要求6所述的方法，其中，在所述绝缘体层上形成第二导体层的同时，在所述至少一个公共孔中的其余公共孔中形成与所述第二导体层相同材料的第二连接部的步骤包括：
    在使用金属材料形成所述薄膜晶体管的栅极图案的同时，使用所述金属材料在所述至少一个公共孔中的其余公共孔中形成第二连接部，所述第二连接部与所述薄膜晶体管的源、漏极图案的另一个电接触。
  8. 根据权利要求5-7中任一项所述的方法，其中，所述绝缘体层包括栅绝缘层，
    在所述绝缘体层上形成至少一个公共孔连接至所述第一导体层的步骤包括：
    在所述栅绝缘层上与所述源、漏极图案相对应的部位处形成所述至少一个公共孔连接至所述薄膜晶体管的源、漏极图案。
  9. 根据权利要求8所述的方法，其中还包括步骤：
    在所述第二导体层上形成钝化层，所述钝化层覆盖所述第一连接部；
    将所述钝化层的与所述第一连接部对应的部位刻蚀去除，露出所述第一连接部；和
    在所述钝化层上形成像素电极图案和/或数据线图案，分别通过所述公共孔和所述公共孔中的第一连接部与所述漏极图案和/或所述源极图案电连接。
  10. 根据权利要求9所述的方法，其中，在所述钝化层上形成像素电极图案和数据线图案，分别通过所述公共孔和所述公共孔中的第一连接部和第二连接部与所述漏极图案和所述源极图案电连接。
  11. 一种具有薄膜晶体管的阵列基板，包括：
    形成在基板上的第一导体层；
    形成在所述第一导体层上的绝缘体层；
    形成在所述绝缘体层上的至少一个公共孔，所述至少一个公共孔连接至所述第一导体层；和
    形成在所述绝缘体层上的第二导体层；
    其中使用一次工艺在形成所述第二导体层的同时，以相同材料在所述至少一个公共孔中形成第一连接部，所述第一连接部与所述第一导体层电接触且其厚度与所述第二导体层的厚度相同。
  12. 根据权利要求11所述的阵列基板，其中所述第一导体层包括公共电极图案和/或所述薄膜晶体管的栅极图案，所述第二导体层包括所述薄膜晶体管的源和/或源极图案，第一连接部与所述第一导体层的所述公共电极图案电接触。
  13. 根据权利要求12所述的阵列基板，其中所述绝缘体层包括栅绝缘层或者栅绝缘层和刻蚀阻挡层。
  14. 根据权利要求13所述的阵列基板，其中还包括形成在所述绝缘体层上的钝化层，所述钝化层的与所述第一连接部对应的部位被去除，露出所述第一连接部。
  15. 根据权利要求14所述的阵列基板，其中还包括形成在所述钝化层上的至少一个公共电极连接导线，每个公共电极连接导线电连接所述至少一个公共孔中的第一连接部。
  16. 根据权利要求11所述的阵列基板，其中，所述第一导体层包括所述薄膜晶体管的源、漏极图案，所述第二导体层包括所述薄膜晶体管的栅极图案。
  17. 根据权利要求16所述的阵列基板，其中，所述绝缘体层包括栅绝缘层。
  18. 根据权利要求17所述的阵列基板，其中还包括形成在第二导体层上的钝化层，所述钝化层的与所述第一连接部对应的部位被去除，露出所述第一连接部。
  19. 根据权利要求18所述的阵列基板，其中还包括形成在所述钝化层上的像素电极图案和/或数据线图案，分别通过所述公共孔和所述公共孔中的第一连接部与所述漏极图案和/或所述源极图案电连接。
  20. 根据权利要求19所述的阵列基板，其中还包括形成在所述钝化层上的像素电极图案和数据线图案，分别通过所述公共孔和所述公共孔中的第一连接部和第二连接部与所述漏极图案和所述源极图案电连接。
  21. 一种显示装置，包括如权利要求11-20任一项所述的阵列基板。
PCT/CN2016/082791 2016-03-31 2016-05-20 阵列基板及其制造方法、显示装置 Ceased WO2017166398A1 (zh)

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