WO2017128647A1 - 触发器及振荡系统 - Google Patents

触发器及振荡系统 Download PDF

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Publication number
WO2017128647A1
WO2017128647A1 PCT/CN2016/090470 CN2016090470W WO2017128647A1 WO 2017128647 A1 WO2017128647 A1 WO 2017128647A1 CN 2016090470 W CN2016090470 W CN 2016090470W WO 2017128647 A1 WO2017128647 A1 WO 2017128647A1
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Prior art keywords
tube
voltage
biasing
crystal oscillator
oscillator
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PCT/CN2016/090470
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English (en)
French (fr)
Inventor
张孟文
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深圳市汇顶科技股份有限公司
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Publication date
Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to KR1020177021969A priority Critical patent/KR101980469B1/ko
Priority to EP16884247.4A priority patent/EP3386105B1/en
Priority to US15/654,795 priority patent/US10014847B2/en
Publication of WO2017128647A1 publication Critical patent/WO2017128647A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/02—Details
    • H03B5/06—Modifications of generator to ensure starting of oscillations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
    • H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
    • H03B5/36—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
    • H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
    • H03B5/36—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
    • H03B5/362—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device the amplifier being a single transistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
    • H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
    • H03B5/36—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
    • H03B5/364—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device the amplifier comprising field effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L3/00—Starting of generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B2200/00—Indexing scheme relating to details of oscillators covered by H03B
    • H03B2200/0002—Types of oscillators
    • H03B2200/0012—Pierce oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B2200/00—Indexing scheme relating to details of oscillators covered by H03B
    • H03B2200/006—Functional aspects of oscillators
    • H03B2200/0066—Amplitude or AM detection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B2201/00—Aspects of oscillators relating to varying the frequency of the oscillations
    • H03B2201/03—Varying beside the frequency also another parameter of the oscillator in dependence on the frequency
    • H03B2201/031—Varying beside the frequency also another parameter of the oscillator in dependence on the frequency the parameter being the amplitude of a signal, e.g. maintaining a constant output amplitude over the frequency range

Definitions

  • the present patent application relates to the field of semiconductor technology, and in particular to a trigger and an oscillation system.
  • Some embodiments of the present invention aim to solve at least one of the technical problems in the related art described above to some extent.
  • an object of some embodiments of the present invention is to provide a flip-flop having the advantages of low power consumption, low interference, adjustable hysteresis characteristics, modified duty cycle, and insensitivity to the process.
  • Another object of some embodiments of the present invention is to provide an oscillating system.
  • an embodiment of the present invention provides a flip-flop, including: a first voltage input terminal; a bias voltage input terminal; a first biasing tube, the first biasing tube including a first end, a second end and a control end, the control end of the first biasing tube being connected to the bias voltage input, the first biasing tube being configured to be a first component of an external device connected to the trigger
  • the scaling is N, the N is greater than 0;
  • the comparison tube includes a first end, a second end, and a control end, and the control end of the comparison tube is connected to the first voltage input end,
  • the comparison tube is configured to scale the second component of the external device connected to the trigger to the N; the first switch tube and the second switch tube, the first switch tube and the second switch tube a first end, a second end, and a control end, respectively, wherein the first a control end of the switch tube is connected to the first voltage input end, a first end of the first switch tube is connected to a second end of the first bias tube,
  • the second end of the shunt tube is connected to the second end of the second switch tube, the first end of the shunt tube is connected to the first end of the comparison tube, and the shunt tube is configured to compare the
  • the amplification ratio of the tube is M, the M is greater than 0; and the voltage output end is respectively connected to the second end of the first switch tube, the control end of the second switch tube, and the second end of the comparison tube Connected.
  • the bias tube and the comparison tube respectively scale the first MOS transistor (bias tube) and the second MOS tube of the oscillator to determine the midpoint voltage of the flip. Then, by setting the ratio of the shunt to the comparison tube, the hysteresis characteristic of the flip-flop and the duty ratio of the oscillator output clock are adjusted, and finally a clock output with a high noise margin and a duty ratio close to 50% is obtained.
  • the power consumption of the flip-flop can be reduced, the interference of the peak current to other modules can be eliminated, and the hysteresis interval can be easily controlled, especially the duty ratio of the current mirror structure crystal oscillator is very good, that is, has low power consumption and low.
  • the trigger according to the above embodiment of the present invention may further have the following additional technical features:
  • the external device is a crystal oscillator
  • the first component is a first MOS transistor of the crystal oscillator
  • the second component is a second MOS transistor of the crystal oscillator.
  • the external device is a bias voltage generating circuit of the crystal oscillator
  • the first biasing component is a current biasing tube of the bias voltage generating circuit
  • the second component is A voltage biasing tube of the bias voltage generating circuit.
  • the biasing tube, the first switching transistor, and the second switching transistor are all n-channel MOS transistors.
  • the comparison tube and the shunt tube are both p-channel MOS tubes.
  • An embodiment of the second invention of the present invention further provides an oscillating system, comprising: an oscillator; and a flip flop, wherein the flip flop is a flip flop according to the above embodiment of the present invention, and the first voltage input of the flip flop The terminal is connected to the voltage input of the oscillator.
  • the biasing tube and the comparing tube of the flip-flop respectively scale the first MOS tube (biasing tube) and the second MOS tube of the oscillator to determine the middle of the flip. Point voltage. Then, by setting the ratio of the shunt to the comparison tube, the hysteresis characteristic of the flip-flop and the duty ratio of the oscillator output clock are adjusted, and finally a clock output with a high noise margin and a duty ratio close to 50% is obtained.
  • the power consumption of the flip-flop can be reduced, the interference of the peak current to other modules can be eliminated, and the hysteresis interval can be easily controlled, especially the duty ratio of the current mirror structure crystal oscillator is very good, that is, has low power consumption and low.
  • oscillating system according to the above embodiment of the present invention may further have the following additional technical features:
  • the first switch when the voltage at the voltage input of the oscillator is a low level signal, the first switch is turned on, the comparator is turned off, and the flip-flop outputs a high level signal, The second switch is turned off; when the voltage of the voltage input terminal of the oscillator rises to the first voltage, the trigger outputs a low level signal, the second switch is turned on, and the shunt tube is Comparing the tube for shunting; when the voltage at the voltage input end of the oscillator rises to a second voltage, the first switching tube is turned off, and the shunt tube shunts the first biasing tube, wherein the The second voltage is greater than the first voltage; when the voltage at the voltage input end of the oscillator is gradually decreased by the second voltage, the first switch tube is turned on, and the shunt tube shunts the comparison tube To reduce the inversion voltage of the comparison tube.
  • a feedback resistor one end of the feedback resistor being coupled to the voltage input of the oscillator and the other end being coupled to the voltage output of the oscillator and the second MOS transistor of the oscillator The drains are connected.
  • the oscillating system is a crystal oscillating system and the oscillator is a crystal oscillator.
  • the crystal oscillator is a two-input crystal oscillator or a single-input crystal oscillator.
  • the single input crystal oscillator includes a bias voltage generating circuit.
  • the bias voltage generating circuit includes a voltage biasing tube and a current biasing tube
  • the voltage biasing tube and the current biasing tube respectively include a control end, a first end, and a second end, wherein a control terminal of the voltage biasing tube is connected to the second end of the current biasing tube, and is connected to a voltage input end of the single-input crystal oscillator through a feedback resistor, the first end of the voltage biasing tube Connected to a drain of the second MOS transistor of the single-input crystal oscillator and a first end of the comparator of the flip-flop, the second end of the voltage biasing tube and the current biasing tube The second end is connected; the control end of the current biasing tube is respectively connected to the control end of the single-input crystal first MOS tube and the control end of the first bias tube of the flip-flop, the current bias a first end of the tube is respectively connected to a source of the first input crystal first MOS tube and a first end of the first bias tube of the trigger
  • the crystal oscillator includes: an amplitude detecting and adjusting circuit, an amplitude detecting and adjusting circuit, and one end of the amplitude detecting circuit is respectively connected to a voltage input end of the crystal oscillator and a crystal oscillator
  • the gates of the two MOS transistors are connected, and the other end of the amplitude detecting and adjusting circuit is connected to the gate of the first MOS transistor of the crystal to detect and adjust the amplitude of the oscillation of the crystal oscillator.
  • the amplitude detecting crystal circuit when the voltage input of the crystal oscillator has no amplitude, the amplitude detecting crystal circuit outputs a constant DC voltage to respectively be the gate of the first MOS transistor of the crystal according to the DC voltage.
  • a control terminal of the first biasing tube of the flip-flop provides a bias voltage; when the amplitude of the voltage input end of the crystal oscillator is gradually increased, the DC voltage output by the amplitude detecting and regulating circuit is also followed Raise.
  • FIG. 1 is a circuit schematic diagram of a flip-flop according to an embodiment of the present invention.
  • FIG. 2 is a circuit schematic diagram of an oscillating system employing a two-pin crystal oscillator in accordance with one embodiment of the present invention
  • FIG. 3 is a circuit schematic diagram of an oscillating system employing a single-pin crystal oscillator in accordance with one embodiment of the present invention
  • FIG. 4 is a circuit schematic diagram of an oscillating system employing a two-pin crystal oscillator with an amplitude detecting circuit, in accordance with one embodiment of the present invention
  • FIG. 5 is a circuit schematic diagram of an oscillating system employing an open loop comparator structure in accordance with one embodiment of the present invention.
  • the flip-flop includes: a first voltage input terminal, a bias voltage input terminal, a first biasing transistor, a comparison transistor, a first switching transistor, a second switching transistor, a shunt tube, and a voltage output terminal.
  • the first biasing tube comprises a first end (such as a source of the MOS tube), a second end (such as a drain of the MOS tube), and a control end (such as a gate of the MOS tube), and the control of the first biasing tube
  • the terminal is connected to the bias voltage input end, and the first biasing tube is configured to scale the first component of the external device connected to the trigger to N, N is greater than 0;
  • the comparing tube includes the first end, the second end, and a control end, the control end of the comparison tube is connected to the first voltage input end, and the comparison tube is configured to scale the second part of the external device connected to the trigger to be N;
  • the first switch tube and the second switch tube respectively comprise a first end, a second end, and a control end, wherein the control end of the first switch tube is connected to the first voltage input end, the first end of the first switch tube is connected to the second end of the first bias tube, and the second The first end of the switch tube is connected to the second end of the
  • the external device is, for example, a crystal oscillator
  • the first component is the first MOS transistor of the crystal oscillator
  • the second component is the second MOS transistor of the crystal oscillator.
  • the first MOS transistor is M 2 in FIG. 1
  • the second MOS transistor is M 1 in FIG.
  • the first tube is arranged offset with respect to a first MOS transistor M 1 shown in FIG 2 (e.g. biased transistor) scaling is N
  • the comparator trigger is configured to tube
  • the scaling of the equivalent resistance between the gate and the drain of the second MOS transistor M 1 with respect to the crystal oscillator shown in FIG. 1 is N.
  • the first component may also be a current biasing tube of the bias voltage generating circuit of the crystal oscillator
  • the second component is, for example, a voltage biasing tube of the bias voltage generating circuit. .
  • the bias tube and the comparison tube respectively scale the first MOS tube and the negative resistance tube to determine the midpoint voltage of the flip. Then, by setting the ratio of the shunt to the comparison tube, the hysteresis characteristic of the flip-flop and the duty ratio of the oscillator output clock are adjusted, and finally a clock output with a high noise margin and a duty ratio close to 50% is obtained.
  • the power consumption of the flip-flop can be reduced, the interference of the peak current to other modules can be eliminated, and the hysteresis interval can be easily controlled, especially the duty ratio of the current mirror structure crystal oscillator is very good, that is, has low power consumption and low.
  • the flip-flop is a Schmitt trigger
  • the Schmitt trigger is connected to a crystal oscillator, that is, the first of the external devices connected to the Schmitt trigger
  • the component is a crystal first MOS transistor M 2 and the second component is a second MOS transistor second MOS transistor M 1 of the crystal oscillator.
  • the Schmitt trigger includes: a first voltage input terminal 1 , a bias voltage input terminal 2 , a first biasing tube M 5 , a comparison tube M 3 , and a first switching tube M 4 ,
  • the bias voltage control terminal and the first input terminal 2 of the biased transistor M 5 is connected to a first biased transistor M 5 is configured to scale crystal Schmitt trigger connected to the first MOS transistor M 2 is N, N is a decimal or an integer greater than zero.
  • M 3 Comparison tube comprising a first end, a second terminal and a control terminal, the control terminal (e.g., gate) coupled to the first voltage input terminal 1,
  • M 3 Comparative pipe is configured to connect to the Schmitt trigger a first MOS transistor of a second crystal oscillator scale MOS transistor M 1 is N, where, N is an integer greater than 0 or a decimal.
  • the crystal first MOS transistor M 2 generates a current through the voltage V B and biases the second MOS transistor M 1 of the crystal oscillator through the feedback resistor R F .
  • the crystal oscillator input terminal voltage V XI and the output terminal voltage V XO have the same DC voltage, which is also the flip voltage of the crystal oscillator.
  • the first biasing tube M 5 and the comparing tube M 3 of the Schmitt trigger respectively scale N times the crystal first MOS tube M 2 and the second MOS tube M 1 respectively , thus applying The flip voltage of the Mitter flip-flop is consistent with the flip voltage of the crystal oscillator and is process-independent, ie, insensitive to the process.
  • the first bias transistor M 5 and the comparison transistor M 3 respectively scale N times the crystal first MOS transistor M 2 and the second MOS transistor M 1 , that is, the power consumption of the Schmitt trigger is reduced by N times.
  • the power consumption of the Schmitt trigger is controllable and can be extremely low.
  • the first switch tube M 4 and the second switch tube M 6 respectively include a first end, a second end and a control end.
  • the control end of the first switch tube M 4 is connected to the first voltage input end 1
  • the first switch tube M 4 The first end is connected to the second end of the first biasing tube M 5
  • the first end of the second switching tube M 6 is connected to the second end of the first biasing tube M 5 .
  • the first biasing tube M 5 , the first switching transistor M 4 , and the second switching transistor M 6 are both n-channel MOS transistors, and the first end is the source of the MOS tube, and the second end is For the drain of the MOS transistor, the control terminal is the gate of the MOS transistor.
  • the shunt tube M 7 includes a first end, a second end and a control end, the control end of the shunt tube, the control end of the shunt tube M 7 is connected to the first voltage input end 1, and the second end of the shunt tube M 7 is The second end of the second switch tube M 6 is connected, the first end of the shunt tube M 7 is connected to the first end of the comparison tube M 3 , and the shunt tube M 7 is configured to have an amplification ratio of the comparison tube M 3 of M, M A decimal or integer greater than zero.
  • the comparison tube M 3 and the shunt tube M 7 are both p-channel MOS transistors, the first end is the source of the MOS tube, and the second end is the drain of the MOS tube, and the control end is It is the gate of the MOS tube.
  • the voltage output terminal V 0 is connected to the second end of the first switch tube M 4 , the control end of the second switch tube M 6 , and the second end of the comparison tube M 3 , respectively.
  • the specific circuit principle of the Schmitt trigger is described below in conjunction with FIG. Referring to FIG. 1, it is assumed that the input terminal voltage V XI of the crystal oscillator is at a low level at the initial moment. At this time, the first switching transistor M 4 is turned on, and the comparison transistor M 3 is not turned on. At this time, the voltage output terminal of the Schmitt trigger is turned on. V 0 is 1, and the second switch M 6 is turned off. Then, the input terminal voltage V XI of the crystal oscillator gradually becomes higher, and the comparison tube M 3 gradually draws current downward.
  • the Schmitt trigger voltage output terminal V 0 is 0, and the second switch tube M 6 is turned on, and the shunt M 7 shunts the current flowing through the comparison tube M 3 . Further, the input terminal voltage V XI of the crystal oscillator continues to rise until the first switching transistor M 4 is turned off, and the current of the first biasing transistor M 5 flows through the shunt tube M 7 .
  • the input terminal voltage V XI of the crystal oscillator is gradually decreased, the first switching transistor M 4 is turned on, and the current of the comparison tube M 3 is shunted by the shunt M 7 , so that the inversion voltage of the comparison tube M 3 is lowered at this time. That is, when V XI falls to the flip voltage of the crystal oscillator, the Schmitt trigger flips, providing a downward hysteresis characteristic. Therefore, by adjusting the ratio of the shunt tube M 7 to the comparison tube M 3 (for example, the shunt tube M 7 is configured to have an amplification ratio of the comparison tube M 3 to M), the hysteresis characteristic can be adjusted.
  • the voltage output terminal V 0 changes from 0 to 1, and the second switch transistor M 6 is turned off, after which the input voltage V XI of the crystal oscillator continues to decrease until the comparison tube M 3 is not turned on. a biased transistor M 5 enters the linear region, so that the Schmitt trigger current consumption becomes zero.
  • Schmitt triggers have constant current consumption for only half a cycle and no spike current is generated, so the power consumption of this structure is extremely low and does not interfere with other circuits.
  • the output load of the Schmitt trigger is relatively small (the M 6 size is very small), the output edge of the Schmitt trigger is steeper, so that the power consumption of the buffer of the next stage is reduced, thereby reducing the overall Power consumption.
  • the second MOS transistor M 1 operates in a large signal state, and if the midpoint voltage of V XI does not change, It will result in the non-linear flow through the second current MOS transistor M 1 becomes large, resulting in decrease in the voltage V X0.
  • the midpoint voltage of V XI is lowered so that the average current of the second MOS transistor M 1 is equal to the bias current supplied from the bias transistor M 2 .
  • the hysteresis characteristic of the Schmitt trigger of the embodiment of the present invention is downward, the hysteresis interval just compensates for the problem that the V XI intermediate voltage drops due to nonlinearity, thereby correcting the oscillator output. Duty cycle.
  • the Schmitt trigger has a bias tube and a comparison tube respectively scaling the first MOS transistor (such as the bias tube) and the second MOS transistor of the oscillator. Determine the midpoint voltage of the flip. Then, by setting the ratio of the shunt to the comparison tube, the hysteresis characteristic of the Schmitt trigger and the duty ratio of the oscillator output clock are adjusted, and finally a clock output with a high noise margin and a duty ratio close to 50% is obtained.
  • the power consumption of the Schmitt trigger can be reduced, the interference of the peak current to other modules can be eliminated, and the hysteresis interval can be easily controlled, especially for the duty ratio of the current mirror crystal oscillator, that is, the low power Low power consumption, low interference, adjustable hysteresis characteristics, corrected duty cycle, and insensitivity to the process.
  • An embodiment of the invention also provides an oscillating system.
  • the crystal oscillation system includes an oscillator and a flip flop.
  • the trigger is, for example, the flip-flop described in the above embodiment of the invention, and the first voltage input terminal 1 of the flip-flop is connected to the voltage input end of the oscillator.
  • the trigger is, for example, a Schmitt trigger described in connection with FIG. 1 in the above embodiment of the present invention.
  • the first switch M 4 is turned on, the comparison transistor M 3 is turned off, the Schmitt trigger outputs a high level signal, and the second The switch M 6 is turned off.
  • the first switch When the oscillator voltage at the input voltage V XI gradually lowered by the second voltage, the first switch is turned on M 4, M 7 Comparative shunt tube pipe to reduce shunt M 3 M 3 - tube voltage is reversed, i.e.
  • V XI falls below the oscillator's flip voltage, the Schmitt trigger flips, providing a downward hysteresis. Therefore, by adjusting the ratio of the shunt tube M 7 to the comparison tube M 3 (for example, the shunt tube M 7 is configured to have an amplification ratio of the comparison tube M 3 to M), the hysteresis characteristic can be adjusted.
  • the voltage output terminal V 0 changes from 0 to 1
  • the second switch transistor M 6 is turned off, after which the input voltage V XI of the oscillator continues to decrease until the comparison tube M 3 is not turned on, first
  • the biasing tube M 5 enters the linear region such that the current consumption of the Schmitt trigger becomes zero.
  • Schmitt triggers have constant current consumption for only half a cycle and no spike current is generated, so the power consumption of this structure is extremely low and does not interfere with other circuits.
  • the output load of the Schmitt trigger is relatively small (the M 6 size is very small)
  • the output edge of the Schmitt trigger is steeper, so that the power consumption of the buffer of the next stage is reduced, thereby reducing the overall Power consumption.
  • the oscillating system of one embodiment of the present invention further includes, for example, a feedback resistor R F .
  • a feedback resistor R F As shown in FIG. 1, one end of the feedback resistor R F is connected to the voltage input terminal of the oscillator, and the other end is connected to the voltage output terminal of the oscillator and the drain of the second MOS transistor M 1 of the oscillator, respectively, when oscillating when the voltage V X0 decreases the voltage output of the filter, the feedback resistor R F midpoint voltage of the voltage controlled oscillator input terminal is lowered so that the oscillator of the second MOS transistor M 1 is equal to the average current biasing of the first MOS transistor M 2 Set the current.
  • the second MOS transistor M 1 when the oscillation of the oscillator is stabilized, since the oscillation amplitude of the input terminal voltage V XI of the oscillator is relatively large, the second MOS transistor M 1 operates in a large signal state, and if the midpoint voltage of the V XI does not change, It will result in the non-linear flow through the second current MOS transistor M 1 becomes large, resulting in decrease in the voltage V X0. However, due to the action of the feedback resistor R F , the midpoint voltage of V XI is lowered so that the average current of the second MOS transistor M 1 is equal to the bias current supplied by the bias transistor M 2 .
  • the hysteresis characteristic of the Schmitt trigger of the embodiment of the present invention is downward, the hysteresis interval just compensates for the problem that the V XI intermediate voltage drops due to nonlinearity, thereby correcting the oscillator output. Duty cycle.
  • the oscillating system described above is, for example, a crystal oscillating system, such as a crystal oscillator.
  • the crystal oscillator is, for example, a dual PIN crystal oscillator (a dual input crystal oscillator, that is, a crystal oscillator having two inputs) or a single PIN crystal oscillator (single input crystal oscillator, that is, one Crystal oscillator at the input).
  • Bias voltage generating circuit includes a voltage biased transistor M 8 and the tube current bias M 9.
  • the voltage biasing tube M 8 and the current biasing tube M 9 respectively include a control end, a first end and a second end, wherein the control end (gate) of the voltage biasing tube M 8 and the current biasing tube M 9 respectively
  • the second end (drain) is connected and connected to the voltage input terminal of the single-pin crystal oscillator through a feedback resistor R F
  • the first end (source) of the voltage biasing tube M 8 is respectively connected to the single PIN crystal oscillator the drain of the second MOS transistor M 1 and the Schmitt trigger comparator transistor M 3 is connected to a first terminal, a bias voltage is connected to the second terminal of transistor M 8 and the bias current of the second end of the tube 9 M
  • current The control terminal of the biasing tube M 9 is respectively connected to the gate of the first PIN crystal first MOS transistor M 2 and the control terminal of the first biasing transistor M 5 of the Schmitt trigger, and the first of the current biasing tube M 9
  • the terminals are respectively connected to the source of the first PIN transistor
  • the biasing tube M 5 of the Schmitt trigger mirrors the current biasing tube M 9 of the Santos crystal oscillator bias voltage generating circuit.
  • the ratio of M 3 to M 8 is N 1
  • the ratio of M 5 to M 9 is N 2 , where N 1 is slightly larger than N 2 . Since the Schmitt trigger is a downward hysteresis characteristic, the midpoint flip voltage of the Schmitt trigger can be increased by setting N 1 slightly larger than N 2 to improve the duty cycle of the oscillator output.
  • FIG. 2 a circuit schematic of an oscillating system employing a dual PIN crystal oscillator, such as a Pierce crystal oscillator, which is an N-type input, is shown. More specifically, as shown in FIG. 4, an oscillation system of a Pierce crystal oscillator having an amplitude detecting and adjusting circuit is shown. Wherein the amplitude adjusting circuit and detecting an end of each gate of the second MOS transistor M and a voltage input terminal double crystal oscillator and two PIN PIN crystal oscillator 1 is connected to an amplitude detecting circuit and the other end with a double regulating crystal PIN The gate of the first MOS transistor M 2 is connected to detect the amplitude of the oscillator after oscillation.
  • the amplitude detecting and regulating circuit when the voltage input end of the crystal oscillator has no amplitude, the amplitude detecting and regulating circuit outputs a constant DC voltage to control the gate of the first MOS transistor and the first biasing tube of the flip-flop according to the DC voltage, respectively.
  • the terminal provides a bias voltage; when the amplitude of the voltage input of the crystal oscillator gradually increases, the DC voltage output from the amplitude detecting and regulating circuit also increases.
  • the amplitude detecting and adjusting circuit and the Pierce crystal oscillator form an amplitude control loop for the purpose of adaptively controlling the amplitude after the oscillation of the oscillator is stabilized.
  • the operation principle of the loop is: when the oscillator input terminal V XI has no amplitude, the amplitude detecting and regulating circuit outputs a constant DC voltage V B to be supplied to the first MOS transistor M 2 and the Schmitt trigger respectively.
  • the gate bias voltage of the first biasing transistor M 5 is then gradually increased as the magnitude of V XI increases and the output voltage V B of the regulating circuit is gradually increased, and then the bias current of the crystal oscillator M 1 is also followed.
  • the bias voltage of the crystal oscillator is reduced due to the amplitude control loop, which indirectly causes the bias voltage (flip voltage) of the M 1 tube to change, and the bias of the Schmitt trigger of the embodiment of the present invention is changed.
  • the current is related to the crystal oscillator, so its duty cycle, hysteresis characteristics, etc. do not change with decreasing power consumption, and have very high robustness.
  • the bias voltage V B provides a gate voltage bias to the current biasing tubes M 2 , M 5 such that the ratios of M 2 and M 5 are 2N: 1 bias current.
  • M 2 is assumed here that the bias current is 2I b, then for the bias current. 5 M A I b / N, then if V IP is greater than the voltage at the positive input terminal of the negative input terminal V IN, the current flowing through it is greater than M 1 I b .
  • the Schmitt input tube M 3 mirrors the current of M 1 and therefore the current flowing through M 3 is greater than B I b /N, that is, greater than the bias current A I b /N of the biasing tube M 5 , the comparator output is high Level (VDD). Similarly, if the positive input voltage V IP is less than the negative input voltage V IN , the comparator outputs a low level (VSS).
  • VDD High Level
  • V IN negative input voltage
  • V IN low level
  • the principle of its hysteresis characteristic is consistent with that described in the example shown in FIG. 2. It should be noted here that in order to prevent the amplifier from flipping, the relationship between A, B and M needs to be satisfied, 2B(M+1)>A.
  • the first biasing tube and the comparing tube of the Schmitt trigger respectively scale the first MOS tube and the second MOS tube to determine the inversion. Point voltage. Then adjust the hysteresis characteristic of the trigger (such as Schmitt trigger) and adjust the duty cycle of the oscillator output clock by setting the ratio of the shunt to the comparison tube, and finally obtain a high noise margin and a duty ratio close to 50%. Clock output.
  • the trigger such as Schmitt trigger
  • the power consumption of the flip-flop can be reduced, the interference of the peak current to other modules can be eliminated, and the hysteresis interval can be easily controlled, especially the duty ratio of the current mirror structure crystal oscillator is very good, that is, has low power consumption and low.
  • Example 1 a trigger, including:
  • the first biasing tube includes a first end, a second end, and a control end, and a control end of the first biasing tube is connected to the bias voltage input end, the first biasing The tube is configured to scale the first component of the external device connected to the trigger to N, the N being greater than 0;
  • the comparison tube includes a first end, a second end, and a control end, the control end of the comparison tube is connected to the first voltage input end, and the comparison tube is configured to be connected to the trigger
  • the second component of the external device has a scaling ratio of the N;
  • first switch tube and a second switch tube respectively include a first end, a second end, and a control end, wherein the control end of the first switch tube and the first end a voltage input end is connected, a first end of the first switch tube is connected to a second end of the first bias tube, a first end of the second switch tube and a second end of the first bias tube Connected to each other;
  • the shunt tube includes a first end, a second end, and a control end, the control end of the shunt tube is connected to the first voltage input end, the second end of the shunt tube and the second switch The second end of the tube is connected, the first end of the shunt tube is connected to the first end of the comparison tube, the shunt tube is configured to enlarge the ratio of the comparison tube to M, the M is greater than 0; as well as
  • the trigger of claim 1 or 2 wherein the external device is a bias voltage generating circuit of a crystal oscillator, and the first component is a current biasing tube of the bias voltage generating circuit, The second component is a voltage biasing tube of the bias voltage generating circuit.
  • Example 5 The flip-flop according to claim 1, wherein the comparison tube and the shunt tube are both p-channel MOS tubes.
  • Example 6 An oscillating system comprising:
  • a flip-flop the flip-flop according to any of claims 1-5, the first voltage input of the flip-flop being connected to a voltage input of the oscillator.
  • Example 7 The oscillating system according to Example 6, wherein,
  • the first switch tube When the voltage of the voltage input end of the oscillator is a low level signal, the first switch tube is turned on, the comparison tube is turned off, the flip-flop outputs a high level signal, and the second switch tube is turned off.
  • the trigger When the voltage of the voltage input terminal of the oscillator rises to a first voltage, the trigger outputs a low level signal, the second switch tube is turned on, and the shunt tube divides the comparison tube;
  • the first switch tube When the voltage of the voltage input terminal of the oscillator rises to a second voltage, the first switch tube is turned off, and the shunt tube shunts the first bias tube, wherein the second voltage is greater than Said first voltage;
  • the first switch tube When the voltage of the voltage input end of the oscillator is gradually decreased by the second voltage, the first switch tube is turned on, and the shunt tube divides the comparison tube to reduce the inversion voltage of the comparison tube.
  • Example 8 The oscillating system according to claim 7, further comprising:
  • a feedback resistor one end of the feedback resistor is connected to the voltage input end of the oscillator, and the other end is connected to the voltage output end of the oscillator and the drain of the second MOS transistor of the oscillator.
  • the bias voltage generating circuit comprises a voltage biasing tube and a current biasing tube, wherein the voltage biasing tube and the current biasing tube respectively comprise a control end, first End and second end, wherein
  • a control end of the voltage biasing tube is connected to the second end of the current biasing tube, and is connected to a voltage input end of the single-input crystal oscillator through a feedback resistor, the first of the voltage biasing tubes a terminal is respectively connected to a drain of the second MOS transistor of the single-input crystal oscillator and a first end of the comparator tube of the flip-flop, the second end of the voltage biasing tube and the current biasing tube Connected to the second end;
  • a control end of the current biasing tube is respectively connected to a gate of the first MOS transistor of the single-input crystal oscillator and a control end of the first biasing tube of the flip-flop, the current biasing tube
  • the first end is respectively connected to the source of the first input transistor first MOS transistor and the first end of the first biasing tube of the flip-flop, and the second end of the current biasing tube is opposite to the voltage
  • the second end of the tube is connected, and is connected to the voltage input end of the single-input crystal oscillator through the feedback resistor, wherein
  • the comparison tube of the flip-flop is configured to scale the voltage bias tube to N 1 , and the N 1 is greater than 0,
  • the trigger is biased transistor configured to scaling the bias current of N 2 tube, wherein the N 2 is greater than 0, the N 1 and N 2 is greater than.
  • An amplitude detecting and adjusting circuit wherein one end of the amplitude detecting and adjusting circuit is respectively connected to a voltage input end of the crystal oscillator and a gate of a second MOS transistor of the crystal oscillator, wherein the amplitude detecting and adjusting circuit The other end is connected to the gate of the first MOS transistor of the crystal to detect and adjust the amplitude of the oscillation of the crystal oscillator.
  • Example 14 The oscillating system according to claim 13, wherein
  • the amplitude detecting and adjusting circuit When the voltage input end of the crystal oscillator has no amplitude, the amplitude detecting and adjusting circuit outputs a constant DC voltage to respectively be the gate of the first MOS transistor of the crystal and the flip-flop according to the DC voltage a control terminal of the first biasing tube provides a bias voltage;
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
  • features defining “first” or “second” may include at least one of the features, either explicitly or implicitly.
  • the meaning of "a plurality” is at least two, such as two, three, etc., unless specifically defined otherwise.
  • the terms “installation”, “connected”, “connected”, “fixed” and the like shall be understood broadly, and may be either a fixed connection or a detachable connection, unless explicitly stated and defined otherwise. , or integrated; can be mechanical or electrical connection; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of two elements or the interaction of two elements, unless otherwise specified Limited.
  • installation can be understood by a person of ordinary skill in the light of the specific circumstances.
  • the first feature "on” or “under” the second feature may be a direct contact of the first and second features, or the first and second features may be indirectly through an intermediate medium, unless otherwise explicitly stated and defined. contact.
  • the first feature "above”, “above” and “above” the second feature may be that the first feature is directly above or above the second feature, or merely that the first feature level is higher than the second feature.
  • the first feature “below”, “below” and “below” the second feature may be that the first feature is directly below or obliquely below the second feature, or merely that the first feature level is less than the second feature.

Abstract

一种触发器及振荡系统，该触发器包括：第一电压输入端（1）；偏置电压输入端（2）；第一偏置管（M5），其被配置为对与触发器相连的外接装置的第一部件的缩放比例为N；比较管（M3），其被配置为与触发器相连的外接装置的第二部件的缩放比例为N；第一开关管（M4）和第二开关管（M6）；分流管（M7），其控制端与第一电压输入端（1）相连，其第二端与第二开关管（M6）的第二端相连，其第一端与比较管（M3）的第一端相连，其被配置为对比较管（M3）的放大比例为M；电压输出端（V0），分别与第一开关管（M4）的第二端、第二开关管（M4）的控制端以及比较管（M3）的第二端相连。所述触发器具有低功耗、低干扰、迟滞特性可调、修正占空比、对工艺不敏感的优点。

Description

触发器及振荡系统 技术领域
本专利申请涉及半导体技术领域，特别涉及一种触发器及振荡系统。
背景技术
传统的施密特触发器在翻转中间态会产生非常大的尖峰电流，这一特性导致触发器的平均功耗变高。而且由于尖峰电流影响，导致LDO(Low Dropout Regulator，低压差线性稳压器)输出发生跳变，从而干扰到其它电路模块。
在晶体振荡器应用中，为了增加振荡器的噪声容限，常见的办法就是在振荡器输出增加施密特触发器。但是由于振荡器的输出一般为近似的非满摆幅的正弦波，因此传统的施密特触发器功耗会非常的大。其次，由于传统的施密特触发器正反馈比较强烈，导致迟滞区间非常大，若振荡器的幅度过小，将无时钟的输出。并且传统的施密特触发器，向上、向下的阈值电压随工艺变化明显，且其翻转的中间点约为二分之一电源电压，从而导致时钟的占空比不易控制。再加上晶体振荡器在振荡稳定后，振荡器输入端的中点电压会下降从而更加恶化输出时钟的占空比。
发明内容
本发明部分实施例旨在至少在一定程度上解决上述相关技术中的技术问题之一。
为此，本发明部分实施例的一个目的在于提出一种触发器，具有低功耗、低干扰、迟滞特性可调、修正占空比、对工艺不敏感的优点。
本发明部分实施例的另一个目的在于提出一种振荡系统。
为了实现上述目的，本发明一个实施例提出了一种触发器，包括：第一电压输入端；偏置电压输入端；第一偏置管，所述第一偏置管包括第一端、第二端和控制端，所述第一偏置管的控制端与所述偏置电压输入端相连，所述第一偏置管被配置为对与所述触发器相连的外接装置的第一部件的缩放比例为N，所述N大于0；比较管，所述比较管包括第一端、第二端和控制端，所述比较管的控制端与所述第一电压输入端相连，所述比较管被配置为对与所述触发器相连的所述外接装置的第二部件的缩放比例为所述N；第一开关管和第二开关管，所述第一开关管和第二开关管分别包括第一端、第二端和控制端，其中，所述第一 开关管的控制端与所述第一电压输入端相连，所述第一开关管的第一端与所述第一偏置管的第二端相连，所述第二开关管的第一端与所述第一偏置管的第二端相连；分流管，所述分流管包括第一端、第二端和控制端，所述分流管的控制端与所述第一电压输入端相连，所述分流管的第二端与所述第二开关管的第二端相连，所述分流管的第一端与所述比较管的第一端相连，所述分流管被配置为对所述比较管的放大比例为M，所述M大于0；以及所述电压输出端分别与所述第一开关管的第二端、所述第二开关管的控制端及所述比较管的第二端相连。
根据本发明一个实施例的触发器，其偏置管、比较管分别对振荡器的第一MOS管(偏置管)、第二MOS管进行等比例的缩放，来确定翻转的中点电压。然后再通过设置分流管与比较管的比例来调节触发器的迟滞特性和调节振荡器输出时钟的占空比，最终获得高噪声容限、占空比接近50％的时钟输出。因此，可以降低触发器的功耗，消除尖峰电流对其它模块的干扰，容易控制迟滞区间，尤其对电流镜结构晶体振荡器的占空比有非常好的修正作用，即具有低功耗、低干扰、迟滞特性可调、修正占空比、对工艺不敏感的优点。
另外，根据本发明上述实施例的触发器还可以具有如下附加的技术特征：
在一些示例中，所述外接装置为晶体振荡器，所述第一部件为所述晶体振荡器的第一MOS管，所述第二部件为所述晶体振荡器的第二MOS管。
在一些示例中，所述外接装置为所述晶体振荡器的偏置电压产生电路，所述第一偏置部件为所述偏置电压产生电路的电流偏置管，所述第二部件为所述偏置电压产生电路的电压偏置管。
在一些示例中，所述偏置管、所述第一开关管和所述第二开关管均为n沟道MOS管。
在一些示例中，所述比较管和所述分流管均为p沟道MOS管。
本发明第二发明的实施例还提出了一种振荡系统，包括：振荡器；和触发器，所述触发器为本发明上述实施例所述的触发器，所述触发器的第一电压输入端与所述振荡器的电压输入端相连。
根据本发明一个实施例的振荡系统，其中触发器的偏置管、比较管分别对振荡器的第一MOS管(偏置管)、第二MOS管进行等比例的缩放，来确定翻转的中点电压。然后再通过设置分流管与比较管的比例来调节触发器的迟滞特性和调节振荡器输出时钟的占空比，最终获得高噪声容限、占空比接近50％的时钟输出。因此，可以降低触发器的功耗，消除尖峰电流对其它模块的干扰，容易控制迟滞区间，尤其对电流镜结构晶体振荡器的占空比有非常好的修正作用，即具有低功耗、低干扰、迟滞特性可调、修正占空比、对工艺不敏感的优点。
另外，根据本发明上述实施例的振荡系统还可以具有如下附加的技术特征：
在一些示例中，当所述振荡器的电压输入端的电压为低电平信号时，所述第一开关管导通，所述比较管关断，所述触发器输出高电平信号，所述第二开关管关断；当所述振荡器的电压输入端的电压上升至第一电压时，所述触发器输出低电平信号，所述第二开关管导通，所述分流管对所述比较管进行分流；当所述振荡器的电压输入端的电压上升至第二电压时，所述第一开关管关断，所述分流管对所述第一偏置管进行分流，其中，所述第二电压大于所述第一电压；当所述振荡器的电压输入端的电压由所述第二电压逐渐降低时，所述第一开关管导通，所述分流管对所述比较管进行分流以降低所述比较管的翻转电压。
在一些示例中，还包括：反馈电阻，所述反馈电阻的一端与所述振荡器的电压输入端相连，另一端分别与所述振荡器的电压输出端和所述振荡器的第二MOS管的的漏极相连。
在一些示例中，所述振荡系统为晶体振荡系统，所述振荡器为晶体振荡器。
在一些示例中，所述晶体振荡器为双输入端晶体振荡器或单输入端晶体振荡器。
在一些示例中，所述单输入端晶体振荡器包括偏置电压产生电路。
在一些示例中，所述偏置电压产生电路包括电压偏置管及电流偏置管，所述电压偏置管及电流偏置管分别包括控制端、第一端和第二端，其中，所述电压偏置管的控制端与所述电流偏置管的第二端相连，并通过反馈电阻与所述单输入端晶体振荡器的电压输入端相连，所述电压偏置管的第一端分别与所述单输入端晶体振荡器的第二MOS管的的漏极及所述触发器的比较管的第一端相连，所述电压偏置管的第二端与所述电流偏置管的第二端相连；所述电流偏置管的控制端分别与所述单输入端晶体第一MOS管的控制端及所述触发器的第一偏置管的控制端相连，所述电流偏置管的第一端分别与所述单输入端晶体第一MOS管的源极及所述触发器的第一偏置管的第一端相连，所述电流偏置管的第二端与所述电压偏置管的第二端相连，并通过所述反馈电阻与所述单输入端晶体振荡器的电压输入端相连，其中，所述触发器的比较管被配置为对所述电压偏置管的缩放比例为N1，所述N1大于0，所述触发器的偏置管被配置为对所述电流偏置管的缩放比例为N2，其中，所述N2大于0，且所述N1大于N2。
在一些示例中，所述晶体振荡器包括：幅度检测及调节电路，幅度检测及调节电路，所述幅度检测电路的一端分别与所述晶体振荡器的电压输入端及所述晶体振荡器的第二MOS管的栅极相连，所述幅度检测及调节电路的另一端与所述晶体第一MOS管的栅极相连，以检测并调整所述晶体振荡器振荡后的幅度。
在一些示例中，当所述晶体振荡器的电压输入端没有振幅时，所述幅度检测晶体电路输出恒定的直流电压，以根据所述直流电压分别为所述晶体第一MOS管的栅极和所述触发器的第一偏置管的控制端提供偏置电压；当所述晶体振荡器的电压输入端的振幅逐渐升高时，所述幅度检测及调节电路输出的所述直流电压也随之升高。
本发明的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本发明的实践了解到。
附图说明
本发明的上述和/或附加的方面和优点从结合下面附图对实施例的描述中将变得明显和容易理解，其中：
图1是根据本发明一个实施例的触发器的电路原理图；
图2是根据本发明一个实施例的采用双引脚晶体振荡器的振荡系统的电路原理图；
图3是根据本发明一个实施例的采用单引脚晶体振荡器的振荡系统的电路原理图；
图4是根据本发明一个实施例的采用带幅度检测电路的双引脚晶体振荡器的振荡系统的电路原理图；以及
图5是根据本发明一个实施例的采用开环比较器结构的振荡系统的电路原理图。
具体实施方式
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
以下结合附图描述根据本发明一个实施例的触发器及振荡系统。
图1是根据本发明一个实施例的触发器的电路原理图。如图1所示，该触发器包括：第一电压输入端、偏置电压输入端、第一偏置管、比较管、第一开关管、第二开关管、分流管和电压输出端。
其中，第一偏置管包括第一端(如MOS管的源极)、第二端(如MOS管的漏极)和控制端(如MOS管的栅极)，第一偏置管的控制端与偏置电压输入端相连，第一偏置管被配置为对与触发器相连的外接装置的第一部件的缩放比例为N，N大于0；比较管包括第一端、第二端和控制端，比较管的控制端与第一电压输入端相连，比较管被配置为对与触发器相连的外接装置的第二部件的缩放比例为N；第一开关管和第二开关管分别包括第一端、第二端和控制端，其中，第一开关管的控制端与第一电压输入端相连，第一开关管的第一端与第一偏置管的第二端相连，第二开关管的第一端与第一偏置管的第二端相连；分流管包括第一端、第二端和控制端，分流管的控制端与第一电压输入端相连，分流管的第二端与第二开关管的第二端相连，分流管的第一端与比较管的第一端相连，分流管被配置为对比较管的放大比例为M，M大于0；电压输出端分别与第一开关管的第二端、第二开关管的控制端及比较管的第二端相连。
其中，在本发明的一个实施例中，外界装置例如为晶体振荡器，第一部件为该晶体振荡器的第一MOS管，第二部件部件为晶体振荡器的第二MOS管。例如图1所示，第一MOS管即为图1中的M2，第二MOS管即为图1中的M1。基于此，结合图1所示，第一偏置管被配置为相对于图1所示的第一MOS管M2(例如偏置管)的缩放比例为N，触发器的比较管被配置为相对于图1中所示的晶体振荡器的第二MOS管M1的栅极与漏极之间的等效电阻的缩放比例为N。进一步地，在本发明的另一个实施例中，第一部件也可以为上述晶体振荡器的偏置电压产生电路的电流偏置管，第二部件例如为偏置电压产生电路的电压偏置管。
根据本发明一个实施例的触发器，其偏置管、比较管分别对第一MOS管、负阻管进行等比例的缩放，来确定翻转的中点电压。然后再通过设置分流管与比较管的比例来调节触发器的迟滞特性和调节振荡器输出时钟的占空比，最终获得高噪声容限、占空比接近50％的时钟输出。因此，可以降低触发器的功耗，消除尖峰电流对其它模块的干扰，容易控制迟滞区间，尤其对电流镜结构晶体振荡器的占空比有非常好的修正作用，即具有低功耗、低干扰、迟滞特性可调、修正占空比、对工艺不敏感的优点。
具体地，在图1所示的示例中，例如，触发器为施密特触发器，该施密特触发器与一个晶体振荡器相连，即与施密特触发器相连的外接装置的第一部件为晶体第一MOS管M2，第二部件为晶体振荡器的第二MOS管第二MOS管M1。其中，结合图1所示，该施密特触发器包括：第一电压输入端1、偏置电压输入端2、第一偏置管M5、比较管M3、第一开关管M4、第二开关管M6、分流管M7及电压输出端V0。
第一偏置管M5的控制端与偏置电压输入端2相连，第一偏置管M5被配置为对与该施密特触发器相连的晶体第一MOS管M2的缩放比例为N，N为大于0的小数或整数。比较管M3包括第一端、第二端和控制端，其控制端(例如栅极)与第一电压输入端1相连，比较管M3被配置为对与该施密特触发器相连的晶体振荡器的第一MOS管第二MOS管M1的缩放比例为N，其中，N为大于0的小数或整数。
具体地说，结合图1，晶体第一MOS管M2通过电压VB产生一个电流并通过反馈电阻RF为晶体振荡器的第二MOS管M1进行偏置。此时晶体振荡器输入端电压VXI和输出端电压VXO的直流电压一致，该电压也即晶体振荡器的翻转电压。
另一方面，在该示例中，施密特触发器的第一偏置管M5和比较管M3分别对晶体第一MOS管M2和第二MOS管M1同比缩放N倍，因此施密特触发器的翻转电压与晶体振荡器的翻转电压是一致的，而且与工艺无关，即对工艺不敏感。同时由于第一偏置管M5和比较管M3分别对晶体第一MOS管M2和第二MOS管M1缩放了N倍，也即施密特触发器的功耗降低了N倍，因而使得施密特触发器的功耗可控，并可做到极低。
第一开关管M4和第二开关管M6分别包括第一端、第二端和控制端，第一开关管M4的控制端与第一电压输入端1相连，第一开关管M4的第一端与第一偏置管M5的第二端相连，第二开关管M6的第一端与第一偏置管M5的第二端相连。在一些示例中，第一偏置管M5、第一开关管M4和第二开关管M6均为n沟道MOS管，则第一端即为MOS管的源极，第二端即为MOS管的漏极，控制端即为MOS管的栅极。
分流管M7包括第一端、第二端和控制端，所述分流管的控制端，分流管M7的控制端与第一电压输入端1相连，分流管M7的第二端与第二开关管M6的第二端相连，分流管M7的第一端与比较管M3的第一端相连，分流管M7被配置为对比较管M3的放大比例为M，M为大于0的小数或整数。其中，在一些示例中，比较管M3和分流管M7均为p沟道MOS管，则第一端即为MOS管的源极，第二端即为MOS管的漏极，控制端即为MOS管的栅极。
电压输出端V0分别与第一开关管M4的第二端、第二开关管M6的控制端以及比较管M3的第二端相连。
为了便于理解，以下结合图1对该施密特触发器的具体电路原理进行描述。结合图1，假设初始时刻晶体振荡器的输入端电压VXI为低电平，此时第一开关管M4导通，比较管M3不开启，此时施密特触发器的电压输出端V0为1，第二开关管M6断开。然后，晶体振荡器的输入端电压VXI逐渐变高，比较管M3逐渐向下抽电流，当达到翻转电压时，施密特触发器电压输出端V0为0，此时第二开关管M6导通，分流器M7分流流经比较管M3的电流。进一步地，晶体振荡器的输入端电压VXI继续升高，直至第一开关管M4断开，第一偏置管M5的电流全部流经分流管M7。
随后，晶体振荡器的输入端电压VXI逐渐降低，第一开关管M4导通，由于分流器M7分流比较管M3的电流，从而使比较管M3此时的翻转电压降低，也即VXI要下降到晶体振荡器的翻转电压下，施密特触发器才发生翻转，从而提供了向下的迟滞特性。因此，通过调整分流管M7与比较管M3的比例(如将分流管M7配置为对比较管M3的放大比例为M)，即可调节迟滞特性。施密特触发器翻转后的电压输出端V0从0变为1，第二开关管M6断开，之后晶体振荡器的输入端电压VXI继续降低，直至比较管M3不开启，第一偏置管M5进入线性区，从而施密特触发器的电流功耗变为0。因此理想地，施密特触发器只有半个周期有恒定电流功耗，并且无尖峰电流产生，因此该结构的功耗极低且不会干扰到其它电路。此外，由于施密特触发器的输出负载比较小(M6尺寸非常小)，因此施密特触发器的输出沿比较陡峭，使得下一级的缓冲器的功耗降低，从而减小了整体的功耗。
此外，当晶体振荡器振荡稳定后，由于晶体振荡器的输入端电压VXI的振荡幅度比较大，因此第二MOS管M1工作在大信号状态下，若VXI的中点电压不变，由于非线性将导致流过第二MOS管M1的电流变大，最终导致VX0的电压降低。但是由于反馈电阻RF的作用，使得VXI的中点 电压下降，以使第二MOS管M1的平均电流等于偏置管M2的提供的偏置电流。需要说明的是，由于本发明实施例的施密特触发器的迟滞特性是向下的，因此该迟滞区间正好补偿了因非线性导致VXI中间电压下降的问题，从而修正了振荡器输出的占空比。
综上，根据本发明一个实施例的施密特触发器，其偏置管、比较管分别对振荡器的第一MOS管(如偏置管)、第二MOS管进行等比例的缩放，来确定翻转的中点电压。然后再通过设置分流管与比较管的比例来调节施密特触发器的迟滞特性和调节振荡器输出时钟的占空比，最终获得高噪声容限、占空比接近50％的时钟输出。因此，可以降低施密特触发器的功耗，消除尖峰电流对其它模块的干扰，容易控制迟滞区间，尤其对电流镜结构晶体振荡器的占空比有非常好的修正作用，即具有低功耗、低干扰、迟滞特性可调、修正占空比、对工艺不敏感的优点。
本发明的一个实施例还提供了一种振荡系统。
具体地，该晶体振荡系统包括振荡器和触发器。其中，该触发器例如为本发明上述实施例中所描述的触发器，该触发器的第一电压输入端1与振荡器的电压输入端相连。
具体地，该触发器例如为本发明上述实施例中结合图1所描述的施密特触发器。参照图1，当振荡器的电压输入端的电压VXI为低电平信号时，第一开关管M4导通，比较管M3关断，施密特触发器输出高电平信号，第二开关管M6关断。
当振荡器的电压输入端的电压VXI上升至第一电压时，即输入端电压VXI逐渐变高，比较管M3逐渐向下抽电流，当达到翻转电压时，施密特触发器输出低电平信号，第二开关管M6导通，分流管M7对比较管M3进行分流。
当振荡器的电压输入端的电压VXI上升至第二电压时，即输入端电压VXI继续升高，第一开关管M4关断，分流管M7对第一偏置管M5进行分流，其中，第二电压大于第一电压。
当振荡器的电压输入端的电压VXI由第二电压逐渐降低时，第一开关管M4导通，分流管M7对比较管M3进行分流以降低比较管M3的翻转电压，也即VXI要下降到振荡器的翻转电压下，施密特触发器才发生翻转，从而提供了向下的迟滞特性。因此，通过调整分流管M7与比较管M3的比例(如将分流管M7配置为对比较管M3的放大比例为M)，即可调节迟滞特性。施密特触发器翻转后的电压输出端V0从0变为1，第二开关管M6断开，之后振荡器的输入端电压VXI继续降低，直至比较管M3不开启，第一偏置管M5进入线性区，从而施密特触发器的电流功耗变为0。因此理想地，施密特触发器只有半个周期有恒定电流功耗，并且无尖峰电流产生，因此该结构的功耗极低且不会干扰到其它电路。此外，由于施密特触发器的输出负载比较小(M6尺寸非常小)，因此施密特触发器的输出沿比较陡峭，使得下一级的缓冲器的功耗降低，从而减小了整体的功耗。
此外，本发明一个实施例的振荡系统例如还包括反馈电阻RF。如图1所示，反馈电阻RF的一端与振荡器的电压输入端相连，另一端分别与振荡器的电压输出端和振荡器的第二MOS管M1的漏极相连，其中，当振荡器的电压输出端的电压VX0降低时，反馈电阻RF控制振荡器的电压输入端的中点电压下降，以使振荡器的第二MOS管M1的平均电流等于第一MOS管M2的偏置电流。具体地说，当振荡器振荡稳定后，由于振荡器的输入端电压VXI的振荡幅度比较大，因此第二MOS管M1工作在大信号状态下，若VXI的中点电压不变，由于非线性将导致流过第二MOS管M1的电流变大，最终导致VX0的电压降低。但是由于反馈电阻RF的作用，使得VXI的中点电压下降，以使第二MOS管M1的平均电流等于偏置管M2的提供的偏置电流。需要说明的是，由于本发明实施例的施密特触发器的迟滞特性是向下的，因此该迟滞区间正好补偿了因非线性导致VXI中间电压下降的问题，从而修正了振荡器输出的占空比。
在本发明的一个实施例中，上述的振荡系统例如为晶体振荡系统，上述的振荡器例如为晶体振荡器。更为具体地，晶体振荡器例如为双PIN晶体振荡器(双输入端晶体振荡器，即具有两个输入端的晶体振荡器)或单PIN晶体振荡器(单输入端晶体振荡器，即具有一个输入端的晶体振荡器)。
以下结合附图，以具体示例对本发明上述实施例的振荡系统进行详细说明。
如图3所示，展示了采用单PIN晶体振荡器的振荡系统的电路原理图，单PIN晶体振荡器例如为具有偏置电压产生电路的Santos晶体振荡器，该Santos晶体振荡器为N型输入。偏置电压产生电路包括电压偏置管M8及电流偏置管M9。电压偏置管M8及电流偏置管M9分别包括控制端、第一端和第二端，其中，电压偏置管M8的控制端(栅极)分别与电流偏置管M9的第二端(漏极)相连，并通过反馈电阻RF与单引脚晶体振荡器的电压输入端相连，电压偏置管M8的第一端(源极)分别与单PIN晶体振荡器的第二MOS管M1的漏极及施密特触发器的比较管M3的第一端相连，电压偏置管M8的第二端与电流偏置管M9的第二端相连；电流偏置管M9的控制端分别与单PIN晶体第一MOS管M2的栅极及施密特触发器的第一偏置管M5的控制端相连，电流偏置管M9的第一端分别与单PIN晶体第一MOS管M2的源极及施密特触发器的第一偏置管M5的第一端相连，电流偏置管M9的第二端分别与电压偏置管M8的第二端相连，并通过反馈电阻RF与单引脚晶体振荡器的电压输入端相连，其中，施密特触发器的比较管M3被配置为对电压偏置管M8的缩放比例为N1，N1大于0，施密特触发器的偏置管M5被配置为对电流偏置管M9的缩放比例为N2，其中，N2大于0，且N1大于N2。
具体地说，如图3所示，比较管M3不再镜像第二MOS管M1，而是镜像第二MOS管M1的电压偏置管M8。而施密特触发器的偏置管M5镜像Santos晶体振荡器偏置电压产生电路的电流偏置管M9。这里需要注意，M3与M8的比值为N1，M5比M9的比值为N2，其中N1略大于N2。由于该施密 特触发器是向下的迟滞特性，通过让N1略大于N2的设置可以提高施密特触发器的中点翻转电压，从而改善振荡器输出的占空比。
如图2所示，展示了采用双PIN晶体振荡器的振荡系统的电路原理图，其中，双PIN晶体振荡器例如为Pierce晶体振荡器，其为N型输入。更为具体地，如图4所示，展示了一种具有幅度检测及调节电路的Pierce晶体振荡器的振荡系统。其中，幅度检测及调节电路的一端分别与双PIN晶体振荡器的电压输入端及双PIN晶体振荡器的第二MOS管M1的栅极相连，幅度及调节检测电路的另一端与双PIN晶体第一MOS管M2的栅极相连，以检测并整振荡器振荡后的幅度。其中，当晶体振荡器的电压输入端没有振幅时，幅度检测及调节电路输出恒定的直流电压，以根据直流电压分别为晶体第一MOS管的栅极和触发器的第一偏置管的控制端提供偏置电压；当晶体振荡器的电压输入端的振幅逐渐升高时，幅度检测及调节电路输出的直流电压也随之升高。
具体地说，如图4所示，幅度检测及调节电路和Pierce晶体振荡器形成幅度控制环路，其目的是为了自适应的控制振荡器振荡稳定后的幅度。该环路的工作原理是：在振荡器输入端VXI没有振幅的时候，幅度检测及调节电路输出一个恒定的直流电压VB以分别提供给晶体第一MOS管M2和施密特触发器的第一偏置管M5的栅极偏置电压，然后随着VXI的幅度增加幅度检测及调节电路输出电压VB逐渐升高，随后晶体振荡器的M1的偏置电流也随之减小，从而降低了第二MOS管M1等效的负阻，由于M1等效负阻的减小使得晶体振荡器输入端VXI的幅度减小，最终整个环路会将VXI维持在一个比较恒定的振荡幅度。
值得注意的是，由于幅度控制环路使得晶体振荡器的偏置电流减小，间接导致M1管的偏置电压(翻转电压)发生改变，本发明实施例的施密特触发器的偏置电流是和晶体振荡器相关的，因此其占空比、迟滞特性等都不会随着功耗的降低而发生变化，有非常高的鲁棒性。
进一步地，如图5所示的示例中，展示了一种采用高噪声容限的差分输入、单端输出的开环比较器结构的振荡系统，该开环比较器为P型输入。该示例中，为方便功能性的描述，此处认为A＝B，则偏置电压VB给电流偏置管M2、M5提供栅压偏置，从而使得M2、M5产生比例为2N:1的偏置电流。这里假设M2的偏置电流为2Ib，那么M5的偏置电流为A Ib/N，此时若正输入端VIP的电压大于负输入端VIN，那么流过M1的电流大于Ib。由于施密特的输入管M3镜像M1的电流因此流过M3的电流大于B Ib/N，也即大于偏置管M5的偏置电流A Ib/N，因此该比较器输出高电平(VDD)。同理，如果正输入端电压VIP小于负输入端电压VIN则比较器输出低电平(VSS)。其迟滞特性的原理同图2所示的示例中所描述的一致。这里需要说明的是，为了防止放大器不翻转，A、B和M的关系需要满足，2B(M+1)>A。
综上，根据本发明一个实施例的振荡系统，其中施密特触发器的第一偏置管、比较管分别对第一MOS管、第二MOS管进行等比例的缩放，来确定翻转的中点电压。然后再通过设置分流管与比较管的比例来调节触发器(如施密特触发器)的迟滞特性和调节振荡器输出时钟的占空比，最终获得高噪声容限、占空比接近50％的时钟输出。因此，可以降低触发器的功耗，消除尖峰电流对其它模块的干扰，容易控制迟滞区间，尤其对电流镜结构晶体振荡器的占空比有非常好的修正作用，即具有低功耗、低干扰、迟滞特性可调、修正占空比、对工艺不敏感的优点。
根据本发明部分实施例，提供了如下例子。
例子1、一种触发器，包括：
第一电压输入端；
偏置电压输入端；
第一偏置管，所述第一偏置管包括第一端、第二端和控制端，所述第一偏置管的控制端与所述偏置电压输入端相连，所述第一偏置管被配置为对与所述触发器相连的外接装置的第一部件的缩放比例为N，所述N大于0；
比较管，所述比较管包括第一端、第二端和控制端，所述比较管的控制端与所述第一电压输入端相连，所述比较管被配置为对与所述触发器相连的所述外接装置的第二部件的缩放比例为所述N；
第一开关管和第二开关管，所述第一开关管和第二开关管分别包括第一端、第二端和控制端，其中，所述第一开关管的控制端与所述第一电压输入端相连，所述第一开关管的第一端与所述第一偏置管的第二端相连，所述第二开关管的第一端与所述第一偏置管的第二端相连；
分流管，所述分流管包括第一端、第二端和控制端，所述分流管的控制端与所述第一电压输入端相连，所述分流管的第二端与所述第二开关管的第二端相连，所述分流管的第一端与所述比较管的第一端相连，所述分流管被配置为对所述比较管的放大比例为M，所述M大于0；以及
电压输出端，所述电压输出端分别与所述第一开关管的第二端、所述第二开关管的控制端及所述比较管的第二端相连。
例子2、根据例子1所述的触发器，其中，所述外接电路为晶体振荡电路，所述第一部件为所述晶体振荡器的第一MOS管，所述第二部件为所述晶体振荡器的第二MOS管。
例子3、根据例子1或2所述的触发器，其中，所述外接装置为晶体振荡器的偏置电压产生电路，所述第一部件为所述偏置电压产生电路的电流偏置管，所述第二部件为所述偏置电压产生电路的电压偏置管。
例子4、根据例子1，2或3所述的触发器，其中，所述第一偏置管、所述第一开关管和所述第二开关管均为n沟道MOS管。
例子5、根据权利要求1所述的触发器，其中，所述比较管和所述分流管均为p沟道MOS管。
例子6、一种振荡系统，包括：
振荡器；和
触发器，所述触发器为根据权利要求1-5任一项所述的触发器，所述触发器的第一电压输入端与所述振荡器的电压输入端相连。
例子7、根据例子6所述的振荡系统，其中，其中，
当所述振荡器的电压输入端的电压为低电平信号时，所述第一开关管导通，所述比较管关断，所述触发器输出高电平信号，所述第二开关管关断；
当所述振荡器的电压输入端的电压上升至第一电压时，所述触发器输出低电平信号，所述第二开关管导通，所述分流管对所述比较管进行分流；
当所述振荡器的电压输入端的电压上升至第二电压时，所述第一开关管关断，所述分流管对所述第一偏置管进行分流，其中，所述第二电压大于所述第一电压；以及
当所述振荡器的电压输入端的电压由所述第二电压逐渐降低时，所述第一开关管导通，所述分流管对所述比较管进行分流以降低所述比较管的翻转电压。
例子8、根据权利要求7所述的振荡系统，其中，还包括：
反馈电阻，所述反馈电阻的一端与所述振荡器的电压输入端相连，另一端分别与所述振荡器的电压输出端和所述振荡器的第二MOS管的漏极相连。
例子9、根据例子6-8任一项所述的振荡系统，其中，所述振荡系统为晶体振荡系统，所述振荡器为晶体振荡器。
例子10、根据例子9所述的振荡系统，其中，所述晶体振荡器为双输入端晶体振荡器或单输入端晶体振荡器。
例子11、根据例子10所述的振荡系统，其中，所述单引脚晶体振荡器包括偏置电压产生电路。
例子12、根据例子11所述的振荡系统，其中，所述偏置电压产生电路包括电压偏置管及电流偏置管，所述电压偏置管及电流偏置管分别包括控制端、第一端和第二端，其中，
所述电压偏置管的控制端与所述电流偏置管的第二端相连，并通过反馈电阻与所述单输入端晶体振荡器的电压输入端相连，所述电压偏置管的第一端分别与所述单输入端晶体振荡器的第二MOS管的漏极及所述触发器的比较管的第一端相连，所述电压偏置管的第二端与所述电流偏置管的第二端相连；
所述电流偏置管的控制端分别与所述单输入端晶体振荡器的第一MOS管的栅极及所述触发器的第一偏置管的控制端相连，所述电流偏置管的第一端分别与所述单输入端晶体第一MOS管的源极及所述触发器的第一偏置管的第一端相连，所述电流偏置管的第二端与所述电压偏置管的第二端相连，并通过所述反馈电阻与所述单输入端晶体振荡器的电压输入端相连，其中，
所述触发器的比较管被配置为对所述电压偏置管的缩放比例为N1，所述N1大于0，
所述触发器的偏置管被配置为对所述电流偏置管的缩放比例为N2，其中，所述N2大于0，且所述N1大于N2。
例子13、根据例子10到12任一项所述的振荡系统，其中，所述晶体振荡器包括：
幅度检测及调节电路，所述幅度检测及调节电路的一端分别与所述晶体振荡器的电压输入端及所述晶体振荡器的第二MOS管的栅极相连，所述幅度检测及调节电路的另一端与所述晶体第一MOS管的栅极相连，以检测并调整所述晶体振荡器振荡后的幅度。
例子14、根据权利要求13所述的振荡系统，其中，
当所述晶体振荡器的电压输入端没有振幅时，所述幅度检测及调节电路输出恒定的直流电压，以根据所述直流电压分别为所述晶体第一MOS管的栅极和所述触发器的第一偏置管的控制端提供偏置电压；
当所述晶体振荡器的电压输入端的振幅逐渐升高时，所述幅度检测及调节电路输出的所述直流电压也随之升高。
在本发明部分实施例的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”、“顺时针”、“逆时针”、“轴向”、“径向”、“周向”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本发明的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。
在本发明中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系，除非另有明确的限定。对于本领域的 普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
在本发明中，除非另有明确的规定和限定，第一特征在第二特征“上”或“下”可以是第一和第二特征直接接触，或第一和第二特征通过中间媒介间接接触。而且，第一特征在第二特征“之上”、“上方”和“上面”可是第一特征在第二特征正上方或斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”可以是第一特征在第二特征正下方或斜下方，或仅仅表示第一特征水平高度小于第二特征。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本发明的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本发明的限制，本领域的普通技术人员在本发明的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (14)

  1. 一种触发器，包括：
    第一电压输入端；
    偏置电压输入端；
    第一偏置管，所述第一偏置管包括第一端、第二端和控制端，所述第一偏置管的控制端与所述偏置电压输入端相连，所述第一偏置管被配置为对与所述触发器相连的外接装置的第一部件的缩放比例为N，所述N大于0；
    比较管，所述比较管包括第一端、第二端和控制端，所述比较管的控制端与所述第一电压输入端相连，所述比较管被配置为对与所述触发器相连的所述外接装置的第二部件的缩放比例为所述N；
    第一开关管和第二开关管，所述第一开关管和第二开关管分别包括第一端、第二端和控制端，其中，所述第一开关管的控制端与所述第一电压输入端相连，所述第一开关管的第一端与所述第一偏置管的第二端相连，所述第二开关管的第一端与所述第一偏置管的第二端相连；
    分流管，所述分流管包括第一端、第二端和控制端，所述分流管的控制端与所述第一电压输入端相连，所述分流管的第二端与所述第二开关管的第二端相连，所述分流管的第一端与所述比较管的第一端相连，所述分流管被配置为对所述比较管的放大比例为M，所述M大于0；以及
    电压输出端，所述电压输出端分别与所述第一开关管的第二端、所述第二开关管的控制端及所述比较管的第二端相连。
  2. 根据权利要求1所述的触发器，其中，所述外接电路为晶体振荡电路，所述第一部件为所述晶体振荡器的第一MOS管，所述第二部件为所述晶体振荡器的第二MOS管。
  3. 根据权利要求1所述的触发器，其中，所述外接装置为晶体振荡器的偏置电压产生电路，所述第一部件为所述偏置电压产生电路的电流偏置管，所述第二部件为所述偏置电压产生电路的电压偏置管。
  4. 根据权利要求1所述的触发器，其中，所述第一偏置管、所述第一开关管和所述第二开关管均为n沟道MOS管。
  5. 根据权利要求1所述的触发器，其中，所述比较管和所述分流管均为p沟道MOS管。
  6. 一种振荡系统，包括：
    振荡器；和
    触发器，所述触发器为根据权利要求1-5任一项所述的触发器，所述触发器的第一电压输入端与所述振荡器的电压输入端相连。
  7. 根据权利要求6所述的振荡系统，其中，
    当所述振荡器的电压输入端的电压为低电平信号时，所述第一开关管导通，所述比较管关断，所述触发器输出高电平信号，所述第二开关管关断；
    当所述振荡器的电压输入端的电压上升至第一电压时，所述触发器输出低电平信号，所述第二开关管导通，所述分流管对所述比较管进行分流；
    当所述振荡器的电压输入端的电压上升至第二电压时，所述第一开关管关断，所述分流管对所述第一偏置管进行分流，其中，所述第二电压大于所述第一电压；以及
    当所述振荡器的电压输入端的电压由所述第二电压逐渐降低时，所述第一开关管导通，所述分流管对所述比较管进行分流以降低所述比较管的翻转电压。
  8. 根据权利要求7所述的振荡系统，其中，还包括：
    反馈电阻，所述反馈电阻的一端与所述振荡器的电压输入端相连，另一端分别与所述振荡器的电压输出端和所述振荡器的第二MOS管的漏极相连。
  9. 根据权利要求6-8任一项所述的振荡系统，其中，所述振荡系统为晶体振荡系统，所述振荡器为晶体振荡器。
  10. 根据权利要求9所述的振荡系统，其中，所述晶体振荡器为双输入端晶体振荡器或单输入端晶体振荡器。
  11. 根据权利要求10所述的振荡系统，其中，所述单引脚晶体振荡器包括偏置电压产生电路。
  12. 根据权利要求11所述的振荡系统，其中，所述偏置电压产生电路包括电压偏置管及电流偏置管，所述电压偏置管及电流偏置管分别包括控制端、第一端和第二端，其中，
    所述电压偏置管的控制端与所述电流偏置管的第二端相连，并通过反馈电阻与所述单输入端晶体振荡器的电压输入端相连，所述电压偏置管的第一端分别与所述单输入端晶体振荡器的第二MOS管的漏极及所述触发器的比较管的第一端相连，所述电压偏置管的第二端与所述电流偏置管的第二端相连；
    所述电流偏置管的控制端分别与所述单输入端晶体振荡器的第一MOS管的栅极及所述触发器的第一偏置管的控制端相连，所述电流偏置管的第一端分别与所述单输入端晶体第一MOS管的源极及所述触发器的第一偏置管的第一端相连，所述电流偏置管的第二端与所述电压偏置管的第二端相连，并通过所述反馈电阻与所述单输入端晶体振荡器的电压输入端相连，其中，
    所述触发器的比较管被配置为对所述电压偏置管的缩放比例为N1，所述N1大于0，
    所述触发器的偏置管被配置为对所述电流偏置管的缩放比例为N2，其中，所述N2大于0，且所述N1大于N2。
  13. 根据权利要求10所述的振荡系统，其中，所述晶体振荡器包括：
    幅度检测及调节电路，所述幅度检测及调节电路的一端分别与所述晶体振荡器的电压输入端及所述晶体振荡器的第二MOS管的栅极相连，所述幅度检测及调节电路的另一端与所述晶体第一MOS管的栅极相连，以检测并调整所述晶体振荡器振荡后的幅度。
  14. 根据权利要求13所述的振荡系统，其中，
    当所述晶体振荡器的电压输入端没有振幅时，所述幅度检测及调节电路输出恒定的直流电压，以根据所述直流电压分别为所述晶体第一MOS管的栅极和所述触发器的第一偏置管的控制端提供偏置电压；
    当所述晶体振荡器的电压输入端的振幅逐渐升高时，所述幅度检测及调节电路输出的所述直流电压也随之升高。
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