WO2017128458A1 - 扫描驱动电路及具有该电路的平面显示装置 - Google Patents

扫描驱动电路及具有该电路的平面显示装置 Download PDF

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Publication number
WO2017128458A1
WO2017128458A1 PCT/CN2016/074226 CN2016074226W WO2017128458A1 WO 2017128458 A1 WO2017128458 A1 WO 2017128458A1 CN 2016074226 W CN2016074226 W CN 2016074226W WO 2017128458 A1 WO2017128458 A1 WO 2017128458A1
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Prior art keywords
controllable switch
control
pull
module
scan
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/074226
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English (en)
French (fr)
Inventor
赵莽
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US15/024,075 priority Critical patent/US9972283B2/en
Publication of WO2017128458A1 publication Critical patent/WO2017128458A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0281—Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/04—Partial updating of the display screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a scan driving circuit and a flat display device having the same.
  • the current flat display device adopts GOA.
  • This abnormal disturbance will be input into the next-stage scan driving circuit by controlling the clock signal, thereby affecting the normal operation of the next-stage scan driving circuit, and finally affecting the normal display of the panel, thereby Affects the stability of the scan drive circuit.
  • the technical problem to be solved by the present invention is to provide a scan driving circuit and a flat display device having the same to ensure the stability of the operation of the scan driving circuit.
  • a technical solution adopted by the present invention is to provide a scan driving circuit, including:
  • a pull-up maintaining module configured to receive the upper-level clock signal, and pull up the pull-down control signal point according to the received upper-level clock signal, and charge the pull-up control signal point;
  • control module connected to the pull-up maintaining module, configured to receive the upper pull-up control signal and the upper-level scan driving signal, and control the pull-up maintaining module according to the received upper pull-up control signal and the upper-level scan driving signal ;
  • An output module connected to the pull-up maintaining module and the control module, for outputting a scan driving signal to the scan line;
  • a scan line for transmitting the scan drive signal to the pixel unit.
  • the scan driving circuit further includes:
  • a forward/reverse scan module for outputting a forward scan drive signal and a reverse scan drive signal to drive the scan drive circuit
  • An input module connected between the forward-reverse scan module and the control module, for receiving a first lower-level clock signal and for the pull-up control signal according to the received first lower-level clock signal Point to charge;
  • a processing module configured to receive the upper pull-up control signal, and control the pull-up maintaining module according to the received upper pull-up control signal.
  • the control module includes a first controllable switch, and an input end of the first controllable switch is connected to the upper-level scan driving signal, and a control end of the first controllable switch is connected to a higher-level pull-up control signal point.
  • the output of the first controllable switch is connected to the pull-up maintaining module.
  • the pull-up maintaining module includes a second controllable switch, a third controllable switch, a fourth controllable switch, a fifth controllable switch, and a first capacitor, and an output end of the second controllable switch is connected to the An output end of the first controllable switch and a control end of the third controllable switch, wherein the control end of the second controllable switch is connected to the control end of the fifth controllable switch and the third controllable switch
  • the output end of the second controllable switch, the third controllable switch and the fifth controllable switch are connected to the open voltage end, and the output end of the fifth controllable switch is connected to a scan line and
  • the output module, one end of the first capacitor is connected to the input end of the fifth controllable switch, and the other end of the first capacitor is connected to the control end of the fifth controllable switch, the fourth controllable
  • the control end of the switch is connected to the upper clock signal, the input end of the fourth controllable switch is connected to the closed voltage end
  • the output module includes a sixth controllable switch and a second capacitor, a control end of the sixth controllable switch is connected to the first end of the second capacitor, and a second end of the second capacitor is connected to the An output end of the fifth controllable switch, an output end of the scan line and the sixth controllable switch, and an input end of the sixth controllable switch is connected to the clock signal of the current stage.
  • the scan driving circuit further includes a voltage stabilizing module for stabilizing the voltage and preventing leakage of the pull-up maintaining module, the voltage stabilizing module includes a seventh controllable switch, and the control end of the seventh controllable switch is connected An input end of the fourth controllable switch and an output voltage of the fourth controllable switch, an input end of the second controllable switch, an output end of the first controllable switch, and an output end of the first controllable switch.
  • the control end of the third controllable switch is connected to the control end of the sixth controllable switch and the first end of the second capacitor.
  • the scan driving circuit further includes a pull-up auxiliary module, configured to prevent the pull-up maintaining module from leaking during charging of a pull-up control signal point in the output module, where the pull-up auxiliary module includes an eighth a controllable switch, the control end of the eighth controllable switch is connected to the input end of the first controllable switch, the input end of the eighth controllable switch is connected to the input end of the second controllable switch, An input end of the third controllable switch, an input end of the fifth controllable switch, and the open voltage end, and an output end of the eighth controllable switch is connected to the control end of the second controllable switch.
  • the pull-up auxiliary module includes an eighth a controllable switch, the control end of the eighth controllable switch is connected to the input end of the first controllable switch, the input end of the eighth controllable switch is connected to the input end of the second controllable switch, An input end of the third controllable switch, an input end of the fifth controllable switch, and the open
  • the forward/reverse scan module includes a ninth controllable switch, a tenth controllable switch, an eleventh controllable switch, and a twelfth controllable switch, and the control end of the ninth controllable switch is connected to the first scan Controlling a voltage, an input end of the ninth controllable switch is connected to a lower level scan signal, an output end of the ninth controllable switch is connected to the input module; and a control end of the tenth controllable switch is connected to a second scan control a voltage, an input end of the tenth controllable switch is connected to the upper scan signal, and an output end of the tenth controllable switch is connected to an output end of the ninth controllable switch;
  • the control end is connected to the first scan control voltage, the input end of the eleventh controllable switch is connected to the third lower stage clock signal, and the output end of the eleventh controllable switch is connected to the pull-up maintenance module; a control end of the twelfth controllable switch is connected
  • the input unit includes a thirteenth controllable switch, the control end of the thirteenth controllable switch is connected to the first lower level clock signal, and the input end of the thirteenth controllable switch is connected to the ninth controllable switch The output end of the thirteenth controllable switch is connected to the input end of the first controllable switch in the control module;
  • the processing module includes a fourteen controllable switch, and a control end of the fourteenth controllable switch is connected to a lower pull-up control signal point, and an input end of the fourteenth controllable switch is connected to the first controllable switch The output end of the fourteenth controllable switch is connected to the output end of the first controllable switch and the output end of the second controllable switch.
  • the first to fourteenth controllable switches are all PMOS type thin film transistors or NMOS type thin film transistors.
  • another technical solution adopted by the present invention is to provide a flat display device comprising the scan driving circuit as described above.
  • the scan driving circuit of the present invention controls the level transmission of the scan signal by the upper pull-up control signal point and the lower pull-up control signal point, This avoids the problem that the scan driving circuit is repeatedly charged during the inactive period, thereby greatly improving the stability of the scan driving circuit.
  • FIG. 1 is a schematic structural view of a scan driving circuit in the prior art
  • FIG. 3 is a schematic structural view of a scan driving circuit of a first embodiment of the present invention.
  • FIG. 4 is a schematic structural view of a scan driving circuit of a second embodiment of the present invention.
  • Figure 5 is a waveform diagram of a scan driving circuit of the present invention.
  • Figure 6 is a block diagram showing the structure of a scan driving circuit of a third embodiment of the present invention.
  • Figure 7 is a block diagram showing the structure of a scan driving circuit of a fourth embodiment of the present invention.
  • Figure 8 is a schematic illustration of a flat display device of the present invention.
  • the circuit shown in FIG. 1 consumes a large amount of power during inactive periods.
  • the transistor PT4 controlled by the first lower clock signal CK(N+2) is still operating continuously, and during the inactive period, the scan driving circuit will
  • the upper-level scan driving signal G(N-1) is continuously written into the pull-up control signal Q(N) of the first stage by the jump of the first lower-level clock signal CK(N+2), although the upper-stage pull-up is
  • the control signal Q(N-1) is always kept low, but the switch of the transistor PT4 must also cause additional loss of dynamic power consumption and some non-ideal working conditions, from the existing scan driving circuit shown in FIG.
  • the timing diagram analysis shows that there is a risk point in the existing scan drive circuit.
  • the existence of this risk point will directly lead to the failure of the whole circuit.
  • the transmission waveform will fluctuate somewhat.
  • the abnormal disturbance is input to the first-stage pull-up control signal Q(N) of the next-stage scan driving circuit by controlling the first lower-level clock signal CK(N+2), thereby affecting the next-stage scan driving circuit.
  • Normal work the last impact The normal display of the board.
  • FIG. 3 is a schematic structural diagram of a scan driving circuit according to a first embodiment of the present invention.
  • the scan driving circuit of the first embodiment of the present invention includes a pull-up maintaining module 300 for receiving the upper-level clock signal CK(N-1) and according to the received upper-level clock signal CK(N- 1) pulling up the pull-down control signal point P and charging the pull-up control signal point Q;
  • the control module 700 is connected to the pull-up maintaining module 300 for receiving the upper pull-up control signal Q(N-1) and
  • the upper stage scans the drive signal G(N-1) and controls the pull-up maintaining module 300 according to the received upper pull-up control signal Q(N-1) and the upper-level scan drive signal G(N-1);
  • the output module 500 is connected to the pull-up maintaining module 300 and the control module 700 for outputting a scan driving signal to the scan line, and a scan line for transmitting the scan driving signal to the pixel unit.
  • the control module 700 includes a first controllable switch PT14, the input end of the first controllable switch PT14 is connected to the upper scan drive signal G(N-1), and the control end of the first controllable switch PT14 is connected.
  • the upper stage pulls up the control signal point Q(N-1), and the output end of the first controllable switch PT14 is connected to the pull-up maintaining module 300.
  • the pull-up maintaining module 300 includes a second controllable switch PT5, a third controllable switch PT6, a fourth controllable switch PT8, a fifth controllable switch PT9, and a first capacitor C1, and the second controllable switch PT5
  • the output end is connected to the output end of the first controllable switch PT14 and the control end of the third controllable switch PT6, and the control end of the second controllable switch PT5 is connected to the control end of the fifth controllable switch PT9
  • the output end of the third controllable switch PT6, the input ends of the second controllable switch PT5, the third controllable switch PT6 and the fifth controllable switch PT9 are connected to the open voltage terminal VGH,
  • the output end of the fifth controllable switch PT9 is connected to a scan line and the output module 500.
  • One end of the first capacitor C1 is connected to the input end of the fifth controllable switch PT9, and the other end of the first capacitor C1 One end is connected to the control end of the fifth controllable switch PT9, the control end of the fourth controllable switch PT8 is connected to the upper clock signal CK(N-1), and the input end of the fourth controllable switch PT8 is connected. Turning off the voltage terminal VGL, the output end of the fourth controllable switch PT8 is connected to the output of the third controllable switch PT6 End.
  • the output module 500 includes a sixth controllable switch PT10 and a second capacitor C2.
  • the control end of the sixth controllable switch PT10 is connected to the first end of the second capacitor C2, and the second end of the second capacitor C2.
  • the terminal is connected to the output end of the fifth controllable switch PT9, the scan line and the output end of the sixth controllable switch PT10, and the input end of the sixth controllable switch PT10 is connected to the local clock signal CK (N ).
  • the scan driving circuit further includes a voltage stabilizing module 400 for stabilizing the voltage and preventing leakage of the pull-up maintaining module 300.
  • the voltage stabilizing module 400 includes a seventh controllable switch PT7, and the seventh controllable switch PT7 The control terminal is connected to the input end of the fourth controllable switch PT8 and the off voltage VGL, and the input end of the seventh controllable switch PT7 is connected to the output end of the second controllable switch PT5, the first The output end of the controllable switch PT14 and the control end of the third controllable switch PT6, the output end of the seventh controllable switch PT7 is connected to the control end of the sixth controllable switch PT10 and the second capacitor C2 First end.
  • the scan driving circuit further includes a pull-up auxiliary module 600 for preventing the pull-up maintaining module 300 from leaking during charging of the pull-up control signal point Q in the output module 500, the pull-up auxiliary module 600
  • the eighth controllable switch PT11 is connected, the control end of the eighth controllable switch PT11 is connected to the input end of the first controllable switch PT14, and the input end of the eighth controllable switch PT11 is connected to the second controllable An input end of the switch PT5, an input end of the third controllable switch PT6, an input end of the fifth controllable switch PT9, and the open voltage terminal VGH, and an output end of the eighth controllable switch PT11 is connected The control end of the second controllable switch PT5 is described.
  • the first to eighth controllable switches PT14, PT5, PT6, PT8-PT10, PT7, and PT11 are all PMOS type thin film transistors.
  • the scan driving circuit controls the level transfer of the upper scanning signal G(N-1) by the upper pull-up control signal point Q(N-1), thereby achieving Under the premise that the scan driving circuit works normally, the load of the clock signal CK is reduced, and the additional power consumption of the scan driving circuit is reduced, and the scan driving circuit of the first embodiment is used for a positive sweep or a reverse sweep circuit.
  • FIG. 4 is a structural diagram of a second embodiment of the scan driving circuit of the present invention.
  • the scan driving circuit of the second embodiment is different from the scan driving circuit of the first embodiment in that the scan driving circuit further includes a forward-reverse scanning module 100 for outputting The forward scan driving signal and the reverse scan driving signal are used to drive the scan driving circuit;
  • the input module 200 is connected between the forward and reverse scan module 100 and the control module 700 for receiving a first lower level
  • the clock signal CK(N+2) charges the pull-up control signal point Q according to the received first lower-level clock signal CK(N+2);
  • the processing module 800 is connected to the control module 700 and
  • the pull-up maintaining module 300 is configured to receive an upper pull-up control signal Q(N+1) and control the pull-up maintaining module 300 according to the received upper pull-up control signal Q(N+1).
  • the forward and reverse scan module 100 includes a ninth controllable switch PT0, a tenth controllable switch PT1, an eleventh controllable switch PT2, and a twelfth controllable switch PT3, and a control end of the ninth controllable switch PT0 Connecting the first scan control voltage U2D, the input end of the ninth controllable switch PT0 is connected to the lower scan signal G(N+1), and the output end of the ninth controllable switch PT0 is connected to the input module 200;
  • the control end of the tenth controllable switch PT1 is connected to the second scan control voltage D2U, and the input end of the tenth controllable switch PT1 is connected to the upper scan signal G(N-1), the tenth controllable switch PT1
  • the output end is connected to the output end of the ninth controllable switch PT0; the control end of the eleventh controllable switch PT2 is connected to the first scan control voltage U2D, and the input end of the eleventh control
  • the input unit 200 includes a thirteenth controllable switch PT4, and the control end of the thirteenth controllable switch PT4 is connected to the first lower level clock signal CK(N+2), and the thirteenth controllable switch PT4 The input end is connected to the output end of the ninth controllable switch PT0, and the output end of the thirteenth controllable switch PT4 is connected to the input end of the first controllable switch PT14 in the control module 700;
  • the processing module 800 includes a fourteenth controllable switch PT15, and a control end of the fourteenth controllable switch PT15 is connected to the lower pull-up control signal point Q(N+1), the fourteenth controllable switch An input end of the PT15 is connected to an input end of the first controllable switch PT14, and an output end of the fourteenth controllable switch PT15 is connected to an output end of the first controllable switch PT14 and the second controllable switch PT5 The output.
  • the first to fourteen controllable switches PT14, PT5, PT6, PT8-PT10, PT7, PT11, PT0-PT4, and PT15 are all PMOS type thin film transistors.
  • the scan driving circuit 1 does not directly pull up the pull-down control signal point P by using the upper-level scan signal G(N-1), but passes the forward-reverse scan module.
  • the selected upper scanning signal G(N-1) and the lower scanning signal G(N+1) pull up the pull-down control signal point P, thereby preventing the scan driving circuit from malfunctioning during the reverse scanning.
  • FIG. 5 is a waveform diagram of the scan driving circuit of the above embodiment of the present invention.
  • the thirteenth controllable switch PT4 and the first controllable switch PT14 are both turned off, and at this time, the first-stage pull-up control signal point Q ( N) maintaining a low level, the current pull-down control signal point P(N) is maintained at a high level, and when the current clock signal CK(N) appears, the current-level scan signal G(N) is output, After the output of the scan signal G(N) signal of the current stage is completed, the pull-down control signal point P(N) of the current stage is pulled to a low level as the upper clock signal CK(N+1) appears.
  • the primary pull-up control signal point Q(N) becomes a high level
  • the local-level scan signal G(N) is stabilized at a high level, when the upper-level control signal point Q(N-1) and the
  • the first controllable switch PT14 and the fourteenth controllable switch PT15 are both in an off state, and the upper level scan signal G(N-
  • the fluctuation of 1) does not affect the variation of the pull-up control signal point Q(N) of the present stage, and thus the scan driving circuit is in a stable state.
  • FIG. 6 is a schematic structural view of a third embodiment of the scan driving circuit of the present invention.
  • the scan driving circuit of the third embodiment is different from the scan driving circuit of the first embodiment in that the first to eighth controllable switches PT14, PT5, PT6, and PT8 are provided.
  • - PT10, PT7 and PT11 are all NMOS type thin film transistors.
  • FIG. 7 is a structural diagram of a fourth embodiment of the scan driving circuit of the present invention.
  • the scan driving circuit of the fourth embodiment is different from the scan driving circuit of the second embodiment in that the first to fourteen controllable switches PT14, PT5, PT6, PT8-PT10, PT7, PT11, PT0-PT4 and PT15 are all NMOS type thin film transistors.
  • FIG. 8 is a schematic diagram of a flat display device according to the present invention.
  • the flat display device may be, for example, an LCD or an OLED including the aforementioned scan driving circuit, the scan driving circuit being disposed at a periphery of the flat display device, for example, disposed at both ends of the flat display device, the scan driving circuit It is any scan drive circuit of the present invention.
  • the scan driving circuit controls the level transmission of the scan signal by the upper pull-up control signal point Q(N-1) and the lower-stage pull-up control signal point Q(N+1), thereby avoiding the scan driving
  • the problem that the circuit is repeatedly charged during the inactive period greatly improves the stability of the scan driving circuit.

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Abstract

一种扫描驱动电路及具有该电路的平面显示装置，所述扫描驱动电路包括上拉维持模块（300），用于接收上级扫描驱动信号（G(N-1)）并根据接收到的所述上级扫描驱动信号（G(N-1)）对下拉控制信号点（P）进行上拉并对上拉控制信号点（Q）进行充电；控制模块（700），连接所述上拉维持模块（300），用于接收上级上拉控制信号（Q(N-1)）及上级扫描驱动信号（G(N-1)）并根据接收到的所述上级上拉控制信号（Q(N-1)）及所述上级扫描驱动信号（G(N-1)）控制所述上拉维持模块（300）；输出模块（500），连接所述上拉维持模块（300）及所述控制模块（700），用于输出扫描驱动信号（G(N)）给扫描线；扫描线，用于将所述扫描驱动信号（G(N)）传输至像素单元，以此避免所述扫描驱动电路在非作用期间被重复充电的问题，进而极大的提高了所述扫描驱动电路的稳定性。

Description

扫描驱动电路及具有该电路的平面显示装置
【技术领域】
本发明涉及显示技术领域，特别是涉及一种扫描驱动电路及具有该电路的平面显示装置。
【背景技术】
目前的平面显示装置中采用GOA，这种非正常的扰动会通过控制时钟信号输入到下一级扫描驱动电路中，进而影响下一级扫描驱动电路的正常工作，最后影响面板的正常显示，从而影响扫描驱动电路的稳定性。
【发明内容】
本发明主要解决的技术问题是提供一种扫描驱动电路及具有该电路的平面显示装置，以保证扫描驱动电路工作的稳定性。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种扫描驱动电路，包括：
上拉维持模块，用于接收上级时钟信号并根据接收到的所述上级时钟信号对下拉控制信号点进行上拉并对上拉控制信号点进行充电；
控制模块，连接所述上拉维持模块，用于接收上级上拉控制信号及上级扫描驱动信号并根据接收到的所述上级上拉控制信号及所述上级扫描驱动信号控制所述上拉维持模块；
输出模块，连接所述上拉维持模块及所述控制模块，用于输出扫描驱动信号给扫描线；及
扫描线，用于将所述扫描驱动信号传输至像素单元。
其中，所述扫描驱动电路还包括：
正反向扫描模块，用于输出正向扫描驱动信号及反向扫描驱动信号来驱动所述扫描驱动电路；
输入模块，连接在所述正反向扫描模块与所述控制模块之间，用于接收一第一下级时钟信号并根据接收到的所述第一下级时钟信号对所述上拉控制信号点进行充电；及
处理模块，连接所述控制模块及所述上拉维持模块，用于接收一上级上拉控制信号并根据接收到的所述上级上拉控制信号控制所述上拉维持模块。
其中，所述控制模块包括第一可控开关，所述第一可控开关的输入端连接所述上级扫描驱动信号，所述第一可控开关的控制端连接上级上拉控制信号点，所述第一可控开关的输出端连接所述上拉维持模块。
其中，所述上拉维持模块包括第二可控开关、第三可控开关、第四可控开关、第五可控开关及第一电容，所述第二可控开关的输出端连接所述第一可控开关的输出端及所述第三可控开关的控制端，所述第二可控开关的控制端连接所述第五可控开关的控制端及所述第三可控开关的输出端，所述第二可控开关、所述第三可控开关及所述第五可控开关的输入端均连接开启电压端，所述第五可控开关的输出端连接一扫描线及所述输出模块，所述第一电容的一端连接所述第五可控开关的输入端，所述第一电容的另一端连接所述第五可控开关的控制端，所述第四可控开关的控制端连接所述上级时钟信号，所述第四可控开关的输入端连接关闭电压端，所述第四可控开关的输出端连接所述第三可控开关的输出端。
其中，所述输出模块包括第六可控开关及第二电容，所述第六可控开关的控制端连接所述第二电容的第一端，所述第二电容的第二端连接所述第五可控开关的输出端、所述扫描线及所述第六可控开关的输出端，所述第六可控开关的输入端连接本级时钟信号。
其中，所述扫描驱动电路还包括稳压模块，用于稳定电压及防止所述上拉维持模块漏电，所述稳压模块包括第七可控开关，所述第七可控开关的控制端连接所述第四可控开关的输入端及所述关闭电压，所述第七可控开关的输入端连接所述第二可控开关的输出端、所述第一可控开关的输出端及所述第三可控开关的控制端，所述第七可控开关的输出端连接所述第六可控开关的控制端及所述第二电容的第一端。
其中，所述扫描驱动电路还包括上拉辅助模块，用于防止所述上拉维持模块在对所述输出模块中的上拉控制信号点充电过程中漏电，所述上拉辅助模块包括第八可控开关，所述第八可控开关的控制端连接所述第一可控开关的输入端，所述第八可控开关的输入端连接所述第二可控开关的输入端、所述第三可控开关的输入端、所述第五可控开关的输入端及所述开启电压端，所述第八可控开关的输出端连接所述第二可控开关的控制端。
其中，所述正反向扫描模块包括第九可控开关、第十可控开关、第十一可控开关及第十二可控开关，所述第九可控开关的控制端连接第一扫描控制电压，所述第九可控开关的输入端连接一下级扫描信号，所述第九可控开关的输出端连接所述输入模块；所述第十可控开关的控制端连接第二扫描控制电压，所述第十可控开关的输入端连接所述上级扫描信号，所述第十可控开关的输出端连接所述第九可控开关的输出端；所述第十一可控开关的控制端连接所述第一扫描控制电压，所述第十一可控开关的输入端连接第三下级时钟信号，所述第十一可控开关的输出端连接所述上拉维持模块；所述第十二可控开关的控制端连接所述第二扫描控制电压，所述第十二可控开关的输入端连接第二下级时钟信号，所述第十二可控开关的输出端连接所述第十一可控开关的输出端；
所述输入单元包括第十三可控开关，所述第十三可控开关的控制端连接第一下级时钟信号，所述第十三可控开关的输入端连接所述第九可控开关的输出端，所述第十三可控开关的输出端连接所述控制模块中第一可控开关的输入端；
所述处理模块包括第十四可控开关，所述第十四可控开关的控制端连接下级上拉控制信号点，所述第十四可控开关的输入端连接所述第一可控开关的输入端，所述第十四可控开关的输出端连接所述第一可控开关的输出端及所述第二可控开关的输出端。
其中，所述第一至第十四可控开关均为PMOS型薄膜晶体管或者NMOS型薄膜晶体管。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种平面显示装置，包括如上所述任一所述的扫描驱动电路。
本发明的有益效果是：区别于现有技术的情况，本发明的所述扫描驱动电路通过所述上级上拉控制信号点及所述下级上拉控制信号点控制扫描信号的级传输入，以此避免所述扫描驱动电路在非作用期间被重复充电的问题，进而极大的提高了所述扫描驱动电路的稳定性。
【附图说明】
图1是现有技术中扫描驱动电路的结构示意图；
图2是现有技术中扫描驱动电路的波形图；
图3是本发明的第一实施例的扫描驱动电路的结构示意图；
图4是本发明的第二实施例的扫描驱动电路的结构示意图；
图5是本发明的扫描驱动电路的波形图；
图6是本发明的第三实施例的扫描驱动电路的结构示意图；
图7是本发明的第四实施例的扫描驱动电路的结构示意图；
图8是本发明的平面显示装置的示意图。
【具体实施方式】
请参阅图1及图2，图1所示电路在非作用期间的功耗较大。图1所示电路中，扫描驱动电路在生成扫描驱动信号之后，第一下级时钟信号CK(N+2)控制的晶体管PT4仍在不断的工作，在非作用期间，所述扫描驱动电路会通过所述第一下级时钟信号CK(N+2)的跳变不断将上级扫描驱动信号G(N-1)写入到本级上拉控制信号Q(N)之中，虽然上级上拉控制信号Q(N-1)一直维持低电平，但是晶体管PT4的开关也必定会造成额外的动态功耗的损失和一些非理想工作状态的产生，从图2所示的现有扫描驱动电路的时序图分析可知，现有扫描驱动电路存在一个风险点，这个风险点的存在会直接导致整个电路的失效，当级传信号受到外界条件的干扰时，传输波形会发生一定的波动，这种非正常的扰动会通过控制所述第一下级时钟信号CK(N+2)输入到下一级扫描驱动电路的本级上拉控制信号Q(N)中，进而影响下一级扫描驱动电路的正常工作，最后影响面板的正常显示。
请参阅图3，是本发明的第一实施例的扫描驱动电路的结构示意图。如图3所示，本发明的第一实施例的扫描驱动电路包括上拉维持模块300，用于接收上级时钟信号CK(N-1)并根据接收到的所述上级时钟信号CK(N-1)对下拉控制信号点P进行上拉并对上拉控制信号点Q进行充电；控制模块700，连接所述上拉维持模块300，用于接收上级上拉控制信号Q(N-1)及上级扫描驱动信号G(N-1)并根据接收到的所述上级上拉控制信号Q(N-1)及所述上级扫描驱动信号G(N-1)控制所述上拉维持模块300；输出模块500，连接所述上拉维持模块300及所述控制模块700，用于输出扫描驱动信号给扫描线；扫描线，用于将所述扫描驱动信号传输至像素单元。
所述控制模块700包括第一可控开关PT14，所述第一可控开关PT14的输入端连接所述上级扫描驱动信号G(N-1)，所述第一可控开关PT14的控制端连接所述上级上拉控制信号点Q(N-1)，所述第一可控开关PT14的输出端连接所述上拉维持模块300。
所述上拉维持模块300包括第二可控开关PT5、第三可控开关PT6、第四可控开关PT8、第五可控开关PT9及第一电容C1，所述第二可控开关PT5的输出端连接所述第一可控开关PT14的输出端及所述第三可控开关PT6的控制端，所述第二可控开关PT5的控制端连接所述第五可控开关PT9的控制端及所述第三可控开关PT6的输出端，所述第二可控开关PT5、所述第三可控开关PT6及所述第五可控开关PT9的输入端均连接开启电压端VGH，所述第五可控开关PT9的输出端连接一扫描线及所述输出模块500，所述第一电容C1的一端连接所述第五可控开关PT9的输入端，所述第一电容C1的另一端连接所述第五可控开关PT9的控制端，所述第四可控开关PT8的控制端连接所述上级时钟信号CK(N-1)，所述第四可控开关PT8的输入端连接关闭电压端VGL，所述第四可控开关PT8的输出端连接所述第三可控开关PT6的输出端。
所述输出模块500包括第六可控开关PT10及第二电容C2，所述第六可控开关PT10的控制端连接所述第二电容C2的第一端，所述第二电容C2的第二端连接所述第五可控开关PT9的输出端、所述扫描线及所述第六可控开关PT10的输出端，所述第六可控开关PT10的输入端连接本级时钟信号CK(N)。
所述扫描驱动电路还包括稳压模块400，用于稳定电压及防止所述上拉维持模块300漏电，所述稳压模块400包括第七可控开关PT7，所述第七可控开关PT7的控制端连接所述第四可控开关PT8的输入端及所述关闭电压VGL，所述第七可控开关PT7的输入端连接所述第二可控开关PT5的输出端、所述第一可控开关PT14的输出端及所述第三可控开关PT6的控制端，所述第七可控开关PT7的输出端连接所述第六可控开关PT10的控制端及所述第二电容C2的第一端。
所述扫描驱动电路还包括上拉辅助模块600，用于防止所述上拉维持模块300在对所述输出模块500中的上拉控制信号点Q充电过程中漏电，所述上拉辅助模块600包括第八可控开关PT11，所述第八可控开关PT11的控制端连接所述第一可控开关PT14的输入端，所述第八可控开关PT11的输入端连接所述第二可控开关PT5的输入端、所述第三可控开关PT6的输入端、所述第五可控开关PT9的输入端及所述开启电压端VGH，所述第八可控开关PT11的输出端连接所述第二可控开关PT5的控制端。
在所述第一实施例中，所述第一至第八可控开关PT14、PT5、PT6、PT8-PT10、PT7及PT11均为PMOS型薄膜晶体管。
在所述第一实施例中，所述扫描驱动电路通过上级上拉控制信号点Q(N-1)控制所述上级扫描信号G(N-1)的级传，从而实现在不影响所述扫描驱动电路正常工作的前提下，降低时钟信号CK的负载，减小所述扫描驱动电路的额外功耗，所述第一实施例的扫描驱动电路用于正扫或者反扫电路。
请参阅图4，是本发明的扫描驱动电路的第二实施例结构示意图。如图4所示，所述第二实施例的扫描驱动电路与所述第一实施例的扫描驱动电路的区别之处在于：所述扫描驱动电路还包括正反向扫描模块100，用于输出正向扫描驱动信号及反向扫描驱动信号来驱动所述扫描驱动电路；输入模块200，连接在所述正反向扫描模块100与所述控制模块700之间，用于接收一第一下级时钟信号CK(N+2)并根据接收到的所述第一下级时钟信号CK(N+2)对所述上拉控制信号点Q进行充电；处理模块800，连接所述控制模块700及所述上拉维持模块300，用于接收一上级上拉控制信号Q(N+1)并根据接收到的所述上级上拉控制信号Q(N+1)控制所述上拉维持模块300。
所述正反向扫描模块100包括第九可控开关PT0、第十可控开关PT1、第十一可控开关PT2及第十二可控开关PT3，所述第九可控开关PT0的控制端连接第一扫描控制电压U2D，所述第九可控开关PT0的输入端连接一下级扫描信号G(N+1)，所述第九可控开关PT0的输出端连接所述输入模块200；所述第十可控开关PT1的控制端连接第二扫描控制电压D2U，所述第十可控开关PT1的输入端连接所述上级扫描信号G(N-1)，所述第十可控开关PT1的输出端连接所述第九可控开关PT0的输出端；所述第十一可控开关PT2的控制端连接所述第一扫描控制电压U2D，所述第十一可控开关PT2的输入端连接第三下级时钟信号CK(N+3)，所述第十一可控开关PT2的输出端连接所述上拉维持模块300；所述第十二可控开关PT3的控制端连接所述第二扫描控制电压D2U，所述第十二可控开关PT3的输入端连接第二下级时钟信号CK(N+1)，所述第十二可控开关PT3的输出端连接所述第十一可控开关PT2的输出端；
所述输入单元200包括第十三可控开关PT4，所述第十三可控开关PT4的控制端连接第一下级时钟信号CK(N+2)，所述第十三可控开关PT4的输入端连接所述第九可控开关PT0的输出端，所述第十三可控开关PT4的输出端连接所述控制模块700中第一可控开关PT14的输入端；
所述处理模块800包括第十四可控开关PT15，所述第十四可控开关PT15的控制端连接所述下级上拉控制信号点Q(N+1)，所述第十四可控开关PT15的输入端连接所述第一可控开关PT14的输入端，所述第十四可控开关PT15的输出端连接所述第一可控开关PT14的输出端及所述第二可控开关PT5的输出端。
在所述第二实施例中，所述第一至第十四可控开关PT14、PT5、PT6、PT8-PT10、PT7、PT11、PT0-PT4及PT15均为PMOS型薄膜晶体管。
在所述第二实施例中，所述扫描驱动电路1没有直接利用上级扫描信号G(N-1)对所述下拉控制信号点P进行上拉控制，而是通过所述正反向扫描模块100选择后的上级扫描信号G(N-1)和下级扫描信号G(N+1)对所述下拉控制信号点P进行上拉，以此避免反扫期间所述扫描驱动电路不能正常工作。
请参阅图5，是本发明上述实施例的所述扫描驱动电路的波形图。根据图5获得所述扫描驱动电路的工作原理如下：当所述上级扫描信号G(N-1)出现时，所述第十可控开关PT1、所述第十三可控开关PT4及所述第一可控开关PT14均导通，此时对所述本级上拉控制信号点Q(N)进行充电至低电平，对所述本级下拉控制信号点P(N)充电至高电平，当所述上级扫描信号G(N-1)结束时，所述第十三可控开关PT4及所述第一可控开关PT14均截止，此时所述本级上拉控制信号点Q(N)维持低电平，所述本级下拉控制信号点P(N)维持高电平，当所述本级时钟信号CK(N)出现时，输出本级扫描信号G(N), 当所述本级扫描信号G(N)信号输出完毕之后，随着上级时钟信号CK(N+1)的出现，所述本级下拉控制信号点P(N)被拉至低电平，所述本级上拉控制信号点Q(N)变成高电平，所述本级扫描信号G(N)稳定在高电平，当所述上级控制信号点Q(N-1)和所述下级控制信号点Q(N+1)稳定输出高电平时，所述第一可控开关PT14和所述第十四可控开关PT15均处于截止状态，此时所述上级扫描信号G(N-1)的波动不会影响所述本级上拉控制信号点Q(N)的变化，因此所述扫描驱动电路处于稳定状态。
请参阅图6，是本发明扫描驱动电路的第三实施例的结构示意图。如图6所示，所述第三实施例的扫描驱动电路与所述第一实施例的扫描驱动电路的区别之处在于：所述第一至第八可控开关PT14、PT5、PT6、PT8-PT10、PT7及PT11均为NMOS型薄膜晶体管。
请参阅图7，是本发明扫描驱动电路的第四实施例的结构示意图。如图7所示，所述第四实施例的扫描驱动电路与所述第二实施例的扫描驱动电路的区别之处在于：所述第一至第十四可控开关PT14、PT5、PT6、PT8-PT10、PT7、PT11、PT0-PT4及PT15均为NMOS型薄膜晶体管。
请参阅图8，为本发明一种平面显示装置的示意图。所述平面显示装置例如可为LCD或OLED，其包括前述的扫描驱动电路，所述扫描驱动电路设置在所述平面显示装置的周边，例如设置在平面显示装置的两端，所述扫描驱动电路为本发明任一种扫描驱动电路。
所述扫描驱动电路通过所述上级上拉控制信号点Q(N-1)及所述下级上拉控制信号点Q(N+1)控制扫描信号的级传输入，以此避免所述扫描驱动电路在非作用期间被重复充电的问题，进而极大的提高了所述扫描驱动电路的稳定性。
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (18)

  1. 一种扫描驱动电路，其中，所述扫描驱动电路包括：
    上拉维持模块，用于接收上级时钟信号并根据接收到的所述上级时钟信号对下拉控制信号点进行上拉并对上拉控制信号点进行充电；
    控制模块，连接所述上拉维持模块，用于接收上级上拉控制信号及上级扫描驱动信号并根据接收到的所述上级上拉控制信号及所述上级扫描驱动信号控制所述上拉维持模块；
    输出模块，连接所述上拉维持模块及所述控制模块，用于输出扫描驱动信号给扫描线；及
    扫描线，用于将所述扫描驱动信号传输至像素单元。
  2. 根据权利要求1所述的扫描驱动电路，其中，还包括：
    正反向扫描模块，用于输出正向扫描驱动信号及反向扫描驱动信号来驱动所述扫描驱动电路；
    输入模块，连接在所述正反向扫描模块与所述控制模块之间，用于接收一第一下级时钟信号并根据接收到的所述第一下级时钟信号对所述上拉控制信号点进行充电；及
    处理模块，连接所述控制模块及所述上拉维持模块，用于接收一上级上拉控制信号并根据接收到的所述上级上拉控制信号控制所述上拉维持模块。
  3. 根据权利要求2所述的扫描驱动电路，其中，所述控制模块包括第一可控开关，所述第一可控开关的输入端连接所述上级扫描驱动信号，所述第一可控开关的控制端连接上级上拉控制信号点，所述第一可控开关的输出端连接所述上拉维持模块。
  4. 根据权利要求3所述的扫描驱动电路，其中，所述上拉维持模块包括第二可控开关、第三可控开关、第四可控开关、第五可控开关及第一电容，所述第二可控开关的输出端连接所述第一可控开关的输出端及所述第三可控开关的控制端，所述第二可控开关的控制端连接所述第五可控开关的控制端及所述第三可控开关的输出端，所述第二可控开关、所述第三可控开关及所述第五可控开关的输入端均连接开启电压端，所述第五可控开关的输出端连接一扫描线及所述输出模块，所述第一电容的一端连接所述第五可控开关的输入端，所述第一电容的另一端连接所述第五可控开关的控制端，所述第四可控开关的控制端连接所述上级时钟信号，所述第四可控开关的输入端连接关闭电压端，所述第四可控开关的输出端连接所述第三可控开关的输出端。
  5. 根据权利要求4所述的扫描驱动电路，其中，所述输出模块包括第六可控开关及第二电容，所述第六可控开关的控制端连接所述第二电容的第一端，所述第二电容的第二端连接所述第五可控开关的输出端、所述扫描线及所述第六可控开关的输出端，所述第六可控开关的输入端连接本级时钟信号。
  6. 根据权利要求5所述的扫描驱动电路，其中，还包括稳压模块，用于稳定电压及防止所述上拉维持模块漏电，所述稳压模块包括第七可控开关，所述第七可控开关的控制端连接所述第四可控开关的输入端及所述关闭电压，所述第七可控开关的输入端连接所述第二可控开关的输出端、所述第一可控开关的输出端及所述第三可控开关的控制端，所述第七可控开关的输出端连接所述第六可控开关的控制端及所述第二电容的第一端。
  7. 根据权利要求6所述的扫描驱动电路，其中，还包括上拉辅助模块，用于防止所述上拉维持模块在对所述输出模块中的上拉控制信号点充电过程中漏电，所述上拉辅助模块包括第八可控开关，所述第八可控开关的控制端连接所述第一可控开关的输入端，所述第八可控开关的输入端连接所述第二可控开关的输入端、所述第三可控开关的输入端、所述第五可控开关的输入端及所述开启电压端，所述第八可控开关的输出端连接所述第二可控开关的控制端。
  8. 根据权利要求7所述的扫描驱动电路，其中，所述正反向扫描模块包括第九可控开关、第十可控开关、第十一可控开关及第十二可控开关，所述第九可控开关的控制端连接第一扫描控制电压，所述第九可控开关的输入端连接一下级扫描信号，所述第九可控开关的输出端连接所述输入模块；所述第十可控开关的控制端连接第二扫描控制电压，所述第十可控开关的输入端连接所述上级扫描信号，所述第十可控开关的输出端连接所述第九可控开关的输出端；所述第十一可控开关的控制端连接所述第一扫描控制电压，所述第十一可控开关的输入端连接第三下级时钟信号，所述第十一可控开关的输出端连接所述上拉维持模块；所述第十二可控开关的控制端连接所述第二扫描控制电压，所述第十二可控开关的输入端连接第二下级时钟信号，所述第十二可控开关的输出端连接所述第十一可控开关的输出端；
    所述输入单元包括第十三可控开关，所述第十三可控开关的控制端连接第一下级时钟信号，所述第十三可控开关的输入端连接所述第九可控开关的输出端，所述第十三可控开关的输出端连接所述控制模块中第一可控开关的输入端；
    所述处理模块包括第十四可控开关，所述第十四可控开关的控制端连接下级上拉控制信号点，所述第十四可控开关的输入端连接所述第一可控开关的输入端，所述第十四可控开关的输出端连接所述第一可控开关的输出端及所述第二可控开关的输出端。
  9. 根据权利要求8所述的扫描驱动电路，其中，所述第一至所述第十四可控开关均为PMOS型薄膜晶体管或者NMOS型薄膜晶体管。
  10. 一种平面显示装置，其中，所述平面显示装置包括扫描驱动电路，所述扫描驱动电路包括：
    上拉维持模块，用于接收上级时钟信号并根据接收到的所述上级时钟信号对下拉控制信号点进行上拉并对上拉控制信号点进行充电；
    控制模块，连接所述上拉维持模块，用于接收上级上拉控制信号及上级扫描驱动信号并根据接收到的所述上级上拉控制信号及所述上级扫描驱动信号控制所述上拉维持模块；
    输出模块，连接所述上拉维持模块及所述控制模块，用于输出扫描驱动信号给扫描线；及
    扫描线，用于将所述扫描驱动信号传输至像素单元。
  11. 根据权利要求10所述的平面显示装置，其中，还包括：
    正反向扫描模块，用于输出正向扫描驱动信号及反向扫描驱动信号来驱动所述扫描驱动电路；
    输入模块，连接在所述正反向扫描模块与所述控制模块之间，用于接收一第一下级时钟信号并根据接收到的所述第一下级时钟信号对所述上拉控制信号点进行充电；及
    处理模块，连接所述控制模块及所述上拉维持模块，用于接收一上级上拉控制信号并根据接收到的所述上级上拉控制信号控制所述上拉维持模块。
  12. 根据权利要求11所述的平面显示装置，其中，所述控制模块包括第一可控开关，所述第一可控开关的输入端连接所述上级扫描驱动信号，所述第一可控开关的控制端连接上级上拉控制信号点，所述第一可控开关的输出端连接所述上拉维持模块。
  13. 根据权利要求12所述的平面显示装置，其中，所述上拉维持模块包括第二可控开关、第三可控开关、第四可控开关、第五可控开关及第一电容，所述第二可控开关的输出端连接所述第一可控开关的输出端及所述第三可控开关的控制端，所述第二可控开关的控制端连接所述第五可控开关的控制端及所述第三可控开关的输出端，所述第二可控开关、所述第三可控开关及所述第五可控开关的输入端均连接开启电压端，所述第五可控开关的输出端连接一扫描线及所述输出模块，所述第一电容的一端连接所述第五可控开关的输入端，所述第一电容的另一端连接所述第五可控开关的控制端，所述第四可控开关的控制端连接所述上级时钟信号，所述第四可控开关的输入端连接关闭电压端，所述第四可控开关的输出端连接所述第三可控开关的输出端。
  14. 根据权利要求13所述的平面显示装置，其中，所述输出模块包括第六可控开关及第二电容，所述第六可控开关的控制端连接所述第二电容的第一端，所述第二电容的第二端连接所述第五可控开关的输出端、所述扫描线及所述第六可控开关的输出端，所述第六可控开关的输入端连接本级时钟信号。
  15. 根据权利要求14所述的平面显示装置，其中，还包括稳压模块，用于稳定电压及防止所述上拉维持模块漏电，所述稳压模块包括第七可控开关，所述第七可控开关的控制端连接所述第四可控开关的输入端及所述关闭电压，所述第七可控开关的输入端连接所述第二可控开关的输出端、所述第一可控开关的输出端及所述第三可控开关的控制端，所述第七可控开关的输出端连接所述第六可控开关的控制端及所述第二电容的第一端。
  16. 根据权利要求15所述的平面显示装置，其中，还包括上拉辅助模块，用于防止所述上拉维持模块在对所述输出模块中的上拉控制信号点充电过程中漏电，所述上拉辅助模块包括第八可控开关，所述第八可控开关的控制端连接所述第一可控开关的输入端，所述第八可控开关的输入端连接所述第二可控开关的输入端、所述第三可控开关的输入端、所述第五可控开关的输入端及所述开启电压端，所述第八可控开关的输出端连接所述第二可控开关的控制端。
  17. 根据权利要求16所述的平面显示装置，其中，所述正反向扫描模块包括第九可控开关、第十可控开关、第十一可控开关及第十二可控开关，所述第九可控开关的控制端连接第一扫描控制电压，所述第九可控开关的输入端连接一下级扫描信号，所述第九可控开关的输出端连接所述输入模块；所述第十可控开关的控制端连接第二扫描控制电压，所述第十可控开关的输入端连接所述上级扫描信号，所述第十可控开关的输出端连接所述第九可控开关的输出端；所述第十一可控开关的控制端连接所述第一扫描控制电压，所述第十一可控开关的输入端连接第三下级时钟信号，所述第十一可控开关的输出端连接所述上拉维持模块；所述第十二可控开关的控制端连接所述第二扫描控制电压，所述第十二可控开关的输入端连接第二下级时钟信号，所述第十二可控开关的输出端连接所述第十一可控开关的输出端；
    所述输入单元包括第十三可控开关，所述第十三可控开关的控制端连接第一下级时钟信号，所述第十三可控开关的输入端连接所述第九可控开关的输出端，所述第十三可控开关的输出端连接所述控制模块中第一可控开关的输入端；
    所述处理模块包括第十四可控开关，所述第十四可控开关的控制端连接下级上拉控制信号点，所述第十四可控开关的输入端连接所述第一可控开关的输入端，所述第十四可控开关的输出端连接所述第一可控开关的输出端及所述第二可控开关的输出端。
  18. 根据权利要求17所述的平面显示装置，其中，所述第一至所述第十四可控开关均为PMOS型薄膜晶体管或者NMOS型薄膜晶体管。
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