WO2017124603A1 - 低温多晶硅tft基板的制作方法及低温多晶硅tft基板 - Google Patents

低温多晶硅tft基板的制作方法及低温多晶硅tft基板 Download PDF

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WO2017124603A1
WO2017124603A1 PCT/CN2016/074500 CN2016074500W WO2017124603A1 WO 2017124603 A1 WO2017124603 A1 WO 2017124603A1 CN 2016074500 W CN2016074500 W CN 2016074500W WO 2017124603 A1 WO2017124603 A1 WO 2017124603A1
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polysilicon
layer
insulating layer
gate
segment
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French (fr)
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张占东
汤富雄
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
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    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
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    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H10D86/0227—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials using structural arrangements to control crystal growth, e.g. placement of grain filters
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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a low temperature polysilicon TFT substrate and a low temperature polysilicon TFT substrate.
  • Low Temperature Poly-silicon (LTPS) technology is a manufacturing technology of a new generation of TFT substrates.
  • the low-temperature polysilicon display has a fast response speed and high brightness, high resolution and low power consumption.
  • Poly-Si has excellent electrical properties and has good driving ability for Active-matrix Organic Light Emitting Diode (AMOLED). Therefore, AMOLED display backplanes based on low temperature polysilicon technology are currently widely used.
  • Excimer Laser Annealing (ELA) technology is a key technology in the LTPS process, which uses laser transient pulses to illuminate the amorphous silicon surface, dissolve it and recrystallize it to form low temperature polysilicon.
  • the driving TFT requires a high electron mobility, so a relatively large crystal lattice is required, and the display TFT needs to have sufficient electron mobility and current uniformity, so that the OLED device can uniformly emit light.
  • FIG. 1 to FIG. 4 are schematic diagrams of a method for fabricating a conventional low-temperature polysilicon TFT substrate, the method comprising:
  • Step 1 providing a substrate 100, the substrate 100 includes a driving area and a display area; depositing a buffer layer 200 on the substrate 100, depositing an amorphous silicon layer 300 on the buffer layer 200;
  • Step 2 the amorphous silicon layer 300 is subjected to excimer laser annealing treatment, and the amorphous silicon layer 300 is crystallized into a polysilicon layer 400;
  • Step 3 the polysilicon layer 400 is patterned to form a first polysilicon segment 410 in the driving region, and a second polysilicon segment 420 located in the display region;
  • Step 4 sequentially forming a gate insulating layer 500 on the buffer layer 200, the first polysilicon segment 410, and the second polysilicon segment 420, and first gates 510 respectively located in the driving region and the display region And a second gate 520, an interlayer insulating layer 600 on the gate insulating layer 500 and the first gate 510 and the second gate 520, and a first source located in the driving region and the display region, respectively a drain 710 and a second source/drain 720;
  • the gate insulating layer 400 and the interlayer insulating layer 600 correspond to the first polysilicon segment 410, A first via 610 and a second via 620 are respectively formed on the second polysilicon section 420.
  • the first source/drain 710 and the second source/drain 720 are respectively via the first via 610.
  • the second via 620 is in contact with the first polysilicon segment 410 and the second polysilicon segment 420.
  • the current ELA crystallization technique cannot effectively control the uniformity of the crystal lattice and the crystal lattice direction, so the crystallization condition is uneven in the distribution of the entire substrate, resulting in uneven display effect.
  • An object of the present invention is to provide a method for fabricating a low-temperature polysilicon TFT substrate, such that crystals of polycrystalline silicon in a driving region and a display region are different, and polycrystalline silicon having a larger lattice size is formed in the driving region to improve electron mobility; In the crystallization process, the chipping is realized, and the polycrystalline silicon having a smaller lattice size is formed, the grain boundary uniformity is ensured, and the uniformity of the current is improved, thereby satisfying the electrical requirements of different TFTs and improving the uniformity of the OLED light emission.
  • Another object of the present invention is to provide a low-temperature polysilicon TFT substrate, wherein there is a difference in crystallinity of the polysilicon in the driving region and the display region, the polycrystalline silicon lattice size of the driving region is large, and the electron mobility is high; the display region realizes fragmentation, polycrystalline silicon crystal
  • the grid size is small, and the uniformity of current is good, which can meet the electrical requirements of different TFTs and improve the uniformity of OLED illumination.
  • the present invention provides a method for fabricating a low temperature polysilicon TFT substrate, comprising the following steps:
  • Step 1 providing a substrate, the substrate includes a driving area and a display area; depositing a heat dissipation layer on the substrate;
  • Step 2 patterning the heat dissipation layer to remove a heat dissipation layer located in the driving region to form a heat dissipation portion located in the display region;
  • Step 3 depositing a buffer layer on the substrate and the heat dissipation section, and depositing an amorphous silicon layer on the buffer layer;
  • Step 4 performing an excimer laser annealing treatment on the amorphous silicon layer to convert the amorphous silicon layer into a polysilicon layer;
  • Step 5 performing a patterning process on the polysilicon layer to form a first polysilicon segment located in the driving region and a second polysilicon segment located in the display region;
  • Step 6 Form a gate insulating layer on the buffer layer, the first polysilicon segment, and the second polysilicon segment;
  • Step 7 deposit a first metal layer on the gate insulating layer, and feed the first metal layer Row patterning processing, respectively forming a first gate and a second gate on the first polysilicon segment and the second polysilicon segment;
  • Step 8 depositing an interlayer insulating layer on the gate insulating layer, the first gate, and the second gate; respectively corresponding to the first polycrystal on the gate insulating layer and the interlayer insulating layer Forming a first via hole and a second via hole above the silicon segment and the second polysilicon segment;
  • Step 9 depositing a second metal layer on the interlayer insulating layer, and patterning the second metal layer to form a first source/drain located in the driving region and located in the display a second source/drain of the region;
  • the first source/drain and the second source/drain are in contact with the first polysilicon segment and the second polysilicon segment via the first via and the second via, respectively.
  • the lattice size in the first polysilicon segment is larger than the lattice size in the second polysilicon segment.
  • the substrate is a glass substrate; the buffer layer, the gate insulating layer, and the interlayer insulating layer are made of silicon nitride, silicon oxide, or a combination of the two; the first gate and the second gate,
  • the material of the first source/drain and the second source/drain is a stacked combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the material of the heat dissipating section is metal.
  • the invention also provides a method for fabricating another low temperature polysilicon TFT substrate, comprising the following steps:
  • Step 1 providing a substrate, the substrate includes a driving area and a display area; depositing a buffer layer on the substrate, and depositing a heat dissipation layer on the buffer layer;
  • Step 2 patterning the heat dissipation layer to remove a heat dissipation layer located in the driving region to form a heat dissipation portion located in the display region;
  • Step 3 depositing an amorphous silicon layer on the buffer layer and the heat dissipation section;
  • Step 4 performing an excimer laser annealing treatment on the amorphous silicon layer to convert the amorphous silicon layer into a polysilicon layer;
  • Step 5 performing a patterning process on the polysilicon layer to form a first polysilicon segment located in the driving region and a second polysilicon segment located in the display region;
  • Step 6 Form a gate insulating layer on the buffer layer, the first polysilicon segment, the second polysilicon segment, and the heat dissipation segment;
  • Step 7 Depositing a first metal layer on the gate insulating layer, and patterning the first metal layer to form a first polysilicon segment and a second polysilicon segment respectively. a first gate and a second gate;
  • Step 8 depositing an interlayer insulating layer on the gate insulating layer, the first gate, and the second gate; respectively corresponding to the first polycrystal on the gate insulating layer and the interlayer insulating layer Forming a first via hole and a second via hole above the silicon segment and the second polysilicon segment;
  • Step 9 depositing a second metal layer on the interlayer insulating layer, and patterning the second metal layer to form a first source/drain located in the driving region and located in the display a second source/drain of the region;
  • the first source/drain and the second source/drain are in contact with the first polysilicon segment and the second polysilicon segment via the first via and the second via, respectively.
  • the lattice size in the first polysilicon segment is larger than the lattice size in the second polysilicon segment.
  • the substrate is a glass substrate; the buffer layer, the gate insulating layer, and the interlayer insulating layer are made of silicon nitride, silicon oxide, or a combination of the two; the first gate and the second gate,
  • the material of the first source/drain and the second source/drain is a stacked combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the material of the heat dissipating section is a non-conductive metal oxide.
  • the present invention also provides a low temperature polysilicon TFT substrate comprising a driving region and a display region, the driving region comprising a substrate, a buffer layer disposed on the substrate, a first polysilicon segment disposed on the buffer layer, a gate insulating layer disposed on the buffer layer and the first polysilicon segment, and a first gate disposed on the gate insulating layer corresponding to the first polysilicon segment, disposed on the gate a first insulating layer and an interlayer insulating layer on the first gate; and a first source/drain provided on the interlayer insulating layer;
  • the display area includes a substrate, a buffer layer disposed on the substrate, a second polysilicon segment disposed on the buffer layer, and a gate insulating layer disposed on the buffer layer and the second polysilicon segment a layer, a second gate disposed on the gate insulating layer above the second polysilicon segment, an interlayer insulating layer disposed on the gate insulating layer and the second gate, and a second source/drain on the interlayer insulating layer;
  • a first via hole is formed on the interlayer insulating layer and the gate insulating layer of the driving region corresponding to the first polysilicon segment, and the first source/drain is connected to the first via via
  • the first polysilicon segments are in contact;
  • a second via hole is formed on the interlayer insulating layer and the gate insulating layer of the display region corresponding to the second polysilicon segment, and the second source/drain is connected to the second via
  • the second polysilicon segments are in contact;
  • a heat dissipating portion is disposed between the substrate and the buffer layer or between the buffer layer and the second polysilicon segment under the second polysilicon segment.
  • the lattice size in the first polysilicon segment is larger than the lattice size in the second polysilicon segment;
  • the substrate is a glass substrate;
  • the buffer layer, the gate insulating layer, and the material of the interlayer insulating layer a silicon nitride, a silicon oxide, or a combination of the two;
  • the first gate, the second gate, the first source/drain, and the second source/drain are made of molybdenum, titanium, aluminum, or copper.
  • the heat sink segment is made of a metal or a non-conductive metal oxide.
  • the smaller polysilicon ensures the uniformity of the grain boundary and improves the uniformity of the current, thereby satisfying the electrical requirements of different TFTs and improving the uniformity of OLED illumination.
  • step 1 is a schematic diagram of step 1 of a method for fabricating a conventional low-temperature polysilicon TFT substrate
  • FIG. 2 is a schematic view showing a step 2 of a method for fabricating a conventional low-temperature polysilicon TFT substrate
  • FIG. 3 is a schematic diagram of a step 3 of a method for fabricating a conventional low-temperature polysilicon TFT substrate
  • FIG. 4 is a schematic diagram of a step 4 of a method for fabricating a conventional low-temperature polysilicon TFT substrate
  • FIG. 5 is a schematic flow chart of a method for fabricating a low temperature polysilicon TFT substrate according to the present invention
  • step 1 is a schematic diagram of step 1 of the method for fabricating the low temperature polysilicon TFT substrate of FIG. 5;
  • step 2 is a schematic diagram of step 2 of the method for fabricating the low temperature polysilicon TFT substrate of FIG. 5;
  • step 3 is a schematic diagram of step 3 of the method for fabricating the low temperature polysilicon TFT substrate of FIG. 5;
  • step 4 is a schematic diagram of step 4 of the method for fabricating the low temperature polysilicon TFT substrate of FIG. 5;
  • step 5 is a schematic diagram of step 5 of the method for fabricating the low temperature polysilicon TFT substrate of FIG. 5;
  • step 6 is a schematic diagram of step 6 of the method for fabricating the low temperature polysilicon TFT substrate of FIG. 5;
  • step 7 is a schematic diagram of step 7 of the method for fabricating the low temperature polysilicon TFT substrate of FIG. 5;
  • step 8 is a schematic diagram of step 8 of the method for fabricating the low temperature polysilicon TFT substrate of FIG. 5;
  • FIG. 14 is a schematic view showing a step 9 of the method for fabricating the low-temperature polysilicon TFT substrate of FIG. 5 and a cross-sectional structural view of the first embodiment of the low-temperature polysilicon TFT substrate of the present invention
  • 15 is a schematic flow chart of another method for fabricating a low temperature polysilicon TFT substrate according to the present invention.
  • step 1 is a schematic diagram of step 1 of the method for fabricating the low temperature polysilicon TFT substrate of FIG. 15;
  • step 2 is a schematic diagram of step 2 of the method for fabricating the low temperature polysilicon TFT substrate of FIG. 15;
  • step 3 is a schematic diagram of step 3 of the method for fabricating the low temperature polysilicon TFT substrate of FIG. 15;
  • step 4 is a schematic diagram of step 4 of the method for fabricating the low temperature polysilicon TFT substrate of FIG. 15;
  • step 5 is a schematic diagram of step 5 of the method for fabricating the low temperature polysilicon TFT substrate of FIG. 15;
  • 21 is a schematic diagram of step 6 of the method for fabricating the low temperature polysilicon TFT substrate of FIG. 15;
  • step 7 is a schematic diagram of step 7 of the method for fabricating the low temperature polysilicon TFT substrate of FIG. 15;
  • step 8 is a schematic diagram of step 8 of the method for fabricating the low temperature polysilicon TFT substrate of FIG. 15;
  • Figure 24 is a schematic view showing a step 9 of the method for fabricating the low-temperature polysilicon TFT substrate of Figure 15 and a cross-sectional structural view of a second embodiment of the low-temperature polysilicon TFT substrate of the present invention.
  • the present invention first provides a method for fabricating a low temperature polysilicon TFT substrate, comprising the following steps:
  • Step 1 As shown in FIG. 6, a substrate 1 is provided.
  • the substrate 1 includes a driving area and a display area.
  • a heat dissipation layer 10 is deposited on the substrate 1.
  • the substrate 1 is a glass substrate.
  • Step 2 As shown in FIG. 7, the heat dissipation layer 10 is patterned to remove the heat dissipation layer located in the driving region, and the heat dissipation portion 11 located in the display region is formed.
  • the material of the heat dissipating section 11 is a metal such as molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu) or the like.
  • Step 3 as shown in FIG. 8, a buffer layer 2 is deposited on the substrate 1 and the heat dissipation section 11, and an amorphous silicon layer 3 is deposited on the buffer layer 2.
  • Step 4 as shown in FIG. 9, the amorphous silicon layer 3 is subjected to an excimer laser annealing treatment to convert the amorphous silicon layer 3 into a polysilicon layer 30.
  • Step 5 As shown in FIG. 10, the polysilicon layer 30 is patterned to form a first polysilicon segment 31 located in the driving region and a second polysilicon segment 32 located in the display region.
  • the lattice size in the first polysilicon segment 31 is larger than the lattice size in the second polysilicon segment 32. Since there is no heat dissipation layer under the first polysilicon segment 31, polycrystalline silicon having a larger lattice size is formed in the driving region; and the heat dissipation portion 11 is disposed under the second polysilicon segment 32, which dissipates heat quickly and keeps heat. The effect is poor, so that the crystallizing can be realized in the crystallization process of the display region, and the polycrystalline silicon having a smaller lattice size is formed, the grain boundary uniformity is ensured, and the uniformity of the current is improved.
  • Step 6 As shown in FIG. 11, a gate insulating layer 4 is formed on the buffer layer 2, the first polysilicon segment 31, and the second polysilicon segment 32.
  • Step 7 as shown in FIG. 12, depositing a first metal layer on the gate insulating layer 4, and patterning the first metal layer to form the first polysilicon segment 31, First The first gate 51 and the second gate 52 on the second polysilicon section 32.
  • Step 8 as shown in FIG. 13, depositing an interlayer insulating layer 6 on the gate insulating layer 4, the first gate 51, and the second gate 52; between the gate insulating layer 4 and the interlayer A first via 61 and a second via 62 are formed on the insulating layer 6 corresponding to the first polysilicon segment 31 and the second polysilicon segment 32, respectively.
  • Step 9 as shown in FIG. 14, depositing a second metal layer on the interlayer insulating layer 6, and patterning the second metal layer to form a first source/drain located in the driving region A pole 71 and a second source/drain 72 located in the display area.
  • the first source/drain 71 and the second source/drain 72 are respectively connected to the first polysilicon segment 31 and the second polysilicon segment 32 via the first via 61 and the second via 62. Contact.
  • the material of the buffer layer 2, the gate insulating layer 4, and the interlayer insulating layer 6 is silicon nitride, silicon oxide, or a combination of the two.
  • the materials of the first gate 51, the second gate 52, the first source/drain 71, and the second source/drain 72 are one or more of molybdenum, titanium, aluminum, and copper. Stack combination.
  • the present invention further provides another method for fabricating a low temperature polysilicon TFT substrate, comprising the following steps:
  • Step 1 As shown in FIG. 16, a substrate 1 is provided.
  • the substrate 1 includes a driving area and a display area.
  • a buffer layer 2 is deposited on the substrate 1, and a heat dissipation layer 10 is deposited on the buffer layer 2.
  • the substrate 1 is a glass substrate.
  • Step 2 As shown in FIG. 17, the heat dissipation layer 10 is patterned to remove the heat dissipation layer 10 located in the drive region, and the heat dissipation portion 11 located in the display region is formed.
  • the material of the heat dissipating section 11 is a non-conductive metal oxide such as alumina.
  • Step 3 As shown in FIG. 18, an amorphous silicon layer 3 is deposited on the buffer layer 2 and the heat dissipation portion 11.
  • Step 4 As shown in FIG. 19, the amorphous silicon layer 3 is subjected to an excimer laser annealing treatment to convert the amorphous silicon layer 3 into a polysilicon layer 30.
  • Step 5 As shown in FIG. 20, the polysilicon layer 30 is patterned to form a first polysilicon segment 31 located in the driving region and a second polysilicon segment 32 located in the display region.
  • the lattice size in the first polysilicon segment 31 is larger than the lattice size in the second polysilicon segment 32. Since there is no heat dissipation layer under the first polysilicon segment 31, the heat preservation effect is better, so polycrystalline silicon having a larger lattice size is formed in the driving region; and the heat dissipation portion 11 is disposed under the second polysilicon segment 32. The heat dissipation is faster, so that the crystallizing can be realized in the crystallization process of the display region, and the polycrystalline silicon having a smaller lattice size is formed, which ensures the uniformity of the grain boundary and improves the uniformity of the current.
  • Step 6 as shown in FIG. 21, in the buffer layer 2, the first polysilicon segment 31, and the second polycrystal A gate insulating layer 4 is formed on the silicon segment 32 and the heat dissipation portion 11.
  • Step 7 depositing a first metal layer on the gate insulating layer 4, and patterning the first metal layer to form the first polysilicon segment 31, The first gate 51 and the second gate 52 on the second polysilicon section 32.
  • Step 8 as shown in FIG. 23, depositing an interlayer insulating layer 6 on the gate insulating layer 4, the first gate 51, and the second gate 52; between the gate insulating layer 4 and the interlayer A first via 61 and a second via 62 are formed on the insulating layer 6 corresponding to the first polysilicon segment 31 and the second polysilicon segment 32, respectively.
  • Step 9 As shown in FIG. 24, a second metal layer is deposited on the interlayer insulating layer 6, and the second metal layer is patterned to form a first source/drain located in the driving region. A pole 71 and a second source/drain 72 located in the display area.
  • the first source/drain 71 and the second source/drain 72 are respectively connected to the first polysilicon segment 31 and the second polysilicon segment 32 via the first via 61 and the second via 62. Contact.
  • the material of the buffer layer 2, the gate insulating layer 4, and the interlayer insulating layer 6 is silicon nitride, silicon oxide, or a combination of the two.
  • the materials of the first gate 51, the second gate 52, the first source/drain 71, and the second source/drain 72 are one or more of molybdenum, titanium, aluminum, and copper. Stack combination.
  • the present invention further provides a low temperature polysilicon TFT substrate, comprising a driving area and a display area, the driving area comprising a substrate 1, a buffer layer 2 disposed on the substrate 1, and being disposed in the a first polysilicon segment 31 on the buffer layer 2, a gate insulating layer 4 disposed on the buffer layer 2 and the first polysilicon segment 31, and corresponding to the first polysilicon segment 31 a first gate 51 on the gate insulating layer 4, an interlayer insulating layer 6 provided on the gate insulating layer 4 and the first gate 51, and a portion provided on the interlayer insulating layer 6. a source/drain 71;
  • the display area includes a substrate 1, a buffer layer 2 disposed on the substrate 1, a second polysilicon segment 32 disposed on the buffer layer 2, and a buffer layer 2 and a second polysilicon. a gate insulating layer 4 on the segment 32, a second gate electrode 52 corresponding to the gate insulating layer 4 corresponding to the second polysilicon segment 32, and the gate insulating layer 4 and the second layer An interlayer insulating layer 6 on the gate 52, and a second source/drain 72 provided on the interlayer insulating layer 6;
  • a first via 61 is formed on the interlayer insulating layer 6 and the gate insulating layer 4 of the driving region corresponding to the first polysilicon segment 31, and the first source/drain 71 passes through the first a via 61 is in contact with the first polysilicon segment 31;
  • a second via 62 is formed on the interlayer insulating layer 6 and the gate insulating layer 4 of the display region corresponding to the second polysilicon segment 32, and the second source/drain 72 is via the second a via 62 is in contact with the second polysilicon segment 32;
  • a heat dissipating segment 11 is disposed between the substrate 1 and the buffer layer 2 or between the buffer layer 2 and the second polysilicon segment 32 under the second polysilicon segment 32.
  • FIG. 14 is a cross-sectional structural view of a first embodiment of a low-temperature polysilicon TFT substrate according to the present invention, wherein in the display region, the second polysilicon segment 32 is below the substrate 1 and the buffer layer.
  • a heat dissipating section 11 is disposed between the two, and the material of the heat dissipating section 11 is a metal such as molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu) or the like.
  • FIG. 24 is a cross-sectional structural view of a second embodiment of a low temperature polysilicon TFT substrate according to the present invention, wherein the display region has a second polysilicon segment 32 below the buffer layer 2 and A heat dissipating section 11 is disposed between the two polysilicon sections 32.
  • the material of the heat dissipating section 11 is a non-conductive metal oxide such as alumina.
  • the lattice size in the first polysilicon segment 31 is larger than the lattice size in the second polysilicon segment 32.
  • the substrate 1 is a glass substrate.
  • the material of the buffer layer 2, the gate insulating layer 4, and the interlayer insulating layer 6 is silicon nitride, silicon oxide, or a combination of the two.
  • the materials of the first gate 51, the second gate 52, the first source/drain 71, and the second source/drain 72 are one or more of molybdenum, titanium, aluminum, and copper. Stack combination.
  • the method for fabricating the low-temperature polysilicon TFT substrate of the present invention and the low-temperature polysilicon TFT substrate are subjected to excimer laser retreat treatment on the amorphous silicon layer by previously providing a heat dissipation layer under the amorphous silicon layer.
  • the crystals of the polycrystalline silicon in the driving region and the display region are different, and polycrystalline silicon having a larger lattice size is formed in the driving region, thereby improving electron mobility; in the crystallization process of the display region, fragmentation is performed to form a lattice size.
  • the small polysilicon ensures the uniformity of the grain boundary and improves the uniformity of the current, thereby satisfying the electrical requirements of different TFTs and improving the uniformity of OLED illumination.

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Abstract

提供了一种低温多晶硅TFT基板的制作方法及低温多晶硅TFT基板，通过在非晶硅层（3）的下方预先设置一层散热层（10），从而在对非晶硅层（3）进行准分子激光退过处理后可使得驱动区域和显示区域的多晶硅的结晶存在差异，在驱动区域形成晶格尺寸较大的多晶硅，提高了电子迁移率；在显示区域的晶化过程中实现碎晶，形成晶格尺寸较小的多晶硅，保证了晶界均一性，提高了电流的均一性，从而满足了不同TFT的电性要求，提高了OLED发光的均一性。

Description

低温多晶硅TFT基板的制作方法及低温多晶硅TFT基板 技术领域
本发明涉及显示技术领域，尤其涉及一种低温多晶硅TFT基板的制作方法及低温多晶硅TFT基板。
背景技术
低温多晶硅(Low Temperature Poly-silicon，LTPS)技术是新一代TFT基板的制造技术，低温多晶硅显示器反应速度较快，且有高亮度、高解析度与低耗电量等优点。多晶硅(Poly-Si)具有优异的电学性能，对于有源矩阵有机发光二极体(Active-matrix Organic Light Emitting Diode，AMOLED)具有较好的驱动能力。因此，基于低温多晶硅技术的AMOLED显示背板目前被广泛使用。
准分子激光退火处理(Excimer Laser Annealing，ELA)技术是LTPS制程中的关键技术，该技术利用激光的瞬间脉冲照射到非晶硅表面，使其溶化并重新结晶形成低温多晶硅。
因为AMOLED驱动需要驱动TFT和显示TFT，驱动TFT需要较高的电子迁移率，所以需要比较大的晶格，显示TFT需要有足够的电子迁移率和电流均一性，从而可以使OLED器件均匀发光。
请参阅图1至图4，为一种现有的低温多晶硅TFT基板的制作方法的示意图，该方法包括：
步骤1、提供基板100，所述基板100包括驱动区域与显示区域；在所述基板100上沉积缓冲层200，在所述缓冲层200上沉积非晶硅层300；
步骤2、对所述非晶硅层300进行准分子激光退火处理，使所述非晶硅层300结晶转变为多晶硅层400；
步骤3、对所述多晶硅层400进行图案化处理，形成位于所述驱动区域的第一多晶硅段410、及位于所述显示区域的第二多晶硅段420；
步骤4、在所述缓冲层200、第一多晶硅段410、及第二多晶硅段420上依次形成栅极绝缘层500、分别位于所述驱动区域与显示区域的第一栅极510与第二栅极520、位于所述栅极绝缘层500及第一栅极510与第二栅极520上的层间绝缘层600、及分别位于所述驱动区域与显示区域的第一源/漏极710与第二源/漏极720；
所述栅极绝缘层400与层间绝缘层600上对应所述第一多晶硅段410、 第二多晶硅段420的上方分别形成有第一过孔610、第二过孔620；所述第一源/漏极710、第二源/漏极720分别经由所述第一过孔610、第二过孔620与所述第一多晶硅段410、第二多晶硅段420相接触。
然而目前的ELA结晶技术对于晶格的均一性和晶格结晶方向不能做到有效控制，所以结晶状况在整个基板的分布上很不均匀，造成显示效果的不均一。
因此，有必要提供一种低温多晶硅TFT基板的制作方法及低温多晶硅TFT基板，以解决上述问题。
发明内容
本发明的目的在于提供一种低温多晶硅TFT基板的制作方法，使得驱动区域和显示区域的多晶硅的结晶存在差异，在驱动区域形成晶格尺寸较大的多晶硅，提高电子迁移率；在显示区域的晶化过程中实现碎晶，形成晶格尺寸较小的多晶硅，保证晶界均一性，提高电流的均一性，从而满足不同TFT的电性要求，提高OLED发光的均一性。
本发明的目的还在于提供一种低温多晶硅TFT基板，驱动区域和显示区域的多晶硅的结晶存在差异，驱动区域的多晶硅晶格尺寸较大，电子迁移率较高；显示区域实现碎晶，多晶硅晶格尺寸较小，电流的均一性较好，可满足不同TFT的电性要求，提高OLED发光的均一性。
为实现上述目的，本发明提供一种低温多晶硅TFT基板的制作方法，包括如下步骤：
步骤1、提供基板，所述基板包括驱动区域与显示区域；在所述基板上沉积散热层；
步骤2、对所述散热层进行图案化处理，除去位于所述驱动区域的散热层，形成位于所述显示区域的散热段；
步骤3、在所述基板与散热段上沉积缓冲层，在所述缓冲层上沉积非晶硅层；
步骤4、对所述非晶硅层进行准分子激光退火处理，使所述非晶硅层结晶转变为多晶硅层；
步骤5、对所述多晶硅层进行图案化处理，形成位于所述驱动区域的第一多晶硅段、及位于所述显示区域的第二多晶硅段；
步骤6、在所述缓冲层、第一多晶硅段、及第二多晶硅段上形成栅极绝缘层；
步骤7、在所述栅极绝缘层上沉积第一金属层，并对所述第一金属层进 行图案化处理，分别形成位于所述第一多晶硅段、第二多晶硅段上的第一栅极、第二栅极；
步骤8、在所述栅极绝缘层、第一栅极、及第二栅极上沉积层间绝缘层；在所述栅极绝缘层、及层间绝缘层上分别对应所述第一多晶硅段、第二多晶硅段上方形成第一过孔、第二过孔；
步骤9、在所述层间绝缘层上沉积第二金属层，并对所述第二金属层进行图案化处理，分别形成位于所述驱动区域的第一源/漏极、及位于所述显示区域的第二源/漏极；
所述第一源/漏极、第二源/漏极分别经由所述第一过孔、第二过孔与所述第一多晶硅段、第二多晶硅段相接触。
所述步骤5中，所述第一多晶硅段中的晶格尺寸大于第二多晶硅段中的晶格尺寸。
所述基板为玻璃基板；所述缓冲层、栅极绝缘层、及层间绝缘层的材料为氮化硅、氧化硅、或二者的组合；所述第一栅极、第二栅极、第一源/漏极、第二源/漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
所述散热段的材料为金属。
本发明还提供另一种低温多晶硅TFT基板的制作方法，包括如下步骤：
步骤1、提供基板，所述基板包括驱动区域与显示区域；在所述基板上沉积缓冲层，在所述缓冲层上沉积散热层；
步骤2、对所述散热层进行图案化处理，除去位于所述驱动区域的散热层，形成位于所述显示区域的散热段；
步骤3、在所述缓冲层、及散热段上沉积非晶硅层；
步骤4、对所述非晶硅层进行准分子激光退火处理，使所述非晶硅层结晶转变为多晶硅层；
步骤5、对所述多晶硅层进行图案化处理，形成位于所述驱动区域的第一多晶硅段、及位于所述显示区域的第二多晶硅段；
步骤6、在所述缓冲层、第一多晶硅段、第二多晶硅段、及散热段上形成栅极绝缘层；
步骤7、在所述栅极绝缘层上沉积第一金属层，并对所述第一金属层进行图案化处理，分别形成位于所述第一多晶硅段、第二多晶硅段上的第一栅极、第二栅极；
步骤8、在所述栅极绝缘层、第一栅极、及第二栅极上沉积层间绝缘层；在所述栅极绝缘层、及层间绝缘层上分别对应所述第一多晶硅段、第二多晶硅段上方形成第一过孔、第二过孔；
步骤9、在所述层间绝缘层上沉积第二金属层，并对所述第二金属层进行图案化处理，分别形成位于所述驱动区域的第一源/漏极、及位于所述显示区域的第二源/漏极；
所述第一源/漏极、第二源/漏极分别经由所述第一过孔、第二过孔与所述第一多晶硅段、第二多晶硅段相接触。
所述步骤5中，所述第一多晶硅段中的晶格尺寸大于第二多晶硅段中的晶格尺寸。
所述基板为玻璃基板；所述缓冲层、栅极绝缘层、及层间绝缘层的材料为氮化硅、氧化硅、或二者的组合；所述第一栅极、第二栅极、第一源/漏极、第二源/漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
所述散热段的材料为不导电的金属氧化物。
本发明还提供一种低温多晶硅TFT基板，包括驱动区域与显示区域，所述驱动区域包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的第一多晶硅段、设于所述缓冲层及第一多晶硅段上的栅极绝缘层、对应所述第一多晶硅段上方设于所述栅极绝缘层上的第一栅极、设于所述栅极绝缘层及第一栅极上的层间绝缘层、及设于所述层间绝缘层上的第一源/漏极；
所述显示区域包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的第二多晶硅段、设于所述缓冲层及第二多晶硅段上的栅极绝缘层、对应所述第二多晶硅段上方设于所述栅极绝缘层上的第二栅极、设于所述栅极绝缘层及第二栅极上的层间绝缘层、及设于所述层间绝缘层上的第二源/漏极；
所述驱动区域的层间绝缘层及栅极绝缘层上对应所述第一多晶硅段上方形成有第一过孔，所述第一源/漏极经由所述第一过孔与所述第一多晶硅段相接触；
所述显示区域的层间绝缘层及栅极绝缘层上对应所述第二多晶硅段上方形成有第二过孔，所述第二源/漏极经由所述第二过孔与所述第二多晶硅段相接触；
所述显示区域中，所述第二多晶硅段的下方于所述基板与缓冲层之间或所述缓冲层与第二多晶硅段之间设有散热段。
所述第一多晶硅段中的晶格尺寸大于第二多晶硅段中的晶格尺寸；所述基板为玻璃基板；所述缓冲层、栅极绝缘层、及层间绝缘层的材料为氮化硅、氧化硅、或二者的组合；所述第一栅极、第二栅极、第一源/漏极、第二源/漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；所述散热段的材料为金属或不导电的金属氧化物。
本发明的有益效果：本发明的低温多晶硅TFT基板的制作方法及低温多晶硅TFT基板，通过在非晶硅层的下方预先设置一层散热层，从而在对非晶硅层进行准分子激光退过处理后可使得驱动区域和显示区域的多晶硅的结晶存在差异，在驱动区域形成晶格尺寸较大的多晶硅，提高了电子迁移率；在显示区域的晶化过程中实现碎晶，形成晶格尺寸较小的多晶硅，保证了晶界均一性，提高了电流的均一性，从而满足了不同TFT的电性要求，提高了OLED发光的均一性。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为一种现有的低温多晶硅TFT基板的制作方法的步骤1的示意图；
图2为一种现有的低温多晶硅TFT基板的制作方法的步骤2的示意图；
图3为一种现有的低温多晶硅TFT基板的制作方法的步骤3的示意图；
图4为一种现有的低温多晶硅TFT基板的制作方法的步骤4的示意图；
图5为本发明的一种低温多晶硅TFT基板的制作方法的示意流程图；
图6为图5的低温多晶硅TFT基板的制作方法的步骤1的示意图；
图7为图5的低温多晶硅TFT基板的制作方法的步骤2的示意图；
图8为图5的低温多晶硅TFT基板的制作方法的步骤3的示意图；
图9为图5的低温多晶硅TFT基板的制作方法的步骤4的示意图；
图10为图5的低温多晶硅TFT基板的制作方法的步骤5的示意图；
图11为图5的低温多晶硅TFT基板的制作方法的步骤6的示意图；
图12为图5的低温多晶硅TFT基板的制作方法的步骤7的示意图；
图13为图5的低温多晶硅TFT基板的制作方法的步骤8的示意图；
图14为图5的低温多晶硅TFT基板的制作方法的步骤9的示意图暨本发明的低温多晶硅TFT基板的第一实施例的剖面结构示意图；
图15为本发明的另一种低温多晶硅TFT基板的制作方法的示意流程图；
图16为图15的低温多晶硅TFT基板的制作方法的步骤1的示意图；
图17为图15的低温多晶硅TFT基板的制作方法的步骤2的示意图；
图18为图15的低温多晶硅TFT基板的制作方法的步骤3的示意图；
图19为图15的低温多晶硅TFT基板的制作方法的步骤4的示意图；
图20为图15的低温多晶硅TFT基板的制作方法的步骤5的示意图；
图21为图15的低温多晶硅TFT基板的制作方法的步骤6的示意图；
图22为图15的低温多晶硅TFT基板的制作方法的步骤7的示意图；
图23为图15的低温多晶硅TFT基板的制作方法的步骤8的示意图；
图24为图15的低温多晶硅TFT基板的制作方法的步骤9的示意图暨本发明的低温多晶硅TFT基板的第二实施例的剖面结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图5，本发明首先提供一种低温多晶硅TFT基板的制作方法，包括如下步骤：
步骤1、如图6所示，提供基板1，所述基板1包括驱动区域与显示区域；在所述基板1上沉积散热层10。
具体地，所述基板1为玻璃基板。
步骤2、如图7所示，对所述散热层10进行图案化处理，除去位于所述驱动区域的散热层，形成位于所述显示区域的散热段11。
具体地，所述散热段11的材料为金属，如钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)等。
步骤3、如图8所示，在所述基板1与散热段11上沉积缓冲层2，在所述缓冲层2上沉积非晶硅层3。
步骤4、如图9所示，对所述非晶硅层3进行准分子激光退火处理，使所述非晶硅层3结晶转变为多晶硅层30。
步骤5、如图10所示，对所述多晶硅层30进行图案化处理，形成位于所述驱动区域的第一多晶硅段31、及位于所述显示区域的第二多晶硅段32。
具体地，所述第一多晶硅段31中的晶格尺寸大于第二多晶硅段32中的晶格尺寸。由于所述第一多晶硅段31下方没有散热层，因此会在驱动区域形成晶格尺寸较大的多晶硅；而所述第二多晶硅段32下方具有散热段11，散热较快，保温效果差，因此可以在显示区域的晶化过程中实现碎晶，形成晶格尺寸较小的多晶硅，保证了晶界均一性，提高了电流的均一性。
步骤6、如图11所示，在所述缓冲层2、第一多晶硅段31、及第二多晶硅段32上形成栅极绝缘层4。
步骤7、如图12所示，在所述栅极绝缘层4上沉积第一金属层，并对所述第一金属层进行图案化处理，分别形成位于所述第一多晶硅段31、第 二多晶硅段32上的第一栅极51、第二栅极52。
步骤8、如图13所示，在所述栅极绝缘层4、第一栅极51、及第二栅极52上沉积层间绝缘层6；在所述栅极绝缘层4、及层间绝缘层6上分别对应所述第一多晶硅段31、第二多晶硅段32上方形成第一过孔61、第二过孔62。
步骤9、如图14所示，在所述层间绝缘层6上沉积第二金属层，并对所述第二金属层进行图案化处理，分别形成位于所述驱动区域的第一源/漏极71、及位于所述显示区域的第二源/漏极72。
所述第一源/漏极71、第二源/漏极72分别经由所述第一过孔61、第二过孔62与所述第一多晶硅段31、第二多晶硅段32相接触。
具体地，所述缓冲层2、栅极绝缘层4、及层间绝缘层6的材料为氮化硅、氧化硅、或二者的组合。
具体地，所述第一栅极51、第二栅极52、第一源/漏极71、第二源/漏极72的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
请参阅图15，本发明还提供另一种低温多晶硅TFT基板的制作方法，包括如下步骤：
步骤1、如图16所示，提供基板1，所述基板1包括驱动区域与显示区域；在所述基板1上沉积缓冲层2，在所述缓冲层2上沉积散热层10。
具体地，所述基板1为玻璃基板。
步骤2、如图17所示，对所述散热层10进行图案化处理，除去位于所述驱动区域的散热层10，形成位于所述显示区域的散热段11。
具体地，所述散热段11的材料为不导电的金属氧化物，如氧化铝。
步骤3、如图18所示，在所述缓冲层2、及散热段11上沉积非晶硅层3。
步骤4、如图19所示，对所述非晶硅层3进行准分子激光退火处理，使所述非晶硅层3结晶转变为多晶硅层30。
步骤5、如图20所示，对所述多晶硅层30进行图案化处理，形成位于所述驱动区域的第一多晶硅段31、及位于所述显示区域的第二多晶硅段32。
具体地，所述第一多晶硅段31中的晶格尺寸大于第二多晶硅段32中的晶格尺寸。由于所述第一多晶硅段31下方没有散热层，保温效果较佳，因此会在驱动区域形成晶格尺寸较大的多晶硅；而所述第二多晶硅段32下方具有散热段11，散热较快，因此可以在显示区域的晶化过程中实现碎晶，形成晶格尺寸较小的多晶硅，保证了晶界均一性，提高了电流的均一性。
步骤6、如图21所示，在所述缓冲层2、第一多晶硅段31、第二多晶 硅段32、及散热段11上形成栅极绝缘层4。
步骤7、如图22所示，在所述栅极绝缘层4上沉积第一金属层，并对所述第一金属层进行图案化处理，分别形成位于所述第一多晶硅段31、第二多晶硅段32上的第一栅极51、第二栅极52。
步骤8、如图23所示，在所述栅极绝缘层4、第一栅极51、及第二栅极52上沉积层间绝缘层6；在所述栅极绝缘层4、及层间绝缘层6上分别对应所述第一多晶硅段31、第二多晶硅段32上方形成第一过孔61、第二过孔62。
步骤9、如图24所示，在所述层间绝缘层6上沉积第二金属层，并对所述第二金属层进行图案化处理，分别形成位于所述驱动区域的第一源/漏极71、及位于所述显示区域的第二源/漏极72。
所述第一源/漏极71、第二源/漏极72分别经由所述第一过孔61、第二过孔62与所述第一多晶硅段31、第二多晶硅段32相接触。
具体地，所述缓冲层2、栅极绝缘层4、及层间绝缘层6的材料为氮化硅、氧化硅、或二者的组合。
具体地，所述第一栅极51、第二栅极52、第一源/漏极71、第二源/漏极72的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
请参阅图14与图24，本发明还提供一种低温多晶硅TFT基板，包括驱动区域与显示区域，所述驱动区域包括基板1、设于所述基板1上的缓冲层2、设于所述缓冲层2上的第一多晶硅段31、设于所述缓冲层2及第一多晶硅段31上的栅极绝缘层4、对应所述第一多晶硅段31上方设于所述栅极绝缘层4上的第一栅极51、设于所述栅极绝缘层4及第一栅极51上的层间绝缘层6、及设于所述层间绝缘层6上的第一源/漏极71；
所述显示区域包括基板1、设于所述基板1上的缓冲层2、设于所述缓冲层2上的第二多晶硅段32、设于所述缓冲层2及第二多晶硅段32上的栅极绝缘层4、对应所述第二多晶硅段32上方设于所述栅极绝缘层4上的第二栅极52、设于所述栅极绝缘层4及第二栅极52上的层间绝缘层6、及设于所述层间绝缘层6上的第二源/漏极72；
所述驱动区域的层间绝缘层6及栅极绝缘层4上对应所述第一多晶硅段31上方形成有第一过孔61，所述第一源/漏极71经由所述第一过孔61与所述第一多晶硅段31相接触；
所述显示区域的层间绝缘层6及栅极绝缘层4上对应所述第二多晶硅段32上方形成有第二过孔62，所述第二源/漏极72经由所述第二过孔62与所述第二多晶硅段32相接触；
所述显示区域中，所述第二多晶硅段32的下方于所述基板1与缓冲层2之间或所述缓冲层2与第二多晶硅段32之间设有散热段11。
请参阅图14，为本发明的低温多晶硅TFT基板的第一实施例的剖面结构示意图，其中，所述显示区域中，所述第二多晶硅段32的下方于所述基板1与缓冲层2之间设有散热段11，所述散热段11的材料为金属，如钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)等。
请参阅图24，为本发明的低温多晶硅TFT基板的第二实施例的剖面结构示意图，其中，所述显示区域中，所述第二多晶硅段32的下方于所述缓冲层2与第二多晶硅段32之间设有散热段11，所述散热段11的材料为不导电的金属氧化物，如氧化铝。
具体地，所述第一多晶硅段31中的晶格尺寸大于第二多晶硅段32中的晶格尺寸。
具体地，所述基板1为玻璃基板。
具体地，所述缓冲层2、栅极绝缘层4、及层间绝缘层6的材料为氮化硅、氧化硅、或二者的组合。
具体地，所述第一栅极51、第二栅极52、第一源/漏极71、第二源/漏极72的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
综上所述，本发明的低温多晶硅TFT基板的制作方法及低温多晶硅TFT基板，通过在非晶硅层的下方预先设置一层散热层，从而在对非晶硅层进行准分子激光退过处理后可使得驱动区域和显示区域的多晶硅的结晶存在差异，在驱动区域形成晶格尺寸较大的多晶硅，提高了电子迁移率；在显示区域的晶化过程中实现碎晶，形成晶格尺寸较小的多晶硅，保证了晶界均一性，提高了电流的均一性，从而满足了不同TFT的电性要求，提高了OLED发光的均一性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (10)

  1. 一种低温多晶硅TFT基板的制作方法，包括如下步骤：
    步骤1、提供基板，所述基板包括驱动区域与显示区域；在所述基板上沉积散热层；
    步骤2、对所述散热层进行图案化处理，除去位于所述驱动区域的散热层，形成位于所述显示区域的散热段；
    步骤3、在所述基板与散热段上沉积缓冲层，在所述缓冲层上沉积非晶硅层；
    步骤4、对所述非晶硅层进行准分子激光退火处理，使所述非晶硅层结晶转变为多晶硅层；
    步骤5、对所述多晶硅层进行图案化处理，形成位于所述驱动区域的第一多晶硅段、及位于所述显示区域的第二多晶硅段；
    步骤6、在所述缓冲层、第一多晶硅段、及第二多晶硅段上形成栅极绝缘层；
    步骤7、在所述栅极绝缘层上沉积第一金属层，并对所述第一金属层进行图案化处理，分别形成位于所述第一多晶硅段、第二多晶硅段上的第一栅极、第二栅极；
    步骤8、在所述栅极绝缘层、第一栅极、第二栅极上沉积层间绝缘层；在所述栅极绝缘层、及层间绝缘层上分别对应所述第一多晶硅段、第二多晶硅段上方形成第一过孔、第二过孔；
    步骤9、在所述层间绝缘层上沉积第二金属层，并对所述第二金属层进行图案化处理，分别形成位于所述驱动区域的第一源/漏极、及位于所述显示区域的第二源/漏极；
    所述第一源/漏极、第二源/漏极分别经由所述第一过孔、第二过孔与所述第一多晶硅段、第二多晶硅段相接触。
  2. 如权利要求1所述的低温多晶硅TFT基板的制作方法，其中，所述步骤5中，所述第一多晶硅段中的晶格尺寸大于第二多晶硅段中的晶格尺寸。
  3. 如权利要求1所述的低温多晶硅TFT基板的制作方法，其中，所述基板为玻璃基板；所述缓冲层、栅极绝缘层、及层间绝缘层的材料为氮化硅、氧化硅、或二者的组合；所述第一栅极、第二栅极、第一源/漏极、第二源/漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
  4. 如权利要求1所述的低温多晶硅TFT基板的制作方法，其中，所述散热段的材料为金属。
  5. 一种低温多晶硅TFT基板的制作方法，包括如下步骤：
    步骤1、提供基板，所述基板包括驱动区域与显示区域；在所述基板上沉积缓冲层，在所述缓冲层上沉积散热层；
    步骤2、对所述散热层进行图案化处理，除去位于所述驱动区域的散热层，形成位于所述显示区域的散热段；
    步骤3、在所述缓冲层、及散热段上沉积非晶硅层；
    步骤4、对所述非晶硅层进行准分子激光退火处理，使所述非晶硅层结晶转变为多晶硅层；
    步骤5、对所述多晶硅层进行图案化处理，形成位于所述驱动区域的第一多晶硅段、及位于所述显示区域的第二多晶硅段；
    步骤6、在所述缓冲层、第一多晶硅段、第二多晶硅段、及散热段上形成栅极绝缘层；
    步骤7、在所述栅极绝缘层上沉积第一金属层，并对所述第一金属层进行图案化处理，分别形成位于所述第一多晶硅段、第二多晶硅段上的第一栅极、第二栅极；
    步骤8、在所述栅极绝缘层、第一栅极、第二栅极上沉积层间绝缘层；在所述栅极绝缘层、及层间绝缘层上分别对应所述第一多晶硅段、第二多晶硅段上方形成第一过孔、第二过孔；
    步骤9、在所述层间绝缘层上沉积第二金属层，并对所述第二金属层进行图案化处理，分别形成位于所述驱动区域的第一源/漏极、及位于所述显示区域的第二源/漏极；
    所述第一源/漏极、第二源/漏极分别经由所述第一过孔、第二过孔与所述第一多晶硅段、第二多晶硅段相接触。
  6. 如权利要求5所述的低温多晶硅TFT基板的制作方法，其中，所述步骤5中，所述第一多晶硅段中的晶格尺寸大于第二多晶硅段中的晶格尺寸。
  7. 如权利要求5所述的低温多晶硅TFT基板的制作方法，其中，所述基板为玻璃基板；所述缓冲层、栅极绝缘层、及层间绝缘层的材料为氮化硅、氧化硅、或二者的组合；所述第一栅极、第二栅极、第一源/漏极、第二源/漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
  8. 如权利要求5所述的低温多晶硅TFT基板的制作方法，其中，所述散热段的材料为不导电的金属氧化物。
  9. 一种低温多晶硅TFT基板，包括驱动区域与显示区域，所述驱动区域包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的第一多晶硅段、设于所述缓冲层及第一多晶硅段上的栅极绝缘层、对应所述第一多晶硅段上方设于所述栅极绝缘层上的第一栅极、设于所述栅极绝缘层及第一栅极上的层间绝缘层、及设于所述层间绝缘层上的第一源/漏极；
    所述显示区域包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的第二多晶硅段、设于所述缓冲层及第二多晶硅段上的栅极绝缘层、对应所述第二多晶硅段上方设于所述栅极绝缘层上的第二栅极、设于所述栅极绝缘层及第二栅极上的层间绝缘层、及设于所述层间绝缘层上的第二源/漏极；
    所述驱动区域的层间绝缘层及栅极绝缘层上对应所述第一多晶硅段上方形成有第一过孔，所述第一源/漏极经由所述第一过孔与所述第一多晶硅段相接触；
    所述显示区域的层间绝缘层及栅极绝缘层上对应所述第二多晶硅段上方形成有第二过孔，所述第二源/漏极经由所述第二过孔与所述第二多晶硅段相接触；
    所述显示区域中，所述第二多晶硅段的下方于所述基板与缓冲层之间或所述缓冲层与第二多晶硅段之间设有散热段。
  10. 如权利要求9所述的低温多晶硅TFT基板，其中，所述第一多晶硅段中的晶格尺寸大于第二多晶硅段中的晶格尺寸；所述基板为玻璃基板；所述缓冲层、栅极绝缘层、及层间绝缘层的材料为氮化硅、氧化硅、或二者的组合；所述第一栅极、第二栅极、第一源/漏极、第二源/漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；所述散热段的材料为金属或不导电的金属氧化物。
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