WO2017118061A1 - 形成掩膜图案的方法、薄膜晶体管及形成方法、显示装置 - Google Patents

形成掩膜图案的方法、薄膜晶体管及形成方法、显示装置 Download PDF

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Publication number
WO2017118061A1
WO2017118061A1 PCT/CN2016/097813 CN2016097813W WO2017118061A1 WO 2017118061 A1 WO2017118061 A1 WO 2017118061A1 CN 2016097813 W CN2016097813 W CN 2016097813W WO 2017118061 A1 WO2017118061 A1 WO 2017118061A1
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Prior art keywords
negative photoresist
exposed
forming
mask
mask pattern
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PCT/CN2016/097813
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English (en)
French (fr)
Inventor
张斌
周婷婷
刘震
曹占锋
舒适
姚琪
关峰
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京东方科技集团股份有限公司
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Priority to US15/519,324 priority Critical patent/US10236361B2/en
Publication of WO2017118061A1 publication Critical patent/WO2017118061A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • G—PHYSICS
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    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/094—Multilayer resist systems, e.g. planarising layers
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    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
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    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2002—Exposure; Apparatus therefor with visible light or UV light, through an original having an opaque pattern on a transparent support, e.g. film printing, projection printing; by reflection of visible or UV light from an original such as a printed image
    • G03F7/201—Exposure; Apparatus therefor with visible light or UV light, through an original having an opaque pattern on a transparent support, e.g. film printing, projection printing; by reflection of visible or UV light from an original such as a printed image characterised by an oblique exposure; characterised by the use of plural sources; characterised by the rotation of the optical device; characterised by a relative movement of the optical device, the light source, the sensitive system or the mask
    • G—PHYSICS
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    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • G—PHYSICS
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    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • G03F7/2026—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure for the removal of unwanted material, e.g. image or background correction
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • G03F7/203—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure comprising an imagewise exposure to electromagnetic radiation or corpuscular radiation
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • G—PHYSICS
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    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/40—Treatment after imagewise removal, e.g. baking

Definitions

  • Embodiments of the present disclosure relate to a method of forming a mask pattern, a thin film transistor, a method of forming a thin film transistor, and a display device including the same.
  • the patterning process is a process of forming a film into a layer comprising at least one pattern.
  • the patterning process generally comprises: forming a mask pattern on the film, etching away the portion of the film not covered by the mask pattern, and then peeling off the remaining mask pattern to obtain a desired film pattern.
  • the mask pattern 1 having a step is formed by using a halftone mask, and the fabrication process of the halftone mask is complicated.
  • At least one embodiment of the present disclosure provides a method of forming a mask pattern, comprising:
  • Forming a negative photoresist on the substrate and the negative photoresist has the following characteristics: after being exposed in an oxygen-free environment, the exposed portion can be cured; after exposure in an aerobic environment, the exposed portion is exposed The surface cannot be cured, and other exposed portions other than the surface can be cured;
  • the negative photoresist is first exposed using a first common mask such that the fully cured portion of the negative photoresist is exposed, the semi-cured portion, and the removed portion are not Be exposed
  • the negative photoresist is subjected to a second exposure using a second common mask such that the semi-cured portion of the negative photoresist is exposed, and the removal portion is not Be exposed
  • the uncured negative photoresist is removed to form a mask pattern.
  • the semi-cured portion of the negative photoresist is located between the fully cured portion and the removed portion and in close proximity to the fully cured portion.
  • the second common mask and the first common mask are the same mask
  • the second exposure is such that the semi-cured portion of the negative photoresist is exposed and the removed portion is not exposed.
  • the adjusting the exposure parameter comprises:
  • Adjusting an angle at which the exposure machine emits light such that the negative photoresist receives an increase in the range of light irradiation increases the amount of exposure, increases the distance between the mask and the substrate, or combination.
  • the increasing the exposure amount includes increasing the exposure time and/or increasing the illumination of the exposure machine.
  • the oxygen-free environment is a vacuum environment or an inert gas environment.
  • the semi-cured portion of the negative photoresist is located between the fully cured portion and the removed portion, and in close proximity to the fully cured portion;
  • the negative photoresist is subjected to a second exposure using a second common mask such that the semi-cured portion of the negative photoresist is exposed, and the removal portion is not Being exposed, wherein the second common mask and the first common mask are different masks.
  • the forming a negative photoresist on the substrate comprises:
  • a negative photoresist is coated on the substrate, or a negative photoresist is formed on the substrate by a transfer method.
  • Embodiments of the present disclosure provide a method for forming a mask pattern, which can be normally cured by exposure to a negative photoresist in an oxygen-free environment, and cannot be normally cured through an exposed surface in an aerobic environment, except for a surface.
  • the other exposed portions can be normally cured, and the first photoresist is subjected to the first exposure in an oxygen-free environment by using the first common mask, so that the fully cured portion of the negative photoresist is exposed, The semi-cured portion and the removed portion are not exposed; then the second photoresist is subjected to a second exposure in an aerobic environment using a second common mask to make the semi-cured portion of the negative photoresist The exposure and removal portions are not exposed; finally, the uncured negative photoresist is removed to form a mask pattern.
  • the mask pattern includes a pattern formed correspondingly to the fully cured portion and a pattern corresponding to the semi-cured portion, and the thickness of the pattern formed by the semi-cured portion is smaller than the pattern formed by the fully cured portion.
  • the method for forming the mask pattern can form a mask pattern having an uneven thickness by using a common mask, thereby avoiding the use of a halftone mask.
  • At least one embodiment of the present disclosure provides a method of forming a thin film transistor, the method comprising:
  • the mask pattern includes a body portion and a step portion around the body portion, and the thickness of the body portion is greater than The thickness of the step portion;
  • the remaining mask pattern is stripped to form a metal oxide layer pattern and an etch barrier pattern.
  • the material of the metal oxide layer is indium gallium zinc oxide, indium tin zinc oxide, zinc indium tin oxide or magnesium indium zinc oxide.
  • At least one embodiment of the present disclosure provides a method of forming a thin film transistor, the method comprising:
  • the mask pattern includes a body portion and a step portion around the body portion, and the thickness of the body portion is greater than The thickness of the step portion;
  • the remaining mask pattern is stripped to form a polysilicon layer pattern.
  • the method before the forming a polysilicon layer on a substrate, the method further includes:
  • a buffer layer is formed on the substrate, the buffer layer being between the substrate and the polysilicon layer.
  • At least one embodiment of the present disclosure provides a thin film transistor formed using the method of forming a thin film transistor described in any of the above.
  • At least one embodiment of the present disclosure provides a display device including the above-described thin film transistor.
  • 1 is a mask pattern having a step in a conventional technique
  • FIG. 2 is a flow diagram of a method of forming a mask pattern in accordance with an embodiment of the present disclosure
  • FIG. 3 is a schematic structural view of the negative photoresist formed on the substrate of FIG. 2;
  • Figure 4 is a schematic view showing the first exposure of step S02 in Figure 2;
  • Figure 5 is a schematic view showing the structure of Figure 3 after the first exposure
  • FIG. 6 is a schematic view showing a correspondence relationship between a negative photoresist and a mask pattern
  • Figure 7 is a schematic view showing the structure of Figure 5 after the second exposure
  • FIG. 8 is a schematic structural view showing a positional relationship between a fully cured portion and a semi-cured portion in a negative photoresist according to an embodiment of the present disclosure
  • FIG. 9 is a schematic structural view showing a positional relationship between a fully cured portion and a semi-cured portion in a negative photoresist according to another embodiment of the present disclosure.
  • FIG. 10 is a schematic structural view showing a positional relationship between a fully cured portion and a semi-cured portion in a negative photoresist according to still another embodiment of the present disclosure.
  • FIG. 11 is a schematic structural view showing a positional relationship between a fully cured portion and a semi-cured portion in a negative photoresist according to still another embodiment of the present disclosure
  • FIG. 12 is a schematic diagram of adjusting the angle of light emitted by the exposure machine during the second exposure of step S03 in FIG. 2;
  • Figure 13 is a schematic view showing the exposure of the second mask when the second exposure is performed in step S03 of Figure 2;
  • FIG. 14 is a flow chart showing a method of forming a thin film transistor according to an embodiment of the present disclosure
  • Figure 15 is a schematic view showing the structure formed after the step S141 of Figure 14;
  • Figure 16 is a schematic view showing the structure formed after the step S142 of Figure 14;
  • Figure 17 is a schematic view showing the structure formed after the step S143 of Figure 14;
  • Figure 18 is a schematic view showing the structure formed after the step S144 of Figure 14;
  • Figure 19 is a schematic view showing the structure formed after the step S145 of Figure 14;
  • Figure 20 is a schematic view showing the structure formed after the step S146 of Figure 14;
  • 21 is a schematic flow chart of a method of forming a thin film transistor according to another embodiment of the present disclosure.
  • Figure 22 is a schematic view showing the structure formed after the step S211 of Figure 21;
  • Figure 23 is a schematic view showing the structure formed after the step S212 of Figure 21;
  • Figure 24 is a schematic view showing the structure formed after the step S213 of Figure 21;
  • Figure 25 is a schematic view showing the structure formed after the step S214 of Figure 21;
  • 26 is a schematic structural view formed corresponding to step S215 of FIG. 21;
  • Figure 27 is a schematic view showing the structure formed after the step S216 of Figure 21;
  • Figure 28 is a schematic view showing the structure in which a buffer layer is formed between the substrate and the polysilicon layer in Figure 22 .
  • a common mask refers to a mask that includes only a light transmitting portion and a light opaque portion
  • the halftone mask refers to a light transmissive portion, a semi-transmissive portion, and an impervious portion.
  • a mask for the light department The masks used in the embodiments of the present disclosure are all common masks.
  • At least one embodiment of the present disclosure provides a method of forming a mask pattern, as shown in FIG. 2, the method includes:
  • a negative photoresist 11 is formed on the substrate 10, and the negative photoresist 11 has the following characteristics: After exposure in an oxygen atmosphere, the exposed portion can be cured; after exposure in an aerobic environment, the exposed portion of the surface cannot be cured, and other exposed portions other than the surface can be cured.
  • the resulting structure is shown in Figure 3.
  • the exposed portion can be cured; after exposure in an aerobic environment, the exposed portion of the surface cannot be cured, and the exposed portions other than the surface can be cured.
  • the negative photoresist may be directly obtained by removing nano silver from the surface of a TCTF (Nano-silver Transparent Conductive Transfer Film) of the model MS100D3G4 manufactured by Hitachi Chemical Co., Ltd.
  • the substrate may be made of a material such as Corning, Asahi Glass, or quartz glass, which is not limited by the embodiments of the present disclosure.
  • the negative photoresist 11 shown in FIG. 3 is first exposed by the first common mask 8 so that the fully cured portion of the negative photoresist 11 is completely cured.
  • the exposed, semi-cured portion 13 and the removed portion 14 are not exposed.
  • the structure shown in FIG. 5 can be obtained.
  • the shaded portion in FIG. 5 indicates that the negative photoresist at the fully cured portion 12 is cured after exposure, and is not It represents other meanings; in addition, due to the limitation of the process precision, the fully cured portion 12 is cured after being exposed, and the sides thereof are mostly beveled surfaces instead of the ideal straight faces.
  • the light transmitting portion 81 of the first common mask 8 may correspond to the fully cured portion 12 of the negative photoresist 11, and the opaque portion 82 may correspond to the semi-curing of the negative photoresist 11.
  • the portion 13 and the removing portion 14 such that when ultraviolet light is irradiated onto the first common mask 8, the opaque portion 82 can block ultraviolet light from being irradiated onto the semi-cured portion 13 and the removing portion 14 to cause negative lithography
  • the fully cured portion 12 of the glue 11 is exposed, and the semi-cured portion 13 and the removed portion 14 are not exposed.
  • a part of the negative photoresist which needs to be completely cured is referred to as a fully cured portion, and a portion in which a negative photoresist is required to be partially cured is referred to as a semi-cured portion.
  • the portion to be removed in the negative photoresist is referred to as a removal portion.
  • the positional relationship of the fully cured portion, the semi-cured portion, and the removed portion is not limited, and may be determined according to a mask pattern to be formed, and the fully cured portion may correspond to a thick portion and a semi-cured portion of the mask pattern.
  • the removal portion can correspond to a portion to be removed.
  • the semi-cured portion 13 of the negative photoresist 11 may correspond to the step portion 101 of the mask pattern 1 and be completely cured.
  • Part 12 can correspond to the table
  • the body portion 102 adjacent to the step 101, that is, the semi-cured portion may be located between the fully cured portion and the removed portion, and in close proximity to the fully cured portion, so that a mask pattern having a step may be formed. Since the mask pattern having the step is applied more, the present disclosure and the drawings are described by taking a mask pattern having a step as an example.
  • the negative photoresist shown in FIG. 5 is subjected to a second exposure using a second common mask, so that the semi-cured portion of the negative photoresist is exposed, and the removed portion is not exposed. Thereby a structure as shown in Fig. 7 is obtained.
  • the method for performing the second exposure of the negative photoresist by using the second common mask is not limited as long as the semi-cured portion of the negative photoresist is The exposure and removal portions are not exposed.
  • the fully cured portion of the negative photoresist may be re-exposed or not exposed, which is not limited herein, and may be determined according to actual conditions.
  • the uncured negative photoresist 11 i.e., the removed portion 14 shown in Fig. 7 is removed to form the mask pattern shown in Fig. 1.
  • the method of removing the uncured negative photoresist is not limited.
  • the developer may be used to remove the uncured negative photoresist.
  • Embodiments of the present disclosure provide a method for forming a mask pattern, which can be normally cured by exposure to a negative photoresist in an oxygen-free environment, and cannot be normally cured through an exposed surface in an aerobic environment, except for a surface.
  • the other exposed portions can be normally cured, and the first photoresist is subjected to the first exposure in an oxygen-free environment by using the first common mask, so that the fully cured portion of the negative photoresist is exposed, The semi-cured portion and the removed portion are not exposed; then the second photoresist is subjected to a second exposure in an aerobic environment using a second common mask to expose the semi-cured portion of the negative photoresist The portion is not exposed; finally, the uncured negative photoresist is removed to form a mask pattern.
  • the mask pattern includes a pattern formed by the fully cured portion and a pattern formed by the semi-cured portion, and the thickness of the pattern formed by the semi-cured portion is smaller than the pattern formed by the fully cured portion.
  • the method for forming the mask pattern can form a mask pattern having an uneven thickness by using a common mask, thereby avoiding the use of a halftone mask.
  • a TFT Thin Film Transistor plays a very important role in a TFT-LCD (Thin Film Transistor Liquid Crystal Display).
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the semi-cured portion of the negative photoresist is located between the fully cured portion and the removed portion and in close proximity to the fully cured portion. In this way, a film pattern having a step can be formed.
  • the embodiment of the present disclosure does not limit the shape of the fully cured portion and the semi-cured portion, and may be determined according to actual conditions.
  • the fully cured portion may be a rectangular parallelepiped, a cylinder or the like
  • the semi-cured portion may be a rectangular ring, a circular ring, a rectangular parallelepiped or the like.
  • the shape of the portion other than the step in the mask pattern is mostly a rectangular parallelepiped, and the embodiment of the present disclosure and the drawings are described by taking a completely solidified portion as a rectangular parallelepiped as an example.
  • the fully cured portion is a rectangular parallelepiped
  • the semi-cured portion may be adjacent to the fully cured portion as shown in FIG. 8, and the semi-cured portion 13 is adjacent to one side of the fully cured portion 12; It is shown that the semi-cured portion 13 is adjacent to two opposite sides of the fully cured portion 12; as shown in FIG. 10, the semi-cured portion 13 is adjacent to the three sides of the fully cured portion 12; It is shown that the semi-cured portion 13 surrounds the fully cured portion 12.
  • the first The second mask is used for the second exposure of the negative photoresist so that the semi-cured portion of the negative photoresist is exposed, and the step of removing the removed portion can be achieved by two methods, which will be described in detail below.
  • the second common mask and the first common mask are the same mask, and in the aerobic environment, the second photoresist is used to perform the second photoresist.
  • Sub-exposure so that the semi-cured portion of the negative photoresist is exposed, and the removed portion is not exposed, including:
  • the position correspondence between the first common mask and the negative photoresist is maintained, wherein the first common mask
  • the positional correspondence between the film and the negative photoresist refers to the position of the light transmitting portion and the opaque portion of the first common mask and the fully cured portion, the semi-cured portion and the removed portion of the negative photoresist. Relationship, for example, in the second exposure and the first exposure, the light transmitting portions of the first common mask are all corresponding to the fully cured portion of the negative photoresist, and the opaque portions are both negative and negative.
  • the semi-cured portion corresponds to the removed portion, and the positional relationship between the first common mask and the negative photoresist in the two exposures is unchanged.
  • This method only needs A mask pattern having a step can be formed by using a common mask, and a mask pattern having a step is formed compared to the halftone mask used in the conventional technique, which greatly saves production time and reduces production cost.
  • adjusting the exposure parameter may include: adjusting an angle at which the exposure machine emits light to increase a range in which the negative photoresist receives the light, increasing the exposure amount, and increasing the gap between the mask and the substrate. Any one of the distances or a combination thereof.
  • the semi-cured portion is exposed by adjusting the angle at which the exposure machine emits light.
  • the method can change the path of the light so that part of the light 200 is directly irradiated to the semi-cured portion, thereby causing the semi-cured portion to be exposed.
  • the semi-cured portion is exposed by increasing the exposure amount.
  • part of the light beam will be diffracted at the boundary between the light transmitting portion and the opaque portion of the mask, and the partial light beam is irradiated to the semi-cured portion.
  • the number of beams that are diffracted in practice is very small, so it is necessary to increase the amount of exposure to increase the number of beams that are diffracted, so that a sufficient number of beams are irradiated to the semi-cured portion by diffraction, so that the semi-cured portion is exposed.
  • the distance between the mask and the substrate if the distance between the mask and the substrate is small, the diffracted light is irradiated in the semi-cured portion to a small extent, which is insufficient to illuminate all of the semi-cured portions.
  • the distance between the mask and the substrate it is possible to increase the range in which the diffracted light is irradiated on the semi-cured portion, so that the semi-cured portion is exposed.
  • the semi-cured portion of the negative photoresist may be exposed, and the removed portion may not be exposed, and only one of them may be used or may be arbitrarily combined, which is not limited herein.
  • increasing the exposure amount includes increasing the exposure time and/or increasing the illumination of the exposure machine. That is, the exposure amount can be increased only by increasing the exposure time or by merely increasing the illuminance of the exposure machine.
  • the exposure time and the illuminance of the exposure machine can be increased at the same time to increase the exposure amount, which is not limited herein, and may be determined according to actual conditions.
  • the second photoresist in aerobic environment, is subjected to a second exposure using a second common mask to expose the semi-cured portion of the negative photoresist.
  • the removal is not exposed including:
  • the second photoresist is subjected to a second exposure using a second common mask to The semi-cured portion of the negative photoresist is exposed, and the removed portion is not exposed, wherein the second common mask and the first common mask are different masks.
  • the negative lithography shown in FIG. 5 is performed by using the second common mask 9.
  • the glue 11 performs a second exposure, wherein the light transmitting portion 91 of the second common mask 9 can correspond to the fully cured portion 12 and the semi-cured portion 13 of the negative photoresist 11, and the opaque portion 92 can correspond to negative
  • the removal portion 14 of the photoresist 11 is such that when the ultraviolet light is irradiated onto the second normal mask 9, the semi-cured portion 13 can be exposed and the removed portion 14 is not exposed.
  • the first method only needs to adopt a common mask, which can save production time and reduce production cost.
  • the oxygen-free environment in which the negative photoresist 11 is first exposed by using the first common mask 8 is a vacuum environment or an inert gas environment, wherein the inert gas may be helium gas, Argon gas, helium gas, etc. are not limited herein.
  • forming a negative photoresist on a substrate includes: coating a negative photoresist on the substrate, or forming a negative photoresist on the substrate by a transfer method.
  • the method is simple to operate and easy to implement.
  • At least one embodiment of the present disclosure provides a method of forming a thin film transistor. Referring to FIG. 14, the method includes:
  • a metal oxide layer 15 and an etch barrier layer 16 are sequentially formed on the substrate 10, and the resulting structure is as shown in FIG.
  • the material of the metal oxide layer may be indium gallium zinc oxide, indium tin zinc oxide, zinc indium tin oxide or magnesium indium zinc oxide, and is not limited herein.
  • the material of the etch barrier layer may be a material such as silicon nitride, silicon oxide or silicon oxynitride. The thickness of the metal oxide layer and the etch barrier layer are not limited in the embodiments of the present disclosure.
  • the method for forming the metal oxide layer and the etch barrier layer is not limited.
  • the metal oxide layer and the etch barrier layer may be deposited on the substrate by a sputtering method or a thermal evaporation method.
  • the mask pattern 1 is formed on the etch barrier layer 16 by the above-described method of forming a marina pattern, wherein the mask pattern 1 includes a body portion 102 and a step portion 101 around the body portion 102, and the body portion The thickness of 102 is larger than the thickness of the step portion 101, and the resulting structure is as shown in FIG.
  • the body portion and the step portion of the mask pattern may respectively adopt a fully cured portion and a semi-cured portion of the negative photoresist in the mask pattern formed by the mask pattern forming method described above, and the mask pattern forming process is referred to the above mask.
  • the mold pattern forming method will not be described here.
  • the portion of the metal oxide layer 15 and the etch stop layer 16 that is not covered by the mask pattern 1 is etched away to form the structure shown in FIG.
  • the portion where the metal oxide layer 15 and the etch barrier layer 16 are not covered by the mask pattern 1 may be etched by dry etching, wet etching, or the like, and the etching method employed is not limited in the embodiment of the present disclosure.
  • the mask pattern 1 shown in Fig. 17 is ashed to remove the step portion 101 and the main body portion 102 is thinned to form the structure shown in Fig. 18.
  • the portion of the etch stop layer 16 shown in FIG. 18 which is not covered by the ash mask pattern 1 is etched away to form the structure shown in FIG.
  • the remaining mask pattern 1 in FIG. 19 is peeled off to form a metal oxide layer pattern 150 and an etch barrier pattern 160, and the resulting structure is as shown in FIG.
  • the metal oxide layer pattern 150 and the etch barrier layer pattern 160 in FIG. 20 form a step at the edge.
  • This structure is called a SWC (Side Wing Contact) structure, and after the structure is formed, it can be formed on the pattern. Source drain.
  • the thin film transistor may further include other components, for example, may also include a gate metal.
  • the layer, the gate insulating layer and the source/drain metal layer, the method of forming the thin film transistor may further include forming a gate, a gate insulating layer, a source and a drain, and the like on the substrate, and details are not described herein.
  • the metal oxide thin film transistor can be formed by the above method, and the thin film transistor has a very high mobility and a reaction speed, and is widely used in display devices such as mobile phones and tablet computers.
  • the material of the metal oxide layer is indium gallium zinc oxide, indium tin zinc oxide, zinc indium tin oxide or magnesium indium zinc oxide.
  • At least one embodiment of the present disclosure provides a method of forming a thin film transistor, as shown in FIG. 21, the method comprising:
  • a polysilicon layer 17 is formed on the substrate 10, and the resulting structure is as shown in FIG.
  • an amorphous silicon layer may be formed on a substrate, and then the amorphous silicon layer is processed by an excimer laser annealing method, thereby converting the amorphous silicon layer into a polysilicon layer, and the embodiment of the present disclosure is for forming a polysilicon layer.
  • the method is not limited.
  • the mask pattern 1 is formed on the polysilicon layer 17 by any of the above methods for forming a mask pattern, wherein the mask pattern 1 includes a body portion 102 and a step portion 101 located around the body portion 102, and the thickness of the body portion 102 is greater than The thickness of the step portion 101 is as shown in Fig. 23.
  • the body portion and the step portion of the mask pattern may respectively form a fully cured portion and a semi-cured portion of the negative photoresist in the mask pattern formed by the mask pattern forming method described above, and the forming process is performed with reference to the above-described forming mask pattern. The method is not repeated here.
  • the portion of the polysilicon layer 17 shown in FIG. 23 that is not covered by the mask pattern 1 is doped for the first time to form the structure shown in FIG.
  • the mask pattern 1 shown in Fig. 24 is ashed to remove the step portion 101 and the main body portion 102 is thinned to form the structure shown in Fig. 25.
  • a portion which is not covered by the ashed mask pattern 1 in the polysilicon layer 17 shown in FIG. 25 is doped a second time to form the structure shown in FIG. 26, wherein the doped polysilicon layer passes only the second
  • the impurity concentration of the sub-doped portion is smaller than the impurity concentration of the portion that is twice doped.
  • the first doping as heavy doping
  • the second doping as light doping
  • the impurity concentration after heavy doping to be greater than the impurity concentration after light doping
  • the remaining mask pattern 1 in FIG. 26 is peeled off to form the polysilicon layer pattern 170 shown in FIG.
  • the thin film transistor may further include other components, for example, a gate metal layer may also be included.
  • the gate insulating layer and the source/drain metal layer, the thin film transistor forming method may further include forming a gate, a gate insulating layer, a source and a drain, and the like on the substrate, and details are not described herein again.
  • the LTPS (Low Temperature Poly-Silicon) thin film transistor can be formed by the above method, and the thin film transistor has the characteristics of high mobility and fast response speed, and is widely used in display devices such as mobile phones and tablet computers.
  • the method before the polysilicon layer 17 is formed on the substrate 10, the method further includes: forming a buffer layer 18 on the substrate 10, the buffer layer 18 being located between the substrate 10 and the polysilicon layer 17, the buffer The layer can increase the adhesion of the polysilicon layer to the substrate.
  • the resulting structure is shown in FIG.
  • At least one embodiment of the present disclosure provides a thin film transistor which can be formed by any of the above methods for forming a thin film transistor, and can also be formed by any of the thin film transistor formation methods provided in the third embodiment.
  • the former is a metal oxide thin film transistor and the latter is a polysilicon thin film transistor, and both of these thin film transistors are widely used in display technology.
  • the display device may be a display device such as a liquid crystal display, an electronic paper, an OLED (Organic Light-Emitting Diode) display, or any display product such as a television, a digital camera, a mobile phone, a tablet computer, or the like including the display device or component.
  • a display device such as a liquid crystal display, an electronic paper, an OLED (Organic Light-Emitting Diode) display, or any display product such as a television, a digital camera, a mobile phone, a tablet computer, or the like including the display device or component.

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Abstract

提供了一种掩膜图案的形成方法，包括：在衬底（10）上形成负性光刻胶（11）；在无氧环境中，利用第一普通掩膜板（8）对负性光刻胶（11）进行第一次曝光，以使得负性光刻胶（11）的完全固化部（12）被曝光、半固化部（13）和去除部（14）不被曝光；在有氧环境中，利用第二普通掩膜板（9）对负性光刻胶（11）进行第二次曝光，以使得负性光刻胶（11）的半固化部（13）被曝光、去除部（14）不被曝光；去除掉未固化的负性光刻胶（11），形成掩膜图案。还提供了一种利用该掩模图案形成薄膜晶体管的方法、利用该掩模图案形成的薄膜晶体管以及具有该薄膜晶体管的显示装置。

Description

形成掩膜图案的方法、薄膜晶体管及形成方法、显示装置 技术领域
本公开的实施例涉及一种形成掩膜图案的方法、薄膜晶体管、形成薄膜晶体管的方法、以及包含该薄膜晶体管的显示装置。
背景技术
目前，显示装置中的膜层大多通过构图工艺形成。构图工艺是将薄膜形成包含至少一个图案的层的工艺。构图工艺一般包括：在薄膜上形成掩膜图案，刻蚀掉掩膜图案未覆盖的薄膜部分，然后将剩下的掩膜图案剥离，便可得到所需要的薄膜图案。
在实际生产过程中，通常需要形成具有台阶的薄膜图案，此时就需要形成图1所示的具有台阶的掩膜图案1。目前均采用半色调掩膜板形成上述掩膜图案，而半色调掩膜板的制作工艺较复杂。
发明内容
本公开的至少一个实施例提供了一种形成掩膜图案的方法，包括：
在衬底上形成负性光刻胶，且所述负性光刻胶具有以下特性：在无氧环境中经过曝光后，被曝光部分能够固化；在有氧环境中经过曝光后，被曝光部分的表面不能固化，除表面外的其他被曝光部分能够固化；
在无氧环境中，利用第一普通掩膜板对所述负性光刻胶进行第一次曝光，以使得所述负性光刻胶的完全固化部被曝光、半固化部和去除部不被曝光；
在有氧环境中，利用第二普通掩膜板对所述负性光刻胶进行第二次曝光，以使得所述负性光刻胶的所述半固化部被曝光、所述去除部不被曝光；
去除掉未固化的所述负性光刻胶，形成掩膜图案。
在本公开的一个实施例中，所述负性光刻胶的所述半固化部位于所述完全固化部和所述去除部之间、并紧邻所述完全固化部。
在本公开的一个实施例中，所述第二普通掩膜版和所述第一普通掩膜版为同一掩膜版；
所述在有氧环境中，利用第二普通掩膜版对所述负性光刻胶进行第二次曝光，以使得所述负性光刻胶的所述半固化部被曝光、所述去除部不被曝光包括：
在有氧环境中，保持所述第一普通掩膜版与所述负性光刻胶的位置对应关系并调整曝光参数，利用所述第一普通掩膜版对所述负性光刻胶进行第二次曝光，以使得所述负性光刻胶的所述半固化部被曝光、所述去除部不被曝光。
在本公开的一个实施例中，所述调整曝光参数包括：
调整曝光机发出光线的角度以使得所述负性光刻胶接受光线照射的范围增大、增加曝光量、增加所述掩膜版与所述衬底之间的距离中的任意一种或其组合。
在本公开的一个实施例中，所述增加曝光量包括：增加曝光时间和/或增加曝光机的照度。
在本公开的一个实施例中，所述无氧环境为真空环境或者惰性气体环境。
在本公开的一个实施例中，所述负性光刻胶的所述半固化部位于所述完全固化部和所述去除部之间、并紧邻所述完全固化部；
所述在有氧环境中，利用第二普通掩膜版对所述负性光刻胶进行第二次曝光，以使得所述负性光刻胶的所述半固化部被曝光、所述去除部不被曝光包括：
在有氧环境中，利用第二普通掩膜版对所述负性光刻胶进行第二次曝光，以使得所述负性光刻胶的所述半固化部被曝光、所述去除部不被曝光，其中，所述第二普通掩膜版和所述第一普通掩膜版为不同掩膜板。
在本公开的一个实施例中，所述在衬底上形成负性光刻胶包括：
在衬底上涂覆负性光刻胶，或者通过转印方法在衬底上形成负性光刻胶。
本公开的实施例提供了一种掩膜图案的形成方法，该方法利用负性光刻胶在无氧环境中经过曝光可以正常固化、而在有氧环境中经过曝光表面无法正常固化、除表面外的其他被曝光部分可以正常固化的特点，在无氧环境中利用第一普通掩膜版对负性光刻胶进行第一次曝光，以使得负性光刻胶的完全固化部被曝光、半固化部和去除部不被曝光；接着在有氧环境中利用第二普通掩膜版对负性光刻胶进行第二次曝光，以使得负性光刻胶的半固化部被 曝光、去除部不被曝光；最后，去除掉未固化的负性光刻胶，形成掩膜图案。该掩膜图案包括完全固化部对应形成的图案和半固化部对应形成的图案，半固化部对应形成的图案的厚度小于完全固化部对应形成的图案。该掩膜图案的形成方法只需采用普通掩膜版即可形成厚度不均的掩膜图案，从而避免了使用半色调掩膜版。
本公开的至少一个实施例提供了一种形成薄膜晶体管的方法，所述方法包括：
在衬底上依次形成金属氧化物层、刻蚀阻挡层；
在所述刻蚀阻挡层上采用上述掩膜图案的形成方法形成掩膜图案，其中，所述掩膜图案包括本体部和位于所述本体部周围的台阶部，且所述本体部的厚度大于所述台阶部的厚度；
刻蚀掉所述金属氧化物层和所述刻蚀阻挡层中所述掩膜图案未覆盖的部分；
对所述掩膜图案进行灰化，以去除所述台阶部、并减薄所述本体部；
刻蚀掉所述刻蚀阻挡层中灰化后的所述掩膜图案未覆盖的部分；
剥离剩下的所述掩膜图案，以形成金属氧化物层图案和刻蚀阻挡层图案。
在本公开的一个实施例中，所述金属氧化物层的材料为铟镓锌氧化物、铟锡锌氧化物、锌铟锡氧化物或者镁铟锌氧化物。
本公开的至少一个实施例提供了一种形成薄膜晶体管的方法，所述方法包括：
在衬底上形成多晶硅层；
在所述多晶硅层上采用上述掩膜图案的形成方法形成掩膜图案，其中，所述掩膜图案包括本体部和位于所述本体部周围的台阶部，且所述本体部的厚度大于所述台阶部的厚度；
对所述多晶硅层中所述掩膜图案未覆盖的部分进行第一次掺杂；
对所述掩膜图案进行灰化，以去除所述台阶部、并减薄所述本体部；
对所述多晶硅层中灰化后的所述掩膜图案未覆盖的部分进行第二次掺杂，其中，掺杂后的所述多晶硅层中仅经过第二次掺杂的部分的杂质浓度小于经过两次掺杂的部分的杂质浓度；
剥离剩下的所述掩膜图案，以形成多晶硅层图案。
在本公开的一个实施例中，所述在衬底上形成多晶硅层之前，所述方法还包括：
在所述衬底上形成缓冲层，所述缓冲层位于所述衬底和所述多晶硅层之间。
本公开的至少一个实施例提供了一种薄膜晶体管，该薄膜晶体管采用上述任一种所述的形成薄膜晶体管的方法形成。
本公开的至少一个实施例提供了一种显示装置，该显示装置包括上述的薄膜晶体管。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为惯常技术中的一种具有台阶的掩膜图案；
图2为根据本公开的一个实施例的形成掩膜图案的方法的流程示意图；
图3为图2中在衬底上形成负性光刻胶所形成的结构示意图；
图4为图2中步骤S02第一次曝光的示意图；
图5为图3经过第一次曝光后的结构示意图；
图6为负性光刻胶与掩膜图案的对应关系的示意图；
图7为图5经过第二次曝光后的结构示意图；
图8为根据本公开的一个实施例的负性光刻胶中完全固化部和半固化部的位置关系的结构示意图；
图9为根据本公开的另一个实施例的负性光刻胶中完全固化部和半固化部的位置关系的结构示意图；
图10为根据本公开的再一个实施例的负性光刻胶中完全固化部和半固化部的位置关系的结构示意图；
图11为根据本公开的又一个实施例的负性光刻胶中完全固化部和半固化部的位置关系的结构示意图；
图12为图2中步骤S03第二次曝光时，调整曝光机发出光线角度的示意图；
图13为图2中步骤S03第二次曝光时，采用第二掩膜版曝光的示意图；
图14为根据本公开的一个实施例的薄膜晶体管的形成方法的流程示意图；
图15为对应图14步骤S141后形成的结构示意图；
图16为对应图14步骤S142后形成的结构示意图；
图17为对应图14步骤S143后形成的结构示意图；
图18为对应图14步骤S144后形成的结构示意图；
图19为对应图14步骤S145后形成的结构示意图；
图20为对应图14步骤S146后形成的结构示意图；
图21为根据本公开的另一实施例的薄膜晶体管的形成方法的流程示意图；
图22为对应图21步骤S211后形成的结构示意图；
图23为对应图21步骤S212后形成的结构示意图；
图24为对应图21步骤S213后形成的结构示意图；
图25为对应图21步骤S214后形成的结构示意图；
图26为对应图21步骤S215后形成的结构示意图；
图27为对应图21步骤S216后形成的结构示意图；以及
图28为在图22中的衬底和多晶硅层之间形成有缓冲层的结构示意图。
附图标记：
1-具有台阶的掩膜图案；
101-台阶部；
102-本体部；
8-第一普通掩膜版；
81-第一普通掩膜版的透光部；
82-第一普通掩膜版的不透光部；
9-第二普通掩膜版；
91-第二普通掩膜版的透光部；
92-第二普通掩膜版的不透光部；
10-衬底；
11-负性光刻胶；
12-负性光刻胶的完全固化部；
13-负性光刻胶的半固化部；
14-负性光刻胶的去除部；
15-金属氧化物层；
16-刻蚀阻挡层；
150-金属氧化物层图案；
160-刻蚀阻挡层图案；
17-多晶硅层；
170-多晶硅层图案；
18-缓冲层；
200-光线。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
在本公开的描述中，需要理解的是，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于对本公开进行描述以及简化描述，而不是表示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
在本公开的实施例中，普通掩膜版指的是仅包括透光部和不透光部的掩膜版，半色调掩膜版指的是包括透光部、半透光部和不透光部的掩膜版。本公开实施例中采用的掩膜板均为普通掩膜版。
实施例一
本公开的至少一个实施例提供了一种掩膜图案的形成方法，如图2所示，该方法包括：
在衬底10上形成负性光刻胶11，且负性光刻胶11具有以下特性：在无 氧环境中经过曝光后，被曝光部分能够固化；在有氧环境中经过曝光后，被曝光部分的表面不能固化，除表面外的其他被曝光部分能够固化。所形成的结构如图3所示。
上述负性光刻胶在无氧环境中经过曝光后，被曝光部分可以固化；在有氧环境中经过曝光后，被曝光部分的表面无法固化，除表面外的其他被曝光部分可以固化。示例的，该负性光刻胶可以是由Hitachi Chemical(日立化成)公司生产的型号为MS100D3G4的TCTF(nano-silver Transparent Conductive Transfer Film，纳米银透明导电薄膜)除去表面的纳米银后直接得到。
上述衬底可以是康宁、旭硝子玻璃(Asahi Glass)、石英玻璃等材质，本公开的实施例对此不作限定。
参考图4所示，在无氧环境中，利用第一普通掩膜版8对图3所示的负性光刻胶11进行第一次曝光，以使得负性光刻胶11的完全固化部12被曝光、半固化部13和去除部14不被曝光。
经过第一次曝光后可以得到如图5所示的结构，需要说明的是，为了便于区分，图5中阴影部分表示完全固化部12处的负性光刻胶被曝光后发生固化，并不代表其他含义；另外，由于工艺精度的限制，完全固化部12被曝光后发生固化，其侧面大多为斜面，而不是理想的直面。
例如，如图4所示，第一普通掩膜版8的透光部81可以对应负性光刻胶11的完全固化部12、不透光部82可以对应负性光刻胶11的半固化部13和去除部14，这样当紫外光照射到该第一普通掩膜版8时，不透光部82可以阻挡紫外光照射到半固化部13和去除部14上，以使得负性光刻胶11的完全固化部12被曝光、半固化部13和去除部14不被曝光。
这里需要说明的是，为了区别负性光刻胶的不同部分，将负性光刻胶中需要完全固化的称为完全固化部、将负性光刻胶中需要部分固化的称为半固化部、将负性光刻胶中需要去除的称为去除部。在本公开中对于完全固化部、半固化部和去除部的位置关系不作限定，可以根据需要形成的掩膜图案来确定，完全固化部可以对应掩膜图案中厚度较厚的部分、半固化部可以对应掩膜图案中厚度较薄的部分、去除部可以对应需要去除的部分。例如，若要形成如图1所示的具有台阶的掩膜图案1，则参考图6所示，负性光刻胶11的半固化部13可以对应掩膜图案1的台阶部101、完全固化部12可以对应台 阶部101紧邻的本体部102，即半固化部可以位于完全固化部和去除部之间、并紧邻完全固化部，这样可以形成具有台阶的掩膜图案。由于具有台阶的掩膜图案应用较多，因此本公开以及附图均以形成具有台阶的掩膜图案为例进行说明。
在有氧环境中，利用第二普通掩膜版对图5所示的负性光刻胶进行第二次曝光，以使得负性光刻胶的半固化部被曝光、去除部不被曝光，从而得到如图7所示的结构。
这里需要说明的是，在本公开的实施例中，对于利用第二普通掩膜版对负性光刻胶进行第二次曝光的方法不作限定，只要使得负性光刻胶的半固化部被曝光、去除部不被曝光即可。同时需要说明的是，在第二次曝光中，可以对负性光刻胶的完全固化部进行再次曝光，也可以不对其进行曝光，这里不作限定，可以根据实际情况而定。
去除掉图7所示的未固化的负性光刻胶11(即去除部14)，形成图1所示的掩膜图案。
在本公开的实施例中，对于去除未固化的负性光刻胶的方法不作限定，示例的，可以采用显影液去除掉未固化的负性光刻胶。
本公开的实施例提供了一种掩膜图案的形成方法，该方法利用负性光刻胶在无氧环境中经过曝光可以正常固化、而在有氧环境中经过曝光表面无法正常固化、除表面外的其他被曝光部分可以正常固化的特点，在无氧环境中利用第一普通掩膜版对负性光刻胶进行第一次曝光，以使得负性光刻胶的完全固化部被曝光、半固化部和去除部不被曝光；接着在有氧环境中利用第二普通掩膜版对负性光刻胶进行第二次曝光，以使得负性光刻胶的半固化部被曝光、去除部不被曝光；最后，去除掉未固化的负性光刻胶，形成掩膜图案。该掩膜图案包括完全固化部形成的图案和半固化部形成的图案，半固化部形成的图案的厚度小于完全固化部形成的图案。该掩膜图案的形成方法只需采用普通掩膜版即可形成厚度不均的掩膜图案，从而避免了使用半色调掩膜版。
TFT(Thin Film Transistor，薄膜晶体管)在TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示器)中扮演着非常重要的角色。在薄膜晶体管的制作过程中，需要形成具有台阶的薄膜图案，因此具有台阶的掩膜图案应用较为广泛。
在本公开的一个实施例中，负性光刻胶的半固化部位于完全固化部和去除部之间、并紧邻完全固化部。这样，可以形成具有台阶的薄膜图案。需要说明的是，本公开的实施例对于完全固化部、半固化部的形状不作限定，可以根据实际情况而定。示例的，完全固化部可以为长方体、圆柱等，半固化部可以为矩形环、圆环、长方体等。在制作TFT时，掩膜图案中除台阶的部分的形状大多为长方体，本公开的实施例以及附图均以完全固化部为长方体为例进行说明。进一步需要说明的是，若完全固化部为长方体，则半固化部紧邻完全固化部可以是如图8所示，半固化部13紧邻完全固化部12的一个侧边；还可以是如图9所示，半固化部13紧邻完全固化部12中两个相对的侧边；还可以是如图10所示，半固化部13紧邻完全固化部12的三个侧边；还可以是如图11所示，半固化部13包围完全固化部12。这里不作限定，根据实际需要确定。本公开实施例以及附图均以完全固化部、半固化部均为长方体、半固化部紧邻完全固化部中两个相对的侧边为例进行说明。
若负性光刻胶的半固化部位于完全固化部和去除部之间、并紧邻完全固化部，即若要形成图1所示的具有台阶的掩膜图案，在有氧环境中，利用第二普通掩膜版对负性光刻胶进行第二次曝光，以使得负性光刻胶的半固化部被曝光、去除部不被曝光的步骤可以采用两种方法实现，下面详细说明。
在本公开的一个实施例中，第二普通掩膜版和第一普通掩膜版为同一掩膜版，在有氧环境中，利用第二普通掩膜版对负性光刻胶进行第二次曝光，以使得负性光刻胶的半固化部被曝光、去除部不被曝光包括：
在有氧环境中，保持第一普通掩膜版与负性光刻胶的位置对应关系并调整曝光参数，利用第一普通掩膜版对负性光刻胶进行第二次曝光，以使得负性光刻胶的半固化部被曝光、去除部不被曝光。
这里需要说明的是，利用第一普通掩膜版对负性光刻胶进行第一次曝光后，保持第一普通掩膜版与负性光刻胶的位置对应关系，其中，第一普通掩膜版与负性光刻胶的位置对应关系是指第一普通掩膜版中的透光部、不透光部与负性光刻胶的完全固化部、半固化部和去除部的位置对应关系，例如，在第二次曝光和第一次曝光中，第一普通掩膜版的透光部均与负性光刻胶的完全固化部对应、不透光部均与负性光刻胶的半固化部和去除部对应，前后两次曝光中第一普通掩膜版与负性光刻胶的位置对应关系不变。该方法只需 采用一个普通掩膜版即可形成具有台阶的掩膜图案，相较于惯常技术中采用的半色调掩膜板形成具有台阶的掩膜图案，极大节约了生产时间、降低了生产成本。
本公开的实施例对于调整曝光参数的方法不作限定。在本公开的一个实施例中，调整曝光参数可以包括：调整曝光机发出光线的角度以使得负性光刻胶接受光线照射的范围增大、增加曝光量、增加掩膜板与衬底之间的距离中的任意一种或其组合。
下文对采用上述的调整曝光参数的方法对半固化部进行曝光进行描述。
通过调整曝光机发出光线的角度对半固化部进行曝光。参考图12所示，该方法可以改变光线的路径，从而使得部分光线200直接照射到半固化部，进而使得半固化部被曝光。
通过增加曝光量对半固化部进行曝光。光照射到掩膜板上时，部分光束会在掩膜版的透光部与不透光部的交界处会发生衍射，进而使得该部分光束照射到半固化部。但是实际中发生衍射的光束数量非常少，因此需要增加曝光量，以增大发生衍射的光束数量，从而使得足够多数量的光束通过衍射照射到半固化部，进而使得半固化部被曝光。
增加掩膜板与衬底之间的距离：若掩膜版与衬底之间的距离较小，则发生衍射的光线照射在半固化部的范围较小，不足以照射所有半固化部，因此，增加掩膜版与衬底之间的距离，可以增大发生衍射的光线照射在半固化部的范围，从而使得半固化部被曝光。
上述三种方法都可以实现负性光刻胶的半固化部被曝光、去除部不被曝光，可以仅采用其中的一种、或者将其任意组合，这里不作限定。
在本公开的一个实施例中，上述增加曝光量包括：增加曝光时间和/或增加曝光机的照度。即可以仅通过增加曝光时间或者仅通过增加曝光机的照度来增加曝光量，还可以是同时增加曝光时间和曝光机的照度来增加曝光量，这里不作限定，可以根据实际情况而定。
在本公开的一个可选择实施例中，在有氧环境中，利用第二普通掩膜版对负性光刻胶进行第二次曝光，以使得负性光刻胶的半固化部被曝光、去除部不被曝光包括：
在有氧环境中，利用第二普通掩膜版对负性光刻胶进行第二次曝光，以 使得负性光刻胶的半固化部被曝光、去除部不被曝光，其中，第二普通掩膜版和第一普通掩膜版为不同掩膜版。
这里需要说明的是，利用第一普通掩膜版对负性光刻胶进行第一次曝光后，参考图13所示，利用第二普通掩膜版9对图5所示的负性光刻胶11进行第二次曝光，其中，第二普通掩膜版9的透光部91可以对应负性光刻胶11的完全固化部12和半固化部13，不透光部92可以对应负性光刻胶11的去除部14，这样当紫外光照射到该第二普通掩膜版9时，可以实现半固化部13被曝光、去除部14不被曝光。
第一种方法相比第二种方法，只需采用一个普通掩膜板即可，可以节约生产时间、降低生产成本。
在本公开的一个实施例中，利用第一普通掩膜版8对负性光刻胶11进行第一次曝光的无氧环境为真空环境或者惰性气体环境，其中，惰性气体可以是氦气、氩气、氖气等，这里不作限定。
在本公开的一个实施例中，在衬底上形成负性光刻胶包括：在衬底上涂覆负性光刻胶，或者通过转印方法在衬底上形成负性光刻胶。该方法操作简单，容易实现。
实施例二
本公开的至少一个实施例提供了一种薄膜晶体管的形成方法，参考图14所示，该方法包括：
在衬底10上依次形成金属氧化物层15、刻蚀阻挡层16，所形成的结构如图15所示。
上述金属氧化物层的材料可以是铟镓锌氧化物、铟锡锌氧化物、锌铟锡氧化物或者镁铟锌氧化物等，这里不作限定。上述刻蚀阻挡层的材料可以是氮化硅、氧化硅或氮氧化硅等材料。本公开实施例对于金属氧化物层和刻蚀阻挡层的厚度均不作限定。
本公开实施例对于金属氧化物层、刻蚀阻挡层的形成方法不作限定，示例的，金属氧化物层、刻蚀阻挡层可以通过溅射方法或者热蒸发的方法沉积在衬底上。
在刻蚀阻挡层16上采用上述制作腌模图案的方法形成掩膜图案1，其中，掩膜图案1包括本体部102和位于本体部102周围的台阶部101，且本体部 102的厚度大于台阶部101的厚度，所形成的结构如图16所示。
例如，掩膜图案的本体部和台阶部可以分别采用上述掩模图案形成方法形成的掩模图案中的负性光刻胶的完全固化部和半固化部，掩模图案的形成过程参见上述掩模图案形成方法，这里不再赘述。
刻蚀掉金属氧化物层15和刻蚀阻挡层16中未被掩膜图案1覆盖的部分，形成图17所示的结构。
可以采用干法刻蚀、湿法刻蚀等刻蚀金属氧化物层15和刻蚀阻挡层16未被掩模图案1覆盖的部分，本公开的实施例对所采用的刻蚀方法不作限定。
对图17所示的掩膜图案1进行灰化，以去除台阶部101、并减薄本体部102，形成图18所示的结构。
刻蚀掉图18所示的刻蚀阻挡层16中灰化后的掩膜图案1未覆盖的部分，形成图19所示的结构。
剥离图19中剩下的掩膜图案1，以形成金属氧化物层图案150和刻蚀阻挡层图案160，形成的结构如图20所示。
图20中金属氧化物层图案150和刻蚀阻挡层图案160在边缘处形成台阶，该种结构被称为SWC(Side Wing Contact，侧翼连接)结构，形成该结构后，可以在该图案上形成源漏极。
需要说明的是，本公开的实施例中仅详细介绍薄膜晶体管中与发明点相关的结构的形成方法，本领域技术人员能够获知，薄膜晶体管还可以包含其他的部件，例如：还可以包含栅金属层、栅绝缘层和源漏金属层，则薄膜晶体管的形成方法还可以包括在衬底上形成栅极、栅绝缘层和源漏极等，这里不再赘述。
通过上述方法可以形成金属氧化物薄膜晶体管，该薄膜晶体管具有非常高的迁移率和反应速度，广泛应用在手机、平板电脑等显示器件中。
可选的，金属氧化物层的材料为铟镓锌氧化物、铟锡锌氧化物、锌铟锡氧化物或者镁铟锌氧化物。
实施例三
本公开的至少一个实施例提供了一种形成薄膜晶体管的方法，参考图21所示，该方法包括：
在衬底10上形成多晶硅层17，所形成的结构如图22所示。
例如，可以是在衬底上形成非晶硅层，然后采用准分子激光退火方法对非晶硅层进行处理，从而使得非晶硅层转换成多晶硅层，本公开的实施例对于形成多晶硅层的方法不作限定。
在多晶硅层17上采用上述任一种形成掩模图案的方法形成掩膜图案1，其中，掩膜图案1包括本体部102和位于本体部102周围的台阶部101，且本体部102的厚度大于台阶部101的厚度，所形成的结构如图23所示。
例如，掩膜图案的本体部和台阶部可以分别上述掩模图案形成方法所形成的掩模图案中的负性光刻胶的完全固化部和半固化部，其形成过程参考上述形成掩模图案的方法，这里不再赘述。
对图23所示的多晶硅层17中掩膜图案1未覆盖的部分进行第一次掺杂，形成图24所示的结构。
对图24所示的掩膜图案1进行灰化，以去除台阶部101、并减薄本体部102，形成图25所示的结构。
对图25所示的多晶硅层17中灰化后的掩膜图案1未覆盖的部分进行第二次掺杂，形成图26所示的结构，其中，掺杂后的多晶硅层中仅经过第二次掺杂的部分的杂质浓度小于经过两次掺杂的部分的杂质浓度。
需要说明的是，本领域技术人员通常将第一次掺杂称为重掺杂，第二次掺杂称为轻掺杂，重掺杂后的杂质浓度要大于轻掺杂后的杂质浓度。
剥离图26中剩下的掩膜图案1，以形成图27所示的多晶硅层图案170。
需要说明的是，本公开实施例中仅详细介绍薄膜晶体管中与发明点相关的结构的形成方法，本领域技术人员能够获知，薄膜晶体管还可以包含其他的部件，例如：还可以包含栅金属层、栅绝缘层和源漏金属层，则薄膜晶体管的形成方法还可以包括在衬底上形成栅极、栅绝缘层和源漏极等，这里不再赘述。
通过上述方法可以形成LTPS(Low Temperature Poly-Silicon，低温多晶硅)薄膜晶体管，该薄膜晶体管具有迁移率高、反应速度快等特点，广泛应用在手机、平板电脑等显示器件中。
在本公开的一个实施例中，衬底10上形成多晶硅层17之前，该方法还包括：在衬底10上形成缓冲层18，缓冲层18位于衬底10和多晶硅层17之间，该缓冲层可以增加多晶硅层与衬底的附着力。所形成的结构如图28所示。
实施例四
本公开的至少一个实施例提供了一种薄膜晶体管，该薄膜晶体管可以采用上述任一种形成薄膜晶体管的方法形成，还可以采用实施例三提供的任一项薄膜晶体管的形成方法形成。前者为金属氧化物薄膜晶体管，后者为多晶硅薄膜晶体管，这两种薄膜晶体管在显示技术领域均有广泛应用。
实施例五
本公开的至少一个实施例提供了一种显示装置，包括：根据实施例四的任一项薄膜晶体管。该显示装置可以为液晶显示器、电子纸、OLED(Organic Light-Emitting Diode，有机发光二极管)显示器等显示器件以及包括这些显示器件的电视、数码相机、手机、平板电脑等任何具有显示功能的产品或者部件。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。
本申请要求于2016年1月4日递交的中国专利申请第201610004474.2号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (14)

  1. 一种掩膜图案的形成方法，其包括：
    在衬底上形成负性光刻胶，且所述负性光刻胶具有以下特性：在无氧环境中经过曝光后，被曝光部分能够固化；在有氧环境中经过曝光后，被曝光部分的表面不能固化，除表面外的其他被曝光部分能够固化；
    在无氧环境中，利用第一普通掩膜版对所述负性光刻胶进行第一次曝光，以使得所述负性光刻胶的完全固化部被曝光、半固化部和去除部不被曝光；
    在有氧环境中，利用第二普通掩膜版对所述负性光刻胶进行第二次曝光，以使得所述负性光刻胶的所述半固化部被曝光、所述去除部不被曝光；
    去除掉未固化的所述负性光刻胶，形成掩膜图案。
  2. 根据权利要求1所述的形成方法，其中，所述负性光刻胶的所述半固化部位于所述完全固化部和所述去除部之间、并紧邻所述完全固化部。
  3. 根据权利要求2所述的形成方法，其中，所述第二普通掩膜版和所述第一普通掩膜版为同一掩膜版；
    所述在有氧环境中，利用第二普通掩膜版对所述负性光刻胶进行第二次曝光，以使得所述负性光刻胶的所述半固化部被曝光、所述去除部不被曝光包括：
    在有氧环境中，保持所述第一普通掩膜版与所述负性光刻胶的位置对应关系并调整曝光参数，利用所述第一普通掩膜版对所述负性光刻胶进行第二次曝光，以使得所述负性光刻胶的所述半固化部被曝光、所述去除部不被曝光。
  4. 根据权利要求3所述的形成方法，其中，所述调整曝光参数包括：
    调整曝光机发出光线的角度以使得所述负性光刻胶接受光线照射的范围增大、增加曝光量、增加所述掩膜板与所述衬底之间的距离中的任意一种或其组合。
  5. 根据权利要求4所述的形成方法，其中，所述增加曝光量包括：
    增加曝光时间和/或增加曝光机的照度。
  6. 根据权利要求1所述的形成方法，其中，所述无氧环境为真空环境或者惰性气体环境。
  7. 根据权利要求1或2所述的形成方法，其中，所述在有氧环境中，利用第二普通掩膜版对所述负性光刻胶进行第二次曝光，以使得所述负性光刻胶的所述半固化部被曝光、所述去除部不被曝光包括：
    在有氧环境中，利用第二普通掩膜版对所述负性光刻胶进行第二次曝光，以使得所述负性光刻胶的所述半固化部被曝光、所述去除部不被曝光。
  8. 根据权利要求1-7任一项所述的形成方法，其中，所述在衬底上形成负性光刻胶包括：
    在衬底上涂覆负性光刻胶，或者通过转印方法在衬底上形成负性光刻胶。
  9. 一种薄膜晶体管的形成方法，其特包括：
    在衬底上依次形成金属氧化物层、刻蚀阻挡层；
    在所述刻蚀阻挡层上采用权利要求1-8任一项所述的方法形成掩膜图案，其中，所述掩膜图案包括本体部和位于所述本体部周围的台阶部，且所述本体部的厚度大于所述台阶部的厚度；
    刻蚀掉所述金属氧化物层和所述刻蚀阻挡层中所述掩膜图案未覆盖的部分；
    对所述掩膜图案进行灰化，以去除所述台阶部、并减薄所述本体部；
    刻蚀掉所述刻蚀阻挡层中灰化后的所述掩膜图案未覆盖的部分；
    剥离剩下的所述掩膜图案，以形成金属氧化物层图案和刻蚀阻挡层图案。
  10. 根据权利要求9所述的形成方法，其中，所述金属氧化物层的材料为铟镓锌氧化物、铟锡锌氧化物、锌铟锡氧化物或者镁铟锌氧化物。
  11. 一种薄膜晶体管的形成方法，包括：
    在衬底上形成多晶硅层；
    在所述多晶硅层上采用权利要求1-8任一项所述的方法形成掩膜图案，其中，所述掩膜图案包括本体部和位于所述本体部周围的台阶部，且所述本体部的厚度大于所述台阶部的厚度；
    对所述多晶硅层中所述掩膜图案未覆盖的部分进行第一次掺杂；
    对所述掩膜图案进行灰化，以去除所述台阶部、并减薄所述本体部；
    对所述多晶硅层中灰化后的所述掩膜图案未覆盖的部分进行第二次掺杂，其中，掺杂后的所述多晶硅层中仅经过第二次掺杂的部分的杂质浓度小于经过两次掺杂后的部分的杂质浓度；
    剥离剩下的所述掩膜图案，以形成多晶硅层图案。
  12. 根据权利要求11所述的形成方法，其中，所述在衬底上形成多晶硅层之前，所述方法还包括：
    在所述衬底上形成缓冲层，所述缓冲层位于所述衬底和所述多晶硅层之间。
  13. 一种薄膜晶体管，其中，采用权利要求9-10或11-12任一项所述的方法形成所述薄膜晶体管。
  14. 一种显示装置，其中，包括：权利要求13所述的薄膜晶体管。
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US10236361B2 (en) 2019-03-19
CN105575776B (zh) 2019-03-15

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