WO2017114311A1 - 系统级封装模块组件、系统级封装模块及电子设备 - Google Patents

系统级封装模块组件、系统级封装模块及电子设备 Download PDF

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Publication number
WO2017114311A1
WO2017114311A1 PCT/CN2016/111735 CN2016111735W WO2017114311A1 WO 2017114311 A1 WO2017114311 A1 WO 2017114311A1 CN 2016111735 W CN2016111735 W CN 2016111735W WO 2017114311 A1 WO2017114311 A1 WO 2017114311A1
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Prior art keywords
chip
package module
boss
substrate
magnetic core
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PCT/CN2016/111735
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English (en)
French (fr)
Inventor
龚玉平
侯召政
王军鹤
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP16881100.8A priority Critical patent/EP3385985B1/en
Publication of WO2017114311A1 publication Critical patent/WO2017114311A1/zh
Priority to US16/022,055 priority patent/US11133128B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/04—Fixed inductances of the signal type  with magnetic core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/24—Magnetic cores
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/02—Casings
    • H01F27/027—Casings specially adapted for combination of signal type inductors or transformers with electronic circuits, e.g. mounting on printed circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/28—Coils; Windings; Conductive connections
    • H01F27/30—Fastening or clamping coils, windings, or parts thereof together; Fastening or mounting coils or windings on core, casing, or other support
    • H01F27/306—Fastening or mounting coils or windings on core, casing or other support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F3/00—Cores, Yokes, or armatures
    • H01F3/10—Composite arrangements of magnetic circuits
    • H01F3/14—Constrictions; Gaps, e.g. air-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/04—Fixed inductances of the signal type  with magnetic core
    • H01F2017/048—Fixed inductances of the signal type  with magnetic core with encapsulating core, e.g. made of resin and magnetic powder
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Definitions

  • the present invention relates to the field of electronic device packaging technologies, and in particular, to a system-in-package module component, a system-in-package module, and an electronic device.
  • the SiP Module System in Package (ModuleIC) with its miniature size and low power consumption is considered to be the most suitable solution for portable products.
  • the system-in-package module encapsulates a large number of electronic components, such as chips, resistors, and the like, in a very small package.
  • the biggest advantage is that it saves space and consumes less power.
  • the wireless communication module including WLAN, Bluetooth, GPS, WiMAX, and DVB-H/T-DMB can be imported into the electronic device through the system package module.
  • the electronic components such as the control chip, the resistor and the inductor integrated in the existing system package module are disposed on the surface of the substrate, and the inductance is disposed on the upper surface of the chip.
  • the thickness of the system-level package is larger in thickness and does not conform to the portable
  • the product emphasizes the characteristics of thinning.
  • the invention provides a system-level package module assembly, which can reduce the overall thickness space of the system-level package module assembly, thereby realizing the thinning of the electronic product.
  • a first aspect of the present invention provides a system-in-package module assembly including a substrate, a chip electrically connected to the substrate, an inductor, and an electrical component, wherein the substrate includes a first surface, and the first a second surface opposite to the receiving groove, the receiving groove penetrating the second surface and the first surface; the inductor comprises a magnetic core and an inductor embedded in the magnetic core, the magnetic
  • the core includes a base body and a boss protruding from an outer surface of the base body, the base body being provided with the boss The outer surface is in contact with the second surface, the boss is received in the receiving groove, the chip includes a mounting surface, the chip is mounted on the first surface, and the mounting surface is The first surface is oppositely spaced, the boss in the receiving groove is projected on the mounting surface of the chip, and the electrical component is located on the periphery of the chip.
  • the inductor coil includes a connecting segment extending from the magnetic core, and the second surface is provided with a first pad, the connecting segment and the first Pad soldering.
  • the first surface is provided with a second pad
  • the chip is soldered to the second pad by a soldering body
  • the chip There is a gap with the first surface such that heat is dissipated from the core.
  • the inductor coil is embedded in the boss of the magnetic core, or the inductor coil portion is embedded In the boss of the magnetic core, another portion is embedded in the base of the magnetic core.
  • a system-in-package module includes the system-in-package module assembly and the molded body of any one of the possible implementations of the first aspect, wherein the molded body is formed in the On the first surface, and covering the first surface, the chip, the electrical component, and the receiving groove.
  • the molded body can prevent the chip and the electrical component from being damaged.
  • a window is disposed on the plastic package at a position of the chip for exposing the chip to achieve effective heat dissipation of the chip.
  • the system-in-package module further includes a heat dissipation cover, the heat dissipation cover is embedded in the plastic body, and the heat dissipation cover is disposed on the first surface A space is formed between the first surface and the first surface, and the chip and the electrical component are shielded and housed in the space.
  • a surface of the molding body opposite to the second surface is provided with a window for exposing the heat dissipation cover and the first surface The opposite part.
  • the second surface is further provided with a guiding ball electrically connected to the substrate, the guiding The height at which the ball protrudes from the second surface is greater than the thickness of the base of the core.
  • a third aspect of the present invention provides an electronic device, comprising: a circuit board and the system-in-package module assembly described in any one of the foregoing possible aspects, wherein the second surface of the substrate faces the circuit board Soldering with the board.
  • the system-in-package module assembly of the present invention embeds an inductor of an inductor in the substrate, saves space in the thickness direction of the substrate, reduces thickness of the system-in-package module assembly, and saves electronic equipment.
  • the space of thickness enables the purpose of thinning electronic equipment.
  • FIG. 1 is a schematic cross-sectional view of a system-in-package module assembly according to the present invention, wherein a cross-sectional intercept position is a center position of an inductance of the system-in-package module assembly;
  • FIG. 2 is a schematic cross-sectional view of the system-in-package module assembly of FIG. 1 after removing a chip;
  • FIG. 3 and FIG. 4 are two different perspective top views of the system-in-package module assembly shown in FIG. 1;
  • FIG. 5 is a schematic cross-sectional view of a system-in-package module of the present invention, wherein a cross-sectional intercept position is a center position of an inductance of the system-in-package module;
  • FIG. 6 is a schematic cross-sectional view showing the system-level package module of FIG. 5 with a heat dissipation cover;
  • FIG. 7 is a schematic cross-sectional view of the system-in-package module shown in FIG. 6 with the plastic body removed.
  • a system-in-package module assembly of the present invention includes a substrate 10 , a chip 12 electrically connected to the substrate 10 , an inductor 15 , and
  • the electrical component 17 includes a first surface 111, a second surface 112 opposite to the first surface 111, and a receiving groove 113.
  • the receiving groove 113 extends through the second surface 112 and the first surface.
  • the inductor 15 includes a magnetic core 151 and an inductor 153 embedded in the magnetic core 151.
  • the magnetic core 151 includes a base 154 and a boss 155 protruding from an outer surface of the base 154.
  • An outer surface of the base 154 is formed with the outer surface of the boss and the second surface 112 is disposed to cover the receiving slot 113.
  • the boss 155 is received in the receiving slot 113, and the chip 151 includes a mounting surface 120, the chip 12 is mounted on the first surface 111, and the mounting surface 120 is spaced apart from the first surface 111.
  • the boss 155 in the receiving groove 113 is projected onto the first surface 111.
  • the electrical component 17 is located at the periphery of the chip 12.
  • the inductive coil 153 is embedded in the boss 155 of the magnetic core 151, or the inductive coil 153 is partially embedded in the boss 155 of the magnetic core 151, and the other portion is embedded in the magnetic
  • the base 154 of the core 151 is inside.
  • the inductor coil 153 is embedded in the boss 155.
  • the substrate 10 is a rectangular plate body, and the receiving groove 113 is a through groove.
  • the receiving groove 113 is disposed at a central portion of the substrate 10 to penetrate the substrate 10 .
  • a first pad 114 is disposed on the second surface 112, and the first pad 114 is located at opposite sides of the receiving slot 113.
  • the vault 155 is disposed at a central position of the surface of the base 154.
  • the inductive coil 153 includes a connecting portion 156 extending from the boss 155. The inductive coil 153 is received in the receiving slot 113, and the connecting portion 156 protrudes from the receiving slot 113 and the first soldering
  • the disk 114 is soldered to electrically connect the inductor coil 153 to the substrate 10.
  • the substrate 10 when the substrate 10 is in a horizontal plane, the first surface 111 is disposed upward, the chip 12 is mounted on the first surface 111, and the mounting surface 120 is spaced apart from the first surface 111 to The chip 12 can be ensured to have a gap with the first surface, and the mounting surface 120 is located directly above the receiving groove 113.
  • the receiving groove so that the boss 155 can be projected onto the mounting surface 120, so as to dissipate heat from the magnetic core 151.
  • the magnetic core 151 is integrally molded by magnetic powder, that is, the boss 155 is integrally formed with the base 154.
  • the inductor coil 153 is first mounted on the substrate 10, and then the inductor coil 153 is molded by magnetic powder to form a boss 155 and a base 154 covering the inductor coil 153, thereby forming a magnetic core. 151 and the inductance 15 of the inductor 153.
  • the boss 155 fills the entire receiving slot 113. It can be understood that there may be a gap between the boss 155 and the inner side wall of the receiving groove 112.
  • the system-in-package module assembly of the present invention embeds part of the structure of the inductor 15 in the substrate 10, saving space in the thickness direction of the substrate 10, thereby reducing the thickness of the system-in-package module assembly.
  • the first surface 111 is provided with a second pad 115
  • the chip 12 is soldered to the second pad 115 by the solder body 121
  • the chip 12 and the first There is a gap between a surface 111.
  • the solder body 121 is soldered to the second pad 115 in advance
  • the chip 12 is a flip chip
  • the surface facing the first surface 111 and the solder body 121 are fixed by reflow soldering, so that the solder body 121 will
  • the chip support has a gap with the first surface 111, that is, a gap with the boss 155 in the receiving groove 113. It can be understood that the solder body 121 can be preformed on the chip 12 and fixed to the substrate by soldering.
  • a third pad 116 is further disposed on the first surface 111 at an outer position of the second pad 115, and the third pad 116 is used for soldering and fixing with the electrical component 17.
  • the electrical component 17 is a component such as a resistor or a capacitor. It can be understood that the electrical component 17 can also be electrically connected to the substrate 10 by being connected to a wire disposed in the substrate 10; or, the electrical component 17 is provided with a lead, corresponding to the first surface 111 of the substrate 10. A conductive hole is disposed on the lead, and the pin is inserted into the conductive hole and fixed by soldering or the like.
  • the present invention provides a system-in-package module.
  • the system-in-package module includes the system-in-package module assembly and a molding body 20.
  • the molding body 20 is formed on the first surface. 111, covering the first surface 111, the chip 12, the electrical component 17 and the receiving groove 113.
  • the molding body 20 is injection molded on the first surface 111 of the substrate 10 and completely encloses the chip 12 while sealing the boss 155 in the receiving groove 113.
  • the molded body 20 can effectively prevent the chip 12 and the electrical component 17 from being damaged.
  • a window 21 is opened on the molding body 20 at a position of the chip 12, and the window The port 21 is used to expose the chip 12 to facilitate efficient heat dissipation of the chip 12.
  • the window 21 exposes a side of the chip 12 away from the substrate 10.
  • the window 21 removes a portion corresponding to the chip 12 by grinding, thereby exposing Chip 12.
  • the molded body 20 may be formed by masking the exposed portion of the chip to form a partial leakage of the chip 12.
  • the second surface 112 is further provided with a guiding ball 18 electrically connected to the substrate 10, and the height of the guiding ball 18 protruding from the second surface 112 is greater than the thickness of the base 154 of the magnetic core 151. .
  • the second surface 112 is further disposed with a plurality of solder joints 117 around the base 154, and the conductive ball 18 is implanted at the solder joints, and is formed by reflow soldering, wherein the guiding ball 18 is used.
  • the substrate circuit signal is extracted and soldered to the circuit board of the electronic device to electrically connect the substrate 10 and the circuit board of the electronic device.
  • the system-in-package module further includes a heat dissipation cover 22 , the heat dissipation cover 22 is disposed on the first surface 111 and formed between the first surface 111 and the first surface Space, the chip 12 and the electrical component 17 are housed in the space.
  • the heat dissipation cover 22 includes a top wall 221 and a side wall 222 disposed at an edge of the top wall. The sidewall 222 is abutted against the first surface, and the top wall 221 is spaced apart from the first surface 111 to form the space.
  • the chip 12 and the electrical component 17 and the boss 155 located under the chip 12 are located in the Within the space, the chip 12 is in contact with the top wall.
  • the heat shield is used to dissipate heat from the chip 12 and electrical components.
  • the system-in-package module assembly further includes a molding body 24, and the molding body 24 is injection-molded on the first surface 111, And covering the first surface 111, the heat dissipation cover 22, the chip 12, the electrical component 17 and the receiving groove. Further, a window is formed on the surface of the molding body 24 opposite to the second surface 112 for exposing a portion of the heat dissipation cover 22 opposite to the first surface 111. Specifically, the molding body 24 is injection molded on the first surface 111 of the substrate 10, and completely encloses the heat dissipation cover 22 and the chip 12, and simultaneously seals the boss 155 in the receiving groove 113.
  • the molded body 20 can effectively prevent the heat shield 22, the chip 12, and the electrical component 17 from being damaged.
  • a window (not shown) on the molding body 24 faces the top wall 221 of the heat dissipation cover 22, and since the top wall 221 is disposed opposite to the chip 12, the window is used to expose the heat dissipation cover.
  • the heat sink is more effectively dissipated, thereby further dissipating heat to the chip 12.
  • the portion corresponding to the chip 12 is removed by grinding, and then exposed. Chip 12 is output.
  • the present invention also includes an electronic device including a circuit board and the system-in-package module, the second surface 112 of the substrate 10 facing the circuit board and being soldered to the circuit board.
  • the substrate 10 and the circuit board are soldered and fixed by a conductive ball and the substrate 10 and the circuit board are electrically connected.
  • the substrate 10 and the circuit board may also be electrically connected by wires or pads or the like.
  • the system-in-package module assembly of the present invention embeds the inductor coil 153 of the inductor 15 in the substrate 10, and accommodates the core portion in the receiving slot, thereby saving space in the thickness direction of the substrate 10, The thickness of the system-level package module is reduced, thereby saving space for the thickness of the electronic device, and achieving the purpose of thinning the electronic device.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Coils Or Transformers For Communication (AREA)

Abstract

一种系统级封装模块组件，包括基板（10）、与基板电连接的芯片（12）、电感（15）及电器元件（17），基板包括第一表面（111）、与第一表面相对的第二表面（112）及收容槽（113），收容槽贯穿第二表面以及第一表面；电感包括磁芯（151）及电感线圈（153），磁芯包括基体（154）及凸设于基体的一外表面的凸台（155），基体凸设有凸台的外表面与第二表面贴合，凸台收容于收容槽内，电感线圈嵌设于凸台内，芯片包括一安装面（120），芯片装设于第一表面上且安装面与第一表面间隔相对，收容槽内的凸台正投影于芯片的安装面上，电器元件位于芯片周缘。还提供一种系统级封装模块及电子设备。

Description

系统级封装模块组件、系统级封装模块及电子设备
本申请要求于2015年12月28日提交中国专利局、申请号为201510998716.X，发明名称为“系统级封装模块组件、系统级封装模块及电子设备”的中国专利请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及电子器件封装技术领域，尤其涉及一种系统级封装模块组件、系统级封装模块及电子设备。
背景技术
随着可携式消费性电子产品市场快速成长，如何加速改善可携式产品在轻薄短小、低耗电方面的性能，成为系统厂商面临的重要课题。具备微型体积、低耗电特点的系统级封装模块(SiP Module System in Package或称ModuleIC)被视为是最适合应用在可携式产品上的解决方案。
系统级封装模块将大量的电子组件，如芯片、电阻等及线路包覆在极小的封装内最大的优点是可节省空间及低耗电。无线通信模块包括WLAN、Bluetooth、GPS、WiMAX和DVB-H/T-DMB等都可以通过系统封装模块导入电子设备中。现有的系统封装模块整合的控制芯片、电阻及电感等电子元件设于基板的表面，并且电感设置在芯片上方，如此在厚度尺寸上，系统级封装结果的厚度尺寸较大，不符合可携式产品强调的薄型化的特性。
本发明提供了一种系统级封装模块组件，可以减小系统级封装模块组件整体厚度空间，进而实现电子产品的薄型化。
本发明第一方面提供一种系统级封装模块组件，所述系统级封装模块组件包括基板、与所述基板电连接的芯片、电感、电器元件，所述基板包括第一表面、与所述第一表面相对的第二表面及收容槽，所述收容槽贯穿所述第二表面以及所述第一表面；所述电感包括磁芯及嵌设于所述磁芯内的电感线圈，所述磁芯包括基体及凸设于所述基体的一外表面的凸台，所述基体设有所述凸台的 外表面与所述第二表面贴合，所述凸台收容于所述收容槽内，所述芯片包括一安装面，所述芯片装设于所述第一表面上且所述安装面与所述第一表面间隔相对，所述收容槽内的凸台正投影于所述芯片的所述安装面上，所述电器元件位于所述芯片周缘。
在第一方面的第一种可能实现方式中，所述电感线圈包括伸出所述磁芯的连接段，所述第二表面上设有第一焊盘，所述连接段与所述第一焊盘焊接。
结合第一种可能实现方式，在第二种可能的实现方式中，所述第一表面上设有第二焊盘，所述芯片通过焊接体与所述第二焊盘焊接，并且所述芯片与所述第一表面之间具有间隙，如此以便所述磁芯的散热。
结合第一方面、第一种或者第二种可能实现方式，在第三种可能的实现方式中，所述电感线圈嵌设于所述磁芯的凸台内，或者所述电感线圈部分嵌设于所述磁芯的凸台内，另一部分嵌设于所述磁芯的基体内。
本发明第二方面，提供一种系统级封装模块，所述系统级封装模块包括上述第一方面的任一种可能实现方式所述系统级封装模块组件及塑封体，所述塑封体成型于所述第一表面上，并覆盖所述第一表面、所述芯片、所述电器元件及所述收容槽。所述塑封体可以防止芯片、电器元件被损坏。
在第二方面的第一种可能的实现方式中，所述塑封体上位于所述芯片的位置开设有窗口，用于露出所述芯片，实现对芯片进行有效散热。
在第二方面的第二种可能实现方式中，所述系统级封装模块还包括散热罩，所述散热罩嵌设于所述塑封体内，并且所述散热罩罩设于所述第一表面并与第一表面之间形成空间，所述芯片及电器元件遮蔽收容于所述空间内。
结合第二种可能实现方式，在第三种可能的实现方式中，所述塑封体上与所述第二表面相反的表面上开设有窗口，所述用于露出所述散热罩与第一表面相对的部分。
结合第二方面，第二方面的第一至三种可能实现方式，在第四种可能的实现方式中，所述第二表面上还设有与基板电性连接的导接球体，所述导接球体凸出第二表面的高度大于所述磁芯的基体的厚度。
本发明第三方面提供一种电子设备，其包括电路板及以上第二方面任一种可能实现的方式中所述的系统级封装模块组件，所述基板的第二表面朝向所述电路板并与电路板焊接导通。
本发明所述的系统级封装模块组件将电感的电感线圈嵌设于所述基板内，节省所述基板的厚度方向上的空间，减小了系统级封装模块组件的厚度，进而节省了电子设备厚度的空间，实现电子设备薄型化的目的。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明提供的系统级封装模块组件的截面示意图，其中，截面截取位置为所述系统级封装模块组件的电感的中心位置；
图2为图1所示的系统级封装模块组件的去除芯片后的截面示意图；
图3与图4为图1所示的系统级封装模块组件的两个不同角度俯视图；
图5为本发明的系统级封装模块的截面示意图，其中截面截取位置为所述系统级封装模块的电感的中心位置；
图6为图5所述的系统级封装模块设有散热罩的截面示意图；
图7为图6所示的系统级封装模块去除塑封体的截面示意图。
具体实施方式
为使得本发明的发明目的、特征、优点能够更加的明显和易懂，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，下面所描述的实施例仅仅是本发明一部分实施例，而非全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本发明的实施例例如能够以除了在这里图示或描述的那些以外的顺序 实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
下面通过具体实施例，分别进行详细的说明。
请参考图1、图2与图3，本发明一种系统级封装模块组件，其特征在于：所述系统级封装模块组件包括基板10、与所述基板10电连接的芯片12、电感15及电器元件17，所述基板10包括第一表面111、与所述第一表面111相对的第二表面112及收容槽113，所述收容槽113贯穿所述第二表面112以及所述第一表面111；所述电感15包括磁芯151及嵌设于所述磁芯151内的电感线圈153，所述磁芯151包括基体154及凸设于所述基体154的个外表面的凸台155。所述基体154凸设有所述凸台的一个外表面与所述第二表面112贴合并覆盖所述收容槽113，所述凸台155收容于所述收容槽113内，所述芯片151包括一安装面120，所述芯片12装设于所述第一表面111上且所述安装面120与所述第一表面111间隔相对，所述收容槽113内的凸台155正投影于所述芯片12的所述安装面120上，所述电器元件17位于所述芯片12周缘。
进一步的，所述电感线圈153嵌设于所述磁芯151的凸台155内，或者所述电感线圈153部分嵌设于述磁芯151的凸台155内，另一部分嵌设于所述磁芯151的基体154内。本实施例中，所述电感线圈153嵌设于所述凸台155内。
请一并参阅图4，本实施例中，所述基板10为矩形板体，所述收容槽113为通槽，所述收容槽113设于所述基板10的中部位置贯穿所述基板10。所述第二表面112上设有第一焊盘114，所述第一焊盘114位于所述收容槽113相对两侧位置。所诉凸台155是设置于所述基体154的表面的中部位置。所述电感线圈153包括伸出所述凸台155的连接段156，所述电感线圈153收容于所述收容槽113内，所述连接段156伸出所述收容槽113与所述第一焊盘114焊接，进而实现所述电感线圈153与所述基板10的电性连接。需要说明的是，当所述基板10位于水平面时，所述第一表面111朝上设置，所述芯片12装于第一表面111上，安装面120与所述第一表面111间隔相对，以保证芯片12与第一表面可以有间隙，同时安装面120是位于所述收容槽113的正上方朝向 所述收容槽，进而使所述凸台155可以正投影于所述安装面120上，如此以便所述磁芯151的散热。
复参图1-2，所述磁芯151通过磁粉一体成型，即所述凸台155与所述基体154一体成型。本实施例中，将所述电感线圈153先装设于所述基板10上，然后通过磁粉塑封所述电感线圈153，形成包覆电感线圈153的凸台155及基体154，进而形成包括磁芯151与电感线圈153的所述电感15。其中，所述凸台155填充满整个收容槽113。可以理解，所述凸台155与所述收容槽112的槽内侧壁之间也可以有间隙。本发明所述的系统级封装模块组件将电感15的部分结构嵌设于所述基板10内，节省所述基板10的厚度方向上的空间，进而减小了系统级封装模块组件的厚度。
复参图3，进一步的，所述第一表面111上设有第二焊盘115，所述芯片12通过焊接体121与所述第二焊盘115焊接，并且所述芯片12与所述第一表面111之间具有间隙。具体的，所述焊接体121预先焊接于第二焊盘115，所述芯片12为倒装芯片，其朝向第一表面111的表面与焊接体121通过回流焊接固定，这样焊接体121将所述芯片支撑使其与第一表面111具有间隙，也就是与收容槽113内的凸台155之间具有间隙。可以理解，所述焊接体121可以预先成型于芯片12上，通过焊接方式与基板固定。
进一步的，所述第一表面111上位于所述第二焊盘115的外侧位置还设有第三焊盘116，所述第三焊盘116用于与所述电器元件17焊接固定。本实施例中，所述电器元件17被电阻、电容等元器件。可以理解，所述电器元件17也可以与设于基板10内的导线连接而实现与基板10电性连接；或者，所述电器元件17上设置引脚，相应的在基板10的第一表面111上设置导电孔，引脚插入导电孔并通过焊锡等方式固定。
请参阅图5，本发明提供一种系统级封装模块所述系统级封装模块包括所述系统级封装模块组件及塑封体20，本实施例中，所述塑封体20成型于所述第一表面111上，并覆盖所述第一表面111、所述芯片12、所述电器元件17及所述收容槽113。具体的，所述塑封体20通过注塑成型于所述基板10的第一表面111上，并完全包封所述芯片12，同时将所述凸台155密封于所述收容槽113内，所述塑封体20可以有效防止芯片12、电器元件17被损坏。更进一步的，所述塑封体20上位于所述芯片12的位置开设有窗口21，所述窗 口21用于露出所述芯片12，方便芯片12进行有效散热。本实施例中，所述窗口21露出所述芯片12远离所述基板10的一侧，所述窗口21在所述塑封体20形成后，通过研磨方式将与芯片12对应的部分去掉，进而露出芯片12。在其它实施方式中，可以通过贴膜包封的方式将芯片需要露出部分隔离后成型所述塑封体20，实现芯片12的部分外漏。
进一步的，所述第二表面112上还设有与基板10电性连接的导接球体18，所述导接球体18凸出第二表面112的高度大于所述磁芯151的基体154的厚度。具体的，所述第二表面112上位于所述基体154周围还设有数个焊点117，在焊点处植入所述导接球体18，并通过回流焊接成型，其中，导接球体18用于引出基板电路信号，并与电子设备的电路板焊接，进而实现所述基板10与所述电子设备的电路板电性导通。
请参阅图6与图7，本发明另一实施方式中，所述系统级封装模块还包括散热罩22，所述散热罩22罩设于所述第一表面111并与第一表面之间形成空间，所述芯片12及电器元件17收容于所述空间内。具体的，散热罩22包括顶壁221及设于顶壁边缘的侧壁222。所述侧壁222与第一表面抵持，所述顶壁221与第一表面111间隔相对进而形成所述空间，所述芯片12及电器元件17及位于芯片12下方的凸台155位于所述空间内，所述芯片12与所述顶壁接触。所述散热罩用于对芯片12及电器元件的散热。
本实施实力中，当所述系统级封装模块还包括散热罩22时，所述系统级封装模块组件还的塑封体24，所述塑封体24模内注塑成型于所述第一表面上111，并覆盖所述第一表面111、所述散热罩22、所述芯片12、所述电器元件17及所述收容槽。更进一步的，所述塑封体24上与所述第二表面112相反的表面上开设有窗口，所述用于露出所述散热罩22与第一表面111相对的部分。具体的，所述塑封体24通过注塑成型于所述基板10的第一表面111上，并完全包封所述散热罩22、芯片12，同时将所述凸台155密封于所述收容槽113内，所述塑封体20可以有效防止散热罩22、芯片12、电器元件17被损坏。所述塑封体24上的窗口(图未标)正对所述散热罩22的顶壁221，由于所述顶壁221与所述芯片12相对设置，所以所述窗口用于露出散热罩，使散热罩更有效散热，进而实现对所述芯片12进一步的散热。本实施例中，所述窗口在所述塑封体24形成后，通过研磨方式将与芯片12对应的部分去掉，进而露 出芯片12。
本发明还包括一种电子设备，其包括电路板及所述的系统级封装模块，所述基板10的第二表面112朝向所述电路板并与电路板焊接导通。本实施例中，所述基板10与所述电路板通过导接球体焊接固定并实现基板10与电路板导通。在其它实施方式中，所述基板10与所述电路板也可以通过导线或者焊盘等其它方式导通。
本发明所述的系统级封装模块组件将电感15的电感线圈153嵌设于所述基板10内，并使磁芯部分收容于收容槽内，节省所述基板10的厚度方向上的空间，减小了系统级封装模块的厚度，进而节省了电子设备厚度的空间，实现电子设备薄型化的目的。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (10)

  1. 一种系统级封装模块组件，其特征在于：所述系统级封装模块组件包括基板、与所述基板电连接的芯片、电感、电器元件，所述基板包括第一表面、与所述第一表面相对的第二表面及收容槽，所述收容槽贯穿所述第二表面以及所述第一表面；所述电感包括磁芯及嵌设于所述磁芯内的电感线圈，所述磁芯包括基体及凸设于所述基体的一外表面的凸台，所述基体设有所述凸台的外表面与所述第二表面贴合，所述凸台收容于所述收容槽内，所述芯片包括一安装面，所述芯片装设于所述第一表面上且所述安装面与所述第一表面间隔相对，所述收容槽内的凸台正投影于所述芯片的所述安装面上，所述电器元件位于所述芯片周缘。
  2. 根据权利要求1所述的系统级封装模块组件，其特征在于：所述电感线圈包括伸出所述磁芯的连接段，所述第二表面上设有第一焊盘，所述连接段与所述第一焊盘焊接。
  3. 根据权利要求2所述的系统级封装模块组件，其特征在于：所述第一表面上设有第二焊盘，所述芯片通过焊接体与所述第二焊盘焊接，并且所述芯片与所述第一表面之间具有间隙。
  4. 根据权利要求1-3任一项所述的系统级封装模块组件，其特征在于：所述电感线圈嵌设于所述磁芯的凸台内，或者所述电感线圈部分嵌设于所述磁芯的凸台内，另一部分嵌设于所述磁芯的基体内。
  5. 一种系统级封装模块，其特征在于：所述系统级封装模块包括如权利要求1-4任一项所述系统级封装模块组件及塑封体，所述塑封体成型于所述第一表面上，并覆盖所述第一表面、所述芯片、所述电器元件及所述收容槽。
  6. 根据权利要求5所述的系统级封装模块，其特征在于：所述塑封体上位于所述芯片的位置开设有窗口，用于露出所述芯片。
  7. 根据权利要求5所述的系统级封装模块，其特征在于：所述系统级封装模块还包括散热罩，所述散热罩嵌设于所述塑封体内，并且所述散热罩罩设于所述第一表面并与第一表面之间形成空间，所述芯片及电器元件遮蔽收容于所述空间内。
  8. 根据权利要求7所述的系统级封装模块，其特征在于：所述塑封体上与所述第二表面相反的表面上开设有窗口，所述用于露出所述散热罩与第一表面相对的部分。
  9. 根据权利要求5-8任一项所述的系统级封装模块组件，其特征在于：所述第二表面上还设有与基板电性连接的导接球体，所述导接球体凸出第二表面的高度大于所述磁芯的基体的厚度。
  10. 一种电子设备，其特征在于：包括电路板及权利要求6-9任一项所述的系统级封装模块，所述基板的第二表面朝向所述电路板并与电路板焊接导通。
PCT/CN2016/111735 2015-12-28 2016-12-23 系统级封装模块组件、系统级封装模块及电子设备 WO2017114311A1 (zh)

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