WO2017112327A1 - Boîtiers de dispositif électronique avec blindage emi et procédés associés - Google Patents

Boîtiers de dispositif électronique avec blindage emi et procédés associés Download PDF

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Publication number
WO2017112327A1
WO2017112327A1 PCT/US2016/063731 US2016063731W WO2017112327A1 WO 2017112327 A1 WO2017112327 A1 WO 2017112327A1 US 2016063731 W US2016063731 W US 2016063731W WO 2017112327 A1 WO2017112327 A1 WO 2017112327A1
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WO
WIPO (PCT)
Prior art keywords
electronic device
device package
layer
substrate
electronic
Prior art date
Application number
PCT/US2016/063731
Other languages
English (en)
Inventor
Eric Li
Joshua HEPPNER
Rajendra Dias
Mitul Modi
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to CN201680068857.4A priority Critical patent/CN108292646B/zh
Publication of WO2017112327A1 publication Critical patent/WO2017112327A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • Embodiments described herein relate generally to electronic device packages.
  • Electromagnetic interference (EMI) shielding is routinely used on electronic device packages with small form factors. EMI shielding is important when electronic components are positioned close together in order to reduce or prevent disturbances in operation.
  • One mechanism for creating EMI shielding is with a conformal sputtering technique. In this case, the material of the EMI shield is sputtered or deposited on an exposed outer surface of the electronic device package to a desired thickness in order to create an EMI shield layer.
  • FIG. 1 illustrates an electronic device package in accordance with an example
  • FIG. 2 illustrates a schematic representation of a top view of the electronic device package of FIG. 1 ;
  • FIG. 3 illustrates a substrate with electronic components disposed thereon in accordance with an example of a method for making an electronic device package
  • FIG. 4 illustrates positioning a mold chase to assist in encapsulating electronic components on a substrate in a mold compound in accordance with an example of a method for making an electronic device package
  • FIG. 5 illustrates encapsulating a mold compound over electronic components on a substrate by molding the mold compound about the electronic components in accordance with an example of a method for making an electronic device package
  • FIG. 6 illustrates a substrate with electronic components thereon and a layer of mold compound encapsulating the electronic components following removal of a mold chase in accordance with an example of a method for making an electronic device package
  • FIG. 7 illustrates dividing a substrate with a mold compound thereon between electronic components in order to separate the electronic components from one another into discrete packages in accordance with an example of a method for making an electronic device package
  • FIG. 8 illustrates electronic device packages following separation from a common substrate in accordance with an example of a method for making an electronic device package
  • FIG. 9 illustrates electronic device packages with an EMI material layer formed thereon in accordance with an example of a method for making an electronic device package
  • FIG. 10 illustrates an electronic device package with an EMI material layer formed thereon in accordance with another example
  • FIG. 1 1 illustrates a substrate with electronic components disposed thereon accordance with an example of a method for making an electronic device package
  • FIG. 12 illustrates a mold compound encapsulating electronic
  • FIG. 13 illustrates dividing the substrate with a mold compound thereon between electronic components in order to separate the electronic components from one another into discrete packages in accordance with an example of a method for making an electronic device package
  • FIG. 14 illustrates electronic device packages after separation in accordance with an example of a method for making an electronic device package
  • FIG. 15 illustrates electronic device packages with an EMI layer formed thereon in accordance with an example of a method for making an electronic device package
  • FIG. 16 is a schematic illustration of an exemplary computing system.
  • Consisting essentially of or “consists essentially of” have the meaning generally ascribed to them by U.S. Patent law. In particular, such terms are generally closed terms, with the exception of allowing inclusion of additional items, materials, components, steps, or elements, that do not materially affect the basic and novel characteristics or function of the item(s) used in connection therewith. For example, trace elements present in a composition, but not affecting the composition's nature or characteristics would be permissible if present under the “consisting essentially of” language, even though not expressly recited in a list of items following such terminology.
  • an open ended term in the specification like “comprising” or “including,” it is understood that direct support should be afforded also to “consisting essentially of” language as well as “consisting of” language as if stated explicitly and vice versa.
  • the term “substantially” refers to the complete or nearly complete extent or degree of an action, characteristic, property, state, structure, item, or result.
  • an object that is “substantially” enclosed would mean that the object is either completely enclosed or nearly completely enclosed.
  • the exact allowable degree of deviation from absolute completeness may in some cases depend on the specific context. However, generally speaking the nearness of completion will be so as to have the same overall result as if absolute and total completion were obtained.
  • compositions that is "substantially” is equally applicable when used in a negative connotation to refer to the complete or near complete lack of an action, characteristic, property, state, structure, item, or result.
  • a composition that is “substantially free of” particles would either completely lack particles, or so nearly completely lack particles that the effect would be the same as if it completely lacked particles.
  • a composition that is "substantially free of” an ingredient or element may still actually contain such item as long as there is no measurable effect thereof.
  • EMI shielding layers are often created using a deposition technique, such as conformal sputtering. Such techniques typically have a slow deposition rate which can limit the overall throughput of the process. In addition, such processes are typically highly directional processes where the deposition rate onto the sides of an object can be significantly lower than the deposition rate onto the top of an object (e.g., the side deposition rate can be about 50% of the top deposition rate). As a result, an EMI shielding layer created by such a technique often has more material on a top surface than is needed for an effective EMI shield, thus wasting material and slowing throughput of the process.
  • a deposition technique such as conformal sputtering.
  • Such techniques typically have a slow deposition rate which can limit the overall throughput of the process.
  • such processes are typically highly directional processes where the deposition rate onto the sides of an object can be significantly lower than the deposition rate onto the top of an object (e.g., the side deposition rate can be about 50% of the top deposition rate).
  • an electronic device package can include a bottom surface and a side surface extending from the bottom surface. The side surface can be oriented at a non-perpendicular angle relative to the bottom surface.
  • an electronic device package can include a top planar surface having a first area, a bottom planar surface having a second area, and a side surface extending between the top surface and the bottom surface. The second area can be larger than the first area.
  • an electronic device package can include a substrate defining a plane, an electronic component disposed on the substrate, and a layer of material disposed about a lateral side of the electronic component.
  • the layer of material can be oriented at an angle of less than 90 degrees relative to the plane.
  • the electronic device package 100 can include a substrate 1 10 and an electronic component 120 disposed on the substrate 1 10, such as on a top surface 1 1 1 of the substrate 1 10.
  • the substrate 1 10 can include a grounding plane or trace 1 15 that can extend between lateral side surfaces 1 12, 1 13 of the substrate 1 10.
  • the electronic component 120 can be any electronic device or component that may be included in an electronic device package, such as a semiconductor device (e.g., a die, a chip, or a processor).
  • the electronic component 120 can be encapsulated, such as with a mold compound or material 130 (e.g., an epoxy), to protect the electronic component 120 as well as electrical traces (not shown) or other electrical features or connections.
  • the mold compound 130 can envelope the electronic component 120 and overlay the top surface 1 1 1 of the substrate 1 10.
  • a top surface 130 can have any suitable shape or configuration.
  • a top surface 130 can have any suitable shape or configuration. For example, a top surface
  • the side surfaces 132, 133 of the mold compound 130 can be planar surfaces, curved surfaces, etc.
  • the electronic device package 100 can have a top surface 161 , side surfaces 162, 163, and a bottom surface 164.
  • the side surfaces 162, 163 can extend from the bottom surface 164, such as between the top surface 161 and the bottom surface 164.
  • the electronic device package 100 can also include a layer 140 of material disposed about one or more sides of the package.
  • one or more of the surfaces 161 -164 of the electronic device package 100 can be formed by the layer 140 of material.
  • the top surface 161 and the side surfaces 162, 163 can be formed by the layer 140 of material.
  • portions of the layer 140 of material can be disposed about a top side 151 and/or one or more lateral sides 152, 153 of the electronic component 120. Furthermore, a portion of the layer 140 of material can be disposed about a portion of the substrate 1 10, such as about a lateral side of the substrate 1 10. In one aspect, the layer 140 of material can be a continuous layer or a discontinuous layer. In another aspect, the layer 140 of material can be the same material on the top surface 161 as on the side surface 162 and/or the side surface 163. Some portion of the substrate 1 10 can remain uncovered by the layer 140 of material, such as a bottom surface 1 14 of the substrate 1 10. In this case, the bottom surface 1 14 of the substrate 1 10 can form the bottom surface 164 of the electronic device package 100.
  • the layer 140 of material as a whole, or individual portions can be of any suitable shape or configuration.
  • the portion of the layer 140 of material disposed about the top side 151 of the electronic component 120 can be planar, as illustrated.
  • the portions of the layer 140 of material disposed about the lateral side 152 and/or the lateral side 153 can be planar.
  • the layer 140 of material will have generally the same shape or configuration as the surfaces 131 -133 of the underlying mold compound 130 and or the side surfaces 1 12, 1 13 of the substrate 1 10.
  • the layer 140 of material can form at least a portion of an EMI shield for the electronic component 120.
  • the layer 140 of material forming the top surface 161 and the side surfaces 162, 163 can form an EMI shield with the grounding plane or trace 1 15 included in the substrate 1 10.
  • at least a portion of the layer 140 can be formed of an electrically conductive material.
  • the mold compound 130 can be a dielectric or electrically insulating material disposed between the electronic component 120 and the layer 140 of material. Any suitable dielectric or insulating material can be utilized in the mold compound 130. It should be recognized that the top surface 161 , the side surface 162, and the side surface 163 can be formed at least in part by the layer 140 of material and configured individually or in any combination as an EMI shield.
  • the layer 140 of material can have a thickness 105a on the top surface 161 that is equal to, or substantially equal to, a thickness 105b on the at least one of the side surfaces 162, 163.
  • the thickness 105b of the layer 140 of material on the side surface 162, 163 can be within about 80% of the thickness 105a of the layer 140 of material on the top surface 161 .
  • the thickness 105a and/or the thickness 105b of the layer 140 of material can be from about 0.5 ⁇ to about 15 ⁇ . In a particular aspect, thickness 105a and/or the thickness 105b can be from about 2 ⁇ to about 5 ⁇ . If the layer 140 of material is configured as an EMI shield, the thicknesses 105a, 105b can be increased if a less conductive material is used, such as for cost savings.
  • the substrate 1 10 can define a plane 1 16, such as with the top surface 1 1 1 of the substrate 1 10.
  • the substrate 1 10 can also define a plane 1 17, such as with the bottom surface 1 14 of the substrate 1 10.
  • at least a portion of the layer 140 of material can be oriented at an angle 102a, 102b of less than 90 degrees relative to the plane 1 16 and/or oriented at an angle 103a, 103b of less than 90 degrees relative to the plane 1 17.
  • each side surface 162, 163 can be oriented at a non- perpendicular angle relative to the bottom surface 164.
  • each side surface 162, 163 can be oriented at a non-perpendicular angle 104a, 104b, respectively, relative to the top surface 161 .
  • the side surfaces 162, 163 can each have a first portion 166a, 167a extending from the bottom surface 164 and oriented at the angle 103a, 103b relative to the bottom surface 164.
  • the first portions 166a, 167a can be disposed about the lateral sides of the substrate 1 10.
  • the side surfaces 162, 163 can each have a second portion 166b, 167b extending from the top surface 161 and oriented at the angle 104a, 104b relative to the top surface 161 .
  • the second portions 166b, 167b can be disposed on and/or about the lateral sides of the mold compound 130.
  • the angle 103a and the angle 104a can be equal or different from one another.
  • the angle 103b and the angle 104b can be equal or different from one another.
  • the angles on the same side of the electronic device package 100 can be the same or different from one another.
  • the angle 103a and the angle 103b can be equal or different from one another.
  • the angle 104a and the angle 104b can be equal or different from one another.
  • the angles on opposite sides of the electronic device package 100 can be the same or different from one another.
  • a component of the electronic device package 100 can include the top side 151 and the lateral side 152 and/or the lateral side 153 of the layer 140 of a conductive material, where one or both of the lateral side conductive layers is oriented at the non-perpendicular angle 104a, 104b relative to the top conductive layer.
  • an area 168 of the bottom surface 164 can be larger than an area 169 of the top surface 161 .
  • the top and bottom surfaces 161 , 164 can be planar in this example, although other configurations are possible.
  • Length 106a and width 107a dimensions of the bottom surface 164 can be greater than corresponding length 106b and width 107b dimensions of the top surface 161 .
  • FIGS. 3-9 illustrate an exemplary method or process for making an electronic device package, such as the electronic device package 100.
  • FIG. 3 illustrates a substrate 109 with electronic components 120, 120', 120" disposed on the substrate 109.
  • FIG. 4 illustrates a mold chase 170, which can be used to aid in encapsulating the electronic components 120, 120', 120", in a mold compound
  • FIG. 5 illustrates encapsulating the electronic components 120, 120', 120" in a mold compound 129 by molding the mold compound 129 about the electronic components 120, 120', 120".
  • Molding can include any suitable type of molding process, such as a transfer molding process and/or a compression molding process.
  • FIG. 3 illustrates a substrate 109 with electronic components 120, 120', 120" disposed on the substrate 109.
  • FIG. 4 illustrates a mold chase 170, which can be used to aid in encapsulating the electronic components 120, 120', 120", in a mold compound
  • FIG. 5 illustrates encapsulating the
  • mold chase 170 can be configured and positioned relative to the substrate 109 to minimize or prevent the formation of the mold compound portions 136, 137.
  • the side surface 132 about a lateral side of the electronic component 120 can be formed on the mold compound 129 such that the side surface 132 is oriented at the angle 102a relative to the plane 1 16 defined by the substrate 109 and/or the angle 103a relative to the plane 1 17 defined by the substrate 109.
  • the side surface 133 about a lateral side of the electronic component 120 can also be formed on the mold compound 129 such that the side surface 133 is oriented at the angle 102b relative to the plane 1 16 and/or the angle 103b relative to the plane 1 17.
  • the side surface 132 can be oriented at the angle 104a relative to the top surface 131 about a top side of the electronic component 120.
  • the side surface 133 can be oriented at the angle 104b relative to the top surface 131 .
  • the angles 102a-b, 103a-b, 104a-b are less than 90 degrees.
  • Similar side surfaces can be formed in the mold compound 129 about the electronic components 120', 120".
  • FIG. 7 illustrates dividing the substrate 109 and the mold compound 129 between the electronic components 120, 120', 120" in order to separate the electronic components from one another into discrete packages.
  • the substrate 109 can be subdivided into substrates of individual packages, such as the substrate 1 10 (see FIG. 8).
  • the mold compound 129 can be subdivided into mold compounds of individual packages, such as the mold compound 130 (see FIG. 8).
  • FIG. 7 illustrates dividing the substrate 109 and the mold compound 129 by cutting, such as with a saw blade 180 (shown in two positions).
  • any suitable technique including mechanical and chemical techniques, can be utilized to divide or separate the substrate 109 and/or the mold compound 129, such as cutting (e.g., laser), sawing, shearing, milling, broaching, etching, etc. Due to formation of the side surfaces 132, 133 of the mold compound 130 by the mold chase 170 and the minimized size or absence of the mold compound portions 136, 137, the thickness 106 of the material to be divided can be minimized, which can simplify and the process of forming individual packages.
  • cutting e.g., laser
  • sawing e.g., sawing, shearing, milling, broaching, etching, etc. Due to formation of the side surfaces 132, 133 of the mold compound 130 by the mold chase 170 and the minimized size or absence of the mold compound portions 136, 137, the thickness 106 of the material to be divided can be minimized, which can simplify and the process of forming individual packages.
  • Dividing the substrate 109 can form the side surfaces 1 12, 1 13 of the substrate 1 10, as shown in FIG. 8.
  • the substrate 109 can be divided to form the side surface 1 12 of the substrate 1 10 oriented at the angle 102a relative to the plane 1 16 and/or the angle 103a relative to the plane 1 17.
  • the substrate 109 can be divided to form the side surface 1 13 of the substrate 1 10 oriented at the angle 102b relative to the plane 1 16 and/or the angle 103b relative to the plane 1 17.
  • Similar side surfaces can be formed from the substrate 109 on subdivided substrates 1 10', 1 10".
  • angles of the side surfaces 1 12, 132 of the substrate 1 10 and the mold compound 130 relative to the plane 1 16 and/or the plane 1 17 are equal.
  • angles of the side surfaces 1 13, 133 of the substrate 1 10 and the mold compound 130 relative to the plane 1 16 and/or the plane 1 17 are equal. It should be recognized, however, that angles of substrate and mold compound side surfaces of can be different.
  • the saw blade 180 can be beveled to provide the angled substrate side surfaces 1 12, 1 13.
  • a component of the electronic device package 100 can include the top molded surface 131 and the side molded surface 132 and/or the side molded surface 133, where one or both of the side molded surfaces is oriented at a non- perpendicular angle relative to the top molded surface.
  • the layer 140 of material can be formed on the surfaces 131 -133 of the mold compound 130 to form the electronic device package 100. Portions of the layer 140 of material can be disposed about top and lateral sides of the electronic component 120. In addition, a portion of the layer 140 of material can be formed on a surface of the substrate 1 10, such as on the side surfaces 1 12, 1 13 of the substrate.
  • the layer 140 can be formed by depositing material on the mold compound 130 and the substrate 1 10. Material can be deposited in any suitable manner, such as by a sputtering process.
  • material will be deposited in a direction perpendicular to the top surface 131 of the mold compound 130, the top surface 1 1 1 of the substrate 1 10, and/or the bottom surface 1 14 of the substrate 1 10. It should be recognized that material can be deposited in any suitable direction relative to such features in order to deposit material in a direction that is non- parallel to the lateral side surfaces 132, 133 of the mold compound 130 and the side surfaces 1 12, 1 13 of the substrate 1 10.
  • the orientation of the lateral side surfaces 132, 133 of the mold compound 130 and the side surfaces 1 12, 1 13 of the substrate 1 10 can be configured based on the material deposition direction such that the side surfaces are oriented non-parallel to the deposition direction.
  • the orientation of the top surface 131 of the mold compound 130 can be perpendicular to the deposition direction.
  • the sputtering deposition rate onto the side surfaces can be increased, thereby improving process throughput speed and material usage efficiency.
  • Increased deposition rate onto the side surfaces can reduce the disparity in layer 140 thickness between the top and side surfaces.
  • layer 140 thickness uniformity can be maximized by minimizing a perpendicular orientation of the side surfaces 162, 163 relative to the top surface 161 of the electronic device package 100.
  • angles 102a-b, 103a-b, 104a-b can range from less than 90 degrees to greater than 0 degrees, limited only by practical considerations such as package size, which may be increased as these angles decrease thereby
  • a portion of the lateral side surface 162, 163 can extend over or above a portion of the electronic component 120, which can facilitate minimizing the angles 102a-b, 103a-b, 104a-b (e.g., minimizing the perpendicular orientation of the side surfaces 162, 163 relative to the top surface 161 ) while also minimizing the size of the package 100 for given angles 102a-b, 103a-b, 104a-b.
  • the layer 140 of material can form an electromagnetic shield as discussed above.
  • a component of the electronic device package 100 can include the layer 140 of material deposited on the top and side molded surfaces 131 -133.
  • the layer 140 of material can provide electromagnetic interference shielding.
  • FIG. 10 illustrates an electronic device package 200 in accordance with another example.
  • the electronic device package 200 is similar in many respects to the electronic device package 100 discussed above.
  • the electronic device package 200 includes a substrate 210, an electronic component 220, a mold compound 230, and a layer 240 of material, as discussed above.
  • the electronic component 220 can be disposed on a top surface 21 1 of the substrate 210
  • the mold compound 230 can encapsulate the electronic component 220
  • the layer 240 of material can form an EMI shield about the electronic component 220, such with a grounding plane or trace 215 in the substrate 210.
  • the electronic device package 200 can have a top surface 261 , side surfaces 262, 263, and a bottom surface 264.
  • the side surfaces 262, 263 can extend from the bottom surface 264, such as between the top surface 261 and the bottom surface 264.
  • the layer 240 of material can be disposed about one or more sides of the electronic device package 200.
  • one or more of the surfaces 261 -264 of the electronic device package 200 can be formed by the layer 240 of material.
  • the top surface 261 and the side surfaces 262, 263 can be formed by the layer 240 of material.
  • portions of the layer 240 of material can be disposed about a top side 251 and/or one or more lateral sides 252, 253 of the electronic component 220. Furthermore, a portion of the layer 240 of material can be disposed about a portion of the substrate 210, such as about a lateral side of the substrate 210. A bottom surface 214 of the substrate 210 can form the bottom surface 264 of the electronic device package 200.
  • the layer 240 of material can have a thickness 205a on the top surface 261 that is equal to a thickness 205b on the side surface 262, 263.
  • the thickness 205b of the layer 240 of material on the side surface 262, 263 can be within about 80% of the thickness 205a of the layer 240 of material on the top surface 261 .
  • the thickness 205a and/or the thickness 205b of the layer 240 of material can be from about 0.5 ⁇ to about 15 ⁇ . In a particular aspect, thickness 205a and/or the thickness 205b can be from about 2 ⁇ to about 5 ⁇ .
  • the substrate 210 can define a plane 216, such as with the top surface 21 1 of the substrate 210.
  • the substrate 210 can also define a plane 217, such as with the bottom surface 214 of the substrate 210.
  • at least a portion of the layer 240 of material can be oriented at an angle 202a, 202b of less than 90 degrees relative to the plane 216 and/or oriented at an angle 203a, 203b of less than 90 degrees relative to the plane 217.
  • each side surface 262, 263 can be oriented at a non-perpendicular angle relative to the bottom surface 264.
  • each side surface 262, 263 can be oriented at a non-perpendicular angle 204a, 204b, respectively, relative to the top surface 261 .
  • the angle 202a and the angle 202b can be equal or different from one another.
  • the angle 203a and the angle 203b can be equal or different from one another.
  • the angle 204a and the angle 204b can be equal or different from one another.
  • the angles on opposite sides of the electronic device package 200 can be the same or different from one another.
  • FIGS. 1 1 -15 illustrate a method for making an electronic device package, such as the electronic device package 200.
  • FIG. 1 1 illustrates a substrate 209 with electronic components 220, 220', 220" disposed on the substrate 209.
  • FIG. 12 illustrates encapsulating the electronic components 220, 220', 220" in a mold compound 229 by molding the mold compound 229 about the electronic components 220, 220', 220".
  • Molding can include any suitable type of molding process, such as a transfer molding process and/or a compression molding process.
  • FIG. 13 illustrates dividing the substrate 209 and the mold compound 229 between the electronic components 220, 220', 220" in order to separate the electronic components from one another into discrete packages.
  • the substrate 209 can be subdivided into substrates of individual packages, such as the substrate 210 (see FIG. 14).
  • the mold compound 229 can be subdivided into mold compounds of individual packages, such as the mold compound 230 (see FIG. 14).
  • FIG. 13 illustrates dividing the substrate 209 and the mold compound 229 by cutting, such as with a saw blade 280 (shown in two positions). Any suitable technique can be utilized to divide or separate the substrate 209 and/or the mold compound 229, such as cutting (e.g., laser), sawing, shearing, milling, broaching, etc.
  • cutting e.g., laser
  • Dividing the substrate 209 can form the side surfaces 232, 223 of the mold compound 230 and the side surfaces 212, 213 of the substrate 210, as shown in FIG. 14.
  • the mold compound 229 can be divided to form the side surface 232 of the mold compound 230 oriented at the angle 202a relative to the plane 216 and/or the angle 203a relative to the plane 217.
  • the mold compound 229 can be divided to form the side surface 233 of the mold compound 230 oriented at the angle 202b relative to the plane 216 and/or the angle 203b relative to the plane 217.
  • the side surface 232 of the mold compound 230 can be oriented at the angle 204a relative to the top surface 231 of the mold compound 230.
  • the side surface 233 of the mold compound 230 can be oriented at the angle 204b relative to the top surface 231 of the mold compound 230.
  • Similar side surfaces can be formed from the mold compound 229 about the electronic components 220', 220".
  • the side surfaces 232, 233 can be formed by removing a portion of the mold compound material 229.
  • the substrate 209 can be divided to form the side surface 212 of the substrate 210 oriented at the angle 202a relative to the plane 216 and/or the angle 203a relative to the plane 217.
  • the substrate 209 can be divided to form the side surface 213 of the substrate 210 oriented at the angle 202b relative to the plane 216 and/or the angle 203b relative to the plane 217.
  • the angles 202a-b, 203a-b, 204a-b are less than 90 degrees.
  • Similar side surfaces can be formed from the substrate 209 on subdivided substrates 210', 210".
  • the saw blade 280 can be beveled to provide the angled mold compound side surfaces 232, 233 and the angled substrate side surfaces 212, 213.
  • a component of the electronic device package 200 can include the top mold compound surface 231 and the side mold compound surface 232 and/or the side mold compound surface 233, where one or both of the side mold compound surfaces is oriented at a non-perpendicular angle relative to the top mold compound surface.
  • the layer 240 of material can be formed on the surfaces 231 -233 of the mold compound 230 to form the electronic device package 200. Portions of the layer 240 of material can be disposed about top and lateral sides of the electronic component 220. In addition, a portion of the layer 240 of material can be formed on a surface of the substrate 210, such as on the side surfaces 212, 213 of the substrate.
  • the layer 240 can be formed by depositing material on the mold compound 230 and the substrate 210. Material can be deposited in any suitable manner, such as by a sputtering process.
  • Material typically will be deposited in a direction perpendicular to the top surface 231 of the mold compound 230, the top surface 21 1 of the substrate 210, and/or the bottom surface 214 of the substrate 210, as shown in FIG. 15. It should be recognized that material can be deposited in any suitable direction relative to such features in order to deposit material in a direction that is non- parallel to the lateral side surfaces 232, 233 of the mold compound 230 and the lateral side surfaces 212, 213 of the substrate 210.
  • the orientation of the lateral side surfaces 232, 233 of the mold compound 230 and the side surfaces 212, 213 of the substrate 210 can be configured based on the material deposition direction such that the side surfaces are oriented non- parallel to the deposition direction.
  • the orientation of the top surface 231 of the mold compound 230 can be perpendicular to the deposition direction.
  • the sputtering deposition rate onto the side surfaces can be increased, thereby improving process throughput speed and material usage efficiency.
  • Increased deposition rate onto the side surfaces can reduce the disparity in layer 240 thickness between the top and side surfaces.
  • layer 240 thickness uniformity can be maximized by minimizing a perpendicular orientation of the side surfaces 262, 263 relative to the top surface 261 of the electronic device package 200.
  • angles 202a-b, 203a-b, 204a-b can range from less than 90 to degrees to greater than 0 degrees, limited only by practical considerations such as package size, which may be increased as these angles decrease thereby "widening" the package 200.
  • a portion of the lateral side surface 262, 263 can extend over or above a portion of the electronic component 220, which can facilitate minimizing the angles 202a-b, 203a-b, 204a-b (e.g. , minimizing the perpendicular orientation of the side surfaces 262, 263 relative to the top surface 261 ) while also minimizing the size of the package 200 for given angles 202a-b, 203a-b, 204a-b.
  • FIG. 16 illustrates an example computing system 301 .
  • the computing system 301 can include an electronic device package 300 as disclosed herein, coupled to a motherboard 360.
  • the computing system 301 can also include a processor 381 , a memory device 382, a radio 383, a heat sink 384, a port 385, a slot, or any other suitable device or component, which can be operably coupled to the motherboard 360.
  • the computing system 301 can comprise any type of computing system, such as a desktop computer, a laptop computer, a tablet computer, a smartphone, a server, etc.
  • an electronic device package comprising a bottom surface, and a side surface extending from the bottom surface, wherein the side surface is oriented at a non-perpendicular angle relative to the bottom surface.
  • the side surface is formed by a layer of material.
  • the layer of material forms an electromagnetic shield.
  • the electronic device package further comprises a top surface, wherein the side surface is oriented at a non- perpendicular angle relative to the top surface.
  • the top surface is formed by the layer of material.
  • the layer of material is a continuous layer.
  • the layer of material is a discontinuous layer.
  • the layer of material is the same material on the top surface as on the side surface.
  • a thickness of the layer of material on the side surface is within about 80% of a thickness of the layer of material on the top surface.
  • the layer of material on the top surface and the side surface is equal in thickness.
  • the layer of material has a thickness of from about 0.5 ⁇ to about 15 ⁇ .
  • the layer of material of the top surface forms an electromagnetic shield.
  • the side surface comprises a first portion extending from the bottom surface and oriented at a first angle relative to the bottom surface, and a second portion extending from the top surface and oriented at a second angle relative to the top surface.
  • the first angle is equal to the second angle.
  • the layer of material of the second portion is disposed on a mold compound.
  • the first portion and the second portion of the side surface are located on a same side of the electronic device package.
  • an electronic device package comprising a top planar surface having a first area, a bottom planar surface having a second area, wherein the second area is larger than the first area, and a side surface extending between the top surface and the bottom surface.
  • the side surface is formed by a layer of material.
  • the layer of material forms an electromagnetic shield.
  • the side surface is oriented at a non-perpendicular angle relative to the top planar surface.
  • the top planar surface is formed by the layer of material.
  • the layer of material is a continuous layer.
  • the layer of material is a discontinuous layer.
  • the layer of material is the same material on the top surface as on the side surface.
  • a thickness of the layer of material on the side surface is within about 80% of a thickness of the layer of material on the top planar surface.
  • the layer of material on the top planar surface and the side surface is equal in thickness.
  • the layer of material has a thickness of from about 0.5 ⁇ to about 15 ⁇ .
  • the layer of material of the top planar surface forms an electromagnetic shield.
  • the side surface comprises a first portion extending from the bottom planar surface and oriented at the first angle relative to the bottom planar surface, and a second portion extending from the top planar surface and oriented at a second angle relative to the top planar surface.
  • the first angle is equal to the second angle.
  • the layer of material of the second portion is disposed on a mold compound.
  • the first portion and the second portion of the side surface are located on a same side of the electronic device package.
  • length and width dimensions of the bottom planar surface are greater than corresponding length and width dimensions of the top planar surface.
  • the electronic device package comprises a substrate defining a plane, an electronic component disposed on the substrate, and a layer of material disposed about a lateral side of the electronic component, wherein the layer of material is oriented at an angle of less than 90 degrees relative to the plane.
  • the layer of material has a thickness of from about 0.5 ⁇ to about 15 ⁇ .
  • the layer of material forms an electromagnetic shield.
  • the electronic component comprises a semiconductor device.
  • the electronic device package comprises a mold compound disposed between the electronic component and the layer of material.
  • a portion of the layer of material is disposed about a top side of the electronic component.
  • a thickness of the layer of material on the lateral side is within about 80% of a thickness of the layer of material on the top side.
  • the layer of material on the top side and the lateral side is equal in thickness.
  • the portion of the layer of material disposed about the top side of the electronic component is planar.
  • a portion of the layer of material is disposed about a portion of the substrate.
  • the portion of the layer of material is disposed about a lateral side of the substrate.
  • the portion of the layer of material disposed about the lateral side of the substrate is oriented at a second angle less than 90 degrees relative to the plane.
  • the first angle is equal to the second angle.
  • the substrate includes a ground plane.
  • the mold material envelops the electronic component.
  • the mold material overlays a top surface of the substrate.
  • a computing system comprising a motherboard, and an electronic device package operably coupled to the motherboard, the electronic device package including a bottom surface, and a side surface extending from the bottom surface, wherein the side surface is oriented at a non-perpendicular angle relative to the bottom surface.
  • the computing system comprises a desktop computer, a laptop, a tablet, a smartphone, a server, or a combination thereof.
  • the computing system further comprises a processor, a memory device, a heat sink, a radio, a slot, a port, or a combination thereof operably coupled to the motherboard.
  • a component of an electronic device package comprising a top molded surface, and a side molded surface, wherein the side molded surface is oriented at a non-perpendicular angle relative to the top molded surface.
  • the component of the electronic device package further comprises a layer deposited on the top and side molded surfaces.
  • the layer provides
  • a component of an electronic device package comprising a top conductive layer, and a side conductive layer, wherein the side conductive layer is oriented at a non-perpendicular angle relative to the top conductive layer.
  • a thickness of the side conductive layer is within about 80% of a thickness of the top conductive layer.
  • the top conductive layer and the side conductive layer are equal in thickness.
  • each of the top conductive layer and the side conductive layer has a thickness of from about 0.5 ⁇ to about 15 ⁇ .
  • the side conductive layer comprises a first portion extending from the top conductive layer and oriented at the first angle, and a second portion extending from a bottom surface and oriented at a second angle relative to the bottom surface.
  • the first angle is equal to the second angle.
  • the first portion is disposed on a mold compound.
  • the first portion and the second portion of the side conductive layer are located on a same side of the electronic device package.
  • a method for making an electronic device package comprising disposing an electronic component on a substrate, the substrate defining a plane, encapsulating the electronic component in a mold compound, forming a side surface on the mold compound about a lateral side of the electronic component, such that the side surface is oriented at an angle of less than 90 degrees relative to the plane, and forming a layer of material on the surface of the mold compound.
  • encapsulating the electronic component comprises molding the mold compound about the electronic component.
  • molding comprises transfer molding.
  • molding comprises compression molding.
  • the electronic component comprises a plurality of electronic components.
  • the side surface is formed by molding the mold material.
  • the side surface is formed by removing a portion of the mold material.
  • the electronic component is a plurality of electronic components and further comprising dividing the substrate between the electronic components in order to separate the plurality of electronic components from one another into discrete packages.
  • dividing the substrate between electronic components is accomplished by sawing with a beveled saw blade and wherein the dividing forms a side surface of the substrate at an angle of less than 90 degrees relative to the plane.
  • the angle of the substrate is equal to the angle of the side surface of the mold material.
  • the electronic component is a plurality of electronic components and further comprising dividing the substrate between the electronic components in order to separate the plurality of electronic components from one another into discrete packages.
  • dividing the substrate between electronic components is accomplished by sawing with a beveled saw blade and wherein the dividing forms the side surface of the mold compound.
  • a portion of the layer of material is formed on the surface of the substrate.
  • a portion of the layer of material is disposed about a top side of the electronic component.
  • forming the layer of material comprises sputtering.
  • the layer of material forms an electromagnetic shield.
  • a method of maximizing thickness uniformity of a layer deposited on a top and side surface of an electronic device package comprises minimizing a perpendicular orientation of the side surface relative to a top surface of the electronic device package, and depositing material on the top surface and the side surface.
  • depositing material comprises sputtering.
  • material is deposited in a direction perpendicular to the top surface.
  • a method of making a computing system comprises obtaining a motherboard, obtaining an electronic device package including a bottom surface, and a side surface extending from the bottom surface, wherein the side surface is oriented at a non- perpendicular angle relative to the bottom surface, and coupling the electronic device package to the motherboard.
  • the computing system comprises a desktop computer, a laptop, a tablet, a smartphone, a server, or a combination thereof.
  • the method further comprises coupling a processor, a memory device, a heat sink, a radio, a slot, a port, or a combination thereof to the motherboard.
  • Circuitry used in electronic components or devices (e.g. a die) of an electronic device package can include hardware, firmware, program code, executable code, computer instructions, and/or software.
  • components and devices can include a non-transitory computer readable storage medium which can be a computer readable storage medium that does not include signal.
  • the computing devices recited herein may include a processor, a storage medium readable by the processor (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.
  • Volatile and non-volatile memory and/or storage elements may be a RAM, EPROM, flash drive, optical drive, magnetic hard drive, solid state drive, or other medium for storing electronic data.
  • Node and wireless devices may also include a transceiver module, a counter module, a processing module, and/or a clock module or timer module.
  • One or more programs that may implement or utilize any techniques described herein may use an application programming interface (API), reusable controls, and the like.
  • API application programming interface
  • Such programs may be implemented in a high level procedural or object oriented programming language to communicate with a computer system.
  • the program(s) may be implemented in assembly or machine language, if desired.
  • the language may be a compiled or interpreted language, and combined with hardware implementations.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

La présente invention concerne une technologie de boîtier de dispositif électronique. Dans un exemple, un boîtier de dispositif électronique peut comprendre une surface inférieure et une surface latérale s'étendant depuis la surface inférieure. La surface latérale peut être orientée à un angle non perpendiculaire par rapport à la surface inférieure. Dans un autre exemple, un boîtier de dispositif électronique peut comprendre une surface plane supérieure ayant une première aire, une surface plane inférieure ayant une deuxième aire, et une surface latérale s'étendant entre la surface supérieure et la surface inférieure. La deuxième aire peut être supérieure à la première aire. Dans un autre exemple supplémentaire, un boîtier de dispositif électronique peut comprendre un substrat définissant un plan, un composant électronique disposé sur le substrat, et une couche de matériau disposée autour d'un côté latéral du composant électronique. La couche de matériau peut être orientée à un angle inférieur à 90 degrés par rapport au plan.
PCT/US2016/063731 2015-12-24 2016-11-24 Boîtiers de dispositif électronique avec blindage emi et procédés associés WO2017112327A1 (fr)

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KR102497577B1 (ko) * 2015-12-18 2023-02-10 삼성전자주식회사 반도체 패키지의 제조방법
JP6615341B2 (ja) * 2016-06-08 2019-12-04 三菱電機株式会社 半導体装置およびその製造方法
EP3462486B1 (fr) * 2017-09-29 2021-03-24 Qorvo US, Inc. Méthode de réalisation d'un module double face à protection électromagnétique
US20200075547A1 (en) 2018-08-31 2020-03-05 Qorvo Us, Inc. Double-sided integrated circuit module having an exposed semiconductor die
CN110875204B (zh) * 2018-09-04 2022-03-18 中芯集成电路（宁波）有限公司 晶圆级封装方法以及封装结构

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110316156A1 (en) * 2010-06-24 2011-12-29 Stats Chippac, Ltd. Semiconductor Device and Method of Forming RDL Along Sloped Side Surface of Semiconductor Die for Z-Direction Interconnect
US20150303075A1 (en) * 2014-04-18 2015-10-22 Samsung Electronics Co., Ltd. Method of fabricating a semiconductor package

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3997888B2 (ja) * 2002-10-25 2007-10-24 セイコーエプソン株式会社 電気光学装置、電気光学装置の製造方法及び電子機器
US7482686B2 (en) * 2004-06-21 2009-01-27 Braodcom Corporation Multipiece apparatus for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages and method of making the same
CN102422730B (zh) * 2009-05-13 2016-03-16 莱尔德电子材料(深圳)有限公司 用于emi屏蔽应用的导电膜
US8084300B1 (en) * 2010-11-24 2011-12-27 Unisem (Mauritius) Holdings Limited RF shielding for a singulated laminate semiconductor device package
KR101711045B1 (ko) * 2010-12-02 2017-03-02 삼성전자 주식회사 적층 패키지 구조물
US9881875B2 (en) * 2013-07-31 2018-01-30 Universal Scientific Industrial (Shanghai) Co., Ltd. Electronic module and method of making the same
US9754918B2 (en) * 2014-05-09 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D chip-on-wafer-on-substrate structure with via last process

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110316156A1 (en) * 2010-06-24 2011-12-29 Stats Chippac, Ltd. Semiconductor Device and Method of Forming RDL Along Sloped Side Surface of Semiconductor Die for Z-Direction Interconnect
US20150303075A1 (en) * 2014-04-18 2015-10-22 Samsung Electronics Co., Ltd. Method of fabricating a semiconductor package

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US20180366421A1 (en) 2018-12-20
CN108292646B (zh) 2022-11-08
US9847304B2 (en) 2017-12-19
CN108292646A (zh) 2018-07-17
US20170186708A1 (en) 2017-06-29

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