WO2017101805A1 - 一种芯片接合系统及方法 - Google Patents

一种芯片接合系统及方法 Download PDF

Info

Publication number
WO2017101805A1
WO2017101805A1 PCT/CN2016/110057 CN2016110057W WO2017101805A1 WO 2017101805 A1 WO2017101805 A1 WO 2017101805A1 CN 2016110057 W CN2016110057 W CN 2016110057W WO 2017101805 A1 WO2017101805 A1 WO 2017101805A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
motion
stage
substrate
motion stage
Prior art date
Application number
PCT/CN2016/110057
Other languages
English (en)
French (fr)
Inventor
陈勇辉
唐世弋
李会丽
Original Assignee
上海微电子装备（集团）股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 上海微电子装备（集团）股份有限公司 filed Critical 上海微电子装备（集团）股份有限公司
Priority to KR1020187020190A priority Critical patent/KR102261989B1/ko
Priority to SG11201805110SA priority patent/SG11201805110SA/en
Priority to US16/062,435 priority patent/US20180366353A1/en
Priority to JP2018531251A priority patent/JP2018537862A/ja
Priority to EP16874862.2A priority patent/EP3392904A4/en
Publication of WO2017101805A1 publication Critical patent/WO2017101805A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67259—Position monitoring, e.g. misposition detection or presence detection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67282—Marking devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H01L21/67712—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations the substrate being handled substantially vertically
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68309—Auxiliary support including alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68354—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7565—Means for transporting the components to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7598—Apparatus for connecting with bump connectors or layer connectors specially adapted for batch processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/8313—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/951—Supplying the plurality of semiconductor or solid-state bodies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/9512—Aligning the plurality of semiconductor or solid-state bodies
    • H01L2224/95136—Aligning the plurality of semiconductor or solid-state bodies involving guiding structures, e.g. shape matching, spacers or supporting members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps

Definitions

  • the present invention relates to the field of semiconductor manufacturing, and in particular to a chip bonding system and method.
  • the flip chip bonding process is an interconnection formed by connecting a chip to a carrier, where the carrier can be a substrate or other material. Due to the trend toward lightness, thinness, and miniaturization of electronic products, the application of die bonding technology is increasing. Combining the die bonding process with the wafer level packaging process enables the fabrication of packages with smaller package sizes and higher performance. Form, if the die bonding process is combined with the TSV (through silicon via) process, a three-dimensional structure that is more competitive in cost and performance can be produced.
  • TSV through silicon via
  • the unbonded bonding chip 2 is placed on the carrier 1 in such a manner that the device surface 3 is upward, and the bonding chip 2 is bonded by means of robot grabbing and flipping.
  • the pitch L of the bonding chip 2 can be adjusted according to different process requirements. Specifically, as shown in FIG. 2, the bonding chip 2 on the carrier 1 first picks up a bonding chip 2 on the carrier 1 by the flipping robot 5. And flipping, the bonding chip 2 is handed over to the mobile robot 6, and after the moving robot 6 is moved over the substrate 4, the alignment mark on the front side of the bonding chip 2 and the alignment mark on the substrate 4 are aligned by the image sensor 7.
  • the bonding chip 2 is pressed down to complete the bonding.
  • the shortcoming of this scheme is that the whole process flow is completed in series. For the process of pressing down the bonding time, only one chip can be joined once by moving. If it is necessary to join several hundred chips on the substrate, then the robot 5 needs to be flipped. The mobile robot 6 moves a few hundred times, so that the equipment yield is very low, time-consuming and power-consuming, and it is difficult to meet the mass production demand.
  • the present invention proposes a chip bonding apparatus and method using three motion stages, respectively for providing a source end of a chip, rearranging a chip position, and carrying a substrate bonded to the chip, using two
  • the moving mechanism moves the chip between the three motion stages, rearranges the chip position and flips it, and then bonds it to the substrate at a time, thereby reducing the number of movements of the mechanical device that is turned over, improving the production efficiency, and satisfying the mass production. demand.
  • the present invention provides a chip bonding system including a first moving stage for providing a chip, a second moving stage for carrying an interposer, and a base for carrying a chip-bonded substrate.
  • a three motion stage further comprising a first motion mechanism for grasping a chip from the first motion stage to be placed on the second motion stage, for grasping the adapter board from the second motion stage a second motion mechanism disposed on the third motion stage, a host system for controlling a chip bonding system, the adapter board can fix the chip, and the second motion mechanism can flip the adapter board, The substrate is bonded to the chip.
  • a detection system for detecting the position of the object on the first motion stage, the second motion stage, and the third motion stage is further included.
  • said detection system includes a first alignment subsystem for aligning said first motion mechanism with said chip position for causing said first motion mechanism to switch said chip to said switch a second alignment subsystem for aligning the board, a third alignment subsystem for causing the second motion mechanism to align the adapter plate with the substrate, the first alignment subsystem, The second alignment subsystem, the third alignment subsystem is coupled to the host system signal.
  • a first motion stage control subsystem for controlling movement of said first motion stage
  • a second motion stage control subsystem for controlling motion of said second motion stage
  • the third motion stage control sub-system of the motion station movement, the first motion stage control subsystem, the second motion stage control subsystem, and the third motion stage control subsystem are respectively connected to the host system signal.
  • a first motion control subsystem for controlling the first motion mechanism is further included for controlling A second motion control subsystem of the second motion mechanism, the first motion control subsystem and the second motion control subsystem being signally coupled to the host system.
  • said first motion stage secures said chip by bonding said chip.
  • the adapter plate fixes the chip by electrostatic adsorption or vacuum adsorption or organic glue bonding.
  • the substrate is a metallic material or a semiconductor material or an organic material.
  • the bonding of the substrate to the chip is bonding or thermocompression bonding.
  • the adapter plate has alignment marks for rearranging the chips as reference points.
  • said substrate has an alignment mark corresponding to said alignment mark, said alignment mark and said alignment mark being used to cause said chip when said chip on said adapter plate is bonded to said substrate The chip is aligned with the substrate.
  • the present invention also provides a die bonding method using the die bonding system as described above, comprising the steps of:
  • Step one the chip is fixed on the first motion stage, and the first motion mechanism grabs the chip from the first motion stage;
  • Step two the first motion mechanism places the grasped chip on the transfer board of the second motion stage, and rearranges the chips on the transfer board;
  • Step three the second motion mechanism grabs the adapter board from the second motion stage
  • Step four the second motion mechanism flips the adapter plate to engage the chip that has been rearranged on the adapter plate with the substrate;
  • Step 5 The second motion mechanism carries the adapter board away to separate the adapter board from the chip.
  • the rearrangement of the chips on the transfer board in the second step is implemented by: after the first motion mechanism grabs the chip from the first motion stage, The host system controls the second motion stage to drive the adapter plate to rotate or move to cause the first motion mechanism The chip is placed at a corresponding position on the adapter plate.
  • the present invention has the beneficial effects that the present invention provides a chip bonding system including a first motion stage for providing a chip, a second motion stage for carrying an adapter board, and the like.
  • a third motion stage carrying a substrate engaged with the chip, further comprising a first motion mechanism for grasping a chip from the first motion stage to be placed on the second motion stage for the second motion
  • the mechanism can flip the adapter plate and the substrate engages the chip.
  • the present invention also provides a die bonding method using the die bonding system as described above, comprising the steps of:
  • Step one the chip is fixed on the first motion stage, and the first motion mechanism grabs the chip from the first motion stage;
  • Step two the first motion mechanism places the grasped chip on the transfer board of the second motion stage, and rearranges the chips on the transfer board;
  • Step three the second motion mechanism grabs the adapter board from the second motion stage
  • Step four the second motion mechanism flips the adapter plate to engage the chip that has been rearranged on the adapter plate with the substrate;
  • Step 5 The second motion mechanism carries the adapter board away to separate the adapter board from the chip.
  • a first motion stage for providing a source end of the chip a second motion stage for rearranging the chip position and carrying the adapter board, and a substrate carrying the substrate bonded to the chip are used.
  • the third motion stage uses two motion mechanisms to grab the chip and place the chip between the three motion stages.
  • the motion mechanism grabs the chip from the first motion stage and places it on the second motion stage, the chip can be finally When the substrate is bonded, the chip is placed on the second motion stage, that is, the chip is rearranged according to the form of bonding with the substrate, so that the adapter plate is flipped once and the rearranged chip is When the substrate is bonded, there is no need to arrange again, so that the entire chip bonding system
  • the mechanism that realizes the flipping can realize one-time flipping of all the chips according to the process requirements, which improves the production efficiency, saves time, and can meet the mass production requirements.
  • FIG. 1 and 2 are schematic views of a flip chip bonding process in the prior art
  • FIG. 3 is a schematic structural view of a chip bonding system provided by the present invention.
  • FIG. 4 is a schematic structural view of an adapter plate provided by the present invention.
  • FIG. 5 and FIG. 6 are schematic diagrams of placing an interposer chip on a substrate according to the present invention.
  • Figure 7 is a schematic view showing the structure of a substrate provided by the present invention.
  • the invention shows: 000-host system, 001-first motion station control subsystem, 002-second motion platform control subsystem, 003-third motion platform control subsystem, 010-first motion mechanism, 011- a motion control subsystem, 020-second motion mechanism, 021-second motion control subsystem, 100-first motion platform, 101-first alignment subsystem, 200-second motion platform, 201-second pair Quasi-score system, 300-third motion stage, 301-third alignment subsystem, 10-chip, 20-array board, 21-alignment mark, 22-alignment area, 23-to-temporary joint area, 30 - substrate, 31-bonded area.
  • the present invention provides a die bonding system including a first moving stage 100 for providing a chip 10, a second moving stage 200 for carrying the adapter board 20, and a carrier 10 for carrying the chip 10.
  • the third motion stage 300 of the bonded substrate 30 further includes a first motion mechanism 010 for grasping the chip 10 from the first motion stage 100 and placed on the adapter plate 20 of the second motion stage 200, for The second motion stage 200 grabs the second motion mechanism 020 of the adapter plate 20 placed on the base 30 on the third motion stage 300, and the first motion control subsystem 011 for controlling the first motion mechanism 010, for Controlling the second motion control subsystem 021 of the second motion mechanism 020, the entire chip bonding system is controlled by the host system 000, and the host system 000 is also connected with a first motion station control subsystem 001 capable of controlling the first motion platform 100, capable of The second motion stage control subsystem 002 that controls the second motion stage 200 and the third motion stage control subsystem 003 that can control the third motion stage 300.
  • a first alignment subsystem 101 for detecting the position of the chip 10 on the first motion stage 100, a second alignment subsystem 201 for detecting the position of the adapter board 20 on the second motion table 200, The third alignment subsystem 301 for detecting the placement position of the chip 10 on the substrate 30 on the third motion stage 300, the first alignment subsystem 101, the second alignment subsystem 201, and the third alignment subsystem 301 are all hosted by the host.
  • System 000 is directly controlled.
  • the first alignment subsystem 101, the second alignment subsystem 201, and the third alignment subsystem 301 can be used to detect the temperature information on the respective motion stations, in addition to detecting the position information on the respective motion stations. Pressure information, etc.
  • the order of placing the first motion table 100 and the second motion table 200 and the third motion table 300 is to facilitate the movement of the first motion mechanism 010 and the second motion mechanism 020, and is sufficient to move or rotate the three motion tables. Space.
  • the first motion stage 100 provides the chip 10, and the first motion stage 100 itself can control the motion of multiple degrees of freedom through the first motion stage control subsystem 001.
  • the chip 10 can be adhered to the viscous flexible organic material carried by the first motion stage 100, such as the chip 10 can be bonded to the organic film, or the chip 10 can be fixed on the first motion stage 100.
  • the first alignment subsystem 101 on the first motion stage 100 detects the position of the chip 10 on the first motion stage 100 and supplies it to the host system 000, and the first motion is controlled by the host system 000 through the first motion control subsystem 011.
  • the accuracy of the capture of the chip 10 by the mechanism 010 on the first motion stage 100 such as the first alignment subsystem 101 detecting the type 10 of the chip 10 in the first motion, according to the type of chip 10 to be grasped each time.
  • the position and number of the station 100, and controlled by the first motion control subsystem 011 The first motion mechanism 010 picks up a chip 10 of this kind at the location where the chip 10 of the type is located.
  • the manner in which the first motion mechanism 010 grabs the chip 10 may be other methods such as electrostatic adsorption or vacuum adsorption.
  • the adsorption force on the chip 10 is greater than the force of the fixed chip 10 on the first motion table 100, thereby ensuring the grasping. Take the chip 10 smoothly.
  • the second motion stage 200 carries an adapter plate 20, and the second motion stage 200 itself can control the motion of multiple degrees of freedom through the second motion stage control subsystem 002.
  • the chip 10 on the first motion stage 100 is grasped and placed on the interposer 20 by the first motion mechanism 010. Referring to FIG. 4, the distribution of the chip 10 on the interposer 20 is different from the distribution of the chip 10 on the first moving stage 100.
  • the area on the interposer 20 for arranging the chip 10 and the entire substrate 30 or substrate A certain area of 30 is mirror-imaged such that after the chip 10 on the interposer 20 is subsequently flipped by 180°, the arrangement of the chips 10 is the same as that of the corresponding area on the substrate 30.
  • the second motion stage 200 After the first motion mechanism 010 grabs the chip 10 from the first motion stage 100, the second motion stage 200 needs to be rotated or moved according to the arrangement of the chip 10 in the adapter board 20, and the second motion stage 200 is rotating or moving.
  • the second alignment subsystem 201 detects the position on the adapter plate 20 on the second motion stage 200 for placing the chip 10, and then the host system 000 controls the first motion mechanism 010 to place the captured chip 10. On the adapter plate 20.
  • the adapter plate 20 is temporarily engaged with the chip 10.
  • the temporary bonding may be electrostatic adsorption, vacuum adsorption or bonding using an organic glue.
  • the first motion mechanism 010 places the chip 10 on the adapter board 20, the chip 10 is temporarily provided.
  • the first motion mechanism 010 instantaneously releases the fixing force to the chip 10, so that the chip 10 is fixed to the adapter board 20.
  • the adapter plate 20 has an alignment mark 21 on the alignment area 22, and the mark is used as a reference point when the first movement mechanism 010 arranges the chips 10 one by one on the adapter plate 20.
  • the second alignment subsystem 201 will inform the host system 000 with respect to the alignment mark 21, the position at which the chip 10 should be discharged, and the host system 000 controls the first motion mechanism 010 to place the chip 10 in the rotation by the first motion control subsystem 011.
  • the second motion mechanism 020 can grasp both sides of the adapter plate 20 by vacuum adsorption or electrostatic adsorption or by mechanically grasping the adapter plate 20.
  • the second motion mechanism 020 has a flipping function, and the adapter plate 20 is flipped. At 180°, the chip 10 on the interposer 20 is bonded to the substrate 30.
  • the substrate 30 is a metallic material or a semiconductor material or an organic material.
  • the substrate 30 has an alignment mark (not shown) corresponding to the alignment mark 21, and when the second movement mechanism 020 reverses the adapter plate 20, the third alignment subsystem 301 detects the substrate 30. Aligning the position of the mark with the alignment mark 21 on the adapter plate 20, and controlling the third motion stage 300 by the third motion stage control subsystem 003, and controlling the second motion mechanism 020 by the second motion control subsystem 021, The second motion mechanism 020 drives the adapter plate 20 to move and reverse, and the third motion table control subsystem 003 controls the movement and movement of the third motion table 300, thereby aligning the alignment mark 21 with the alignment mark, and the transfer will be performed at this time.
  • the chip on the board 20 is bonded to the substrate 30, the chip 10 can be accurately placed on the substrate 30 where it is intended to be bonded to the chip 10.
  • the substrate 30 is divided into a plurality of bonding regions 31.
  • the space for accommodating the chip 10 on the adapter board 20 is the same as the space for accommodating the chip 10 in a certain bonding region 31, and the second motion mechanism 020 is transferred once.
  • the bonding of the bonding pads 30 to the substrate 30 completes the bonding of one bonding region 31.
  • the substrate 30 is bonded to the chip 10 by bonding, or the substrate 30 is pressed downward by the second motion mechanism 020, while the third stage 300 heats the substrate 30, so that the chip 10 and the substrate 30 are performed. Hot press bonding.
  • the present invention also provides a chip bonding method using the above-described chip bonding system, which specifically includes the following steps:
  • Step 1 a plurality of chips 10 are adhered to the first motion stage 100. There may be a plurality of types of chips 10, the type and number of which are determined according to the requirements of the chip 10 to be finally bonded to the substrate 30;
  • Step 2 The host system 000 controls the first motion mechanism 010 to move to the vicinity of the first motion stage 100 through the first motion control subsystem 011, and the first alignment subsystem 101 detects that the chip 10 to be captured is on the first motion platform 100. And sent to the host system 000, according to the position detected by the first alignment subsystem 101, the host system 000 sends a signal to the first motion control subsystem 011, The first motion control subsystem 011 controls the first motion mechanism 010 to grab the chip 10 on the first motion stage 100, and if the chip 10 is required to change the captured posture when it is captured, the first motion station can control the point.
  • the system 001 controls the first motion stage 100 to rotate or move, and the first motion mechanism 010 can also move to change the grasping posture.
  • Step 3 The adapter plate 20 on the second motion stage 200 is pre-defined to which bonding area 31 on the substrate 30 to be bonded, and is arranged on the adapter board 20 according to the chip arrangement on the bonding area 31.
  • the arrangement pattern of the joint region 31 after mirroring defines the position and arrangement of the chips 10 that need to be temporarily joined.
  • the motion table 200 moves or rotates.
  • the movement of the first motion mechanism 010 is performed according to the alignment mark 21 in the alignment area 22 on the adapter board 20, and the movement or rotation of the second motion stage 200 is required according to the chip 10.
  • the host system 000 controls the first motion mechanism 010 to place the chip 10 to the switch through the first motion control subsystem 011.
  • the portion of the board 20 to be temporarily joined is thus temporarily engaged with the connecting board 20.
  • the temporary engaging force of the interposer 20 and the chip 10 is greater than the bonding force of the first moving mechanism 010 to fix the chip 10, and the second alignment is System 201 is detection accuracy of placement.
  • Step 4 After the adapter board 20 temporarily engages enough chips 10, the host system 000 controls the second motion mechanism 020 to grasp both sides of the adapter board 20 through the second motion control subsystem 021, and moves to the In the vicinity of the three motion stage 300, the position of the joint area 31 on the base 30 to be engaged is detected by the third alignment subsystem 301, and the second motion mechanism 020 moves the adapter plate 20 to the vicinity of the joint area 31, or the third motion.
  • the table 300 cooperates with the movement of the second motion mechanism 020, so that the second motion mechanism 020 carries the adapter plate 20 to the upper side of the joint region 31, and the adapter plate 20 is turned 180°, and then the chip 10 on the adapter plate 20 is at this time.
  • the arrangement and the bonding area 31 need to be bonded to the chip 10.
  • the arrangement is the same.
  • the second motion mechanism 020 brings the adapter plate 20 downward with the joint region 31.
  • the adapter plate 20 is instantaneously released to adsorb the chip 10.
  • the adsorption force, or the attraction of the substrate 30 to the chip 10 is greater than the attraction of the adapter plate 20 to the chip 10, so that the chip 10 is fixed on the substrate 30, and the adapter plate 20 can be separated from the chip 10 according to the process requirements, so that The chip 10 is bonded to the substrate 30; if the chip 10 is required to be thermocompression bonded to the substrate 30, the adapter plate 20 gives the chip 10 a downward pressure while the third stage 300 heats the substrate 30 to heat up the chip 10. It is thermocompression bonded to the substrate 30.
  • the chip 10 to be bonded on each of the bonding regions 31 can be temporarily bonded to the interposer 20 first, and then all the chips 10 in the region are replaced by the interposer 20. All of the bonding regions 31 are bonded to the substrate 30, and the interposer 20 can also temporarily engage the individual chips 10.
  • the interposer 20 temporarily engages the chip 10 in the entire bonding region 31, it is necessary to ensure that the heights of all the chips 10 in the region are uniform, so that each chip is bonded to the substrate 30 after the interposer 20 is flipped by 180°. 10 can access the substrate 30.
  • the second moving mechanism 020 for inverting can realize all the chips 10 to be bonded to the substrate 30 in a single process according to the process requirement, thereby improving production efficiency and saving time. Can meet the needs of mass production.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Die Bonding (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)

Abstract

一种芯片接合系统及方法，使用用于提供芯片(10)的源端第一运动台(100)，将芯片(10)的位置重新排布并承载着转接板(20)的第二运动台(200)，以及承载与芯片(10)接合的基底(30)的第三运动台(300)，使用两个运动机构(010,020)在三个运动台之间进行抓取芯片(10)、放置芯片(10)，当运动机构(010)从第一运动台(100)上抓取芯片(10)放置在第二运动台(200)时，可以按照芯片(10)最终与基底(30)接合时的形态而将芯片放置在第二运动台(200)上，也就是将芯片(10)按照与基底(30)接合的形态进行重新排布，这样将转接板(20)一次性翻转后，将已重新排布后的芯片与基底接合时，无需再次排布，这样整个芯片接合系统中，实现翻转的机构只需实现一次翻转，就可以将所有芯片按照工艺要求与基底一次性接合，这样提高了生产效率，节省了时间，满足了量产化需求。

Description

一种芯片接合系统及方法 技术领域
本发明涉及半导体制造领域，特别涉及一种芯片接合系统及方法。
背景技术
倒装芯片接合工艺是将芯片与载片连接形成的一种互连形式，这里的载片可以是基底或者其它材料。由于电子产品朝着轻、薄和小型化的趋势发展，使得芯片接合技术的应用日益增多，将芯片接合工艺与晶圆级封装工艺相结合，能够制作出封装尺寸更小、性能更高的封装形式，如果将芯片接合工艺与TSV(硅通孔)工艺相结合，能够制作出成本和性能更有竞争力的三维立体结构。
请参照图1，现有的芯片倒装接合设备中，未接合的接合芯片2以器件面3向上的方式放置在承载台1上，采用机械手抓取和翻转的方式将上述接合芯片2接合到基底4上，接合芯片2的间距L可根据不同工艺需求调整，具体地，如图2所示，承载台1上的接合芯片2首先通过翻转机械手5拾取承载台1上的一颗接合芯片2并进行翻转，再将接合芯片2交接给移动机械手6，移动机械手6运动到基底4上方后，通过图像传感器7将接合芯片2正面的对准标记和基底4上的对准标记进行对准后将接合芯片2下压完成接合。该方案的缺点是：整个工艺流程都是串行完成，对于下压接合时间长的工艺，由于移动一次只能接合一颗芯片，若是基底上需要接合几百颗芯片，那么需要翻转机械手5与移动机械手6运动几百次，这样设备产率非常低，耗时耗电，难以满足量产需求。
因此针对上述问题，有必要发明一种芯片接合系统及方法，以提高芯片接合的效率，满足量产需求。
发明内容
为解决上述问题，本发明提出了一种芯片接合装置及方法，使用三个运动台、分别用于提供芯片的源端、将芯片位置重新排布、以及承载与芯片接合的基底，使用两个运动机构在三个运动台之间移动芯片，将芯片位置重新排布并翻转后一次性粘接在基底上，这样减少了起翻转作用的机械装置的运动次数，提高了生产效率，满足量产需求。
为达到上述目的，本发明提供一种芯片接合系统，包括依次排列的用于提供芯片的第一运动台、用于承载转接板的第二运动台、用于承载与芯片接合的基底的第三运动台，还包括用于从所述第一运动台上抓取芯片放置在所述第二运动台的第一运动机构、用于从所述第二运动台上抓取所述转接板放置在所述第三运动台上的第二运动机构、用于控制芯片接合系统的主机系统，所述转接板可固定所述芯片，所述第二运动机构可翻转所述转接板，所述基板与所述芯片接合。
作为优选，还包括用于探测所述第一运动台、所述第二运动台以及所述第三运动台上物体位置的探测系统。
作为优选，所述探测系统包括用于使所述第一运动机构与所述芯片位置对准的第一对准分系统、用于使所述第一运动机构将所述芯片与所述转接板对准的第二对准分系统、用于使所述第二运动机构将所述转接板与所述基底对准的第三对准分系统，所述第一对准分系统、所述第二对准分系统、所述第三对准分系统与所述主机系统信号连接。
作为优选，还包括用于控制所述第一运动台运动的第一运动台控制分系统、用于控制所述第二运动台运动的第二运动台控制分系统、用于控制所述第三运动台运动的第三运动台控制分系统，所述第一运动台控制分系统、所述第二运动台控制分系统、所述第三运动台控制分系统分别与所述主机系统信号连接。
作为优选，还包括用于控制第一动机构的第一运动控制分系统、用于控 制第二运动机构的第二运动控制分系统，所述第一运动控制分系统与所述第二运动控制分系统与所述主机系统信号连接。
作为优选，所述第一运动台通过粘接所述芯片将所述芯片固定。
作为优选，所述转接板通过静电吸附或者真空吸附或者有机胶粘接固定所述芯片。
作为优选，所述基底为金属材料或者半导体材料或者有机材料。
作为优选，所述基底与所述芯片的接合方式为粘接或者热压接合。
作为优选，所述转接板上具有用于使所述芯片的重新排布而作为参考点的对准标记。
作为优选，所述基底上具有与所述对准标记对应的排列标记，当所述转接板上的芯片与所述基底接合时，所述对准标记与所述排列标记用于使所述芯片与所述基底位置对准。
本发明还提供一种使用如上所述的芯片接合系统的芯片接合方法，包括以下步骤：
步骤一，所述芯片固定在所述第一运动台上，所述第一运动机构从所述第一运动台上抓取所述芯片；
步骤二，所述第一运动机构将抓取的芯片放置在所述第二运动台的转接板上，并将芯片在所述转接板上的所述芯片被重新排布；
步骤三，所述第二运动机构从所述第二运动台上抓取所述转接板；
步骤四，所述第二运动机构将所述转接板翻转，将所述转接板上已重新排布的所述芯片与所述基底接合；
步骤五，所述第二运动机构将所述转接板带走，使所述转接板与所述芯片分离。
作为优选，所述步骤二中的所述转接板上的芯片的重新排布的实现方式为通过在所述第一运动机构从所述第一运动台上抓取所述芯片后，所述主机系统控制所述第二运动台带动所述转接板转动或者移动使所述第一运动机构 将所述芯片放置在所述转接板相应位置上。
与现有技术相比，本发明的有益效果是：本发明提供一种芯片接合系统，包括依次排列的用于提供芯片的第一运动台、用于承载转接板的第二运动台、用于承载与芯片接合的基底的第三运动台，还包括用于从所述第一运动台上抓取芯片放置在所述第二运动台的第一运动机构、用于从所述第二运动台上抓取所述转接板放置在所述第三运动台上的第二运动机构、用于控制芯片接合系统的主机系统，所述转接板可固定所述芯片，所述第二运动机构可翻转所述转接板，所述基板与所述芯片接合。
本发明还提供一种使用如上所述的芯片接合系统的芯片接合方法，包括以下步骤：
步骤一，所述芯片固定在所述第一运动台上，所述第一运动机构从所述第一运动台上抓取所述芯片；
步骤二，所述第一运动机构将抓取的芯片放置在所述第二运动台的转接板上，并将芯片在所述转接板上的所述芯片被重新排布；
步骤三，所述第二运动机构从所述第二运动台上抓取所述转接板；
步骤四，所述第二运动机构将所述转接板翻转，将所述转接板上已重新排布的所述芯片与所述基底接合；
步骤五，所述第二运动机构将所述转接板带走，使所述转接板与所述芯片分离。
本发明提供的芯片接合系统及方法中，使用用于提供芯片的源端第一运动台，将芯片位置重新排布并承载着转接板的第二运动台，以及承载与芯片接合的基底的第三运动台，使用两个运动机构在三个运动台之间进行抓取芯片、放置芯片，当运动机构从第一运动台上抓取芯片放置在第二运动台时，可以按照芯片最终与基底接合时的形态而将芯片放置在第二运动台上，也就是将芯片按照与基底接合的形态进行重新排布，这样将转接板一次性翻转后，将已重新排布后的芯片与基底接合时，无需再次排布，这样整个芯片接合系 统中，实现翻转的机构只需实现一次翻转，就可以将所有芯片按照工艺要求与基底一次性接合，这样提高了生产效率，节省了时间，能够满足量产化需求。
附图说明
图1和图2皆为现有技术中倒装芯片接合工艺示意图；
图3为本发明提供的芯片接合系统结构示意图；
图4为本发明提供的转接板结构示意图；
图5和图6皆为本发明提供的将转接板芯片放置在基底上的示意图；
图7为本发明提供的基底结构示意图。
现有技术图示：1-承载台、2-接合芯片、3-器件面、4-基底、5-翻转机械手、6-移动机械手、7-图像传感器；
本发明图示：000-主机系统、001-第一运动台控制分系统、002-第二运动台控制分系统、003-第三运动台控制分系统、010-第一运动机构、011-第一运动控制分系统、020-第二运动机构、021-第二运动控制分系统、100-第一运动台、101-第一对准分系统、200-第二运动台、201-第二对准分系统、300-第三运动台、301-第三对准分系统、10-芯片、20-转接板、21-对准标记、22-对准区域、23-待临时接合区域、30-基底、31-接合区域。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
请参照图3，本发明提供一种芯片接合系统，包括依次排列的用作提供芯片10的第一运动台100、用于承载转接板20的第二运动台200、用于承载与芯片10接合的基底30的第三运动台300，还包括用于从第一运动台100上抓取芯片10放置在第二运动台200的转接板20上的第一运动机构010、用于从 第二运动台200上抓取转接板20放置在第三运动台300上的基底30上的第二运动机构020、用于控制第一运动机构010的第一运动控制分系统011，用于控制第二运动机构020的第二运动控制分系统021，整个芯片接合系统由主机系统000控制，主机系统000还信号连接有能够控制第一运动台100的第一运动台控制分系统001、能够控制第二运动台200的第二运动台控制分系统002、能够控制第三运动台300的第三运动台控制分系统003。
此外，还包括用于探测第一运动台100上芯片10位置的第一对准分系统101、用于探测第二运动台200上转接板20的位置的第二对准分系统201、用于探测第三运动台300上基底30上芯片10放置位置的第三对准分系统301，第一对准分系统101、第二对准分系统201以及第三对准分系统301皆由主机系统000直接控制。第一对准分系统101、第二对准分系统201以及第三对准分系统301除了用于探测各自对应的运动台上的位置信息，还可以用于探测各自对应运动台上的温度、压力信息等。
第一运动台100和第二运动台200以及第三运动台300的放置次序以方便第一运动机构010与第二运动机构020运动为准，且要给予足够的使三个运动台移动或者转动的空间。
第一运动台100提供芯片10，第一运动台100本身可以通过第一运动台控制分系统001控制实现多自由度的运动。一般地，可将芯片10粘附在第一运动台100承载的具有黏性的柔性有机材料上，如可使芯片10粘接在有机膜上，或者芯片10被固定在第一运动台100承载着具有芯片限位功能的刚性材料上。
第一运动台100上的第一对准分系统101探测第一运动台100上芯片10的位置，并输送给主机系统000，并由主机系统000通过第一运动控制分系统011控制第一运动机构010在第一运动台100上芯片10的抓取的准确性，如根据每次要抓取的芯片10的种类，由第一对准分系统101探测到该种类的芯片10在第一运动台100上的位置以及个数，并由第一运动控制分系统011控 制第一运动机构010到该种类芯片10所在的位置处抓取一个该种类的芯片10。
第一运动机构010抓取芯片10的方式可以为静电吸附或者真空吸附等其它方式，在抓取芯片10时，对芯片10的吸附力大于第一运动台100上固定芯片10的力从而保证抓取芯片10的顺利进行。
第二运动台200上承载着转接板20，第二运动台200本身可以通过第二运动台控制分系统002控制实现多自由度的运动。由第一运动机构010将第一运动台100上的芯片10抓取放置到转接板20上。请参照图4，转接板20上的芯片10的分布与第一运动台100上的芯片10的分布方式不同，该转接板20上用于排布芯片10的区域与整个基底30或者基底30的某一个区域呈镜像分布，这样在后续将转接板20上的芯片10翻转180°后，其芯片10的排布则与基底30上对应区域的排布方式相同。
第一运动机构010从第一运动台100上将芯片10抓取后，第二运动台200需要根据芯片10在转接板20的排列方式作转动或者移动，第二运动台200在转动或者移动的过程中由第二对准分系统201探测第二运动台200上转接板20上用于放置芯片10的位置，待然后由主机系统000控制第一运动机构010将抓取的芯片10放置在转接板20上。
转接板20是与芯片10进行临时接合的，临时接合的方式可以是静电吸附、真空吸附或者使用有机胶粘合，当第一运动机构010将芯片10放置在转接板20上芯片10临时接合的位置处时，第一运动机构010瞬间解除对芯片10的固定力，从而使芯片10被固定在转接板20上。
转接板20上具有对准标记21，位于对准区域22内，该标记是在第一运动机构010将芯片10逐个排布在转接板20上时以对准标记21作为参考点，由第二对准分系统201将相对于对准标记21，芯片10应当排放的位置告知主机系统000，由主机系统000通过第一运动控制分系统011控制第一运动机构010将芯片10放置在转接板20上。
第二运动机构020通过真空吸附或者静电吸附的方式或者通过机械结构抓取转接板20，可抓取转接板20的两侧，第二运动机构020具有翻转功能，将转接板20翻转180°，将转接板20上的芯片10与基底30接合。
较佳地，基底30为金属材料或者半导体材料或者有机材料。
请参照图7，基底30上具有与对准标记21对应的排列标记(未图示)，当第二运动机构020将转接板20翻转后，第三对准分系统301探测基底30上的排列标记与转接板20上的对准标记21的位置，并由第三运动台控制分系统003控制第三运动台300、以及通过第二运动控制分系统021控制第二运动机构020，第二运动机构020带动转接板20移动及翻转，而第三运动台控制分系统003控制第三运动台300的运动及移动，从而使对准标记21与排列标记对准，此时将转接板20上的芯片与基底30接合时，芯片10才能准确放置在基底30上预定与芯片10接合之处。
请继续参照图7，基底30上划分为若干个接合区域31，转接板20上容纳芯片10的空间与某个接合区域31容纳芯片10的空间大小相同，第二运动机构020每运送一次转接板20至基底30上，完成一个接合区域31的接合。
较佳地，基底30与芯片10的接合方式为粘接，或者由第二运动机构020给予基底30向下的压力，同时第三运动台300对基底30进行加热，使得芯片10与基底30进行热压接合。
本发明还提供一种使用上述的芯片接合系统的芯片接合方法，具体包括以下步骤：
步骤一：第一运动台100上粘附着若干个芯片10，可以有多种种类的芯片10，种类与数量根据最终要与基底30接合的芯片10要求为准；
步骤二：主机系统000通过第一运动控制分系统011控制第一运动机构010移动到第一运动台100附近，第一对准分系统101探测需要抓取的芯片10在第一运动台100上的位置，并发送给主机系统000，根据第一对准分系统101所探测得的位置，主机系统000发送信号给予第一运动控制分系统011， 第一运动控制分系统011控制第一运动机构010到第一运动台100上抓取芯片10，如果需要芯片10被抓取的时候改变被抓取的姿态，那么可以由第一运动台控制分系统001控制着第一运动台100进行转动或者移动，第一运动机构010也可以运动从而改变抓取的姿态。
步骤三：第二运动台200上的转接板20上事先划定好需要与基底30上哪一个接合区域31接合，按照该接合区域31上的芯片排布，在转接板20上划定该接合区域31镜像后的排布图案，划定需要临时接合的芯片10的位置以及排列方式。当第一运动机构010将芯片10从第一运动台100上抓取芯片10后，移动至第二运动台200附近，由第二对准分系统201探测该芯片10在转接板20上待临时接合区域23，并发送给主机系统000，由主机系统000通过第二运动控制分系统021控制第二运动机构020的移动，以及由主机系统000通过第二运动台控制分系统002控制第二运动台200移动或者转动，较佳地，第一运动机构010的移动根据转接板20上对准区域22内的对准标记21而进行，第二运动台200的移动或者转动根据芯片10需要与转接板20临时接合时的姿态而进行，当第二运动台200移动或者转动完成后，主机系统000通过第一运动控制分系统011控制着第一运动机构010将芯片10放置到转接板20的待临时接合之处从而与连接板20临时接合，放置时，转接板20与芯片10的临时接合力大于第一运动机构010固定芯片10的结合力，由第二对准分系统201探测放置位置的准确性。
步骤四：当转接板20上临时接合了足够的芯片10后，由主机系统000通过第二运动控制分系统021控制第二运动机构020抓取转接板20的两侧，并移动至第三运动台300附近，由第三对准分系统301探测基底30上需要被接合的接合区域31的位置，第二运动机构020将转接板20移动至该接合区域31附近，或者第三运动台300配合第二运动机构020的运动，从而使第二运动机构020携带转接板20至该接合区域31的上方，将转接板20翻转180°，则此时转接板20上芯片10的排布与该接合区域31上需要与芯片10接合的 排布方式相同，此时第二运动机构020将转接板20向下与该接合区域31靠近，当转接板20上的芯片10接触到基底30时，瞬间释放转接板20吸附芯片10的吸附力，或者基底30对芯片10的吸引力大于转接板20对芯片10的吸引力，使得芯片10固定在基底30上，此时可以按照工艺要求使转接板20离开芯片10，使得芯片10粘合在基底30上；如果需要使芯片10与基底30热压接合，那么转接板20给予芯片10向下的压力，同时第三运动台300对基底30进行加热升温，使得芯片10与基底30热压接合在一起。
本发明中转接板20上既可以将每一个接合区域31上所需要接合的芯片10先全部临时接合至转接板20上，然后由转接板20将该区域内的所有芯片10一次性全部与基底30上该接合区域31接合，转接板20也可以临时接合单个的芯片10。在转接板20临时接合整个接合区域31内的芯片10时，需要保证该区域内所有芯片10的高度一致，这样在将转接板20翻转180°之后，与基底30接合时，每个芯片10都能接触到基底30。
本发明提供的芯片接合系统及方法中，实现翻转的第二运动机构020只需实现一次翻转，就可以将所有芯片10按照工艺要求与基底30一次性接合，这样提高了生产效率，节省了时间，能够满足量产化需求。
显然本领域的技术人员可以对发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包括这些改动和变型在内。

Claims (13)

  1. 一种芯片接合系统，其特征在于，包括依次排列的用于提供芯片的第一运动台、用于承载转接板的第二运动台、用于承载与芯片接合的基底的第三运动台，还包括用于从所述第一运动台上抓取芯片放置在所述第二运动台的第一运动机构、用于从所述第二运动台上抓取所述转接板放置在所述第三运动台上的第二运动机构、用于控制芯片接合系统的主机系统，所述转接板可固定所述芯片，所述第二运动机构可翻转所述转接板，所述基板与所述芯片接合。
  2. 如权利要求1所述的芯片接合系统，其特征在于，还包括用于探测所述第一运动台、所述第二运动台以及所述第三运动台上物体位置的探测系统。
  3. 如权利要求2所述的芯片接合系统，其特征在于，所述探测系统包括用于使所述第一运动机构与所述芯片位置对准的第一对准分系统、用于使所述第一运动机构将所述芯片与所述转接板对准的第二对准分系统、用于使所述第二运动机构将所述转接板与所述基底对准的第三对准分系统，所述第一对准分系统、所述第二对准分系统、所述第三对准分系统与所述主机系统信号连接。
  4. 如权利要求1所述的芯片接合系统，其特征在于，还包括用于控制所述第一运动台运动的第一运动台控制分系统、用于控制所述第二运动台运动的第二运动台控制分系统、用于控制所述第三运动台运动的第三运动台控制分系统，所述第一运动台控制分系统、所述第二运动台控制分系统、所述第三运动台控制分系统分别与所述主机系统信号连接。
  5. 如权利要求1所述的芯片接合系统，其特征在于，还包括用于控制第一动机构的第一运动控制分系统、用于控制第二运动机构的第二运动控制分系统，所述第一运动控制分系统与所述第二运动控制分系统与所述主机系统信号连接。
  6. 如权利要求1所述的芯片接合系统，其特征在于，所述第一运动台通过粘接所述芯片将所述芯片固定。
  7. 如权利要求1所述的芯片接合系统，其特征在于，所述转接板通过静电吸附或者真空吸附或者有机胶粘接固定所述芯片。
  8. 如权利要求1所述的芯片接合系统，其特征在于，所述基底为金属材料或者半导体材料或者有机材料。
  9. 如权利要求1所述的芯片接合系统，其特征在于，所述基底与所述芯片的接合方式为粘接或者热压接合。
  10. 如权利要求1所述的芯片接合系统，其特征在于，所述转接板上具有用于使所述芯片的重新排布而作为参考点的对准标记。
  11. 如权利要求10所述的芯片接合系统，其特征在于，所述基底上具有与所述对准标记对应的排列标记，当所述转接板上的芯片与所述基底接合时，所述对准标记与所述排列标记用于使所述芯片与所述基底位置对准。
  12. 一种使用如权利要求1～11中任意一项所述的芯片接合系统的芯片接合方法，其特征在于，包括以下步骤：
    步骤一，所述芯片固定在所述第一运动台上，所述第一运动机构从所述第一运动台上抓取所述芯片；
    步骤二，所述第一运动机构将抓取的芯片放置在所述第二运动台的转接板上，并将芯片在所述转接板上的所述芯片被重新排布；
    步骤三，所述第二运动机构从所述第二运动台上抓取所述转接板；
    步骤四，所述第二运动机构将所述转接板翻转，将所述转接板上已重新排布的所述芯片与所述基底接合；
    步骤五，所述第二运动机构将所述转接板带走，使所述转接板与所述芯片分离。
  13. 如权利要求12所述的芯片接合方法，其特征在于，所述步骤二中的所述转接板上的芯片的重新排布的实现方式为通过在所述第一运动机构从所述 第一运动台上抓取所述芯片后，所述主机系统控制所述第二运动台带动所述转接板转动或者移动使所述第一运动机构将所述芯片放置在所述转接板相应位置上。
PCT/CN2016/110057 2015-12-15 2016-12-15 一种芯片接合系统及方法 WO2017101805A1 (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020187020190A KR102261989B1 (ko) 2015-12-15 2016-12-15 칩-본딩 시스템 및 방법
SG11201805110SA SG11201805110SA (en) 2015-12-15 2016-12-15 Chip-bonding system and method
US16/062,435 US20180366353A1 (en) 2015-12-15 2016-12-15 Chip-bonding system and method
JP2018531251A JP2018537862A (ja) 2015-12-15 2016-12-15 チップボンディングシステム及び方法
EP16874862.2A EP3392904A4 (en) 2015-12-15 2016-12-15 Chip-bonding system and method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510938394.X 2015-12-15
CN201510938394.XA CN105470173B (zh) 2015-12-15 2015-12-15 一种芯片接合系统及方法

Publications (1)

Publication Number Publication Date
WO2017101805A1 true WO2017101805A1 (zh) 2017-06-22

Family

ID=55607742

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/110057 WO2017101805A1 (zh) 2015-12-15 2016-12-15 一种芯片接合系统及方法

Country Status (8)

Country Link
US (1) US20180366353A1 (zh)
EP (1) EP3392904A4 (zh)
JP (1) JP2018537862A (zh)
KR (1) KR102261989B1 (zh)
CN (1) CN105470173B (zh)
SG (1) SG11201805110SA (zh)
TW (1) TWI564932B (zh)
WO (1) WO2017101805A1 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105470173B (zh) * 2015-12-15 2018-08-14 上海微电子装备（集团）股份有限公司 一种芯片接合系统及方法
CN107452644B (zh) * 2016-05-31 2020-11-20 上海微电子装备（集团）股份有限公司 分体式芯片载板搬运键合装置
CN107665828A (zh) * 2016-07-29 2018-02-06 上海微电子装备（集团）股份有限公司 一种自动键合装置及方法
CN107665827B (zh) * 2016-07-29 2020-01-24 上海微电子装备（集团）股份有限公司 芯片键合装置和方法
US10882298B2 (en) * 2016-11-07 2021-01-05 Asm Technology Singapore Pte Ltd System for adjusting relative positions between components of a bonding apparatus
CN109390249A (zh) * 2017-08-10 2019-02-26 上海微电子装备（集团）股份有限公司 半导体制造装置
CN109037420B (zh) * 2018-07-02 2021-01-08 惠州雷通光电器件有限公司 一种倒装芯片固晶装置及方法
CN109655469A (zh) * 2018-12-27 2019-04-19 深圳市燕麦科技股份有限公司 一种柔性电路板的对接测试装置及其对接测试方法
US10910239B1 (en) * 2019-07-10 2021-02-02 Mikro Mesa Technology Co., Ltd. Method of transferring micro devices and device transfer system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6640423B1 (en) * 2000-07-18 2003-11-04 Endwave Corporation Apparatus and method for the placement and bonding of a die on a substrate
CN102655193A (zh) * 2012-03-11 2012-09-05 无锡派图半导体设备有限公司 平移式芯片倒装装置
CN105470173A (zh) * 2015-12-15 2016-04-06 上海微电子装备有限公司 一种芯片接合系统及方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59227328A (ja) * 1983-06-09 1984-12-20 Mitsubishi Electric Corp 放電加工装置
TW295675B (en) * 1995-02-23 1997-01-11 Ind Tech Res Inst The chip bonding system
JP2000058707A (ja) * 1998-08-17 2000-02-25 Citizen Watch Co Ltd 半導体パッケージの製造方法
DE19840210A1 (de) * 1998-09-03 2000-03-09 Fraunhofer Ges Forschung Verfahren zur Handhabung einer Mehrzahl von Schaltungschips
TWI395253B (zh) * 2004-12-28 2013-05-01 Mitsumasa Koyanagi 使用自我組織化功能之積體電路裝置的製造方法及製造裝置
CN100414679C (zh) * 2006-04-12 2008-08-27 中南大学 热超声倒装芯片键合机
TWI322476B (en) * 2006-10-05 2010-03-21 Advanced Semiconductor Eng Die bonder and die bonding method thereof
CN101409240B (zh) * 2008-03-21 2010-09-08 北京德鑫泉科技发展有限公司 可使用芯片的智能标签及倒装芯片模块生产设备
KR100844346B1 (ko) * 2008-03-25 2008-07-08 주식회사 탑 엔지니어링 본딩 장비의 제어방법
WO2012133760A1 (ja) * 2011-03-30 2012-10-04 ボンドテック株式会社 電子部品実装方法、電子部品実装システムおよび基板
JP2013065757A (ja) * 2011-09-20 2013-04-11 Toshiba Corp 半導体チップのピックアップ方法及び半導体チップのピックアップ装置
KR20130079031A (ko) * 2012-01-02 2013-07-10 삼성전자주식회사 반도체 칩 실장 장치
US9142532B2 (en) * 2012-04-24 2015-09-22 Bondtech Co., Ltd. Chip-on-wafer bonding method and bonding device, and structure comprising chip and wafer
TWI473180B (zh) * 2012-08-24 2015-02-11 Gallant Micro Machining Co Ltd Wafer bonding device
WO2014046052A1 (ja) * 2012-09-23 2014-03-27 国立大学法人東北大学 チップ支持基板、チップ支持方法、三次元集積回路、アセンブリ装置及び三次元集積回路の製造方法
US10312118B2 (en) * 2014-01-16 2019-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Bonding apparatus and method
DE102016113328B4 (de) * 2015-08-31 2018-07-19 Besi Switzerland Ag Verfahren für die Montage von mit Bumps versehenen Halbleiterchips auf Substratplätzen eines Substrats

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6640423B1 (en) * 2000-07-18 2003-11-04 Endwave Corporation Apparatus and method for the placement and bonding of a die on a substrate
CN102655193A (zh) * 2012-03-11 2012-09-05 无锡派图半导体设备有限公司 平移式芯片倒装装置
CN105470173A (zh) * 2015-12-15 2016-04-06 上海微电子装备有限公司 一种芯片接合系统及方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3392904A4 *

Also Published As

Publication number Publication date
EP3392904A1 (en) 2018-10-24
JP2018537862A (ja) 2018-12-20
SG11201805110SA (en) 2018-07-30
US20180366353A1 (en) 2018-12-20
KR102261989B1 (ko) 2021-06-08
CN105470173B (zh) 2018-08-14
CN105470173A (zh) 2016-04-06
TW201628056A (zh) 2016-08-01
TWI564932B (zh) 2017-01-01
EP3392904A4 (en) 2018-12-12
KR20180095874A (ko) 2018-08-28

Similar Documents

Publication Publication Date Title
WO2017101805A1 (zh) 一种芯片接合系统及方法
US10950572B2 (en) Die bonder and methods of using the same
US8912045B2 (en) Three dimensional flip chip system and method
JP2005302858A (ja) ウェハの接合装置
TWI704633B (zh) 一種晶片鍵合裝置
TW201814820A (zh) 芯片鍵合裝置及鍵合方法
TWI612604B (zh) 倒裝晶片鍵合裝置及鍵合方法
WO2016188371A1 (zh) 硅片传输系统
US20150262858A1 (en) Attaching device and attaching method
WO2019029602A1 (zh) 半导体制造装置
TW202017092A (zh) 一種晶片鍵合裝置
TW201921559A (zh) 安裝覆晶之系統及方法
TWI655707B (zh) Chip universal batch bonding device and method
CN206806294U (zh) 一种芯片键合装置
TW201519332A (zh) 高產出之高精度晶片接合裝置
TWI768337B (zh) 黏晶裝置及半導體裝置的製造方法
CN107665828A (zh) 一种自动键合装置及方法
JP5516684B2 (ja) ウェハ貼り合わせ方法、位置決め方法と、これを有する半導体製造装置
KR102284943B1 (ko) 본딩 장치 및 본딩 방법
TWI703668B (zh) 大尺寸晶片接合裝置
CN108511362A (zh) 一种芯片键合装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16874862

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2018531251

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 11201805110S

Country of ref document: SG

ENP Entry into the national phase

Ref document number: 20187020190

Country of ref document: KR

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 1020187020190

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 2016874862

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2016874862

Country of ref document: EP

Effective date: 20180716