WO2017101179A1 - 液晶面板的扇出走线结构及液晶面板 - Google Patents

液晶面板的扇出走线结构及液晶面板 Download PDF

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Publication number
WO2017101179A1
WO2017101179A1 PCT/CN2016/070296 CN2016070296W WO2017101179A1 WO 2017101179 A1 WO2017101179 A1 WO 2017101179A1 CN 2016070296 W CN2016070296 W CN 2016070296W WO 2017101179 A1 WO2017101179 A1 WO 2017101179A1
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Prior art keywords
wires
fan
end point
wire
line
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Ceased
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PCT/CN2016/070296
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English (en)
French (fr)
Inventor
王聪
杜鹏
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US14/907,393 priority Critical patent/US10101622B2/en
Publication of WO2017101179A1 publication Critical patent/WO2017101179A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present patent application relates to the field of liquid crystal display technology, and in particular to a fan-out wiring structure of a liquid crystal panel and a liquid crystal panel.
  • LTPS low temperature polysilicon thin film transistor
  • the source side uses high pin count (high pin) Count) design, using only a set of Fanout connection structures and a driver chip on the source side, so that the first trace and the last one on both sides of the fan-out connection structure There is a large difference in resistance between the line and the middle of the trace.
  • the first trace and the last trace are the maximum impedance (Rmax), and the middle trace is the minimum impedance (Rmin).
  • Rmax the maximum impedance
  • Rmin minimum impedance
  • a larger resistance difference ie, Rmax
  • Rmax is formed between the first trace and the last trace of the two sides of the fan-out connection structure, respectively, and the middle trace.
  • the value of -Rmin) is more obvious.
  • the impedance difference of the fan-out connection structure is too large, which may cause resistance/capacitance delay (RC).
  • RC resistance/capacitance delay
  • Mura color difference
  • the color difference between the two sides of the panel and the middle is minimized, but the problem of display unevenness of the display panel cannot be overcome. Therefore, it is necessary to develop a new fan-out wiring structure to solve the above problems.
  • the purpose of this patent application is to provide a fan-out trace structure of a liquid crystal panel.
  • the adjacent two traces of the fan-out trace structure have equal impedances, and the maximum impedance value between the traces is reduced. And the minimum impedance value, so that the display panel achieves the uniformity of the screen during the display process, thereby improving the color difference (Mura) of the fanout structure and the color shift condition, which is advantageous for the large-scale liquid crystal display (for example, LTPS). the design of.
  • the first embodiment of the present patent application provides a fan-out trace structure of a liquid crystal panel
  • the fan-out trace structure of the liquid crystal panel includes: a substrate; the first region includes a plurality of first resistivities a first wire, each of the first wires includes a first end point and a second end point opposite to the first end point, and the first end points of the plurality of first wires are electrically connected to the signal transmission interface; a second region comprising a plurality of second wires having a second resistivity, each second wire comprising a third end point and a fourth end point opposite the third end point, the fourth end of the plurality of second wires being electrically connected
  • the signal receiving interface, and the second end of each of the first wires is electrically connected to the third end of each of the second wires, and the line is collinear through each of the first wires and/or each of the second wires Or parallel connection structure to form a number of fan-out traces, so that each fan-out trace has the same imped
  • each of the first wires is electrically connected to each of the second wires in a straight line manner at the second end point and the third end point through a via.
  • each of the first wires is electrically connected to each of the second wires in a parallel connection manner at the second end point and the third end point through a via hole, so that each of the first wires and each of the first wires In addition to the vias at the electrical connections, each of the first wires and each of the second wires are formed in a parallel straight line to form a plurality of fan-out traces.
  • first routing area and the second routing area are disposed on the same or different material layers, so that the plurality of first wires are the same as the plurality of second wires or Different material layers form an electrical connection.
  • the line between the first end points of the plurality of first wires forms a first reference line
  • the line between the fourth end points of the plurality of second wires forms a second reference line
  • the angle is defined as ⁇
  • the vertical projection pitch of the two first end points of each two first wires on the third reference line is defined as p1
  • the first end of each first wire is adjacent to the adjacent one.
  • a vertical line position of a fan-out trace defines a fifth end point, and a distance between a first end point of each first wire and a fifth end point of an adjacent shorter fan-out line is defined as x, each of the first wires
  • the angle between the line connecting the first end point and the fifth end point of the adjacent shorter fan-out line and the first reference line is defined as ⁇ , on the first end of the first wire
  • An angle between the first reference line and each of the third reference lines is ⁇
  • each of the first wires is along the first end point Forming a first lead extending in a direction perpendicular to the third reference line, a portion of the first lead of each first lead relative to a point of intersection between the first lead and the third reference line
  • the length is defined as y
  • the distance between the fourth end point of each two second wires on the second reference line is defined as p2
  • the fourth end point of each fan out line is perpendicular to the adjacent longer fan out line.
  • the line position defines a sixth end point, and a distance between a fourth end point of each fan outgoing line and a sixth end point of an adjacent longer fan out line is defined as d, and a fourth end point of each second wire and a sixth end point thereof
  • the first resistivity of the plurality of first wires is smaller than the second resistivity of the plurality of second wires, and the first fan-out trace includes only the first wire, and the second fan-out wire is routed to The last fanout trace includes the first wire and the second wire, respectively.
  • the sheet resistance value of each of the first wires is defined as R1
  • the sheet resistance value of each of the second wires is defined as R2, so that the second wire of the nth fan-out trace leaves the fan relative to the first fan.
  • a second embodiment of the present patent application provides a liquid crystal panel including a driving circuit and a fan-out wiring structure.
  • the fan-out wiring structure adopts the fan-out wiring structure described in the first embodiment.
  • a fan-out trace structure of a liquid crystal panel is provided.
  • the adjacent two traces of the fan-out trace structure have equal impedances, and the maximum impedance value and the minimum impedance value between the traces are reduced, so that the display panel is in the display process.
  • the purpose of achieving uniformity of the screen is to improve the color difference (Mura) of the Fanout structure and the state of color shift, which is advantageous for the design of a large-sized liquid crystal display (for example, LTPS).
  • FIG. 1 is a block schematic diagram showing a fan-out wiring structure of a liquid crystal panel according to an embodiment of the present patent application.
  • FIG. 2 is a schematic diagram showing the principle mechanism of a fan-out wiring structure of a liquid crystal panel according to an embodiment of the present patent application.
  • FIG. 3 is a schematic view showing the wiring of the fan-out wiring structure of the liquid crystal panel according to the first embodiment of the present patent application.
  • FIG. 4 is a schematic view showing the wiring of the fan-out wiring structure of the liquid crystal panel according to the second embodiment of the present patent application.
  • FIG. 5 is a schematic structural view of a first wire and a second wire of a fan-out wiring structure according to an embodiment of the present patent application.
  • FIG. 1 is a block schematic diagram of a fan-out trace structure of a liquid crystal panel according to an embodiment of the present patent application.
  • the fan-out routing structure 100 is used for electrically connecting the signal transmission interface of the driving circuit 102 and the signal receiving interface of the liquid crystal panel 104 for transmitting the signal of the driving circuit 102 and the power supply to the display of the liquid crystal panel 104. region.
  • FIG. 2 it is a schematic diagram of the principle mechanism of the fan-out trace structure of the liquid crystal panel according to the embodiment of the present patent application.
  • three fan-out lines are taken as an example, but are not limited thereto.
  • a line between the first end points pt1 of the plurality of first wires W1 forms a first reference line B1
  • a line between the fourth end points pt4 of the plurality of second wires W2 forms a second reference line B2
  • a plurality of third reference lines B3 are formed by the first end point pt1 of each of the first wires W1 and each of the third reference lines B3 is parallel to the second reference line B2, wherein each of the fan-out lines 100 and the first
  • the angle between the two reference lines B2 is defined as ⁇
  • the vertical projection pitch of the two first end points pt1 of the two first wires W1 on the third reference line B3 is defined as p1, each of the first wires
  • the pitch of the fifth end point pt5 of the line 100 is defined as x
  • the line between the first end point pt1 of each first wire W1 and the fifth end point pt5 of the adjacent shorter fan-out line 100 and the said An angle between a reference line B1 is defined as ⁇
  • the first reference line B1 and each of the third reference lines B3 are on the first end point pt1 of the first wire W1.
  • each first wire W1 extends from the first end point pt1 along a direction perpendicular to the third reference line B3 to form a first lead T1, and a first end of each first wire W1
  • the length of a portion of the first lead 115 between two points of the intersection pt1 with respect to the intersection 113 of the first lead T1 and the third reference line B3 is defined as y
  • the fourth end point of each two second wires W2 is at the second
  • the spacing on the reference line B2 is defined as p2
  • the vertical connection position of the fourth end point pt4 of each fan outgoing line 100 and the adjacent longer one fanout line 100 defines a sixth end point pt6, and each fan exit line 100
  • the distance between the fourth end point pt4 and the sixth end point pt6 of the adjacent longer fan out line 100 is defined as d
  • the distance between the fourth end point pt4 of each second wire W2 and its sixth end point pt6 is defined as p3, so that the phase
  • FIG. 2 is a schematic diagram showing the principle mechanism of the fan-out wiring structure of the liquid crystal panel according to the embodiment of the present patent application
  • FIG. 3 is a schematic diagram of the fan-out wiring structure of the liquid crystal panel according to the first embodiment of the present patent application. Schematic diagram of the wiring.
  • the fan-out wiring structure 100 of the liquid crystal panel is electrically connected to the signal transmission interface of the driving circuit 102 and the signal receiving interface of the liquid crystal panel 104.
  • the fan-out wiring structure 100 includes a substrate 105 (labeled in FIG. 5). A region 106 and a second region 108.
  • the first region 106 includes a plurality of first wires W1 having a first resistivity, each of the first wires W1 including a first end point pt1 and a second end point pt2 opposite to the first end point pt1, the plurality of first wires
  • the first endpoint pt1 of W1 is electrically connected to the signal transmission interface.
  • the first region 106 refers to the region where the first wire W1 is located.
  • the second region 108 includes a plurality of second wires W2 having a second resistivity, each second wire W2 including a third end point pt3 and a fourth end point pt4 opposite the third end point pt3, the plurality of second wires pt2
  • the fourth end point pt4 is electrically connected to the signal receiving interface
  • the second end point pt2 of each first wire W1 is electrically connected to the third end point pt3 of each second wire W2, through each of the first wires W1 and / or each of the second wires W2 is formed in a linear collinear structure or a parallel connection structure to form a plurality of fan-out traces 100 such that each of the fan-out traces 100 has the same impedance value.
  • the second area 108 refers to the area where the second wire W2 is located.
  • the liquid crystal panel may be added.
  • Array substrate array trace (Wire On array, WOA) uses resilience, in other words, the fanout routing structure of this patent application does not compress to the prior WOA space trace.
  • each of the first wires W1 is electrically connected in a straight line manner at the second end point pt2 and the third end point pt3 through a via 110 (such as a partial enlarged area A1).
  • each of the first wires W1 is electrically connected to each of the second wires W2 in a parallel connection manner at the second end point pt2 and the third end point pt3 through a via 110.
  • Each of the first wires W1 and each of the second wires W2 is connected in a parallel straight line manner except for the via holes 110 at the electrical connection.
  • a plurality of fanout traces 100 are formed.
  • the first trace area 106 and the second trace area 108 are disposed on the same or different material layers, so that the plurality of first wires W1 and the plurality of second wires W2 Electrical connections are made in the same or different material layers.
  • the first trace region 106 and the second trace region 108 are on the same plane of the substrate 105
  • the first trace region 106 and the second trace region 108 are on different material layers of the substrate 105 and the dielectric layer 112 (marked on Figure 5) Electrical isolation.
  • the connection between the first end points pt1 of the plurality of first wires W1 forms a first reference line B1
  • the connection between the fourth end points pt4 of the plurality of second wires W2 The line forms a second reference line B2
  • a plurality of third reference lines B3 are formed by the first end point pt1 of each first wire W1 and each third reference line B3 is parallel to the second reference line B2
  • each of The angle between the fanout trace 100 and the second reference line B2 is defined as ⁇
  • the vertical projection pitch definition of the two first endpoints pt1 of each two first wires W1 on the third reference line B3 is defined.
  • a vertical position of the first end point pt1 of each first wire W1 and an adjacent shorter fan-out line 100 defines a fifth end point pt5, and the first end point pt1 of each first wire W1 is
  • the pitch of the fifth end point pt5 of the adjacent one of the fan-out traces 100 is defined as x, the first end point pt1 of each first wire W1 and the fifth end point pt5 of the adjacent shorter fan-out line 100
  • the angle between the connection between the line and the first reference line B1 is defined as ⁇ , and the first reference line B1 is on the first end point pt1 of the first wire W1.
  • each of the first wires W1 extending from the first end point pt1 in a direction perpendicular to the third reference line B3 to form a first lead T1
  • each The length of a portion of the first lead between the first end point pt1 of the first wire W1 relative to the intersection of the first lead T1 and the third reference line B3 is defined as y
  • the number of each of the two second wires W2 The spacing of the four endpoints on the second reference line B2 is defined as p2
  • the vertical connection position of the fourth endpoint pt4 of each fanout trace 100 and the adjacent longer fanout trace 100 defines a sixth endpoint pt6,
  • the distance between the fourth end point pt4 of each of the outgoing traces 100 and the sixth end point pt6 of the adjacent longer one of the fan-out traces 100 is defined as d
  • the pitch is defined as p3
  • the first resistivity of the plurality of first wires W1 is smaller than the second resistivity of the plurality of second wires W2, and the first fan-out trace 100 includes only the first wire W1, the second strip
  • the fanout traces 100 to the last fanout traces 100 include the first wire W1 and the second wire W2, respectively.
  • the sheet resistance value of each of the first wires W1 is defined as R1
  • the sheet resistance value of each of the second wires W2 is defined as R2 such that the second wire W2 of the nth fan-out trace 100 is opposite to the first
  • the present patent application provides a liquid crystal panel including a fan-out trace structure, and the fan-out trace structure adopts the fan-out trace structure 100 described above.
  • the first wire W1 and the second wire W2 are structurally schematic, the buffer layer 107 and the gate insulating layer 109 are sequentially formed on the substrate 105, and the first is formed on the gate insulating layer 109.
  • a wire W1 (or a second wire W2) (for example, formed by etching a conductive layer), then forming a dielectric layer 111 on the first wire W1 (or the second wire W2) to cover the first wire W1, and dielectrically A via hole is formed in the layer 111 at the end position (for example, the second end point) of the first wire W1, and then the second wire W2 (or the first wire W1) is formed on the dielectric layer 111 to make the first wire W1 and the second wire
  • the wire W2 forms a straight line collinear connection structure or a parallel connection structure.
  • the fan-out trace structure of the liquid crystal panel of the patent application has the same impedance through the adjacent two traces of the fan-out trace structure, and reduces the maximum impedance value and the minimum impedance value between the traces, so that the display panel is displayed.
  • the purpose of the uniformity of the screen is achieved, thereby improving the color difference of the fan-out structure and the state of the color shift, which is advantageous for the design of the liquid crystal display to be large-sized.

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  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
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  • Engineering & Computer Science (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种液晶面板的扇出走线（100）结构，包括基材（105）；第一区域（106）包括具有第一电阻率的第一导线（W1），第一导线（W1）包括第一端点（pt1）以及相对所述第一端点（pt1）的第二端点（pt2），第一端点（pt1）电性连接所述信号传送接口；以及第二区域（108）包括若干具有第二电阻率的第二导线（W2），每一第二导线（W2）包括第三端点（pt3）以及相对所述第三端点（pt3）的第四端点（pt4），第四端点（pt4）电性连接所述信号接收接口，并且第二端点（pt2）相对应电性连接第三端点（pt3），通过每一第一导线（W1）及/或每一第二导线（W2）以直线共线结构或是平行连接结构方式来形成若干条扇出走线（100），使每一扇出走线（100）具有相同的阻抗值。所述扇出走线（100）通过减少各条走线之间的最大阻抗值与最小阻抗值，使显示面板在显示过程中达到画面均一性的目的，从而改善扇出结构的颜色差异。

Description

液晶面板的扇出走线结构及液晶面板 技术领域
本专利申请涉及一种液晶显示器技术领域，且特别是涉及一种液晶面板的扇出走线结构及液晶面板。
 背景技术
随着半导体技术的发展，视频产品，特别是数字化的视频或影像装置已经成为在一般日常生活中所常见的产品。这些数字化的视频或影像装置中，显示器是一个重要组件，以显示相关信息。而低温多晶硅薄膜晶体管(LTPS TFT)可应用于液晶显示器的驱动组件，使得此项产品成为显示器的主流，于个人计算器、游戏机、监视器等市场成为未来主导性产品。
LTPS小尺寸面板设计中，源极(source)侧都是采用高接脚数(high pin count)的设计，在源极(source)侧只使用一组扇出(Fanout)连接结构和一颗驱动芯片，这样在扇出连接结构的两侧边的第一根走线与最后一根走线分别与中间的那根走线之间会形成很大的电阻差异，例如第一根走线与最后一根走线为最大阻抗(Rmax)，所述中间走线为最小阻抗(Rmin)，尤其是当显示面板大尺寸化时，扇出连接结构的两侧边的第一根走线与最后一根走线分别与中间的那根走线之间会形成更大的电阻差异(即Rmax-Rmin的值)越发明显。
在现有技术的显示面板运作中，扇出连接结构的阻抗差异太大，会造成电阻/电容延迟(RC delay)之间的差异较为明显，使得当面板显示画面时，显示面板的两侧边与中间形成颜色差异(Mura)。在现有技术中是通过采用电阻率较小的金属作为扇出连接结构(Fanout)的走线，尽量减少面板两侧与中间的颜色差异，但是仍然无法克服显示面板的显示不均的问题。因此需要发展一种新式的扇出走线结构，以解决上述问题。
 技术问题
有监于此，本专利申请的目的在于提供一种液晶面板的扇出走线结构，通过扇出走线结构的相邻两条走线具有相等的阻抗，减少各条走线之间的最大阻抗值与最小阻抗值，使显示面板在显示过程中达到画面均一性的目的，从而改善扇出(Fanout)结构的颜色差异(Mura)以及色偏的状况，有利于液晶显示器(例如LTPS)大尺寸化的设计。
 技术解决方案
为达到上述发明目的，本专利申请第一实施例中提供一种液晶面板的扇出走线结构，所述液晶面板的扇出走线结构包括：基材；第一区域，包括若干具有第一电阻率的第一导线，每一第一导线包括第一端点以及相对所述第一端点的第二端点，所述若干第一导线的第一端点电性连接所述信号传送接口；以及一第二区域，包括若干具有第二电阻率的第二导线，每一第二导线包括第三端点以及相对所述第三端点的第四端点，所述若干第二导线的第四端点电性连接所述信号接收接口，并且每一第一导线的第二端点相对应电性连接每一第二导线的第三端点，通过每一第一导线及/或每一第二导线以直线共线结构或是平行连接结构方式以形成若干条扇出走线，使每一扇出走线具有相同的阻抗值。
在一实施例中，每一第一导线通过一过孔在所述第二端点以及所述第三端点以直线连结方式相对应电性连接每一第二导线。
在一实施例中，每一第一导线通过一过孔在所述第二端点以及所述第三端点以平行连结方式相对应电性连接每一第二导线，使每一第一导线及每一第二导线除了在电性连接处的所述过孔之外，每一第一导线及每一第二导线皆以平行直线连结方式来形成若干条扇出走线。
在一实施例中，所述第一走线区域与所述第二走线区域设置于相同或是不相同的材质层，使所述若干第一导线与所述若干第二导线在相同或是不相同的材质层形成电性连接。
在一实施例中，所述若干第一导线的第一端点之间的连线形成一第一基准线，所述若干第二导线的第四端点之间的连线形成一第二基准线，通过每一第一导线的第一端点形成若干第三基准线并且每一第三基准线平行于所述第二基准线，其中每一扇出走线与所述第二基准线之间的夹角定义为θ，每两条第一导线的两个第一端点在所述第三基准在线的垂直投影间距定义为p1，每一第一导线的第一端点与相邻较短的一条扇出走线的垂直连线位置定义第五端点，每一第一导线的第一端点与相邻较短的一条扇出走线的第五端点的间距定义为x，每一第一导线的第一端点与相邻较短的一条扇出走线的第五端点之间的连线与所述第一基准线之间的夹角定义为α，在第一导线的第一端点上所述第一基准线与每一第三基准线的夹角为β，每一第一导线自所述第一端点沿着垂直于所述第三基准线的方向延伸形成第一引线，每一第一导线的第一端点相对于所述第一引线与第三基准线的交点两点之间的部分第一引线的长度定义为y，每两条第二导线的第四端点在所述第二基准在线的间距定义为p2，每一扇出走线的第四端点与相邻较长的一条扇出走线的垂直连线位置定义第六端点，每一扇出走线的第四端点与相邻较长的一条扇出走线的第六端点的间距定义为d，每一第二导线的第四端点与其第六端点的间距定义为p3，使得相邻两条扇出走线之间长度差值ΔL以下列公式表示：ΔL= p3 - x- y= (p2 - p1) * (cos 2θ - sin θ) / cos θ。
在一实施例中，所述若干第一导线的第一电阻率小于所述若干第二导线的第二电阻率，并且第一条扇出走线仅包括第一导线，第二条扇出走线至最后一条扇出走线分别包括所述第一导线以及所述第二导线。
在一实施例中，每一第一导线的片电阻值定义为R1，每一第二导线的片电阻值定义为R2，使得第n条扇出走线的第二导线相对于第一条扇出走线之第一导线的补偿阻抗差值ΔRn是以下列公式表示：ΔRn = R1 *n * (p2 - p1) * (cos 2θ - sin θ) / cos θ，其中n为大于1的正整数。
在一实施例中，所述补偿阻抗差值在第n条扇出走线相对应于第一条扇出走线所需更换为第二导线的长度ln以下列公式表示：ln = [R1 *n * (p2 - p1) * (cos 2θ - sin θ) / cos θ]/(R2-R1)。
本专利申请第二实施例中提供一种液晶面板，包括驱动电路以及扇出走线结构，所述扇出走线结构采用上述第一实施例所述的扇出走线结构。
 有益效果
提供一种液晶面板的扇出走线结构，通过扇出走线结构的相邻两条走线具有相等的阻抗，减少各条走线之间的最大阻抗值与最小阻抗值，使显示面板在显示过程中达到画面均一性的目的，从而改善扇出(Fanout)结构的颜色差异(Mura)以及色偏的状况，有利于液晶显示器(例如LTPS)大尺寸化的设计。
附图说明
图1:为根据本专利申请实施例中液晶面板的扇出走线结构的方框示意图。
图2:为根据本专利申请实施例中液晶面板的扇出走线结构的原理机制之示意图。
图3:为根据本专利申请第一实施例中液晶面板的扇出走线结构的走线示意图。
图4:为根据本专利申请第二实施例中液晶面板的扇出走线结构的走线示意图。
图5:为根据本专利申请实施例中扇出走线结构的第一导线以及第二导线的结构示意图。
 本发明的最佳实施方式
本专利申请说明书提供不同的实施例来说明本专利申请不同实施方式的技术特征。实施例中的各组件的配置是为了清楚说明本专利申请揭示的内容，并非用以限制本专利申请。在不同的图式中，相同的组件符号表示相同或相似的组件。
参考图1，其为根据本专利申请实施例中液晶面板的扇出走线结构的方框示意图。如图1所示，扇出走线结构100用于电性连接驱动电路102的信号传送接口与所述液晶面板104的信号接收接口，用以传送驱动电路102的信号、电源至液晶面板104的显示区域。
参考图2，其为根据本专利申请实施例中液晶面板的扇出走线结构的原理机制之示意图。此处以三条扇出走线为例，但是不限于此。所述若干第一导线W1的第一端点pt1之间的连线形成一第一基准线B1，所述若干第二导线W2的第四端点pt4之间的连线形成一第二基准线B2，通过每一第一导线W1的第一端点pt1形成若干第三基准线B3并且每一第三基准线B3平行于所述第二基准线B2，其中每一扇出走线100与所述第二基准线B2之间的夹角定义为θ，每两条第一导线W1的两个第一端点pt1在所述第三基准线B3上的垂直投影间距定义为p1，每一第一导线W1的第一端点pt1与相邻较短的一条扇出走线100的垂直连线位置定义第五端点pt5，每一第一导线W1的第一端点pt1与相邻较短的一条扇出走线100的第五端点pt5的间距定义为x，每一第一导线W1的第一端点pt1与相邻较短的一条扇出走线100的第五端点pt5之间的连线与所述第一基准线B1之间的夹角定义为α，在第一导线W1的第一端点pt1上所述第一基准线B1与每一第三基准线B3的夹角为β，每一第一导线W1自所述第一端点pt1沿着垂直于所述第三基准线B3的方向延伸形成第一引线T1，每一第一导线W1的第一端点pt1相对于所述第一引线T1与第三基准线B3的交点113两点之间的部分第一引线115的长度定义为y，每两条第二导线W2的第四端点在所述第二基准线B2上的间距定义为p2，每一扇出走线100的第四端点pt4与相邻较长的一条扇出走线100的垂直连线位置定义第六端点pt6，每一扇出走线100的第四端点pt4与相邻较长的一条扇出走线100的第六端点pt6的间距定义为d，每一第二导线W2的第四端点pt4与其第六端点pt6的间距定义为p3，使得相邻两条扇出走线100之间长度差值ΔL以下列公式表示：ΔL= p3 - x- y= (p2 - p1) * (cos 2θ - sin θ) / cos θ。
参考图1至图3，图2为根据本专利申请实施例中液晶面板的扇出走线结构的原理机制之示意图，图3为根据本专利申请第一实施例中液晶面板的扇出走线结构的走线示意图。液晶面板的扇出走线结构100用以电性连接驱动电路102的信号传送接口与所述液晶面板104的信号接收接口，所述扇出走线结构100包括基材105(标示于图5)、第一区域106以及第二区域108。第一区域106包括若干具有第一电阻率的第一导线W1，每一第一导线W1包括第一端点pt1以及相对所述第一端点pt1的第二端点pt2，所述若干第一导线W1的第一端点pt1电性连接所述信号传送接口。第一区域106系指第一导线W1所在的区域。第二区域108包括若干具有第二电阻率的第二导线W2，每一第二导线W2包括第三端点pt3以及相对所述第三端点pt3的第四端点pt4，所述若干第二导线pt2的第四端点pt4电性连接所述信号接收接口，并且每一第一导线W1的第二端点pt2相对应电性连接每一第二导线W2的第三端点pt3，通过每一第一导线W1及/或每一第二导线W2以直线共线结构或是平行连接结构方式以形成若干条扇出走线100，使每一扇出走线100具有相同的阻抗值。第二区域108系指第二导线W2所在的区域。当以每一第一导线W1及/或每一第二导线W2以直线共线结构或是平行连接结构方式(如局部放大区域A1)以形成若干条扇出走线100，可以增加在液晶面板的阵列基板之阵列走线（Wire on array, WOA)使用弹性，换言之，本专利申请之扇出走线结构不会压缩到预先的WOA空间走线。
在一图3的实施例中，每一第一导线W1通过一过孔110(如局部放大区域A1)在所述第二端点pt2以及所述第三端点pt3以直线连结方式相对应电性连接每一第二导线W2。如图4所示的实施例中，每一第一导线W1通过一过孔110在所述第二端点pt2以及所述第三端点pt3以平行连结方式相对应电性连接每一第二导线W2，使每一第一导线W1及每一第二导线W2除了在电性连接处的所述过孔110之外，每一第一导线W1及每一第二导线W2皆以平行直线连结方式来形成若干条扇出走线100。
在一实施例中，所述第一走线区域106与所述第二走线区域108设置于相同或是不相同的材质层，使所述若干第一导线W1与所述若干第二导线W2在相同或是不相同的材质层形成电性连接。例如第一走线区域106与第二走线区域108在基板105的同一平面上，第一走线区域106与第二走线区域108在基板105的不同材质层并且介电层112(标示于图5)做电性隔离。
继续参考图2以及图3，所述若干第一导线W1的第一端点pt1之间的连线形成一第一基准线B1，所述若干第二导线W2的第四端点pt4之间的连线形成一第二基准线B2，通过每一第一导线W1的第一端点pt1形成若干第三基准线B3并且每一第三基准线B3平行于所述第二基准线B2，其中每一扇出走线100与所述第二基准线B2之间的夹角定义为θ，每两条第一导线W1的两个第一端点pt1在所述第三基准线B3上的垂直投影间距定义为p1，每一第一导线W1的第一端点pt1与相邻较短的一条扇出走线100的垂直连线位置定义第五端点pt5，每一第一导线W1的第一端点pt1与相邻较短的一条扇出走线100的第五端点pt5的间距定义为x，每一第一导线W1的第一端点pt1与相邻较短的一条扇出走线100的第五端点pt5之间的连线与所述第一基准线B1之间的夹角定义为α，在第一导线W1的第一端点pt1上所述第一基准线B1与每一第三基准线B3的夹角为β，每一第一导线W1自所述第一端点pt1沿着垂直于所述第三基准线B3的方向延伸形成第一引线T1，每一第一导线W1的第一端点pt1相对于所述第一引线T1与第三基准线B3的交点两点之间的部分第一引线的长度定义为y，每两条第二导线W2的第四端点在所述第二基准线B2上的间距定义为p2，每一扇出走线100的第四端点pt4与相邻较长的一条扇出走线100的垂直连线位置定义第六端点pt6，每一扇出走线100的第四端点pt4与相邻较长的一条扇出走线100的第六端点pt6的间距定义为d，每一第二导线W2的第四端点pt4与其第六端点pt6的间距定义为p3，使得相邻两条扇出走线100之间长度差值ΔL以下列公式表示：ΔL= p3 - x- y= (p2 - p1) * (cos 2θ - sin θ) / cos θ。
在一实施例中，所述若干第一导线W1的第一电阻率小于所述若干第二导线W2的第二电阻率，并且第一条扇出走线100仅包括第一导线W1，第二条扇出走线100至最后一条扇出走线100分别包括所述第一导线W1以及所述第二导线W2。
在一实施例中，每一第一导线W1的片电阻值定义为R1，每一第二导线W2的片电阻值定义为R2，使得第n条扇出走线100的第二导线W2相对于第一条扇出走线100之第一导线W1的补偿阻抗差值ΔRn是以下列公式表示：ΔRn = R1 *n * (p2 - p1) * (cos 2θ - sin θ) / cos θ，其中n为大于1的正整数。
在一实施例中，所述补偿阻抗差值在第n条扇出走线100相对应于第一条扇出走线100所需更换为第二导线W2的长度ln以下列公式表示：ln = [R1 *n * (p2 - p1) * (cos 2θ - sin θ) / cos θ]/(R2-R1)。
在另实施例中，本专利申请提供一种液晶面板，包括扇出走线结构，所述扇出走线结构采用上述之扇出走线结构100。
此外，如图5所示之第一导线W1以及第二导线W2的结构示意图，在基材105上依序形成缓冲层107以及栅极绝缘层109，并且在栅极绝缘层109上形成第一导线W1(或是第二导线W2)(例如以蚀刻导电层的方式形成)，然后在第一导线W1(或是第二导线W2)形成介电层111以覆盖第一导线W1，并且介电层111中于第一导线W1的端点位置(例如第二端点)上形成过孔，随后在介电层111形成第二导线W2(或是第一导线W1)，使第一导线W1与第二导线W2形成直线共线连结结构或是平行连结结构。
本专利申请之液晶面板的扇出走线结构，通过扇出走线结构的相邻两条走线具有相等的阻抗，减少各条走线之间的最大阻抗值与最小阻抗值，使显示面板在显示过程中达到画面均一性的目的，从而改善扇出结构的颜色差异以及色偏的状况，有利于液晶显示器大尺寸化的设计。
虽然本专利申请已用较佳实施例揭露如上，然其并非用以限定本专利申请，本专利申请所属技术领域中具有通常知识者，在不脱离本专利申请的精神和范围内，当可作各种的更动与润饰，因此本专利申请的保护范围当视后附的权利要求范围所界定者为准。

Claims (18)

  1. 一种液晶面板的扇出走线结构，用以电性连接驱动电路的信号传送接口与所述液晶面板的信号接收接口，其中所述扇出走线结构包括：
    一基材；
    一第一区域，包括若干具有第一电阻率的第一导线，每一第一导线包括第一端点以及相对所述第一端点的第二端点，所述若干第一导线的第一端点电性连接所述信号传送接口；以及
    一第二区域，包括若干具有第二电阻率的第二导线，每一第二导线包括第三端点以及相对所述第三端点的第四端点，所述若干第二导线的第四端点电性连接所述信号接收接口，并且每一第一导线的第二端点相对应电性连接每一第二导线的第三端点，通过每一第一导线及/或每一第二导线以直线共线结构或是平行连接结构方式以形成若干条扇出走线，使每一扇出走线具有相同的阻抗值。
  2. 根据权利要求1所述的液晶面板的扇出走线结构，其中每一第一导线通过一过孔在所述第二端点以及所述第三端点以直线连结方式相对应电性连接每一第二导线。
  3. 根据权利要求2所述的液晶面板的扇出走线结构，其中所述第一走线区域与所述第二走线区域设置于相同或是不相同的材质层，使所述若干第一导线与所述若干第二导线在相同或是不相同的材质层形成电性连接。
  4. 根据权利要求1所述的液晶面板的扇出走线结构，其中每一第一导线通过一过孔在所述第二端点以及所述第三端点以平行连结方式相对应电性连接每一第二导线，使每一第一导线及每一第二导线除了在电性连接处的所述过孔之外，每一第一导线及每一第二导线皆以平行直线连结方式来形成若干条扇出走线。
  5. 根据权利要求4所述的液晶面板的扇出走线结构，其中所述第一走线区域与所述第二走线区域设置于相同或是不相同的材质层，使所述若干第一导线与所述若干第二导线在相同或是不相同的材质层形成电性连接。
  6. 根据权利要求1所述的液晶面板的扇出走线结构，其中所述若干第一导线的第一端点之间的连线形成一第一基准线，所述若干第二导线的第四端点之间的连线形成一第二基准线，通过每一第一导线的第一端点形成若干第三基准线并且每一第三基准线平行于所述第二基准线，其中每一扇出走线与所述第二基准线之间的夹角定义为θ，每两条第一导线的两个第一端点在所述第三基准在线的垂直投影间距定义为p1，每一第一导线的第一端点与相邻较短的一条扇出走线的垂直连线位置定义第五端点，每一第一导线的第一端点与相邻较短的一条扇出走线的第五端点的间距定义为x，每一第一导线的第一端点与相邻较短的一条扇出走线的第五端点之间的连线与所述第一基准线之间的夹角定义为α，在第一导线的第一端点上所述第一基准线与每一第三基准线的夹角为β，每一第一导线自所述第一端点沿着垂直于所述第三基准线的方向延伸形成第一引线，每一第一导线的第一端点相对于所述第一引线与第三基准线的交点两点之间的部分第一引线的长度定义为y，每两条第二导线的第四端点在所述第二基准在线的间距定义为p2，每一扇出走线的第四端点与相邻较长的一条扇出走线的垂直连线位置定义第六端点，每一扇出走线的第四端点与相邻较长的一条扇出走线的第六端点的间距定义为d，每一第二导线的第四端点与其第六端点的间距定义为p3，使得相邻两条扇出走线之间长度差值ΔL以下列公式表示：ΔL= p3 - x- y= (p2 - p1) * (cos 2θ - sin θ) / cos θ。
  7. 根据权利要求6所述的液晶面板的扇出走线结构，其中所述若干第一导线的第一电阻率小于所述若干第二导线的第二电阻率，并且第一条扇出走线仅包括第一导线，第二条扇出走线至最后一条扇出走线分别包括所述第一导线以及所述第二导线。
  8. 根据权利要求7所述的液晶面板的扇出走线结构，其中每一第一导线的片电阻值定义为R1，每一第二导线的片电阻值定义为R2，使得第n条扇出走线的第二导线相对于第一条扇出走线之第一导线的补偿阻抗差值ΔRn是以下列公式表示：ΔRn = R1 *n * (p2 - p1) * (cos 2θ - sin θ) / cos θ，其中n为大于1的正整数。
  9. 根据权利要求8所述的液晶面板的扇出走线结构，其中所述补偿阻抗差值在第n条扇出走线相对应于第一条扇出走线所需更换为第二导线的长度ln以下列公式表示：ln = [R1 *n * (p2 - p1) * (cos 2θ - sin θ) / cos θ]/(R2-R1)。
  10. 一种液晶面板，包括：
    一驱动电路；以及
    一扇出走线结构，用以传送所述所述驱动电路的信号至一显示面板，所述扇出走线结构包括：
    一基材；
    一第一区域，包括若干具有第一电阻率的第一导线，每一第一导线包括第一端点以及相对所述第一端点的第二端点，所述若干第一导线的第一端点电性连接所述信号传送接口；以及
    一第二区域，包括若干具有第二电阻率的第二导线，每一第二导线包括第三端点以及相对所述第三端点的第四端点，所述若干第二导线的第四端点电性连接所述信号接收接口，并且每一第一导线的第二端点相对应电性连接每一第二导线的第三端点，通过每一第一导线及/或每一第二导线以直线共线结构或是平行连接结构方式以形成若干条扇出走线，使每一扇出走线具有相同的阻抗值。
  11. 根据权利要求10所述的液晶面板，其中每一第一导线通过一过孔在所述第二端点以及所述第三端点以直线连结方式相对应电性连接每一第二导线。
  12. 根据权利要求11所述的液晶面板，其中所述第一走线区域与所述第二走线区域设置于相同或是不相同的材质层，使所述若干第一导线与所述若干第二导线在相同或是不相同的材质层形成电性连接。
  13. 根据权利要求10所述的液晶面板，其中每一第一导线通过一过孔在所述第二端点以及所述第三端点以平行连结方式相对应电性连接每一第二导线，使每一第一导线及每一第二导线除了在电性连接处的所述过孔之外，每一第一导线及每一第二导线皆以平行直线连结方式来形成若干条扇出走线。
  14. 根据权利要求13所述的液晶面板，其中所述第一走线区域与所述第二走线区域设置于相同或是不相同的材质层，使所述若干第一导线与所述若干第二导线在相同或是不相同的材质层形成电性连接。
  15. 根据权利要求10所述的液晶面板，其中所述若干第一导线的第一端点之间的连线形成一第一基准线，所述若干第二导线的第四端点之间的连线形成一第二基准线，通过每一第一导线的第一端点形成若干第三基准线并且每一第三基准线平行于所述第二基准线，其中每一扇出走线与所述第二基准线之间的夹角定义为θ，每两条第一导线的两个第一端点在所述第三基准在线的垂直投影间距定义为p1，每一第一导线的第一端点与相邻较短的一条扇出走线的垂直连线位置定义第五端点，每一第一导线的第一端点与相邻较短的一条扇出走线的第五端点的间距定义为x，每一第一导线的第一端点与相邻较短的一条扇出走线的第五端点之间的连线与所述第一基准线之间的夹角定义为α，在第一导线的第一端点上所述第一基准线与每一第三基准线的夹角为β，每一第一导线自所述第一端点沿着垂直于所述第三基准线的方向延伸形成第一引线，每一第一导线的第一端点相对于所述第一引线与第三基准线的交点两点之间的部分第一引线的长度定义为y，每两条第二导线的第四端点在所述第二基准在线的间距定义为p2，每一扇出走线的第四端点与相邻较长的一条扇出走线的垂直连线位置定义第六端点，每一扇出走线的第四端点与相邻较长的一条扇出走线的第六端点的间距定义为d，每一第二导线的第四端点与其第六端点的间距定义为p3，使得相邻两条扇出走线之间长度差值ΔL以下列公式表示：ΔL= p3 - x- y= (p2 - p1) * (cos 2θ - sin θ) / cos θ。
  16. 根据权利要求15所述的液晶面板，其中所述若干第一导线的第一电阻率小于所述若干第二导线的第二电阻率，并且第一条扇出走线仅包括第一导线，第二条扇出走线至最后一条扇出走线分别包括所述第一导线以及所述第二导线。
  17. 根据权利要求16所述的液晶面板，其中每一第一导线的片电阻值定义为R1，每一第二导线的片电阻值定义为R2，使得第n条扇出走线的第二导线相对于第一条扇出走线之第一导线的补偿阻抗差值ΔRn是以下列公式表示：ΔRn = R1 *n * (p2 - p1) * (cos 2θ - sin θ) / cos θ，其中n为大于1的正整数。
  18. 根据权利要求17所述的液晶面板，其中所述补偿阻抗差值在第n条扇出走线相对应于第一条扇出走线所需更换为第二导线的长度ln以下列公式表示：ln = [R1 *n * (p2 - p1) * (cos 2θ - sin θ) / cos θ]/(R2-R1)。
PCT/CN2016/070296 2015-12-15 2016-01-06 液晶面板的扇出走线结构及液晶面板 Ceased WO2017101179A1 (zh)

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