WO2017096780A1 - 具有高质量外延层的半导体器件及其制造方法 - Google Patents

具有高质量外延层的半导体器件及其制造方法 Download PDF

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WO2017096780A1
WO2017096780A1 PCT/CN2016/087244 CN2016087244W WO2017096780A1 WO 2017096780 A1 WO2017096780 A1 WO 2017096780A1 CN 2016087244 W CN2016087244 W CN 2016087244W WO 2017096780 A1 WO2017096780 A1 WO 2017096780A1
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semiconductor layer
layer
substrate
semiconductor
fin structure
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French (fr)
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朱慧珑
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority claimed from CN201510888548.9A external-priority patent/CN105609560B/zh
Priority claimed from CN201510888884.3A external-priority patent/CN105633167B/zh
Priority claimed from CN201610439233.0A external-priority patent/CN106098623B/zh
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to US15/781,988 priority Critical patent/US11038057B2/en
Publication of WO2017096780A1 publication Critical patent/WO2017096780A1/zh
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Definitions

  • the present disclosure relates to the field of semiconductors, and more particularly to a semiconductor device having a high quality epitaxial layer and a method of fabricating the same.
  • MOSFETs metal oxide semiconductor field effect transistors
  • a semiconductor device comprising: a substrate; a fin-shaped first semiconductor layer spaced apart from the substrate, wherein the first semiconductor layer extends in a longitudinal extension direction of the curved; and at least partially surrounding a second semiconductor layer on the outer circumference of the first semiconductor layer.
  • a method of fabricating a semiconductor device comprising: forming a first fin structure and a second fin structure extending in a longitudinal extension direction of a bend on a substrate, the first fin structure Stacked on the second fin structure; forming a support portion for supporting the first fin structure on the first fin structure and the second fin structure; at least partially removing the second fin structure from the first fin structure a portion of the bottom portion such that the first fin structure is separated from the second fin structure to form a first semiconductor layer; and the first semiconductor layer is used as a seed layer to grow a second semiconductor layer.
  • the (small) curved first semiconductor suspended relative to the substrate may be utilized
  • the layer serves as a seed layer for growing the second semiconductor layer, and the second semiconductor layer may have high mobility.
  • Such a suspended curved thin seed layer can relax stress in the first semiconductor layer and the second semiconductor layer, thereby helping to suppress defects in the first semiconductor layer or the second semiconductor layer.
  • FIGS. 1-16 are schematic views schematically showing a flow of manufacturing a semiconductor device in accordance with an embodiment of the present disclosure
  • 17-18 are schematic diagrams schematically showing a partial stage in a process of fabricating a semiconductor device in accordance with another embodiment of the present disclosure.
  • a layer/element when referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be a central layer between them/ element. In addition, if a layer/element is "on” another layer/element, the layer/element may be "under” the other layer/element when the orientation is reversed.
  • a semiconductor device having a suspended fin structure refers to a structure protruding from the surface of the substrate, including but not limited to fins in a fin field effect transistor (FinFET); the so-called “suspension” means that the fin is separated from the substrate. .
  • FinFET fin field effect transistor
  • the spacing between the substrates can be filled with other materials (eg, an isolation layer).
  • the fins may include high mobility semiconductor materials to improve device performance.
  • the "high mobility” means that the mobility with respect to silicon (Si) is high.
  • High mobility semiconductor materials such as Ge, SiGe or III-V compound semiconductors, and the like.
  • the fin may be a second semiconductor layer formed on (eg, epitaxially) a first semiconductor layer spaced apart from the substrate on the substrate.
  • the first semiconductor layer may have a fin shape extending in a longitudinal direction of bending (for example, a substantially "C" shape or an "S" shape) and suspended relative to the substrate.
  • the second semiconductor layer can be formed at least partially around the outer circumference of the first semiconductor layer, thereby also being fin-shaped and then can be used as a fin of the device.
  • “partially surrounding” means that there may be a range along the longitudinal extension direction of the first semiconductor layer, within which the second semiconductor layer may completely enclose the outer surface of the first semiconductor layer.
  • the second semiconductor layer may form a closed pattern (for example, a rectangle, a polygon, etc. corresponding to the sectional shape of the first semiconductor layer) in a cross section perpendicular to the longitudinal extension direction of the first semiconductor layer.
  • the first semiconductor layer may be covered by the second semiconductor layer in addition to the surface covered by the support portion.
  • the first semiconductor layer is relatively thin (eg, having a thickness of about 3-20 nm) and is suspended relative to the substrate.
  • the first semiconductor layer may be physically connected to the substrate via the support and thus supported by the substrate.
  • a portion of the first semiconductor layer connected to the support portion may extend beyond a longitudinal extension of the first semiconductor layer.
  • the support portion may include a laterally extending portion extending along a surface of the substrate and a vertically extending portion extending in a direction substantially perpendicular to the surface of the substrate, wherein the vertically extending portion extends to a vertical direction of the first semiconductor layer substantially perpendicular to the surface of the substrate On the side wall.
  • the first semiconductor layer is physically connected to the substrate through the support portion and thus supported by the substrate.
  • the vertically extending portions of the support portion may extend over the vertical sidewalls on opposite sides of the first semiconductor layer to sandwich the first semiconductor layer.
  • the support portion may be provided at both end portions of the fin-shaped first semiconductor layer.
  • an isolation layer may be formed on the substrate for electrically isolating the field.
  • the isolation layer may fill a space between the first and second semiconductor layers and the substrate and expose the second semiconductor layer to a small extent.
  • the isolation layer may be in contact with the second semiconductor layer; and at the remaining locations, the top surface of the isolation layer may be closer to the substrate than the bottom surface of the second semiconductor layer facing the substrate.
  • the isolation layer can have undercuts. In this way, the gate stack can be embedded in the undercut so that the bottom of the gate can be effectively controlled.
  • a plurality of devices may be formed based on the same fin (ie, the second semiconductor layer).
  • respective devices may be formed based on different portions of the fin along its longitudinal extension.
  • there may be more than one, for example two or more, gate stacks that intersect the same fin (ie, the second semiconductor layer) to form respective devices, respectively.
  • the gate stack may include a first gate stack and a second gate stack separated along a longitudinal extension direction of the fin.
  • the first gate stack may intersect a first portion of the fin in a longitudinal extension direction (ie, a second semiconductor layer portion formed around a first portion of the first semiconductor layer in a longitudinal extension direction), and the second gate stack may extend longitudinally with the fin
  • the second portion of the direction i.e., the portion of the second semiconductor layer formed around the outer circumference of the second portion of the first semiconductor layer in the longitudinal extension direction
  • the respective devices of the first gate stack and the second gate stack may be isolated from each other.
  • a dielectric layer can be formed to separate the first portion and the second portion of the first semiconductor layer.
  • the dielectric layer may extend in a direction intersecting the longitudinal extension direction of the first semiconductor layer, and may further separate different portions of the second semiconductor layer.
  • Such a semiconductor device can be produced, for example, as follows. Specifically, a first fin structure and a second fin structure having a curved (eg, substantially "C" shape or "S" shape) longitudinal extension direction may be formed on the substrate, wherein the first fin structure is stacked Above the two fin structure. Subsequently, when at least the portion of the second fin structure close to the bottom of the first fin structure is removed, the first fin structure may be separated from the second fin structure to form a first semiconductor layer, and the first semiconductor layer may be opposite to the first semiconductor layer The substrate (or, relative to the substrate + the remainder of the second fin structure) is suspended.
  • a first fin structure and a second fin structure having a curved (eg, substantially "C" shape or "S” shape) longitudinal extension direction may be formed on the substrate, wherein the first fin structure is stacked Above the two fin structure. Subsequently, when at least the portion of the second fin structure close to the bottom of the first fin structure is removed, the first fin structure may be separated from the second fin structure
  • a support portion may be formed.
  • a support portion can be formed as follows. Specifically, a layered material (hereinafter referred to as a support layer) may be formed on a substrate on which the first and second fin structures are formed, and the support layer is patterned to physically connect the first and second fins The surface of the structure forms a support. In this way, when at least the portion of the second fin structure close to the bottom of the first fin structure is removed, the first semiconductor layer may be physically connected to the remaining portion of the second fin structure through the support portion, and thus by the second fin shape The rest of the structure is supported.
  • a support layer a layered material
  • support can be The layer is patterned into a support that extends from the surface of the substrate to the surface of the first fin structure and thus physically connects the first fin structure to the substrate.
  • the first semiconductor layer can be physically connected to the substrate through the support portion and supported thereby by the substrate.
  • the patterning of the support layer can be performed using a mask.
  • the mask extends over the first and second fin structures beyond the first and second fin structures in a direction perpendicular to the longitudinal extension direction of the first and second fin structures (so that the mask can shield the support) a portion of the layer extending over the surface of the substrate on both sides of the first and second fin structures such that the portion can be subsequently retained; and in the longitudinal extension of the first and second fin structures, the mask is The first and second fin structures cover only a portion of the longitudinal extent of the first and second fin structures (such that the mask obscures only a portion of the longitudinal extent of the first and second fin structures such that the portion is subsequently Can be connected to the support).
  • the mask may cover both end portions of the first and second fin structures, and the resulting support portions may be located at both side ends of the first and second fin structures, respectively.
  • the first semiconductor layer is similar to the cantilever configuration with respect to the substrate, the support being similar to the anchor of the cantilever, anchoring the first semiconductor layer as a cantilever to the substrate.
  • the second fin structure may include a sacrificial layer formed on the substrate, and the first fin shape
  • the structure may include a first semiconductor layer stacked on the sacrificial layer.
  • the sacrificial layer and the first semiconductor layer may be sequentially formed on the substrate, and then the first semiconductor layer and the sacrificial layer may be patterned into a fin structure.
  • the patterning step can be performed into the substrate so as to have protrusions at a position on the substrate corresponding to the fin structure. Subsequently, the sacrificial layer can be selectively removed.
  • a second semiconductor layer can be grown on the surface thereof.
  • the second semiconductor layer can cover all surfaces exposed by the first semiconductor layer (supported portion).
  • This second semiconductor layer may be (curved) finlike like the first semiconductor layer and may then serve as the fin of the device.
  • an isolation layer can be formed on the substrate and a gate stack intersecting the second semiconductor layer can be formed on the isolation layer.
  • the isolation layer may fill a space between the first semiconductor layer, the second semiconductor layer, and the substrate, and at least partially expose the second semiconductor layer.
  • the spacer layer can be obtained by depositing a dielectric such as an oxide and etching back.
  • the material of the support can be Unlike the material of the barrier layer, it does not damage the support during etchback.
  • the isolation layer may be etched back such that the isolation layer is in contact with the second semiconductor layer under the second semiconductor layer; and at the remaining positions, the top surface of the isolation layer is closer to the substrate than the bottom surface of the second semiconductor layer facing the substrate . Further, at the time of etch back, an undercut may be formed under the second semiconductor layer.
  • two or more gate stacks may be formed to form respective devices. Isolation can be formed between the devices as designed.
  • a dielectric layer extending in a direction intersecting the longitudinal extension direction of the first semiconductor layer may be formed on the isolation layer, the dielectric layer may divide the first semiconductor layer into the first portion and the second portion, and may be the second semiconductor The layer is divided into a first part and a second part.
  • the gate stack may be formed to include a first gate stack that intersects the first portion of the second semiconductor layer and a second gate stack that intersects the first portion of the second semiconductor layer.
  • a substrate 1001 is provided.
  • the substrate 1001 may be a substrate of various forms such as, but not limited to, a bulk semiconductor material substrate such as a bulk Si substrate or the like. In the following description, a bulk Si substrate will be described as an example for convenience of explanation.
  • the sacrificial layer 1003 and the first semiconductor layer 1005 are sequentially formed, for example, by epitaxial growth.
  • the sacrificial layer 1003 may include a semiconductor material different from the substrate 1001 and the first semiconductor layer 1005, such as SiGe (the atomic percentage of Ge is, for example, about 5 to 20%), and the thickness is about 10 to 100 nm.
  • the first semiconductor layer 1005 may comprise a suitable semiconductor material, such as Si, having a thickness of between about 10 and 100 nm.
  • the first semiconductor layer 1005 and the sacrificial layer 1003 (and optionally the substrate 1001) thus formed may be patterned to form a fin structure.
  • this can be done as follows.
  • a hard mask layer may be formed on the first semiconductor layer 1005.
  • the hard mask layer can include an oxide (eg, silicon oxide) layer 1007 and a polycrystalline Si layer 1009.
  • the oxide layer 1007 has a thickness of about 2 to 10 nm
  • the polycrystalline Si layer 1009 has a thickness of about 50 to 120 nm.
  • the hard mask is patterned into fins using a pattern transfer technique.
  • a photoresist PR patterned (for example, by exposure, development) may be formed on the hard mask layer.
  • the photoresist PR is patterned in a strip shape extending in the bending direction, and its width (dimension in the horizontal direction in the drawing) may substantially correspond to the interval between the two fin structures. This curved shape can be curved, bowed, polynomial or Its combination and so on.
  • the photoresist PR is patterned into a substantially "C" shape.
  • the polycrystalline Si layer 1009 (relative to the oxide layer 1007) is selectively etched, such as reactive ion etching (RIE), using the photoresist PR as a mask.
  • RIE reactive ion etching
  • the polycrystalline Si layer 1009 can be patterned into a curved strip corresponding to the photoresist PR.
  • FIGS. 3(a) and 3(b) Fig. 3(a) is a plan view
  • Fig. 3(b) is a cross-sectional view taken along line AA' in Fig. 3(a)
  • the photoresist PR is removed.
  • a spacer 1011 is formed on the sidewall of the polycrystalline Si layer 1009. There are various means in the art to form side walls.
  • a layer of nitride (e.g., silicon nitride) may be substantially conformally deposited by, for example, atomic layer deposition (ALD), having a thickness of, for example, about 3 to 20 nm, and then selectively etching the deposited nitride.
  • ALD atomic layer deposition
  • the RIE is removed from its laterally extending portion such that the vertically extending portion remains to form the side wall 1011.
  • the sidewall 1011 covers the sidewall of the Si layer 1009.
  • the polycrystalline Si layer 1009 can be selectively removed (eg, by TMAH solution).
  • the side wall 1011 is also present, so that the side wall 1011 surrounds the outer periphery of the strip-shaped polycrystalline Si layer 1009.
  • a closed pattern is formed.
  • the upper and lower sides of the side wall 1011 can be removed by photolithography, so that the side wall 1011 which is originally a closed pattern can be separated into two parts. Each portion corresponds to a fin structure to be formed, which in this example is two "C" strips as shown in Fig. 3(a).
  • the oxide layer 1007, the first semiconductor layer 1005, and the sacrificial layer 1003 may be selectively etched, such as RIE, by using the sidewall 1011 as a mask.
  • the pattern of the side wall 1011 is transferred to the lower layer to obtain a fin structure.
  • the fin structure includes a first fin structure composed of the semiconductor layer 1005 and a second fin structure composed of the sacrificial layer 1003. Therefore, the width of the first semiconductor layer 1005 (the dimension in the horizontal direction in the drawing) is substantially the same as the width of the spacer 1011 (for example, about 3 to 20 nm).
  • the substrate 1001 can be further selectively etched.
  • the substrate 1001 may have protrusions thereon.
  • the projection of the fin structure on the substrate is located substantially in the middle of the protrusion. Due to the etching characteristics, the etched sacrificial layer 1003 and the protrusions of the substrate 1001 may have a shape that gradually becomes larger from top to bottom. Thereafter, the sidewall spacers 1011 can be selectively removed, and the oxide layer 1007 can be further selectively removed, as shown in FIG.
  • a curved fin-shaped photoresist may be directly formed on the first semiconductor layer 1005, and the first semiconductor layer 1005, the sacrificial layer 1003, and the substrate 1001 may be selectively etched using the photoresist as a mask to form a bend. Fin structure.
  • a curved fin-shaped photoresist may be directly formed on the hard mask layer, the hard mask is patterned into a curved fin by a photoresist, and the first is selectively etched by a hard mask of a curved fin.
  • the semiconductor layer 1005, the sacrificial layer 1003, and the substrate 1001 are formed to form a curved fin structure.
  • fin structures are shown. However, the present disclosure is not limited thereto, and for example, more or less fin structures may be formed. In addition, the layout of the fin structure can be designed differently depending on the device requirements.
  • a support portion may be formed.
  • oxide layer 1015 and nitride layer 1017 may be deposited in a substantially conformal manner on a substrate having a fin structure formed thereon, such as by ALD.
  • the oxide layer 1015 may have a thickness of about 1 to 10 nm
  • the nitride layer 1017 may have a thickness of about 2 to 15 nm.
  • a patterned photoresist 1019 can be formed on the structure shown in FIG.
  • the photoresist 1019 is patterned to cover the ends of the fin structures on both sides (upper and lower sides in the drawing) and extends in the horizontal direction in the drawing. It should be noted here that in the top view of FIG. 8, the appearance of the nitride layer 1017 with the fin structure on the substrate is not shown for convenience, and the same is true in the following plan view.
  • FIG. 9(a) is a plan view
  • Fig. 9(b) is a cross-sectional view taken along line AA' in Fig. 9(a)
  • Fig. 9 ( c) is a cross-sectional view taken along line A1A1' in Fig. 9(a)
  • the nitride layer 1017 is selectively removed by, for example, RIE (relative to the oxide layer 1015) using the photoresist 1019 as a mask.
  • RIE reactive vapor deposition
  • the nitride layer 1017 is left at the ends of both sides of the fin structure (upper and lower sides in FIG.
  • the nitride layer 1017 physically connects the fin structure to the substrate 1001 and thus can support the fin structure (particularly after removing the sacrificial layer 1003 as described below). Thereafter, the photoresist 1019 can be removed.
  • a support layer of a laminate structure of an oxide layer and a nitride layer is formed, and the support layer is patterned into a support portion.
  • the support layer can include a variety of suitable dielectric materials.
  • the support layer may even comprise a semiconductor material or a conductive material.
  • the tip end portion of the nitride layer 1017 can also be selectively removed, for example, by RIE (relative to the oxide layer 1015). However, nitriding A portion of the object layer 1017 remains on the sidewall of the first semiconductor layer 1005 to subsequently support the first semiconductor layer 1005.
  • FIGS. 11(a) and 11(b) correspond to the cross-sectional view in FIG. 9(a)
  • FIG. 11(b) corresponds to the cross-sectional view in FIG. 9(c)
  • the oxide layer 1015 can be selectively removed by, for example, RIE, (relative to the substrate 1001 of the Si material and the first semiconductor layer 1005 and the sacrificial layer 1003 of the SiGe material).
  • RIE reactive vapor deposition
  • the middle portion of the fin structure is completely exposed; further, as shown in FIG. 11(b), at both end portions of the fin structure, the oxide layer 1015 is covered by the nitride layer 1017. And can be retained.
  • FIGS. 12(a) and 12(b) corresponding to the cross-sectional views of FIGS. 11(a) and 11(b), respectively, by, for example, wet etching, (relative to the substrate 1001 of the Si material) And the first semiconductor layer 1005) selectively removes the sacrificial layer 1003.
  • a space 1021 is formed between the fin-shaped first semiconductor layer 1005 and the substrate 1001.
  • the sacrificial layer 1003 is completely removed.
  • the present disclosure is not limited thereto.
  • the sacrificial layer 1003 may be removed only from a portion near the bottom of the first semiconductor layer 1005.
  • the growth around the outer circumference of the first semiconductor layer 1005 can be achieved as follows.
  • the first semiconductor layer 1005 is spaced apart from the substrate 1001 by a spacer 1021, extends substantially parallel to the surface of the substrate, and is supported by the substrate 1001 via the support portion 1015/1017.
  • the support portion 1015/1017 includes a laterally extending portion extending over the surface of the substrate 1001 and a vertically extending portion extending in a direction substantially perpendicular to the surface of the substrate.
  • the vertically extending portion may include a portion extending along a surface of the protrusion of the substrate 1011, a portion extending along a surface of the sacrificial layer 1003 (which has been removed), and extending along a vertical sidewall of the first semiconductor layer 1005.
  • the support portion 1015/1017 physically connects the first semiconductor layer 1005 to the substrate 1001 so that the first semiconductor layer 1005 can be supported.
  • the support portions 1015/1017 may extend on vertical sidewalls on opposite sides (left and right sides in the drawing) of the first semiconductor layer 1005, thereby sandwiching the first semiconductor layer to support the first semiconductor layer 1005 more stably .
  • the extension of the portion where the first semiconductor layer 1005 and the support portion 1015/1017 are connected is smaller than the longitudinal extension of the first semiconductor layer 1005.
  • the "longitudinal extension direction” means the longitudinal direction of the first semiconductor layer 1005, which substantially coincides with the longitudinal direction of the channel region formed later, that is, the direction from the source region to the drain region or vice versa.
  • the first semiconductor layer 1005 forms a structure similar to the cantilever beam with respect to the substrate 1001, and the cantilever beam is anchored to the substrate 1001 through the support portion 1015/1017.
  • the support portion includes the oxide layer 1015 in addition to the nitride layer 1017, but the present disclosure is not limited thereto.
  • the nitride layer 1017 may be formed without forming the oxide layer 1015.
  • subsequent operations can also be performed in the manner described above in connection with Figures 8-12.
  • the support portion may also be other dielectric materials or laminated structures.
  • the mask 1019 (see FIG. 8) for patterning the support portion is not limited to the above shape.
  • the mask may extend beyond the fin structure over the fin structure in a direction perpendicular to the longitudinal extension of the fin structure. In this way, the mask can cover a portion of the nitride layer 1017 that extends over the surface of the substrate 1001 (outside the protrusion), which portion can then remain (acting as a base for the support).
  • the mask in the longitudinal extension direction of the fin structure, the mask may cover only a portion of the longitudinal extension of the fin structure above the fin structure. In this way, a configuration similar to a cantilever-anchoring structure can be formed.
  • Figs. 13(a), 13(b) and 13(c) are a plan view
  • Fig. 13(b) is a cross-sectional view taken along line AA' in Fig. 13(a)
  • Fig. 13 ( c) is a cross-sectional view taken along line A1A1' in Fig. 13(a)
  • the second semiconductor layer 1023 may be grown on the first semiconductor layer 1005.
  • the second semiconductor layer 1023 may include a high mobility material such as a Ge, SiGe or III-V compound semiconductor such as InSb, InGaSb, InAs, GaAs, InGaAs, AlSb, InP, Group III nitride, etc., and the thickness may be About 5 to 15 nm.
  • a composition thereof for example, a percentage of Ge atom
  • the lattice constants of 1005 differ greatly in order to suppress the generation of dislocations or defects.
  • This growth may be selective growth such that the second semiconductor layer 1023 is grown only on the surface of the first semiconductor layer 1005 (and the substrate 1001) of the semiconductor material.
  • the growth of the second semiconductor layer 1023 can be controlled such that it does not completely fill the gap 1021 between the first semiconductor layer 1005 and the substrate 1001. Due to the suspended configuration of the first semiconductor layer 1005, stress in the first semiconductor layer 1005 and the second semiconductor layer 1023 may be relaxed during growth.
  • the lattice constant of the second semiconductor layer 1023 such as a Ge, SiGe or III-V compound semiconductor layer is generally larger than the lattice constant of silicon, and thus the first semiconductor layer 1005 of silicon is The length of the seed grown second semiconductor layer 1023 will increase relative to the first semiconductor layer 1005. Thus, as indicated by the arrow in the figure, the center of the second semiconductor layer 1023 will be shifted to the left side with respect to the original center of the first semiconductor layer 1005. This helps release stress during growth.
  • the occurrence of defects in the first semiconductor layer 1005 or the second semiconductor layer 1023 can be suppressed or avoided. This helps improve device performance (for example, reducing off-state leakage current and boosting on-state current).
  • the remaining surface of the first semiconductor layer 1005 is covered by the second semiconductor layer except for the surface covered by the support portion 1015/1017.
  • the second semiconductor layer 1023 may also be grown on the surface of the substrate 1001.
  • the second semiconductor layer 1023 in the longitudinal extension direction of the first semiconductor layer, completely encloses the outer circumference of the first semiconductor layer 1005 at the remaining longitudinal extent except for the longitudinal extent occupied by the support portion.
  • the second semiconductor layer 1023 forms a closed pattern (a rectangle in this example).
  • the closed pattern is defined by the pattern of the first semiconductor layer 1005 at the cross section, and may be other shapes such as a polygon.
  • the second semiconductor layer 1023 thus shaped can then serve as the fin of the device.
  • a gate stack intersecting the fins may be formed and a final semiconductor device (eg, a FinFET) formed.
  • An isolation layer 1025 is first formed on the second semiconductor layer 1023 formed on the bottom 1001.
  • Such an isolation layer can be formed, for example, by depositing a dielectric material such as an oxide on the substrate and then performing etch back. During the etch back process, the etch back depth is controlled such that the resulting isolation layer 1025 is capable of at least partially exposing the second semiconductor layer 1023.
  • the isolation layer 1025 is also filled with a space 1021.
  • the isolation layer 1025 is in contact with the second semiconductor layer 1023; and at the remaining locations, the top surface of the isolation layer 1025 is lower than the bottom surface of the second semiconductor layer 1023.
  • the isolation layer 1025 may be formed with an undercut (due to etch back).
  • the isolation layer 1025 substantially fills the space between the first semiconductor layer 1005, the second semiconductor layer 1023, and the substrate 1001.
  • the present disclosure is not limited thereto.
  • the top surface of the isolation layer 1025 may be detached from the bottom surface of the second semiconductor layer 1023.
  • a gate stack intersecting the fins may be formed on the isolation layer 1025.
  • this can be done as follows.
  • the gate dielectric layer 1027 and the gate conductor layer 1029 may be sequentially formed.
  • the gate dielectric layer 1027 may include an oxide (eg, SiO 2 or GeO 2 ) having a thickness of about 0.3 to 2 nm, and the gate conductor layer 1029 may include polysilicon; or the gate dielectric layer 1027 may include a thickness of about 1 to 4 nm.
  • the high K gate dielectric such as HfO 2 or Al 2 O 3 , the gate conductor layer 1029 may include a metal gate conductor.
  • a function adjustment layer (not shown), such as TiN, Al, Ti, TiAlC, may be formed between the gate dielectric layer 1027 and the gate conductor layer 1029, and has a thickness of about 1 to 3 nm.
  • the gate dielectric layer 1027 and the gate conductor layer 1029 may be patterned by, for example, photolithography to form a gate stack G.
  • a gate stack G there are two gate stacks G that intersect the same fin structure.
  • the present disclosure is not limited thereto.
  • the layout of the gate stack G can be based on the device design.
  • a gate stack can be used as a mask for halo implantation and extension implantation.
  • a gate spacer can be formed on the sidewalls of the gate stack.
  • Source/drain (S/D) implantation can then be performed using the gate stack and the gate spacer as a mask.
  • the implanted ions may be activated by annealing to form source/drain regions in the second semiconductor layer 1023 on both sides (upper and lower sides in the drawing) of the gate stack G.
  • each of the gate stack G and the fins 1023 constitute respective devices such as FinFETs. Depending on the device design, these devices can be connected or isolated.
  • An example of isolation of devices from each other is shown in FIG. Specifically, as shown in FIG. 16, a dielectric layer 1031 extending in a direction intersecting the longitudinal extension direction of the fin structure may be formed on the isolation layer 1025 to divide the first semiconductor layer 1005 into two parts separated from each other, and The second semiconductor layer 1023 is divided into two portions that are isolated from each other.
  • the second semiconductor layer 1023 and the first semiconductor layer 1005 may be selectively etched by photolithography to form a gap therein. Then, a dielectric material such as an oxide is filled in the gap to form the dielectric layer 1031.
  • the semiconductor device of this embodiment may include a first semiconductor layer 1005 spaced apart from the substrate 1001, and the first semiconductor layer 1005 is physically connected to the substrate 1001 via the support portion 1015/1017 (see FIG. 12 (see FIG. 12). b)).
  • a second semiconductor layer 1023 is formed to serve as a fin of the device.
  • the device further includes an isolation layer 1025 and a gate stack G (1027, 1029) formed on the isolation layer 1025 that intersects the fins 1023. Due to the undercut of the isolation layer 1025, the gate stack can be embedded in the undercut, so that The bottom of the fin 1023 is effectively controlled.
  • the support portion is retained in the final device structure.
  • the support may also be selectively (at least partially) removed (eg, after forming the gate stack), the space resulting from its removal being subsequently filled, for example, by other dielectric layers.
  • the support portions are formed at both end portions of the first semiconductor layer, and both ends of the curved fin structure can be fixed, which is particularly advantageous for the curved fin structure.
  • the present disclosure is not limited thereto, and a support portion may be formed at other portions of the first semiconductor layer in addition to or instead of the both end portions.
  • a substantially "C" shaped curved fin structure is formed, but the present disclosure is not limited thereto, and various curved shapes such as an arc shape, an arc shape, a polynomial curve, and the like, or a combination thereof may be formed.
  • the photoresist PR may be patterned into a substantially "S" shape instead of a substantially "C” shape.
  • Other operations can be performed as described above.
  • the second semiconductor layer 1023 which also extends in a substantially "S" shape can be grown as shown in Fig. 18.
  • the length of the second semiconductor layer 1023 may also be increased relative to the first semiconductor layer 1005 as described above.
  • the center of the second semiconductor layer 1023 will be offset from the original center of the first semiconductor layer 1005. This helps release stress during growth. More specifically, the center may be offset toward the convex side of the curved shape (the upper half of the "S" shape is shifted to the left side, and the lower half of the "S” shape is shifted to the right side). Thereafter, a gate stack intersecting the "S" shaped fins 1023 can be formed in the manner described above.
  • the FinFET is taken as an example, but the present disclosure is not limited thereto.
  • the technology of the present disclosure can be applied to various semiconductor devices, particularly semiconductor devices that require high mobility materials such as Ge, SiGe, III-V compound semiconductor materials, such as various optoelectronic devices such as photodiodes, laser diodes (LD). )Wait.
  • a pn junction can be formed by doping a semiconductor layer epitaxially grown on the seed layer to form a diode.
  • a semiconductor device can be applied to various electronic devices. For example, by integrating a plurality of such semiconductor devices and other devices (eg, other forms of transistors, etc.), an integrated circuit (IC) can be formed, and thereby an electronic device can be constructed. Accordingly, the present disclosure also provides an electronic device including the above semiconductor device.
  • the electronic device can also include a display screen that cooperates with the integrated circuit And components such as wireless transceivers that cooperate with integrated circuits.
  • Such electronic devices are, for example, smart phones, tablet computers (PCs), personal digital assistants (PDAs), and the like.
  • a method of fabricating a chip system is also provided.
  • the method can include the above method of fabricating a semiconductor device.
  • a variety of devices can be integrated on a chip, at least some of which are fabricated in accordance with the methods of the present disclosure.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

公开了具有高质量外延层的半导体器件及其制造方法。半导体器件可以包括：衬底（1001）；与衬底（1001）相隔开的鳍状第一半导体层（1005），其中第一半导体层（1005）沿弯曲的纵向延伸方向延伸；以及至少部分环绕第一半导体层（1005）外周的第二半导体层（1023）。

Description

具有高质量外延层的半导体器件及其制造方法
相关申请的引用
本申请要求于2016年6月17日递交的题为“具有高质量外延层的半导体器件及其制造方法”的中国专利申请201610439233.0的优先权，其内容一并于此用作参考。
技术领域
本公开涉及半导体领域，更具体地，涉及一种具有高质量外延层的半导体器件及其制造方法。
背景技术
随着半导体器件的发展，期望以迁移率高于硅(Si)的半导体材料来制作高性能半导体器件如金属氧化物半导体场效应晶体管(MOSFET)。但是，难以形成高质量的高迁移率半导体材料。
发明内容
本公开的目的至少部分地在于提供一种具有高质量外延层的半导体器件及其制造方法。
根据本公开的一个方面，提供了一种半导体器件，包括：衬底；与衬底相隔开的鳍状第一半导体层，其中第一半导体层沿弯曲的纵向延伸方向延伸；以及至少部分环绕第一半导体层外周的第二半导体层。
根据本公开的另一方面，提供了一种制造半导体器件的方法，包括：在衬底上形成沿弯曲的纵向延伸方向延伸的第一鳍状结构和第二鳍状结构，第一鳍状结构堆叠在第二鳍状结构之上；在第一鳍状结构和第二鳍状结构上形成用以支撑第一鳍状结构的支撑部；至少部分去除第二鳍状结构靠近第一鳍状结构底部的部分，从而第一鳍状结构与第二鳍状结构相分离而形成第一半导体层；以及以第一半导体层为种子层，生长第二半导体层。
根据本公开的实施例，可以利用相对于衬底悬置的(薄)弯曲第一半导体 层作为种子层，来生长第二半导体层，第二半导体层可以具有高迁移率。这种悬置的弯曲薄种子层可以使第一半导体层和第二半导体层中的应力弛豫，从而有助于抑制第一半导体层或第二半导体层中的缺陷。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1-16是示意性示出了根据本公开实施例的制造半导体器件流程的示意图；
图17-18是示意性示出了根据本公开另一实施例的制造半导体器件流程中部分阶段的示意图。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
根据本公开的实施例，提供了一种具有悬置鳍结构的半导体器件。在此，所谓“鳍结构”，是指相对于衬底表面突出的构造，包括但不限于鳍式场效应晶体管(FinFET)中的鳍；所谓“悬置”，是指鳍与衬底相分离。注意，鳍与 衬底之间的间隔可以被其他材料(例如，隔离层)填充。鳍可以包括高迁移率半导体材料，以改善器件性能。在此，所谓的“高迁移率”是指相对于硅(Si)的迁移率要高。高迁移率半导体材料例如Ge、SiGe或III-V族化合物半导体等。
鳍可以是在衬底上与衬底隔开的第一半导体层上(例如，外延)形成的第二半导体层。第一半导体层可以呈沿弯曲(例如，大致“C”形或“S”形)纵向延伸方向延伸的鳍状，且相对于衬底悬置。于是，第二半导体层可以至少部分地环绕第一半导体层的外周形成，从而也呈鳍状且随后可以用作器件的鳍。在此，所谓“部分地环绕”，是指沿第一半导体层的纵向延伸方向可以存在一范围，在该范围内，第二半导体层可以完全包封第一半导体层的外表面。也即，在该范围内，在与第一半导体层的纵向延伸方向垂直的截面上，第二半导体层可以形成闭合图案(例如，与第一半导体层的截面形状相对应的矩形、多边形等)。当然，第一半导体层除了被支撑部覆盖的表面之外，其余表面也可以被第二半导体层覆盖。第一半导体层相对较薄(例如，厚度为约3～20nm)，且相对于衬底悬置。这样，在生长过程中第一半导体层和第二半导体层中的应力可以得以弛豫，且因此可以抑制或避免在第一半导体层或第二半导体层中产生缺陷。
第一半导体层可以经支撑部物理连接到衬底并因此由衬底支撑。在第一半导体层的纵向延伸方向上，第一半导体层与支撑部相连接的部分的延伸范围可以小于第一半导体层的纵向延伸长度。这样，当仅观察第一半导体层、衬底和支撑部之间的位置关系(不考虑其他层结构)时，第一半导体层类似于一种悬梁构造，支撑部类似于悬梁的锚定结构(anchor)。
支撑部可以包括沿衬底表面延伸的横向延伸部分以及沿大致垂直于衬底表面的方向延伸的竖直延伸部分，其中竖直延伸部分延伸至第一半导体层大致垂直于衬底表面的竖直侧壁上。这样，通过该支撑部，将第一半导体层物理连接到衬底上，并因此由衬底支撑。支撑部的竖直延伸部分可以在第一半导体层的相对两侧的竖直侧壁上延伸，从而夹持第一半导体层。
支撑部可以设于鳍状的第一半导体层的两侧端部。
对于形成场效应晶体管的情形，衬底上可以形成有隔离层，用以电隔离场 效应晶体管的栅堆叠和衬底。隔离层可以填充第一和第二半导体层与衬底之间的空间，并少部分地露出第二半导体层。例如，在第二半导体层下方，隔离层可以与第二半导体层相接；而在其余位置处，隔离层的顶面可以比第二半导体层面向衬底的底面要靠近衬底。在第二半导体层下方，隔离层可以具有底切。这样，栅堆叠可以嵌入到该底切中，从而可以有效控制栅的底部。
根据实施例，基于同一鳍(即，第二半导体层)可以形成多个器件。例如，可以基于该鳍沿其纵向延伸方向的不同部分，分别形成相应的器件。在场效应晶体管的情况下，与同一鳍(即，第二半导体层)相交的栅堆叠可以多于一个，例如两个或更多，以分别形成相应的器件。例如，栅堆叠可以包括沿鳍的纵向延伸方向分开的第一栅堆叠和第二栅堆叠。第一栅堆叠可以与鳍沿纵向延伸方向的第一部分(即，绕第一半导体层沿纵向延伸方向的第一部分外周形成的第二半导体层部分)相交，第二栅堆叠可以与鳍沿纵向延伸方向的第二部分(即，绕第一半导体层沿纵向延伸方向的第二部分外周形成的第二半导体层部分)相交。第一栅堆叠和第二栅堆叠各自对应的器件可以彼此隔离。例如，可以形成有电介质层，以将第一半导体层的第一部分和第二部分隔开。该电介质层可以沿与第一半导体层的纵向延伸方向相交的方向延伸，并可以进一步将第二半导体层的不同部分隔开。
这种半导体器件例如可以如下制作。具体地，可以在衬底上形成具有弯曲(例如，大致“C”形或“S”形)纵向延伸方向的第一鳍状结构和第二鳍状结构，其中第一鳍状结构堆叠在第二鳍状结构之上。随后，当至少去除该第二鳍状结构靠近第一鳍状结构底部的部分时，第一鳍状结构可以与第二鳍状结构相分离而形成第一半导体层，第一半导体层可以相对于衬底(或者说，相对于衬底+第二鳍状结构的剩余部分)悬置。
为了支撑随后将悬置的第一半导体层，可以形成支撑部。这种支撑部可以如下形成。具体地，可以在形成有第一和第二鳍状结构的衬底上形成层状材料(以下称作支撑层)，并通过将该支撑层构图为在物理上连接第一和第二鳍状结构的表面来形成支撑部。这样，当至少去除第二鳍状结构靠近第一鳍状结构底部的部分时，第一半导体层可以通过支撑部在物理上连接到第二鳍状结构的剩余部分，并因此由第二鳍状结构的剩余部分支撑。更进一步地，可以将支撑 层构图为从衬底表面延伸至第一鳍状结构的表面并因此将第一鳍状结构与衬底在物理上连接的支撑部。这样，即便第二鳍状结构被完全去除，第一半导体层也可以通过支撑部在物理上连接到衬底并以此由衬底支撑。
支撑层的构图可以利用掩模进行。在垂直于第一和第二鳍状结构纵向延伸方向的方向上，掩模在第一和第二鳍状结构上方延伸超出第一和第二鳍状结构的范围(这样，掩模可以遮蔽支撑层在第一和第二鳍状结构两侧的衬底表面上延伸的部分，从而该部分随后可以得以保留)；而在第一和第二鳍状结构的纵向延伸方向上，掩模在第一和第二鳍状结构上方覆盖第一和第二鳍状结构的纵向延伸长度的仅一部分(这样，掩模遮蔽第一和第二鳍状结构的纵向延伸范围的仅一部分，从而该部分随后可以与支撑部相连)。掩模可以覆盖第一和第二鳍状结构的两侧端部，得到的支撑部可以相应地位于第一和第二鳍状结构的两侧端部。
之后，可以至少去除第二鳍状结构靠近第一鳍状结构底部的部分。这样，第一半导体层相对于衬底类似于悬梁构造，支撑部类似于悬梁的锚定结构(anchor)，将作为悬梁的第一半导体层锚定至衬底。
为了便于去除至少去除第二鳍状结构靠近第一鳍状结构底部的部分或者乃至去除整个第二鳍状结构，第二鳍状结构可以包括在衬底上形成的牺牲层，且第一鳍状结构可以包括叠置在牺牲层上的第一半导体层。例如，可以在衬底上依次形成牺牲层和第一半导体层，然后可以将第一半导体层和牺牲层构图为鳍状结构。在该构图步骤可以进行到衬底中，从而在衬底上与鳍状结构相对应的位置处可以具有突起。随后，可以选择性去除牺牲层。
由于第一半导体层悬置从而其表面露出，可以在其表面上生长第二半导体层。于是，在充分生长的情况下，第二半导体层可以覆盖第一半导体层(被支撑部)露出的所有表面。这种第二半导体层可以同第一半导体层一样呈(弯曲)鳍状，且随后可以充当器件的鳍。
以鳍为基础，可以有多种方式来完成器件的制造。例如，可以在衬底上形成隔离层，并在隔离层上形成与第二半导体层相交的栅堆叠。隔离层可以填充第一半导体层、第二半导体层与衬底之间的空间，且至少部分地露出第二半导体层。隔离层可以通过淀积电介质如氧化物并回蚀来得到。支撑部的材料可以 不同于隔离层的材料，这样在回蚀时不会破坏支撑部。可以将隔离层回蚀为使得在第二半导体层下方，隔离层与第二半导体层相接；而在其余位置处，隔离层的顶面比第二半导体层面向衬底的底面要靠近衬底。此外，在回蚀时，可以在第二半导体层下方形成底切。
此外，在形成栅堆叠时，如上所述，针对同一鳍，可以形成与之相交的两个或更多栅堆叠，以分别形成相应的器件。可以在各器件之间按设计需要形成隔离。例如，可以在隔离层上形成沿与第一半导体层的纵向延伸方向相交的方向延伸的电介质层，该电介质层可以将第一半导体层分为第一部分和第二部分，并可以将第二半导体层分为第一部分和第二部分。栅堆叠可以形成为包括与第二半导体层的第一部分相交的第一栅堆叠以及与第二半导体层的第一部分相交的第二栅堆叠。
本公开可以各种形式呈现，以下将描述其中一些示例。
如图1(a)和1(b)(图1(a)是俯视图，图1(b)是沿图1(a)中AA′线的截面图)所示，提供衬底1001。该衬底1001可以是各种形式的衬底，例如但不限于体半导体材料衬底如体Si衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。
在衬底1001上，例如通过外延生长，依次形成牺牲层1003和第一半导体层1005。牺牲层1003可以包括与衬底1001和第一半导体层1005不同的半导体材料，如SiGe(Ge的原子百分比例如为约5～20％)，厚度为约10～100nm。第一半导体层1005可以包括合适的半导体材料，例如Si，厚度为约10～100nm。
随后，可以对如此形成的第一半导体层1005和牺牲层1003(可选地，还有衬底1001)进行构图，以形成鳍状结构。例如，这可以如下进行。
具体地，可以在第一半导体层1005上形成硬掩模层。在该示例中，硬掩膜层可以包括氧化物(例如，氧化硅)层1007和多晶Si层1009。例如，氧化物层1007的厚度为约2～10nm，多晶Si层1009的厚度为约50～120nm。在该示例中，利用图形转移技术，来将硬掩膜构图为鳍状。为此，可以在硬掩膜层上形成构图(例如，通过曝光、显影)的光刻胶PR。在此，光刻胶PR被构图沿弯曲方向延伸的条状，且其宽度(图中水平方向上的维度)可以大致对应于两个鳍状结构之间的间距。这种弯曲形状可以是弧形、弓形、多项式曲线或 其组合等。在该示例中，光刻胶PR被构图为大致呈“C”形。
接着，如图2所示，以该光刻胶PR为掩模，对多晶Si层1009(相对于氧化层1007)进行选择性刻蚀如反应离子刻蚀(RIE)。这样，可以将多晶Si层1009构图为与光刻胶PR相对应的弯曲条状。接着，如图3(a)和3(b)(图3(a)是俯视图，图3(b)是沿图3(a)中AA′线的截面图)所示，去除光刻胶PR，并在多晶Si层1009的侧壁上形成侧墙(spacer)1011。本领域存在多种手段来形成侧墙。例如，可以通过如原子层淀积(ALD)大致共形淀积一层氮化物(例如，氮化硅)，厚度例如为约3～20nm，然后对淀积的氮化物进行选择性刻蚀如RIE，去除其横向延伸部分，使得竖直延伸部分保留，以形成侧墙1011。侧墙1011覆盖Si层1009的侧壁。之后，如图4(对应于图3(b)中的截面图)所示，可以选择性去除多晶Si层1009(例如，通过TMAH溶液)
注意，尽管图3(a)中未示出，但是在条状多晶Si层1009的上下两端的侧壁上，也存在侧墙1011，从而侧墙1011绕条状多晶Si层1009的外周形成封闭图案。例如可以通过光刻，将侧墙1011上下两侧的部分去除，从而可以将原本为封闭图案的侧墙1011分离为两部分。每一部分对应于将要形成的鳍状结构，在该示例中为如图3(a)所示的两个“C”形条状。
然后，如图5所示，以侧墙1011为掩模，可以依次对氧化物层1007、第一半导体层1005和牺牲层1003进行选择性刻蚀如RIE。这样，将侧墙1011的图案转移到下方的层中，得到鳍状结构。在此，鳍状结构包括由半导体层1005构成的第一鳍状结构和牺牲层1003构成的第二鳍状结构。因此，第一半导体层1005的宽度(图中水平方向的维度)与侧墙1011的宽度大致相同(例如，约3～20nm)。在此，还可以进一步选择性刻蚀衬底1001。因此，在与鳍状结构相对应的位置处，衬底1001上可以具有突起。鳍状结构在衬底上的投影大致位于该突起的中部。由于刻蚀的特性，刻蚀后的牺牲层1003以及衬底1001的突起可以呈从上至下逐渐变大的形状。之后，可以选择性去除侧墙1011，还可以进一步选择性去除氧化物层1007，如图6所示。
尽管在以上利用图形转移技术来形成鳍状结构，但是本公开不限于此。例如，可以直接在第一半导体层1005上形成弯曲鳍状的光刻胶，并以光刻胶为掩模，选择性刻蚀第一半导体层1005、牺牲层1003和衬底1001，以形成弯曲 鳍状结构。或者，也可以在硬掩膜层上直接形成弯曲鳍状的光刻胶，利用光刻胶将硬掩膜构图为弯曲鳍状，并利用弯曲鳍状的硬掩膜依次选择性刻蚀第一半导体层1005、牺牲层1003和衬底1001，以形成弯曲鳍状结构。
在此，示出了两个鳍状结构。但是，本公开不限于此，例如可以形成更多或更少的鳍状结构。另外，鳍状结构的布局可以根据器件需要不同地设计。
在形成鳍状结构之后，可以形成支撑部。例如，如图7所示，可以在形成有鳍状结构的衬底上，例如通过ALD，以大致共形的方式，淀积氧化物层1015和氮化物层1017。氧化物层1015的厚度可以为约1～10nm，氮化物层1017的厚度可以为约2～15nm。之后，如图8中的俯视图所示，可以在图7所示的结构上形成构图的光刻胶1019。该光刻胶1019被构图为覆盖鳍状结构两侧(图中上下两侧)的端部，并沿图中的水平方向延伸。这里需要指出的是，在图8的俯视图中，仅为方便起见，并未示出氮化物层1017随衬底上鳍状结构而起伏的形貌，以下俯视图中同样如此。
随后，如图9(a)、9(b)和9(c)(图9(a)是俯视图，图9(b)是沿图9(a)中AA′线的截面图，图9(c)是沿图9(a)中A1A1′线的截面图)所示，以光刻胶1019为掩模，例如通过RIE(相对于氧化物层1015)选择性去除氮化物层1017。这样，如图9(c)所示，氮化物层1017留在鳍状结构两侧(图9(a)中上下两侧)的端部，并延伸到衬底1001的表面上。这样，氮化物层1017将鳍状结构与衬底1001在物理上连接，并因此可以支撑鳍状结构(特别是在如下所述去除牺牲层1003之后)。之后，可以去除光刻胶1019。
在该实施例中，形成了氧化物层和氮化物层的叠层结构的支撑层，并将该支撑层构图为支撑部。但是，本公开不限于此。支撑层可以包括各种合适的电介质材料。在随后去除支撑部的实施例中，支撑层甚至还可以包括半导体材料或导电材料。
在此需要指出的是，仅为了图示方便起见，图9(c)所示的截面图与图9(a)所示的俯视图在位置上有偏移(特别是图9(c)中两个鳍状结构的位置)。以下相应截面图中同样如此。
此外，如图10(对应于图9(c)中的截面图)所示，还可以例如通过RIE(相对于氧化物层1015)选择性去除氮化物层1017的顶端部分。但是，氮化 物层1017仍有一部分留于第一半导体层1005的侧壁上，以便随后支撑第一半导体层1005。
之后，如图11(a)和11(b)(图11(a)对应于图9(a)中的截面图，图11(b)对应于图9(c)中的截面图)所示，可以通过例如RIE，(相对于Si材料的衬底1001和第一半导体层1005以及SiGe材料的牺牲层1003)，选择性去除氧化物层1015。如图11(a)所示，鳍状结构的中部被完全露出；此外，如图11(b)所示，在鳍状结构的两侧端部处，氧化物层1015被氮化物层1017覆盖，并可以得以保留。然后，如图12(a)和12(b)(分别对应于图11(a)和11(b)的截面图)所示，可以通过例如湿法腐蚀，(相对于Si材料的衬底1001和第一半导体层1005)选择性去除牺牲层1003。这样，在鳍状的第一半导体层1005和衬底1001之间形成间隔1021。
在该示例中，牺牲层1003被全部去除。但是，本公开不限于此。例如，牺牲层1003可以仅有靠近第一半导体层1005底部的部分被去除。这种情况下，同样可以实现下述的绕第一半导体层1005外周的生长。
如图12(a)和12(b)所示，第一半导体层1005通过间隔1021与衬底1001隔开，大致平行于衬底表面延伸，并经支撑部1015/1017而被衬底1001支撑。支撑部1015/1017包括在衬底1001的表面上延伸的横向延伸部分以及沿大致垂直于衬底表面的方向延伸的竖直延伸部分。在该示例中，竖直延伸部分可以包括沿衬底1011的突起的表面延伸的部分、沿牺牲层1003(已经去除)的表面延伸的部分以及沿第一半导体层1005的竖直侧壁延伸的部分。这样，支撑部1015/1017将第一半导体层1005物理连接到衬底1001，从而可以支撑第一半导体层1005。支撑部1015/1017可以在第一半导体层1005的相对两侧(图中左右两侧)的竖直侧壁上延伸，从而夹持第一半导体层，以便更为稳定地支撑第一半导体层1005。在第一半导体层1005的纵向延伸方向上，第一半导体层1005与支撑部1015/1017相连接部分的延伸范围小于第一半导体层1005的纵向延伸长度。在此，所谓“纵向延伸方向”是指第一半导体层1005的长度方向，与之后形成的沟道区的长度方向基本上一致，也即，从源区到漏区的方向或者反之亦然。这样，第一半导体层1005相对于衬底1001，形成类似于悬梁的构造，该悬梁通过支撑部1015/1017锚定到衬底1001。
在以上示例中，支撑部除了氮化物层1017之外，还包括氧化物层1015，但是本公开不限于此。例如，在以上结合图7描述的操作中，可以不形成氧化物层1015，而直接形成氮化物层1017。这样，同样可以按以上结合图8-12描述的方式进行后继操作。当然，支撑部也可以是其他电介质材料或叠层结构。
另外，用来构图支撑部的掩模1019(参见图8)不限于上述形状。一般地，在垂直于鳍状结构纵向延伸方向的方向上，掩模在鳍状结构上方可以延伸超出鳍状结构的范围。这样，掩模可以覆盖氮化物层1017在衬底1001(突起之外的)表面上延伸的部分，这部分随后可以保留(充当支撑部的底座)。另一方面，在鳍状结构的纵向延伸方向上，掩模在鳍状结构上方可以覆盖鳍状结构的纵向延伸长度的仅一部分。这样，可以形成类似悬梁-锚定结构的配置。
然后，如图13(a)、13(b)和13(c)(图13(a)是俯视图，图13(b)是沿图13(a)中AA′线的截面图，图13(c)是沿图13(a)中A1A1′线的截面图)所示，可以在第一半导体层1005上生长第二半导体层1023。在此，第二半导体层1023可以包括高迁移率材料，例如Ge、SiGe或III-V族化合物半导体如InSb、InGaSb、InAs、GaAs、InGaAs、AlSb、InP、三族氮化物等，厚度可以为约5～15nm。在化合物半导体如SiGe的情况下，其成分(例如，Ge原子百分比)可以渐变，使得例如从与第一半导体层1005(在此，Si)的晶格常数相差较少变为与第一半导体层1005的晶格常数相差较大，以便抑制位错或缺陷的生成。
这种生长可以是选择性生长，从而第二半导体层1023只在半导体材料的第一半导体层1005(以及衬底1001)的表面上生长。可以控制第二半导体层1023的生长，使得其没有完全填满第一半导体层1005与衬底1001之间的间隔1021。由于第一半导体层1005的悬置构造，在生长过程中第一半导体层1005和第二半导体层1023中的应力可以得以弛豫。
此外，如图13(a)所示，第二半导体层1023如Ge、SiGe或III-V族化合物半导体层的晶格常数通常大于硅的晶格常数，因此以硅的第一半导体层1005为种子生长的第二半导体层1023的长度相对于第一半导体层1005将增大。于是，如图中箭头所示，第二半导体层1023的中心相对于第一半导体层1005原本的中心将向左侧偏移。这有助于在生长过程中释放应力。
于是，可以抑制或避免第一半导体层1005或第二半导体层1023中产生缺 陷，这有助于改善器件性能(例如，降低关态漏电流以及提升开态电流)。
在该示例中，除了被支撑部1015/1017覆盖的表面之外，第一半导体层1005的其余表面均被第二半导体层覆盖。当然，衬底1001的表面上也可以生长有第二半导体层1023。
在该示例中，沿第一半导体层的纵向延伸方向，除了支撑部所占据的纵向延伸范围之外，在其余纵向延伸范围处，第二半导体层1023完全包封第一半导体层1005的外周。这样，在与第一半导体层1005的纵向延伸方向垂直的截面(即，图13(b)所示的截面)上，第二半导体层1023形成闭合图案(该示例中为矩形)。当然，该闭合图案由第一半导体层1005在该截面处的图案所定，可以为其他形状例如多边形。
如此形状的第二半导体层1023随后可以充当器件的鳍。
在通过上述处理形成鳍1023之后，可以形成与鳍相交的栅堆叠，并形成最终的半导体器件(例如，FinFET)。
为了隔离栅堆叠和衬底，如图14(a)和14(b)(分别对应于图13(a)和13(b)的截面图)在衬底1001上(在该示例中，在衬底1001上形成的第二半导体层1023上)首先形成隔离层1025。这种隔离层例如可以通过在衬底上淀积电介质材料如氧化物，且然后进行回蚀来形成。在回蚀过程中，控制回蚀深度，使得得到的隔离层1025能够至少部分地露出第二半导体层1023。此外，隔离层1025还填充了间隔1021。在该示例中，在第二半导体层1023下方，隔离层1025与第二半导体层1023相接；而在其余位置处，隔离层1025的顶面比第二半导体层面1023的底面要低。另外，在第二半导体层1023下方，隔离层1025可以形成有底切(由于回蚀导致)。
在该实施例中，隔离层1025基本上填满了第一半导体层1005、第二半导体层1023与衬底1001之间的空间。但是，本公开不限于此。例如，隔离层1025的顶面可以与第二半导体层1023的底面脱离。
随后，可以在隔离层1025上形成与鳍相交的栅堆叠。例如，这可以如下进行。具体地，如图15(对应于图14(a)所示的截面图)所示，可以依次形成栅介质层1027和栅导体层1029。例如，栅介质层1027可以包括厚度为约0.3～2nm的氧化物(例如，SiO2或GeO2)，栅导体层1029可以包括多晶硅； 或者，栅介质层1027可以包括厚度为约1～4nm的高K栅介质如HfO2或Al2O3，栅导体层1029可以包括金属栅导体。在高K栅介质/金属栅导体的情况下，在栅介质层1027和栅导体层1029之间还可以形成功函数调节层(未示出)，例如TiN、Al、Ti、TiAlC，厚度为约1～3nm。
之后，如图16中的俯视图所示，可以通过例如光刻，对栅介质层1027和栅导体层1029进行构图，以形成栅堆叠G。在此，有两个栅堆叠G与同一鳍状结构相交。但是，本公开不限于此。例如，可以仅有一个或者有三个或更多栅堆叠与同一鳍状结构相交。栅堆叠G的布局可以根据器件设计而定。
在形成栅堆叠之后，例如可以栅堆叠为掩模，进行晕图(halo)注入和延伸区(extension)注入。接下来，可以在栅堆叠的侧壁上形成栅侧墙。然后，可以栅堆叠及栅侧墙为掩模，进行源/漏(S/D)注入。随后，可以通过退火，激活注入的离子，以在栅堆叠G两侧(图中上下两侧)在第二半导体层1023中形成源/漏区。
本领域技术人员知道多种方式来以鳍为基础制作器件，在此对于形成鳍之后的工艺不再赘述。
各栅堆叠G与鳍1023的相应部分构成相应的器件如FinFET。根据器件设计，这些器件可以相连接或者相隔离。图16中示出了器件之间彼此隔离的示例。具体地，如图16所示，可以在隔离层1025上形成沿其鳍状结构的纵向延伸方向相交的方向延伸的电介质层1031，以便将第一半导体层1005分成彼此隔离的两部分，并将第二半导体层1023分成彼此隔离的两部分。具体地，可以通过光刻，对第二半导体层1023和第一半导体层1005进行选择性刻蚀，从而在其中形成间隙。然后，向间隙中填充电介质材料如氧化物，来形成电介质层1031。
这样，就得到了该实施例的半导体器件。如图15和16所示，该半导体器件可以包括与衬底1001相隔开的第一半导体层1005，第一半导体层1005经支撑部1015/1017而物理连接到衬底1001(参见图12(b))。绕第一半导体层1005的外周，形成有第二半导体层1023，充当该器件的鳍。此外，该器件还包括隔离层1025以及在隔离层1025上形成的与鳍1023相交的栅堆叠G(1027、1029)。由于隔离层1025的底切，栅堆叠可以嵌入到该底切中，从而可以更有 效地控制鳍1023的底部。
在该实施例中，在最终的器件结构中，保留了支撑部。但是，本公开不限于此。支撑部也可以被选择性(至少部分)去除(例如，在形成栅堆叠之后)，其去除而导致的空间随后例如可以被其他电介质层填充。
在以上实施例中，在第一半导体层的两侧端部形成了支撑部，并可以将弯曲鳍状结构的两端固定，这对于弯曲的鳍状结构特别有利。但是本公开不限于此，在两侧端部之外或者代替两侧端部，也可以在第一半导体层的其他部位处形成支撑部。
在以上示例中，形成了大致“C”形的弯曲鳍状结构，但是本公开不限于此，可以形成各种弯曲形状，例如弧形、弓形、多项式曲线等或其组合。例如，如图17所示，在以上结合图1(a)描述的操作中，可以将光刻胶PR构图为大致“S”形，而不是大致“C”形。其他操作可以如上所述进行。这样，在以上结合图13(a)-13(c)描述的操作中，可以生长同样大致呈“S”形延伸的第二半导体层1023，如图18所示。第二半导体层1023的长度同样可以相对于第一半导体层1005变大，如上所述。这样，如图28中箭头所示，第二半导体层1023的中心相对于第一半导体层1005原本的中心将偏移。这有助于在生长过程中释放应力。更具体地，中心可以向弯曲形状的凸出一侧偏移(“S”形上半部向左侧偏移，而“S”形下半部向右侧偏移)。之后，可以按上述方式，形成与“S”形鳍1023相交的栅堆叠。
在以上实施例中，以FinFET为例进行描述，但是本公开不限于此。本公开的技术可以适用于各种半导体器件，特别是需要利用高迁移率材料如Ge、SiGe、III-V族化合物半导体材料等的半导体器件，例如各种光电器件如光电二极管、激光二极管(LD)等。例如，可以通过对种子层上外延生长的半导体层进行相应掺杂来形成pn结，以形成二极管。本领域技术人员知道各种方式来以半导体层为基础制造各种半导体器件。
根据本公开实施例的半导体器件可以应用于各种电子设备。例如，通过集成多个这样的半导体器件以及其他器件(例如，其他形式的晶体管等)，可以形成集成电路(IC)，并由此构建电子设备。因此，本公开还提供了一种包括上述半导体器件的电子设备。电子设备还可以包括与集成电路配合的显示屏幕 以及与集成电路配合的无线收发器等部件。这种电子设备例如智能电话、平板电脑(PC)、个人数字助手(PDA)等。
根据本公开的实施例，还提供了一种芯片系统(SoC)的制造方法。该方法可以包括上述制造半导体器件的方法。具体地，可以在芯片上集成多种器件，其中至少一些是根据本公开的方法制造的。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (35)

  1. 一种半导体器件，包括：
    衬底；
    与衬底相隔开的鳍状第一半导体层，其中第一半导体层沿弯曲的纵向延伸方向延伸；以及
    至少部分环绕第一半导体层外周的第二半导体层。
  2. 根据权利要求1所述的半导体器件，还包括：
    在衬底上形成的隔离层，隔离层至少部分地露出第二半导体层，露出的第二半导体层呈鳍状延伸；以及
    在隔离层上形成的与第二半导体层相交的栅堆叠。
  3. 根据权利要求2所述的半导体器件，其中，至少部分环绕第一半导体层外周的第二半导体层位于第一半导体层与栅堆叠之间。
  4. 根据权利要求1所述的半导体器件，其中，第一半导体层大致呈“C”形或“S”形。
  5. 根据权利要求1所述的半导体器件，其中，第一半导体层沿其纵向延伸方向包括第一部分和第二部分，第二半导体包括至少部分环绕第一半导体层的第一部分外周形成的第一部分以及至少部分环绕第一半导体层的第二部分外周形成的第二部分。
  6. 根据权利要求2所述的半导体器件，其中，第一半导体层沿其纵向延伸方向包括第一部分和第二部分，第二半导体包括至少部分环绕第一半导体层的第一部分外周形成的第一部分以及至少部分环绕第一半导体层的第二部分外周形成的第二部分，且栅堆叠包括与第二半导体层的第一部分相交的第一栅堆叠以及与第二半导体层的第一部分相交的第二栅堆叠。
  7. 根据权利要求5或6所述的半导体器件，还包括：沿与第一半导体层的纵向延伸方向相交的方向延伸的电介质层，其中该电介质层将第一半导体层的第一部分与第二部分相隔离，且将第二半导体层的第一部分与第二部分相隔离。
  8. 根据权利要求1所述的半导体器件，还包括：支撑部，第一半导体层 经支撑部而在物理上连接到衬底。
  9. 根据权利要求8所述的半导体器件，其中，在第一半导体层的纵向延伸方向上，第一半导体层与支撑部相连接的部分的延伸范围小于第一半导体层的纵向延伸长度。
  10. 根据权利要求8所述的半导体器件，其中，支撑部包括沿衬底表面延伸的横向延伸部分以及沿大致垂直于衬底表面的方向延伸的竖直延伸部分，其中竖直延伸部分延伸至第一半导体层大致垂直于衬底表面的竖直侧壁上。
  11. 根据权利要求10所述的半导体器件，其中，支撑部的竖直延伸部分在第一半导体层的相对两侧的竖直侧壁上延伸，从而夹持第一半导体层。
  12. 根据权利要求8所述的半导体器件，其中，支撑部设于鳍状的第一半导体层的两侧端部。
  13. 根据权利要求2所述的半导体器件，其中，隔离层填充第一半导体、第二半导体层与衬底之间的空间。
  14. 根据权利要求2所述的半导体器件，其中，在第二半导体层下方，隔离层与第二半导体层相接；而在其余位置处，隔离层的顶面比第二半导体层面向衬底的底面要靠近衬底。
  15. 根据权利要求14所述的半导体器件，其中，在第二半导体层下方，隔离层具有底切。
  16. 根据权利要求1所述的半导体器件，其中，第一半导体层包括Si，第二半导体层包括Ge、SiGe或III-V族化合物半导体。
  17. 一种制造半导体器件的方法，包括：
    在衬底上形成沿弯曲的纵向延伸方向延伸的第一鳍状结构和第二鳍状结构，第一鳍状结构堆叠在第二鳍状结构之上；
    在第一鳍状结构和第二鳍状结构上形成用以支撑第一鳍状结构的支撑部；
    至少部分去除第二鳍状结构靠近第一鳍状结构底部的部分，从而第一鳍状结构与第二鳍状结构相分离而形成第一半导体层；以及
    以第一半导体层为种子层，生长第二半导体层。
  18. 根据权利要求17所述的方法，其中，第二鳍状结构包括在衬底上形成的牺牲层，第一鳍状结构包括叠置在牺牲层上的第一半导体层。
  19. 根据权利要求18所述的方法，其中，形成第一鳍状结构和第二鳍状结构包括：依次将第一半导体层和牺牲层构图为鳍状结构。
  20. 根据权利要求18所述的方法，其中，至少部分去除第二鳍状结构靠近第一鳍状结构底部的部分包括：选择性去除牺牲层。
  21. 根据权利要求17所述的方法，其中，通过选择性生长，来生长第二半导体层。
  22. 根据权利要求17所述的方法，进一步包括：
    在衬底上形成隔离层，其中隔离层至少部分地露出第二半导体层，露出的第二半导体层呈鳍状延伸；以及
    在隔离层上形成与第二半导体层相交的栅堆叠。
  23. 根据权利要求22所述的方法，其中，隔离层填充第一半导体、第二半导体层与衬底之间的空间。
  24. 根据权利要求17所述的方法，其中，将第一半导体层形成为大致呈“C”形或“S”形。
  25. 根据权利要求17所述的方法，其中，形成支撑部包括：
    在形成有第一和第二鳍状结构的衬底上形成层状材料，并通过将该层状材料构图为在物理上连接第一和第二鳍状结构的表面来形成支撑部。
  26. 根据权利要求27所述的方法，其中，形成支撑部包括：
    在形成有第一和第二鳍状结构的衬底上形成层状材料，并通过将该层状材料构图为从衬底表面延伸至第一鳍状结构的表面并因此将第一鳍状结构与衬底在物理上连接，来形成支撑部。
  27. 根据权利要求26所述的方法，其中，形成层状材料并对其构图包括：
    形成层状材料使其覆盖第一鳍状结构、第二鳍状结构和衬底表面，并形成掩模以遮蔽一部分层状材料，其中，在垂直于第一和第二鳍状结构纵向延伸方向的方向上，掩模在第一和第二鳍状结构上方延伸超出第一和第二鳍状结构的范围；而在第一和第二鳍状结构的纵向延伸方向上，掩模在第一和第二鳍状结构上方覆盖第一和第二鳍状结构的纵向延伸长度的仅一部分；
    选择性去除未被遮蔽的层状材料部分；以及
    去除掩模。
  28. 根据权利要求27所述的方法，其中，在去除掩模后，该方法还包括：
    选择性去除支撑部的顶端部分，以露出第一鳍状结构的顶面以及部分侧壁。
  29. 根据权利要求27所述的方法，其中，形成掩模包括：
    使掩模覆盖第一和第二鳍状结构的两侧端部。
  30. 根据权利要求27所述的方法，其中，形成层状材料包括：
    以大致共形的方式，依次淀积氧化物层和氮化物层。
  31. 根据权利要求22所述的方法，其中，形成隔离层包括：
    在衬底上形成氧化物层；
    对氧化物层进行回蚀，使得在第二半导体层下方，隔离层与第二半导体层相接；而在其余位置处，隔离层的顶面比第二半导体层面向衬底的底面要靠近衬底。
  32. 根据权利要求31所述的方法，其中，在对氧化物层进行回蚀时，在第二半导体层下方形成底切。
  33. 根据权利要求22所述的方法，还包括：
    在隔离层上形成沿与第一半导体层的纵向延伸方向相交的方向延伸的电介质层，该电介质层将第一半导体层分为第一部分和第二部分，并将第二半导体层分为第一部分和第二部分，
    其中，栅堆叠包括与第二半导体层的第一部分相交的第一栅堆叠以及与第二半导体层的第一部分相交的第二栅堆叠。
  34. 一种电子设备，包括由如权利要求1～16中任一项所述的半导体器件形成的集成电路。
  35. 根据权利要求34所述的电子设备，还包括：与所述集成电路配合的显示器以及与所述集成电路配合的无线收发器。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109461738B (zh) 2017-09-06 2021-03-26 中国科学院微电子研究所 半导体存储设备及其制造方法及包括存储设备的电子设备
CN115411108B (zh) * 2021-05-28 2025-08-19 联华电子股份有限公司 切割鳍状结构的方法
US20240088252A1 (en) * 2022-09-08 2024-03-14 International Business Machines Corporation Gate all around transistors with heterogeneous channels
US20240282860A1 (en) * 2023-02-20 2024-08-22 International Business Machines Corporation Nonlinear channel

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101339947A (zh) * 2007-07-02 2009-01-07 恩益禧电子股份有限公司 半导体器件
CN103456638A (zh) * 2012-06-05 2013-12-18 中芯国际集成电路制造(上海)有限公司 自对准GaAs FinFET结构及其制造方法
CN105633167A (zh) * 2015-12-07 2016-06-01 中国科学院微电子研究所 具有高质量外延层的半导体器件及其制造方法
US20160172359A1 (en) * 2014-12-16 2016-06-16 Young-Soo Yoon Moisture blocking structure and/or a guard ring, a semiconductor device including the same, and a method of manufacturing the same

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7105390B2 (en) 2003-12-30 2006-09-12 Intel Corporation Nonplanar transistors with metal gate electrodes
US7352034B2 (en) 2005-08-25 2008-04-01 International Business Machines Corporation Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures
US7829407B2 (en) 2006-11-20 2010-11-09 International Business Machines Corporation Method of fabricating a stressed MOSFET by bending SOI region
US7538391B2 (en) 2007-01-09 2009-05-26 International Business Machines Corporation Curved FINFETs
KR100868100B1 (ko) * 2007-03-05 2008-11-11 삼성전자주식회사 반도체 소자 제조 방법 및 이에 따라 제조된 반도체 소자
JP4966153B2 (ja) 2007-10-05 2012-07-04 株式会社東芝 電界効果トランジスタおよびその製造方法
KR101471858B1 (ko) * 2008-09-05 2014-12-12 삼성전자주식회사 바 타입의 액티브 패턴을 구비하는 반도체 장치 및 그 제조방법
US8169025B2 (en) * 2010-01-19 2012-05-01 International Business Machines Corporation Strained CMOS device, circuit and method of fabrication
US9761666B2 (en) * 2011-06-16 2017-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel field effect transistor
KR101823105B1 (ko) 2012-03-19 2018-01-30 삼성전자주식회사 전계 효과 트랜지스터의 형성 방법
US8883570B2 (en) * 2012-07-03 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate FETs and methods for forming the same
KR101983633B1 (ko) 2012-11-30 2019-05-29 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US9559181B2 (en) * 2013-11-26 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET device with buried sige oxide
US9312344B2 (en) * 2013-03-13 2016-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming semiconductor materials in STI trenches
US9035277B2 (en) 2013-08-01 2015-05-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and fabricating the same
EP3050111A4 (en) 2013-09-27 2017-06-07 Intel Corporation Improved cladding layer epitaxy via template engineering for heterogeneous integration on silicon
EP2978016B1 (en) * 2014-07-25 2018-06-13 IMEC vzw A method for providing an nMOS device and a pMOS device on a silicon substrate and silicon substrate comprising an nMOS device and a pMOS device
US20160035891A1 (en) * 2014-07-31 2016-02-04 Qualcomm Incorporated Stress in n-channel field effect transistors
US9716145B2 (en) * 2015-09-11 2017-07-25 International Business Machines Corporation Strained stacked nanowire field-effect transistors (FETs)
WO2017096781A1 (zh) * 2015-12-07 2017-06-15 中国科学院微电子研究所 具有高质量外延层的纳米线半导体器件及其制造方法
US11575005B2 (en) * 2018-03-30 2023-02-07 Intel Corporation Asymmetrical semiconductor nanowire field-effect transistor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101339947A (zh) * 2007-07-02 2009-01-07 恩益禧电子股份有限公司 半导体器件
CN103456638A (zh) * 2012-06-05 2013-12-18 中芯国际集成电路制造(上海)有限公司 自对准GaAs FinFET结构及其制造方法
US20160172359A1 (en) * 2014-12-16 2016-06-16 Young-Soo Yoon Moisture blocking structure and/or a guard ring, a semiconductor device including the same, and a method of manufacturing the same
CN105633167A (zh) * 2015-12-07 2016-06-01 中国科学院微电子研究所 具有高质量外延层的半导体器件及其制造方法

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