WO2017092172A1 - Tft基板的制作方法 - Google Patents

Tft基板的制作方法 Download PDF

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Publication number
WO2017092172A1
WO2017092172A1 PCT/CN2016/072864 CN2016072864W WO2017092172A1 WO 2017092172 A1 WO2017092172 A1 WO 2017092172A1 CN 2016072864 W CN2016072864 W CN 2016072864W WO 2017092172 A1 WO2017092172 A1 WO 2017092172A1
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Prior art keywords
layer
source
photoresist
drain
tft substrate
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French (fr)
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张晓星
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/912,927 priority Critical patent/US9876040B1/en
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    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
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    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
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    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
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    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
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    • H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
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    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
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    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
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    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
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    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H10D86/0225—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials using crystallisation-promoting species, e.g. using a Ni catalyst
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
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    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
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    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a TFT substrate.
  • TFT Thin Film Transistor
  • LCD Liquid Crystal Display
  • AMOLED Active Matrix Organic Light-Emitting Diode
  • the driving component is directly related to the development direction of high-performance flat panel display devices.
  • LTPS Low Temperature Poly-silicon
  • a-Si amorphous silicon
  • the LTPS crystallization process includes Excimer Laser Anneal (ELA) technology and Solid Phase Crystallization (SPC) technology.
  • ELA Excimer Laser Anneal
  • SPC Solid Phase Crystallization
  • ion-induced crystallization method there is a crystallization method using induced ions such as Ni (nickel) or B (boron).
  • the induced SPC method After the implanted ions complete the induced crystallization, in order to form the semiconductor layer, it is necessary to remove the a-Si (amorphous silicon) originally implanted with the induced ions to form an active layer of the semiconductor. Subsequent to the need to make the source/drain contact area, it is necessary to implant boron ions or phosphorus ions into the active layer region in contact with the source/drain to achieve better contact effect.
  • a-Si amorphous silicon
  • the manufacturing method of the existing TFT substrate mainly includes the following steps:
  • Step 1 as shown in FIG. 1, a substrate 100 is provided, a buffer layer 200 is deposited on the substrate 100, and an amorphous silicon layer 300 is deposited on the buffer layer 200.
  • Step 2 As shown in FIG. 2, the amorphous silicon layer 300 is ion implanted, and high temperature baking is performed to convert amorphous silicon into polycrystalline silicon, thereby obtaining a polysilicon layer 400 on the buffer layer 200 and a polysilicon layer.
  • the ion-inducing layer 500 on 400 is performed.
  • Step 3 As shown in FIG. 3, the ion inducing layer 500 is removed by an etching process to obtain a polysilicon layer 400.
  • Step 4 as shown in FIG. 4, the polysilicon layer 400 is patterned to obtain an island-shaped semiconductor layer 410.
  • Step 5 as shown in FIG. 5, a photoresist is applied onto the island-shaped semiconductor layer 410 and the buffer layer 200, and exposed and developed to obtain a photoresist layer 500.
  • Step 6 as shown in FIG. 6, using the photoresist layer 500 as a shielding layer, performing boron ion implantation on the island-shaped semiconductor layer 410, and obtaining source/drain contact regions on the island-shaped semiconductor layer 410. 600.
  • Step 7 as shown in FIG. 7, the photoresist layer 500 is stripped, a gate insulating layer 700 is deposited on the island-shaped semiconductor layer 410 and the buffer layer 200, and a gate electrode 800 is formed on the gate insulating layer 700.
  • Step 8 as shown in FIG. 8, an interlayer insulating layer 900, a source/drain 910, a flat layer 920, a cathode 930, and a pixel defining layer 940 are formed on the gate insulating layer 700 and the gate 800, and finally the OLED is performed.
  • the evaporation of 950 in order to complete the entire process of the TFT substrate, requires nine mask definitions to perform OLED evaporation, and the process cost is high.
  • An object of the present invention is to provide a method for fabricating a TFT substrate, which can effectively simplify the process, improve production efficiency, and save production cost.
  • the present invention provides a method for fabricating a TFT substrate, comprising the following steps:
  • Step 1 Providing a substrate, depositing a buffer layer on the substrate, and depositing an amorphous silicon layer on the buffer layer;
  • Step 2 ion implantation of the amorphous silicon layer, and high temperature baking to convert amorphous silicon crystal into polycrystalline silicon, to obtain a polysilicon layer on the buffer layer, and an ion inducing layer on the polysilicon layer;
  • Step 3 depositing a first metal layer on the ion inducing layer, applying a photoresist on the first metal layer, providing a halftone mask, and exposing the photoresist by using the halftone mask, Developing, obtaining first and second photoresist segments that are spaced apart from each other; a thickness of both side regions of the first photoresist segment is greater than a thickness of the intermediate region;
  • Step 4 using the first photoresist segment and the second photoresist segment as a shielding layer, etching the first metal layer, the ion inducing layer, and the polysilicon layer to obtain an island-shaped semiconductor and a source/drain region;
  • Step 5 Perform ashing treatment on the first photoresist segment and the second photoresist segment to remove the intermediate region of the first photoresist segment, and use the remaining first photoresist segment as a shielding layer for the island.
  • Step 6 depositing a gate insulating layer on the source/drain; depositing a second metal layer on the gate insulating layer, and patterning the second metal layer to form a gate;
  • Step 7 forming a protective layer on the gate insulating layer and the gate; forming a flat layer on the protective layer; above the corresponding source/drain on the flat layer, the protective layer, and the gate insulating layer Forming a via hole;
  • Step 8 forming a cathode on the flat layer, the cathode being in contact with the source/drain via the via hole; forming a pixel defining layer on the flat layer, and forming on the pixel defining layer Opening to expose a portion of the cathode; OLED is evaporated at the opening.
  • the substrate is a glass substrate.
  • the buffer layer is a silicon nitride layer, a silicon oxide layer, or a composite layer of the two; the thickness of the buffer layer is
  • the thickness of the amorphous silicon layer is
  • the ions implanted in the amorphous silicon layer are boron ions or nickel ions.
  • the first metal layer is a stack combination of one or more of molybdenum, aluminum, and copper; the thickness of the first metal layer is
  • the gate insulating layer is a silicon nitride layer, a silicon oxide layer, or a combination of the two; the thickness of the gate insulating layer is
  • the second metal layer is a stack combination of one or more of molybdenum, aluminum, and copper; the thickness of the second metal layer is
  • the protective layer is a silicon nitride layer, a silicon oxide layer, or a combination of the two; the thickness of the protective layer is
  • the cathode is an indium tin oxide/silver/indium tin oxide composite structure or a single layer of metallic silver; the thickness of the cathode is
  • the invention also provides a method for fabricating a TFT substrate, comprising the following steps:
  • Step 1 Providing a substrate, depositing a buffer layer on the substrate, and depositing an amorphous silicon layer on the buffer layer;
  • Step 2 ion implantation of the amorphous silicon layer, and high temperature baking to convert amorphous silicon crystal into polycrystalline silicon, to obtain a polysilicon layer on the buffer layer, and an ion inducing layer on the polysilicon layer;
  • Step 3 depositing a first metal layer on the ion inducing layer, applying a photoresist on the first metal layer, providing a halftone mask, and exposing the photoresist by using the halftone mask, Developing, obtaining first and second photoresist segments that are spaced apart from each other; a thickness of both side regions of the first photoresist segment is greater than a thickness of the intermediate region;
  • Step 4 using the first photoresist segment and the second photoresist segment as a shielding layer, for the first metal layer, Etching the ion-inducing layer and the polysilicon layer to obtain an island-shaped semiconductor and source/drain regions;
  • Step 5 Perform ashing treatment on the first photoresist segment and the second photoresist segment to remove the intermediate region of the first photoresist segment, and use the remaining first photoresist segment as a shielding layer for the island.
  • Step 6 depositing a gate insulating layer on the source/drain; depositing a second metal layer on the gate insulating layer, and patterning the second metal layer to form a gate;
  • Step 7 forming a protective layer on the gate insulating layer and the gate; forming a flat layer on the protective layer; above the corresponding source/drain on the flat layer, the protective layer, and the gate insulating layer Forming a via hole;
  • Step 8 forming a cathode on the flat layer, the cathode being in contact with the source/drain via the via hole; forming a pixel defining layer on the flat layer, and forming on the pixel defining layer Opening to expose a portion of the cathode; depositing an OLED at the opening;
  • the substrate is a glass substrate
  • the buffer layer is a silicon nitride layer, a silicon oxide layer, or a combination of the two; the thickness of the buffer layer is
  • the thickness of the amorphous silicon layer is
  • the ions implanted in the amorphous silicon layer are boron ions or nickel ions;
  • the first metal layer is a stack combination of one or more of molybdenum, aluminum, and copper; the thickness of the first metal layer is
  • the process only removes the ion-inducing layer of the channel region, and the subsequent source/drain contact regions do not need to be ion implanted again, thereby saving the mask required for ion implantation again; and the source/drain electrodes are also
  • the fabrication is completed under the halftone mask, thereby saving the mask required for the source/drain; and the fabrication of the interlayer insulating layer is omitted because the source/drain is fabricated first, thereby saving the fabrication interlayer.
  • the reticle required for the insulating layer; the method for fabricating the TFT substrate of the present invention reduces the nine masks required in the prior art to six reticle by using a halftone mask process, thereby simplifying the process and improving the production efficiency. Save on production costs.
  • FIG. 1 is a schematic view showing a step 1 of a method for fabricating a conventional TFT substrate
  • FIG. 2 is a schematic view showing a step 2 of a method for fabricating a conventional TFT substrate
  • FIG. 3 is a schematic view showing a step 3 of a method for fabricating a conventional TFT substrate
  • FIG. 4 is a schematic view showing a step 4 of a method for fabricating a conventional TFT substrate
  • FIG. 5 is a schematic view showing a step 5 of a method for fabricating a conventional TFT substrate
  • FIG. 6 is a schematic view showing a step 6 of a method for fabricating a conventional TFT substrate
  • FIG. 7 is a schematic view showing a step 7 of a method for fabricating a conventional TFT substrate
  • FIG. 8 is a schematic view showing a step 8 of a method for fabricating a conventional TFT substrate
  • FIG. 9 is a schematic flow chart of a method of fabricating a TFT substrate of the present invention.
  • FIG. 10 is a schematic view showing a step 1 of a method of fabricating a TFT substrate of the present invention
  • FIG. 11 is a schematic view showing a step 2 of a method of fabricating a TFT substrate of the present invention.
  • FIG. 12 is a schematic view showing a step 3 of a method of fabricating a TFT substrate of the present invention.
  • Figure 13 is a schematic view showing the step 4 of the method for fabricating the TFT substrate of the present invention.
  • FIG. 14 is a schematic view showing a step 5 of a method of fabricating a TFT substrate of the present invention.
  • 15 is a schematic view showing a step 6 of a method of fabricating a TFT substrate of the present invention.
  • 16 is a schematic view showing a step 7 of a method of fabricating a TFT substrate of the present invention.
  • Figure 17 is a schematic view showing the step 8 of the method of fabricating the TFT substrate of the present invention.
  • the present invention provides a method for fabricating a TFT substrate, including the following steps:
  • Step 1 As shown in FIG. 10, a substrate 1 is provided, a buffer layer 2 is deposited on the substrate 1, and an amorphous silicon layer 3 is deposited on the buffer layer 2.
  • the substrate 1 is a glass substrate.
  • the buffer layer 2 is a silicon nitride (SiNx) layer, a silicon oxide (SiOx) layer, or a composite layer of the two; the thickness of the buffer layer 2 is
  • the thickness of the amorphous silicon layer 3 is
  • Step 2 as shown in FIG. 11, ion implantation of the amorphous silicon layer 3, and high temperature baking to convert amorphous silicon crystal into polycrystalline silicon, to obtain a polycrystalline silicon layer 4 on the buffer layer 2, and in polysilicon
  • the ion inducing layer 5 can directly contact the source/drain.
  • ions implanted in the amorphous silicon layer 3 are boron ions or nickel ions.
  • Step 3 depositing a first metal layer 60 on the ion inducing layer 5, applying a photoresist on the first metal layer 60, providing a halftone mask, using the halftone light
  • the mask exposes and develops the photoresist to obtain a first photoresist segment 51 and a second photoresist segment 52 which are spaced apart from each other; a thickness of the two side regions 511 of the first photoresist segment 51 is greater than a thickness of the intermediate region 512 .
  • the first metal layer 60 is a stacked combination of one or more of molybdenum (Mo), aluminum (Al), and copper (Cu); the thickness of the first metal layer 60 is
  • Step 4 as shown in FIG. 13, the first metal layer 60, the ion-inducing layer 5, and the polysilicon layer 4 are etched by using the first photoresist layer 51 and the second photoresist layer 52 as shielding layers. Island semiconductor and source/drain regions 61.
  • Step 5 as shown in FIG. 14, the first photoresist segment 51 and the second photoresist segment 52 are subjected to ashing treatment, and the intermediate region 512 of the first photoresist segment 51 is removed to remove the first light.
  • the blocking portion 51 is a shielding layer, and the first metal layer 60 and the ion inducing layer 5 in the island-shaped semiconductor and source/drain regions 61 are etched to obtain an island-shaped semiconductor layer 40 having a channel region 41, which is located a source/drain contact region 50 on the island-shaped semiconductor layer 40, and a source/drain electrode 6 on the source/drain contact region 50; stripping the remaining first photoresist segment 51 and the second photoresist Segment 52.
  • Step 6 as shown in FIG. 15, depositing a gate insulating layer 7 on the source/drain electrodes 6; depositing a second metal layer on the gate insulating layer 7, and patterning the second metal layer The process is performed to form the gate electrode 8.
  • the gate insulating layer 7 is a silicon nitride layer, a silicon oxide layer, or a combination of the two; the thickness of the gate insulating layer 7 is
  • the second metal layer is a stacked combination of one or more of molybdenum, aluminum, and copper; the thickness of the second metal layer is
  • Step 7 as shown in FIG. 16, a protective layer 9 is formed on the gate insulating layer 7 and the gate electrode 8; a flat layer 10 is formed on the protective layer 9, and the flat layer 10, the protective layer 9, A via 91 is formed above the corresponding source/drain 6 on the gate insulating layer 7.
  • the protective layer 9 is a silicon nitride layer, a silicon oxide layer, or a combination of the two; the thickness of the protective layer 9 is
  • Step 8 as shown in FIG. 17, a cathode 11 is formed on the flat layer 10, the cathode 11 is in contact with the source/drain 6 via the via 91; and a pixel is formed on the flat layer 10.
  • the layer 12 is defined, and an opening 121 is formed on the pixel defining layer 12 to expose a portion of the cathode 11; the OLED 13 is evaporated at the opening 121.
  • the cathode 11 is an indium tin oxide (ITO)/silver (Ag)/indium tin oxide (ITO) composite structure or a single layer of metallic silver; the thickness of the cathode 11 is
  • the method for fabricating the TFT substrate of the present invention does not need to completely remove the ion-inducing layer on the surface of the obtained polysilicon layer after ion implantation-induced crystallization of the amorphous silicon layer, but through a halftone mask process. Only the ion-inducing layer of the channel region is removed, and the subsequent source/drain contact regions do not need to be ion implanted again, thereby saving the mask required for ion implantation again; and the source/drain electrodes are also The fabrication is performed under the halftone mask, thereby saving the mask required for the source/drain; and the fabrication of the interlayer insulating layer is omitted because the source/drain is fabricated first, thereby saving interlayer insulation.
  • the reticle required for the layer; the method for fabricating the TFT substrate of the present invention reduces the nine masks required in the prior art to six reticle by using the halftone mask process, thereby simplifying the process, improving the production efficiency, and saving Production costs.

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Abstract

一种TFT基板的制作方法，在对非晶硅层（3）进行离子植入诱导结晶后，无需将得到的多晶硅层（4）表面的离子诱导层（5）完全去除，而是通过半色调光罩工艺，仅仅去除沟道区（41）的离子诱导层（5），且后续的源/漏极接触区（50）也不需要再进行离子植入，从而节省了再次进行离子植入所需的光罩；同时源/漏极（6）也在半色调光罩下完成制作，从而节省了制作源/漏极所需的光罩；并且因为先制作源/漏极，所以省去了层间绝缘层的制作，从而节省了制作层间绝缘层所需的光罩；TFT基板的制作方法通过使用半色调光罩工艺，将现有技术所需的九道光罩缩减至六道光罩，有效简化了制程，提高了生产效率，节省了生产成本。

Description

TFT基板的制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT基板的制作方法。
背景技术
薄膜晶体管(Thin Film Transistor，简称TFT)是目前液晶显示装置(Liquid Crystal Display，简称LCD)和有源矩阵驱动式有机电致发光显示装置(Active Matrix Organic Light-Emitting Diode，简称AMOLED)中的主要驱动元件，直接关系到高性能平板显示装置的发展方向。
低温多晶硅(Low Temperature Poly-silicon，LTPS)技术是新一代TFT基板的制造技术，与传统非晶硅(a-Si)技术的最大差异在于，低温多晶硅显示器反应速度较快，且有高亮度、高解析度与低耗电量等优点。
目前LTPS结晶工艺有准分子激光退火处理(Excimer LaserAnneal，ELA)技术和固相结晶化(Solid Phase Crystallization，SPC)技术。其中SPC技术因为大尺寸化容易且有较高的成本优势，成为大家争先研究的方向。在传统SPC方向上又包括直接高温长时间加热烘烤方式和离子诱导方式。在离子诱导结晶方式中有利用Ni(镍)或者B(硼)等诱导离子的结晶方式。
在诱导SPC方式中在植入离子完成诱导结晶后，为了形成半导体层，需要将原本植入诱导离子的a-Si(非晶硅)去除用以形成半导体的有源层。后续因为需要做源/漏极的接触区域，又需要对和源/漏极接触的有源层区域植入硼离子或者磷离子，从而实现较好的接触效果。
请参阅图1至图8，现有TFT基板的制作方法主要包括如下步骤：
步骤1、如图1所示，提供基板100，在所述基板100上沉积缓冲层200；在所述缓冲层200上沉积非晶硅层300。
步骤2、如图2所示，对所述非晶硅层300进行离子植入，并进行高温烘烤使非晶硅转变为多晶硅，得到位于缓冲层200上的多晶硅层400、及位于多晶硅层400上的离子诱导层500。
步骤3、如图3所示，采用蚀刻工艺将离子诱导层500去除，得到多晶硅层400。
步骤4、如图4所示，对所述多晶硅层400进行图案化处理，得到岛状半导体层410。
步骤5、如图5所示，在所述岛状半导体层410与缓冲层200上涂布光阻，曝光、显影后得到光阻层500。
步骤6、如图6所示，以所述光阻层500为遮蔽层，对所述岛状半导体层410进行硼离子植入，于所述岛状半导体层410上得到源/漏极接触区600。
步骤7、如图7所示，剥离光阻层500，在所述岛状半导体层410与缓冲层200上沉积栅极绝缘层700；在所述栅极绝缘层700上形成栅极800。
步骤8、如图8所示，在所述栅极绝缘层700、栅极800上形成层间绝缘层900、源/漏极910、平坦层920、阴极930、像素定义层940，最后进行OLED 950的蒸镀，进而完成TFT基板的整个制程，需要九次光罩定义才可以进行OLED蒸镀，制程成本较高。
因此，有必要提供一种TFT基板的制作方法，以解决上述问题。
发明内容
本发明的目的在于提供一种TFT基板的制作方法，可有效简化制程，提高生产效率，节省生产成本。
为实现上述目的，本发明提供一种TFT基板的制作方法，包括如下步骤：
步骤1、提供基板，在所述基板上沉积缓冲层，在所述缓冲层上沉积非晶硅层；
步骤2、对所述非晶硅层进行离子植入，并进行高温烘烤使非晶硅结晶转变为多晶硅，得到位于缓冲层上的多晶硅层、及位于多晶硅层上的离子诱导层；
步骤3、在所述离子诱导层上沉积第一金属层，在所述第一金属层上涂布光阻，提供半色调光罩，利用所述半色调光罩对所述光阻进行曝光、显影，得到相互间隔的第一光阻段与第二光阻段；所述第一光阻段的两侧区域的厚度大于中间区域的厚度；
步骤4、以所述第一光阻段与第二光阻段为遮蔽层，对所述第一金属层、离子诱导层、多晶硅层进行蚀刻，得到岛状半导体与源/漏极区域；
步骤5、对所述第一光阻段与第二光阻段进行灰化处理，去除所述第一光阻段的中间区域，以剩余的第一光阻段为遮蔽层，对所述岛状半导体与源/漏极区域中的第一金属层、及离子诱导层进行蚀刻，得到具有沟道区的岛状半导体层、位于所述岛状半导体层上的源/漏极接触区、及位于所述源/漏极接触区上的源/漏极；剥离剩余的第一光阻段与第二光阻段；
步骤6、在所述源/漏极上沉积栅极绝缘层；在所述栅极绝缘层上沉积第二金属层，并对所述第二金属层进行图案化处理，形成栅极；
步骤7、在所述栅极绝缘层、栅极上形成保护层；在所述保护层上形成平坦层；在所述平坦层、保护层、及栅极绝缘层上对应源/漏极的上方形成过孔；
步骤8、在所述平坦层上制作阴极，所述阴极经由所述过孔与所述源/漏极相接触；在所述平坦层上形成像素定义层，并在所述像素定义层上形成开口以暴露出部分阴极；在所述开口处蒸镀OLED。
所述步骤1中，所述基板为玻璃基板。
所述步骤1中，所述缓冲层为氮化硅层、氧化硅层、或二者的复合层；所述缓冲层的厚度为
Figure PCTCN2016072864-appb-000001
所述步骤1中，所述非晶硅层的厚度为
Figure PCTCN2016072864-appb-000002
所述步骤2中，在所述非晶硅层中植入的离子为硼离子或镍离子。
所述步骤3中，所述第一金属层为钼、铝、铜中的一种或多种的堆栈组合；所述第一金属层的厚度为
Figure PCTCN2016072864-appb-000003
所述步骤6中，所述栅极绝缘层为氮化硅层、氧化硅层、或二者的组合；所述栅极绝缘层的厚度为
Figure PCTCN2016072864-appb-000004
所述步骤6中，所述第二金属层为钼、铝、铜中的一种或多种的堆栈组合；所述第二金属层的厚度为
Figure PCTCN2016072864-appb-000005
所述步骤7中，所述保护层为氮化硅层、氧化硅层、或二者的组合；所述保护层的厚度为
Figure PCTCN2016072864-appb-000006
所述步骤8中，所述阴极为氧化铟锡/银/氧化铟锡复合结构或单层金属银；所述阴极的厚度为
Figure PCTCN2016072864-appb-000007
本发明还提供一种TFT基板的制作方法，包括如下步骤：
步骤1、提供基板，在所述基板上沉积缓冲层，在所述缓冲层上沉积非晶硅层；
步骤2、对所述非晶硅层进行离子植入，并进行高温烘烤使非晶硅结晶转变为多晶硅，得到位于缓冲层上的多晶硅层、及位于多晶硅层上的离子诱导层；
步骤3、在所述离子诱导层上沉积第一金属层，在所述第一金属层上涂布光阻，提供半色调光罩，利用所述半色调光罩对所述光阻进行曝光、显影，得到相互间隔的第一光阻段与第二光阻段；所述第一光阻段的两侧区域的厚度大于中间区域的厚度；
步骤4、以所述第一光阻段与第二光阻段为遮蔽层，对所述第一金属层、 离子诱导层、多晶硅层进行蚀刻，得到岛状半导体与源/漏极区域；
步骤5、对所述第一光阻段与第二光阻段进行灰化处理，去除所述第一光阻段的中间区域，以剩余的第一光阻段为遮蔽层，对所述岛状半导体与源/漏极区域中的第一金属层、及离子诱导层进行蚀刻，得到具有沟道区的岛状半导体层、位于所述岛状半导体层上的源/漏极接触区、及位于所述源/漏极接触区上的源/漏极；剥离剩余的第一光阻段与第二光阻段；
步骤6、在所述源/漏极上沉积栅极绝缘层；在所述栅极绝缘层上沉积第二金属层，并对所述第二金属层进行图案化处理，形成栅极；
步骤7、在所述栅极绝缘层、栅极上形成保护层；在所述保护层上形成平坦层；在所述平坦层、保护层、及栅极绝缘层上对应源/漏极的上方形成过孔；
步骤8、在所述平坦层上制作阴极，所述阴极经由所述过孔与所述源/漏极相接触；在所述平坦层上形成像素定义层，并在所述像素定义层上形成开口以暴露出部分阴极；在所述开口处蒸镀OLED；
其中，所述步骤1中，所述基板为玻璃基板；
其中，所述步骤1中，所述缓冲层为氮化硅层、氧化硅层、或二者的组合；所述缓冲层的厚度为
Figure PCTCN2016072864-appb-000008
其中，所述步骤1中，所述非晶硅层的厚度为
Figure PCTCN2016072864-appb-000009
其中，所述步骤2中，在所述非晶硅层中植入的离子为硼离子或镍离子；
其中，所述步骤3中，所述第一金属层为钼、铝、铜中的一种或多种的堆栈组合；所述第一金属层的厚度为
Figure PCTCN2016072864-appb-000010
本发明的有益效果：本发明的TFT基板的制作方法，在对非晶硅层进行离子植入诱导结晶后，无需将得到的多晶硅层表面的离子诱导层完全去除，而是通过半色调光罩工艺，仅仅去除沟道区的离子诱导层，且后续的源/漏极接触区也不需要再次进行离子植入，从而节省了再次进行离子植入所需的光罩；同时源/漏极也在所述半色调光罩下完成制作，从而节省了制作源/漏极所需的光罩；并且因为先制作源/漏极所以省去了层间绝缘层的制作，从而节省了制作层间绝缘层所需的光罩；本发明的TFT基板的制作方法通过使用半色调光罩工艺，将现有技术所需的九道光罩缩减至六道光罩，有效简化了制程，提高了生产效率，节省了生产成本。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本 发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为一种现有的TFT基板的制作方法的步骤1的示意图；
图2为一种现有的TFT基板的制作方法的步骤2的示意图；
图3为一种现有的TFT基板的制作方法的步骤3的示意图；
图4为一种现有的TFT基板的制作方法的步骤4的示意图；
图5为一种现有的TFT基板的制作方法的步骤5的示意图；
图6为一种现有的TFT基板的制作方法的步骤6的示意图；
图7为一种现有的TFT基板的制作方法的步骤7的示意图；
图8为一种现有的TFT基板的制作方法的步骤8的示意图；
图9为本发明的TFT基板的制作方法的示意流程图；
图10为本发明的TFT基板的制作方法的步骤1的示意图；
图11为本发明的TFT基板的制作方法的步骤2的示意图；
图12为本发明的TFT基板的制作方法的步骤3的示意图；
图13为本发明的TFT基板的制作方法的步骤4的示意图；
图14为本发明的TFT基板的制作方法的步骤5的示意图；
图15为本发明的TFT基板的制作方法的步骤6的示意图；
图16为本发明的TFT基板的制作方法的步骤7的示意图；
图17为本发明的TFT基板的制作方法的步骤8的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图9，本发明提供一种TFT基板的制作方法，包括如下步骤：
步骤1、如图10所示，提供基板1，在所述基板1上沉积缓冲层2，在所述缓冲层2上沉积非晶硅层3。
具体地，所述基板1为玻璃基板。
具体地，所述缓冲层2为氮化硅(SiNx)层、氧化硅(SiOx)层、或二者的复合层；所述缓冲层2的厚度为
Figure PCTCN2016072864-appb-000011
具体地，所述非晶硅层3的厚度为
Figure PCTCN2016072864-appb-000012
步骤2、如图11所示，对所述非晶硅层3进行离子植入，并进行高温烘烤使非晶硅结晶转变为多晶硅，得到位于缓冲层2上的多晶硅层4、及位于多晶硅层4上的离子诱导层5。所述离子诱导层5可直接接触源/漏极。
具体地，在所述非晶硅层3中植入的离子为硼离子或镍离子。
步骤3、如图12所示，在所述离子诱导层5上沉积第一金属层60，在所述第一金属层60上涂布光阻，提供半色调光罩，利用所述半色调光罩对所述光阻进行曝光、显影，得到相互间隔的第一光阻段51与第二光阻段52；所述第一光阻段51的两侧区域511的厚度大于中间区域512的厚度。
具体地，所述第一金属层60为钼(Mo)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合；所述第一金属层60的厚度为
Figure PCTCN2016072864-appb-000013
步骤4、如图13所示，以所述第一光阻段51与第二光阻段52为遮蔽层，对所述第一金属层60、离子诱导层5、多晶硅层4进行蚀刻，得到岛状半导体与源/漏极区域61。
步骤5、如图14所示，对所述第一光阻段51与第二光阻段52进行灰化处理，去除所述第一光阻段51的中间区域512，以剩余的第一光阻段51为遮蔽层，对所述岛状半导体与源/漏极区域61中的第一金属层60、及离子诱导层5进行蚀刻，得到具有沟道区41的岛状半导体层40、位于所述岛状半导体层40上的源/漏极接触区50、及位于所述源/漏极接触区50上的源/漏极6；剥离剩余的第一光阻段51与第二光阻段52。
步骤6、如图15所示，在所述源/漏极6上沉积栅极绝缘层7；在所述栅极绝缘层7上沉积第二金属层，并对所述第二金属层进行图案化处理，形成栅极8。
具体地，所述栅极绝缘层7为氮化硅层、氧化硅层、或二者的组合；所述栅极绝缘层7的厚度为
Figure PCTCN2016072864-appb-000014
具体地，所述第二金属层为钼、铝、铜中的一种或多种的堆栈组合；所述第二金属层的厚度为
Figure PCTCN2016072864-appb-000015
步骤7、如图16所示，在所述栅极绝缘层7、栅极8上形成保护层9；在所述保护层9上形成平坦层10；在所述平坦层10、保护层9、及栅极绝缘层7上对应源/漏极6的上方形成过孔91。
具体地，所述保护层9为氮化硅层、氧化硅层、或二者的组合；所述保护层9的厚度为
Figure PCTCN2016072864-appb-000016
步骤8、如图17所示，在所述平坦层10上制作阴极11，所述阴极11经由所述过孔91与所述源/漏极6相接触；在所述平坦层10上形成像素定义层12，并在所述像素定义层12上形成开口121以暴露出部分阴极11；在所述开口121处蒸镀OLED13。
具体地，所述阴极11为氧化铟锡(ITO)/银(Ag)/氧化铟锡(ITO)复合结构或单层金属银；所述阴极11的厚度为
Figure PCTCN2016072864-appb-000017
综上所述，本发明的TFT基板的制作方法，在对非晶硅层进行离子植入诱导结晶后，无需将得到的多晶硅层表面的离子诱导层完全去除，而是通过半色调光罩工艺，仅仅去除沟道区的离子诱导层，且后续的源/漏极接触区也不需要再次进行离子植入，从而节省了再次进行离子植入所需的光罩；同时源/漏极也在所述半色调光罩下完成制作，从而节省了制作源/漏极所需的光罩；并且因为先制作源/漏极所以省去了层间绝缘层的制作，从而节省了制作层间绝缘层所需的光罩；本发明的TFT基板的制作方法通过使用半色调光罩工艺，将现有技术所需的九道光罩缩减至六道光罩，有效简化了制程，提高了生产效率，节省了生产成本。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (15)

  1. 一种TFT基板的制作方法，包括如下步骤：
    步骤1、提供基板，在所述基板上沉积缓冲层，在所述缓冲层上沉积非晶硅层；
    步骤2、对所述非晶硅层进行离子植入，并进行高温烘烤使非晶硅结晶转变为多晶硅，得到位于缓冲层上的多晶硅层、及位于多晶硅层上的离子诱导层；
    步骤3、在所述离子诱导层上沉积第一金属层，在所述第一金属层上涂布光阻，提供半色调光罩，利用所述半色调光罩对所述光阻进行曝光、显影，得到相互间隔的第一光阻段与第二光阻段；所述第一光阻段的两侧区域的厚度大于中间区域的厚度；
    步骤4、以所述第一光阻段与第二光阻段为遮蔽层，对所述第一金属层、离子诱导层、多晶硅层进行蚀刻，得到岛状半导体与源/漏极区域；
    步骤5、对所述第一光阻段与第二光阻段进行灰化处理，去除所述第一光阻段的中间区域，以剩余的第一光阻段为遮蔽层，对所述岛状半导体与源/漏极区域中的第一金属层、及离子诱导层进行蚀刻，得到具有沟道区的岛状半导体层、位于所述岛状半导体层上的源/漏极接触区、及位于所述源/漏极接触区上的源/漏极；剥离剩余的第一光阻段与第二光阻段；
    步骤6、在所述源/漏极上沉积栅极绝缘层；在所述栅极绝缘层上沉积第二金属层，并对所述第二金属层进行图案化处理，形成栅极；
    步骤7、在所述栅极绝缘层、栅极上形成保护层；在所述保护层上形成平坦层；在所述平坦层、保护层、及栅极绝缘层上对应源/漏极的上方形成过孔；
    步骤8、在所述平坦层上制作阴极，所述阴极经由所述过孔与所述源/漏极相接触；在所述平坦层上形成像素定义层，并在所述像素定义层上形成开口以暴露出部分阴极；在所述开口处蒸镀OLED。
  2. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤1中，所述基板为玻璃基板。
  3. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤1中，所述缓冲层为氮化硅层、氧化硅层、或二者的组合；所述缓冲层的厚度为
    Figure PCTCN2016072864-appb-100001
  4. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤1中， 所述非晶硅层的厚度为
    Figure PCTCN2016072864-appb-100002
  5. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤2中，在所述非晶硅层中植入的离子为硼离子或镍离子。
  6. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤3中，所述第一金属层为钼、铝、铜中的一种或多种的堆栈组合；所述第一金属层的厚度为
    Figure PCTCN2016072864-appb-100003
  7. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤6中，所述栅极绝缘层为氮化硅层、氧化硅层、或二者的组合；所述栅极绝缘层的厚度为
    Figure PCTCN2016072864-appb-100004
  8. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤6中，所述第二金属层为钼、铝、铜中的一种或多种的堆栈组合；所述第二金属层的厚度为
    Figure PCTCN2016072864-appb-100005
  9. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤7中，所述保护层为氮化硅层、氧化硅层、或二者的组合；所述保护层的厚度为
    Figure PCTCN2016072864-appb-100006
  10. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤8中，所述阴极为氧化铟锡/银/氧化铟锡复合结构或单层金属银；所述阴极的厚度为
    Figure PCTCN2016072864-appb-100007
  11. 一种TFT基板的制作方法，包括如下步骤：
    步骤1、提供基板，在所述基板上沉积缓冲层，在所述缓冲层上沉积非晶硅层；
    步骤2、对所述非晶硅层进行离子植入，并进行高温烘烤使非晶硅结晶转变为多晶硅，得到位于缓冲层上的多晶硅层、及位于多晶硅层上的离子诱导层；
    步骤3、在所述离子诱导层上沉积第一金属层，在所述第一金属层上涂布光阻，提供半色调光罩，利用所述半色调光罩对所述光阻进行曝光、显影，得到相互间隔的第一光阻段与第二光阻段；所述第一光阻段的两侧区域的厚度大于中间区域的厚度；
    步骤4、以所述第一光阻段与第二光阻段为遮蔽层，对所述第一金属层、离子诱导层、多晶硅层进行蚀刻，得到岛状半导体与源/漏极区域；
    步骤5、对所述第一光阻段与第二光阻段进行灰化处理，去除所述第一光阻段的中间区域，以剩余的第一光阻段为遮蔽层，对所述岛状半导体与源/漏极区域中的第一金属层、及离子诱导层进行蚀刻，得到具有沟道区的岛状半导体层、位于所述岛状半导体层上的源/漏极接触区、及位于所述源/ 漏极接触区上的源/漏极；剥离剩余的第一光阻段与第二光阻段；
    步骤6、在所述源/漏极上沉积栅极绝缘层；在所述栅极绝缘层上沉积第二金属层，并对所述第二金属层进行图案化处理，形成栅极；
    步骤7、在所述栅极绝缘层、栅极上形成保护层；在所述保护层上形成平坦层；在所述平坦层、保护层、及栅极绝缘层上对应源/漏极的上方形成过孔；
    步骤8、在所述平坦层上制作阴极，所述阴极经由所述过孔与所述源/漏极相接触；在所述平坦层上形成像素定义层，并在所述像素定义层上形成开口以暴露出部分阴极；在所述开口处蒸镀OLED；
    其中，所述步骤1中，所述基板为玻璃基板；
    其中，所述步骤1中，所述缓冲层为氮化硅层、氧化硅层、或二者的组合；所述缓冲层的厚度为
    Figure PCTCN2016072864-appb-100008
    其中，所述步骤1中，所述非晶硅层的厚度为
    Figure PCTCN2016072864-appb-100009
    其中，所述步骤2中，在所述非晶硅层中植入的离子为硼离子或镍离子；
    其中，所述步骤3中，所述第一金属层为钼、铝、铜中的一种或多种的堆栈组合；所述第一金属层的厚度为
    Figure PCTCN2016072864-appb-100010
  12. 如权利要求11所述的TFT基板的制作方法，其中，所述步骤6中，所述栅极绝缘层为氮化硅层、氧化硅层、或二者的组合；所述栅极绝缘层的厚度为
    Figure PCTCN2016072864-appb-100011
  13. 如权利要求11所述的TFT基板的制作方法，其中，所述步骤6中，所述第二金属层为钼、铝、铜中的一种或多种的堆栈组合；所述第二金属层的厚度为
    Figure PCTCN2016072864-appb-100012
  14. 如权利要求11所述的TFT基板的制作方法，其中，所述步骤7中，所述保护层为氮化硅层、氧化硅层、或二者的组合；所述保护层的厚度为
    Figure PCTCN2016072864-appb-100013
  15. 如权利要求11所述的TFT基板的制作方法，其中，所述步骤8中，所述阴极为氧化铟锡/银/氧化铟锡复合结构或单层金属银；所述阴极的厚度为
    Figure PCTCN2016072864-appb-100014
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