WO2017082416A1 - 電子部品パッケージ - Google Patents

電子部品パッケージ Download PDF

Info

Publication number
WO2017082416A1
WO2017082416A1 PCT/JP2016/083592 JP2016083592W WO2017082416A1 WO 2017082416 A1 WO2017082416 A1 WO 2017082416A1 JP 2016083592 W JP2016083592 W JP 2016083592W WO 2017082416 A1 WO2017082416 A1 WO 2017082416A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
electronic component
sealing material
component package
connection body
Prior art date
Application number
PCT/JP2016/083592
Other languages
English (en)
French (fr)
Inventor
泰彦 福岡
忠男 山迫
雅史 廣岡
Original Assignee
京セラ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京セラ株式会社 filed Critical 京セラ株式会社
Priority to EP16864377.3A priority Critical patent/EP3376537A4/en
Priority to JP2017550427A priority patent/JPWO2017082416A1/ja
Priority to US15/773,987 priority patent/US10388628B2/en
Publication of WO2017082416A1 publication Critical patent/WO2017082416A1/ja

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04—Assemblies of printed circuits
    • H05K2201/042—Stacked spaced PCBs; Planar parts of folded flexible circuits having mounted components in between or spaced from each other
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip

Definitions

  • This disclosure relates to an electronic component package including a POP (Package On Package) in which two or more electronic component mounting boards on which electronic components are mounted are stacked.
  • POP Package On Package
  • POP Package On Package
  • Patent Document 1 An electronic component package in which a plurality of semiconductor packages are stacked one above the other is integrated in order to cope with the higher density of electronic devices.
  • POP Package On Package
  • Patent Document 1 An electronic component package in which a plurality of semiconductor packages are stacked one above the other is integrated in order to cope with the higher density of electronic devices.
  • Patent Document 1 An electronic component package in which a plurality of semiconductor packages are stacked one above the other is integrated in order to cope with the higher density of electronic devices.
  • This prior art electronic component package includes a first substrate on which a first electronic component is mounted, a second substrate on which a second electronic component is mounted, a peripheral portion of the first substrate, and a peripheral portion of the second substrate.
  • a frame body as a connection body for joining and electrically connecting the first substrate and the second substrate is provided.
  • An electronic component package that is one of a plurality of embodiments of the present disclosure includes a first substrate, a sealing material, a second substrate, and a connection body.
  • the first substrate has a first surface on which the first electronic component is mounted.
  • the sealing material is located on the first surface and seals the first electronic component and the second electronic component.
  • the second substrate has a second surface on which the second electronic component is mounted and is located inside the sealing material.
  • the connection body electrically connects the first substrate and the second substrate.
  • FIG. 1 is a cross-sectional view of an electronic component package according to one of a plurality of embodiments.
  • FIG. 2 is a plan view of the electronic component package from which the sealing material is omitted.
  • 3 is a cross-sectional view taken along line BB in FIG.
  • FIG. 4A is a plan view showing the first substrate base material.
  • 4B is a partially enlarged plan view showing an example of a state in which an interposer is arranged as a connection body on the first substrate for substrate in FIG. 4A.
  • FIG. 4C is a plan view showing a partially enlarged view of another example of a state in which a ball bump is disposed as a connection body on the first substrate for substrate in FIG. 4A.
  • FIG. 5 is a plan view showing the second substrate base material.
  • FIG. 6 is a flowchart illustrating an example of a manufacturing procedure of the electronic component package.
  • FIG. 7 is a flowchart showing an example of the manufacturing procedure of the electronic component package.
  • FIG. 8A is a simplified cross-sectional view for explaining an example of the manufacturing procedure of the electronic component package.
  • FIG. 8B is a simplified cross-sectional view for explaining an example of the manufacturing procedure of the electronic component package.
  • FIG. 8C is a simplified cross-sectional view for explaining an example of the manufacturing procedure of the electronic component package.
  • FIG. 9A is a simplified cross-sectional view for explaining the manufacturing procedure of the electronic component package according to another one of the embodiments.
  • FIG. 9B is a simplified cross-sectional view for explaining the manufacturing procedure of the electronic component package according to another one of the embodiments.
  • FIG. 9C is a simplified cross-sectional view for explaining the manufacturing procedure of the electronic component package according to another one of the embodiments.
  • FIG. 10 is a cross-sectional view of an electronic component
  • the upper substrate is supported by a contact or surface that is narrower than the area of the substrate. It is done.
  • the second substrate positioned on the upper side is positioned inside a columnar sealing material positioned on the first substrate positioned on the lower side.
  • the sealing material integrally holds the first substrate and the second substrate, the bonding is stronger than the electronic component package that is bonded only by the frame body and the solder bump.
  • being located inside the sealing material includes being positioned in a state inscribed in the side surface of the sealing material.
  • FIG. 1 is a cross-sectional view showing an embodiment of an electronic component package 1.
  • FIG. 2 is a plan view of the electronic component package 1 from which the sealing material 2 is omitted.
  • FIG. 1 is a cross-sectional view taken along line AA in FIG. 3 is a cross-sectional view taken along line BB in FIG.
  • the electronic component package 1 includes a first substrate 4 on which the first electronic component 3 is mounted on the first upper surface 6 and a second substrate 7 on which the second electronic component 5 is mounted on the second upper surface 10.
  • the first upper surface 6 is the first surface.
  • the second upper surface 10 is the second surface.
  • the second substrate 7 is positioned on the first substrate 4 substantially in parallel with a gap ⁇ L1 in the direction Z perpendicular to the first upper surface 6 of the first substrate 4.
  • the area of the second substrate 7 is smaller than that of the first substrate 4.
  • the region of the second substrate 7 is included in the region of the first substrate 4 when the first substrate 4 and the second substrate 7 are viewed in a direction opposite to the direction Z from a position away from the second substrate 7. .
  • the peripheral edge of the second substrate 7 may partially coincide with the peripheral edge of the first substrate 4.
  • the first substrate 4 and the second substrate 7 have a rectangular shape in which two orthogonal sides are a first direction X and a second direction Y.
  • the second substrate 7 is equal in length to the first substrate 4 in the first direction X and is short in the second direction Y.
  • Parallel in the present application is not limited to strict parallelism, but allows manufacturing errors and slight inclinations.
  • the columnar sealing material 2 is located on the first upper surface 6 of the first substrate 4.
  • the sealing material 2 may be located on the entire periphery of the first upper surface 6.
  • the sealing material 2 may be located on the entire surface of the first upper surface 6. Note that the “entire surface” in the present application may exclude contacts that are electrically connected to other elements.
  • the second substrate 7 is located between the sealing materials 2.
  • the second substrate 7 is substantially parallel to the first substrate 4 except for a shift due to a manufacturing error or the like.
  • the electronic component package 1 includes an integral sealing material 2 in a first space 12, a second space 13, and a third space 14.
  • the first space 12 is a space between the first substrate 4 and the second substrate 7.
  • the second space 13 is a space on the second substrate 7.
  • the third space 14 may be a space located outside the portion where the second substrate 7 is narrower in plan view than the first substrate 4.
  • the third space 14 is a space on a region where the first substrate 4 protrudes from the second substrate 7 in plan view.
  • the sealing material 2 seals the first electronic component 3 on the first substrate 4 and the second electronic component 5 on the second substrate 7.
  • the electronic component package 1 may be called a POP (Package On Package).
  • the first substrate 4 has a first connection conductor that forms a predetermined wiring pattern on the first upper surface 6.
  • the first electronic component 3 is connected to the first connection conductor.
  • the first electronic component 3 includes an active electronic component that generates heat during operation, such as an IC chip.
  • the second substrate 7 has a second upper surface 10 on which the second electronic component 5 is mounted.
  • the second substrate 7 has a second wiring conductor that forms a predetermined wiring pattern on the second upper surface 10.
  • the second electronic component 5 is connected to the second wiring conductor.
  • the second electronic component 5 includes, for example, an active electronic component that generates heat during operation of an IC or the like.
  • various electronic components such as a chip inductor, a chip capacitor, a diode, and a chip resistor can be mounted on the first upper surface 6 and the second upper surface 10. These electronic components are shown in a simplified form in a rectangular shape in FIGS. In the present disclosure, the first wiring conductor and the second wiring conductor may be distinguished from each other as a wiring conductor.
  • any one of an organic insulating material, an inorganic insulating material, and a composite insulating material obtained by bonding an inorganic insulating material with a thermosetting resin such as an epoxy resin is individually selected.
  • the organic insulating material includes a thermoplastic resin such as glass epoxy resin, polyimide, fluororesin, polynorbornene, or benzocyclobutene.
  • the inorganic insulating material includes an aluminum oxide sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, a silicon nitride sintered body, a mullite sintered body, a glass ceramic, and the like.
  • the first and second electronic components 3 and 5 may have signal, power supply, and ground terminals on the back side. Each terminal is connected to the first wiring conductor on the first upper surface 6 of the first substrate 4 and the surface mounting electrode pad which is a part of the second wiring conductor on the second upper surface 10 of the second substrate 7. Electrical connection is made through bumps. In the present disclosure, an electrical and mechanical connection may be described as being implemented.
  • the surface mounting conductor bump is made of a solder bump of tin-lead (Sn—Pb) alloy or tin-silver-copper (Sn—Ag—Cu) alloy, or gold (Au).
  • Each surface mounting electrode pad includes a wiring conductor on the first substrate 4 and the second substrate 7, an internal conductor located inside the first substrate 4 and the second substrate 7, and the first substrate 4 and the second substrate 7. Each is electrically connected to a predetermined circuit wiring via at least one of a through conductor such as a via conductor formed from the surface to the inside and a connection body 16 described later. Each terminal of the first and second electronic components 3 and 5 is electrically connected to a corresponding circuit wiring via a surface mounting electrode pad. In another example, the first and second electronic components 3 and 5 may be connected to the wiring conductors of the first substrate 4 and the second substrate 7 by bonding wires.
  • the material of the wiring conductor can include, for example, copper (Cu), nickel (Ni), gold (Au), silver (Ag), and the like.
  • the wiring conductor can include a metal material having a low melting point.
  • a metal material having a low melting point can be used for a wiring conductor on an organic substrate.
  • the wiring conductor can be formed by a metal layer forming method including a thick film method and a thin film method.
  • the organic substrate can be used as the first substrate 4 and the second substrate 7.
  • the organic substrate includes a copper-clad substrate.
  • the copper-clad substrate has a copper foil on a plate of glass epoxy resin obtained by mixing glass fiber or glass powder with a base material made of an organic material such as epoxy resin.
  • the wiring conductor can be formed by removing a part of the copper foil from the copper-clad substrate by pattern etching.
  • An inorganic insulating material can be used as the first substrate 4 and the second substrate 7.
  • a substrate made of an inorganic insulating material can be manufactured using a substrate forming method including, for example, a ceramic green sheet lamination method, an extrusion method, and the like.
  • the inorganic insulating material can include glass ceramics, alumina ceramics, aluminum nitride ceramics, and the like.
  • the wiring conductor for the inorganic insulating material a sintered body containing at least a part of copper, gold, silver, tungsten, and molybdenum can be adopted.
  • the thickness of the wiring conductor can include a range of 5 to 50 ⁇ m.
  • the second substrate 7 has a second lower surface 15.
  • the second lower surface 15 faces the first upper surface 6 of the first substrate 4.
  • the electronic component package 1 includes a connection body 16.
  • the connection body 16 mechanically bonds the first upper surface 6 of the first substrate 4 and the second lower surface 15 of the second substrate 7.
  • the connection body 16 and the first wiring conductor of the first substrate 4 and the second wiring conductor of the second substrate 7 are electrically connected.
  • the connection body 16 may be an interposer.
  • the interposer may have a conductor pattern inside. The conductor pattern transmits an electrical signal between the first substrate 4 and the second substrate 7.
  • the base material of the interposer may be an insulating material such as an epoxy resin, for example.
  • the interposer may have a prismatic shape extending in the second direction Y.
  • the connection body 16 that is an interposer may be indicated as a connection body 16a.
  • the connection body 16 may be a connection body 16b realized by a plurality of solder bumps described later.
  • the first substrate 4 and the second substrate 7 are rectangular plate-like bodies.
  • the peripheral portion 8 of the first substrate 4 includes four side portions 17a, 17b, 17c, and 17d.
  • the peripheral portion 9 of the second substrate 7 includes four side portions 18a, 18b, 18c, and 18d.
  • the second substrate 7 is shorter in the second direction Y than the first substrate 4.
  • the two side portions 18a, 18b, 18c, 18d of the second substrate 7 are located inside the sealing material 2 over the entire length.
  • the two side portions 18a and 18b may contact the sealing material 2 over the entire length.
  • the two side portions 18 c and 18 d extending in the second direction Y are exposed from the side surface of the sealing material 2.
  • the second substrate 7 is partially exposed on the side surface of the sealing material 2.
  • only one side portion 18a of the second substrate 7 may be located inward from the side surface of the sealing material 2, and all of the four side portions 18a to 18d may be It may be located inside from the side.
  • an insulating resin is used as the sealing material 2.
  • the insulating resin includes a cured resin material.
  • the resin material includes a thermosetting resin material.
  • the sealing material 2 can contain a filler.
  • the filler can include an insulating filler and a conductive filler.
  • the filler can be used to bring at least the characteristics of thermal conductivity and thermal expansion coefficient close to a desired range.
  • the thermosetting resin material include an epoxy thermosetting resin, a polyimide thermoplastic resin, and a bismaleide thermosetting resin.
  • Fillers can include metals, metal oxides, and metal nitrides.
  • the metal oxide can include aluminum oxide (Al 2 O 3 ), beryllium oxide (BeO).
  • the metal nitride includes aluminum nitride (AlN).
  • the filler can include silicon carbide (SiC) and carbon-containing materials such as diamond.
  • a part of the second substrate 7 is located inside the sealing material 2 located on the entire first upper surface 6 of the first substrate 4.
  • the second substrate 7 can be substantially parallel to the first substrate 4.
  • the third space 14 in the outer portion of the portions 18a and 18b has an integral sealing material 2.
  • the third space 14 is located between the side portions 17a and 18a and between the side portions 17b and 18b in plan view.
  • the sealing material 2 integrally holds the first substrate 4 and the second substrate 7.
  • the electronic component package 1 has high strength against peeling between the first substrate 4 and the second substrate 7, for example.
  • the second substrate 7 is partially exposed from the side surface of the sealing material 2.
  • the first substrate 4 and the second substrate 7 may be rectangular plate-like bodies in plan view. Since the two side portions 18c and 18d of the second substrate 7 are exposed on the side surfaces of the sealing material 2, a wide area for mounting the second electronic component 5 on the second substrate 7 can be secured.
  • the connection body 16 extends along the side portions 17 c and 17 d of the first substrate 4 and the side portions 18 c and 18 d of the second substrate 7 exposed from the side surface of the sealing material 2.
  • the first substrate 4 can secure a wide area for mounting the first electronic component 3 between the connecting bodies 16.
  • the connecting body 16 is a prismatic interposer extending between the first substrate 4 and the second substrate 7, a large number of electrodes are connected by conductors between the first substrate 4 and the second substrate 7. it can.
  • the connection body 16 is formed as a large bump, the connection resistance between the first substrate 4 and the second substrate 7 can be reduced.
  • the first electronic component 3 and the second electronic component 5 are sealed by the sealing material 2 connected to each other. Therefore, the heat generated from one or both of the first electronic component 3 and the second electronic component 5 can be diffused into the sealing material 2 in the first to third spaces 12 to 14. The diffused heat can be dissipated to the atmosphere from the entire surface of the sealing material 2 in the first to third spaces 12 to 14. The heat generated in one or both of the first electronic component 3 and the second electronic component 5 can be diffused throughout the sealing material 2 in the first to third spaces 12 to 14 by heat conduction.
  • the first substrate 4 and the second substrate 7 are rectangular plate-like bodies.
  • the part of the first space 12 and the part of the second space 13 are integrally connected via the part of the third space 14. Even if the first electronic component 3 and the second electronic component 5 have different heat generation amounts, the generated heat is diffused over the entire first to third spaces 12 to 14 so that the entire surface of the sealing material 2 can be diffused. Can be released to the atmosphere.
  • the 3rd space 14 with the sealing material 2 is located in the outer side of the side parts 18a and 18b.
  • the part of the first space 12 and the part of the second space 13 are connected at two places via two parts in the two third spaces 14.
  • the electronic component package 1 has high thermal conductivity between the sealing material 2 in the first space 12 and the sealing material 2 in the second space 13. Even if the heat generation amounts of the first electronic component 3 and the second electronic component 5 are different, the electronic component package 1 is divided into a portion in the first space 12 and a portion in the second space 13 of the sealing material 2. Can spread in a balanced manner.
  • a part of the sealing material 2 extends over the entire length on the outer sides of the side portions 18a and 18b.
  • the sealing material 2 can ensure a wide heat exchange path between the first space 12 and the second space 13.
  • the sealing material 2 is made of a thermosetting resin
  • the first substrate 4 on which the first electronic component 3 is mounted and the second substrate 7 on which the second electronic component 5 is stacked are laminated in a liquid state.
  • the thermosetting resin can be printed.
  • the precursor of the thermosetting resin can be filled or applied so that the first electronic component 3 mounted on the first substrate 4 and the second electronic component 5 mounted on the second substrate 7 are covered.
  • the precursor of the liquid thermosetting resin is cured by heat curing, and the sealing material 2 that is integrally connected between the first to third spaces 12 to 14 can be formed.
  • the first substrate 4 on which the first electronic component 3 is mounted on the first upper surface 6 and the second substrate 7 on which the second electronic component 5 is mounted on the second upper surface 10 are molded by the sealing material 2.
  • a highly airtight electronic component package 1 can be manufactured.
  • the first upper surface 6 of the first substrate 4 and the second lower surface 15 of the second substrate 7 are joined together by a connecting body 16 made of an interposer, solder balls, or the like.
  • the second lower surface 15 of the second substrate 7 is electrically connected to the wiring pattern on the second upper surface 10.
  • the first substrate 4 and the second substrate 7 are electrically connected.
  • the first substrate 4 and the second substrate 7 are mechanically and electrically connected in a stacked state.
  • the connection body 16 is located along the side portions 17 c and 17 d of the first substrate 4 exposed from the side surface of the sealing material 2 and the side portions 18 c and 18 d of the second substrate 7.
  • FIG. 4A is a plan view showing the base material 21 for the first substrate.
  • the first substrate base material 21 includes a plurality of portions to be the first substrate 4.
  • the first substrate base material 21 is the same material as the first substrate 4.
  • the first substrate 21 may be a rectangular plate having a side length of, for example, 70 mm and a thickness of, for example, 100 ⁇ m or more and 400 ⁇ m or less.
  • the mounting of the component on the first substrate 21 is performed by placing an IC or other electronic component on the first substrate 21 and reflow heating the first substrate 21 and the electronic component. The solder is joined.
  • the first substrate base material 21 is divided into a plurality of pieces by, for example, dicing. Each piece corresponds to the first substrate 4.
  • the first substrate 21 is divided along a plurality of dividing lines 23x and a plurality of dividing lines 23y.
  • the dividing line 23x extends along the first direction X.
  • the plurality of dividing lines 23x are separated from each other in the second direction Y by an interval ⁇ L2.
  • the plurality of dividing lines 23y are separated in the first direction X at an interval ⁇ L3.
  • the dividing line 23y extends in the second direction Y.
  • the interval ⁇ L2 is, for example, 5.05 mm
  • the interval ⁇ L3 is, for example, 5.30 mm.
  • the widths m1 and m2 of the plurality of dividing lines 23x and 23y are, for example, 0.15 mm.
  • the dividing lines 23x and 23y may be a continuous groove.
  • the dividing lines 23x and 23y may be holes arranged at a predetermined interval.
  • connection body 16 aw is placed on each dividing line 23 y of the first substrate base material 21.
  • the connection body 16aw is a base material that is divided into an interposer.
  • the connecting body 16aw may be placed so as to straddle the dividing line 23y along the dividing line 23y.
  • the connection body 16aw includes a conductor that becomes a conductor pattern after being divided along the dividing line 23y.
  • the connection body 16aw is divided along the dividing line 23 by dicing and becomes a connection body 16a which is an interposer of each electronic component package 1.
  • connection body 16 can be a connection body 16b made of solder bumps for connecting between substrates.
  • the plurality of connectors 16b are arranged along the dividing line 23y with the dividing line 23y interposed therebetween.
  • the connecting bodies 16b can be arranged not only along the dividing line 23y but also along the dividing line 23x.
  • FIG. 5 is a plan view showing the second substrate base material 22.
  • the second substrate base material 22 is the same material as the second substrate 7.
  • the second substrate base material 22 is a rectangular plate-like body having a side length of, for example, 70 mm and a thickness of, for example, 100 ⁇ m or more and 400 ⁇ m or less.
  • the second substrate base material 22 has a plurality of slits 25. The mounting of the component on the second substrate 22 is performed by placing an IC or other electronic component and joining the electronic component and the second substrate 22 with solder by reflow heating.
  • the second substrate base material 22 is divided into a plurality of pieces by, for example, dicing. Each piece corresponds to the second substrate 7.
  • the second substrate 22 is divided along a plurality of dividing lines 24x and a plurality of dividing lines 24y.
  • the dividing line 24x extends along the first direction X.
  • the plurality of dividing lines 24x are separated from each other in the second direction Y by an interval ⁇ L4.
  • the plurality of dividing lines 24y are separated in the first direction X at an interval ⁇ L5.
  • the dividing line 24y extends in the second direction Y.
  • the interval ⁇ L5 in the first direction X is, for example, 5.30 mm
  • the interval ⁇ L4 in the second direction Y is, for example, 5.05 mm.
  • the widths m3 and m4 of the plurality of dividing lines 24x and 24y are, for example, 0.15 mm.
  • the dividing lines 24x and 24y may be a continuous groove.
  • the dividing lines 24x and 24y may be holes arranged at a predetermined interval.
  • the second substrate base material 22 has a plurality of slits 25.
  • the plurality of slits 25 of the second substrate base material 22 extend along the first direction X.
  • the plurality of slits 25 can be realized by various processes such as punching with a mold or the like, and dicing.
  • Each of the plurality of slits 25 may be continuous with any one of the plurality of dividing lines 24x.
  • the plurality of slits 25 have a width ⁇ L6 parallel to the second direction Y wider than the width m3 of the dividing line 24x.
  • the width ⁇ L6 of the slit 25 is, for example, 1.00 mm.
  • FIGS. 6 and 7 are flowcharts for explaining an example of the manufacturing procedure of the electronic component package 1.
  • 8A to 8C are simplified cross-sectional views showing an example of the manufacturing procedure of the electronic component package 1.
  • a solder paste is applied on the wiring conductor of the first substrate base material 21.
  • the solder paste is applied onto the wiring conductor including the first wiring conductor in the divided first substrate 4.
  • the solder paste is applied to a region including a region where a solder bump as the connection body 16b is formed.
  • the solder paste is applied by printing such as a screen printing method.
  • the first electronic component 3 and other electronic components are placed on the first wiring conductor.
  • the first substrate 21 on which the first electronic component 3 and other electronic components are arranged is reflow-heated in step s3. By the reflow heating, the first electronic component 3 and other electronic components are mounted on the first substrate 21 via solder.
  • step s4 as shown in FIG. 8A, the first substrate base 21 on which the first electronic component 3 and other electronic components and the connection body 16 are mounted is cleaned.
  • segmented into a piece in the dicing (step s11) mentioned later is shown with the dashed-dotted line. By cleaning, particles, organic substances, and the like attached to the first substrate 21 are removed.
  • step s5 the first substrate base 21 on which the first electronic component 3 and other electronic components and the connection body 16 are mounted is inspected visually.
  • steps s21 to s25 are executed in parallel with steps s1 to s5.
  • step s21 a solder paste is printed on the wiring conductor of the second substrate base material 22 having the plurality of slits 25.
  • the solder paste is applied onto the wiring conductor including the second wiring conductor on the second upper surface 10 in the divided second substrate 7.
  • the solder paste is applied by printing such as a screen printing method.
  • step s22 the second electronic component 5 and other electronic components are placed on the second wiring conductor.
  • step s23 the second substrate base material 22 on which the second electronic component 5 and other electronic components are arranged is reflow-heated.
  • the second electronic component 5 and other electronic components are mounted on the second substrate 22 via solder.
  • the second substrate 22 on which the second electronic component 5 and other electronic components are mounted is cleaned. By cleaning, particles, organic substances, and the like attached to the second substrate 22 are removed.
  • the cleaned substrate 22 for the second substrate is inspected for appearance.
  • the first substrate 21 on which the first electronic component 3 and other electronic components and the connection body 16 are mounted is prepared.
  • a second substrate base material 22 on which the second electronic component 5 and other electronic components are mounted is prepared.
  • the second substrate base material 22 is arranged on the first substrate base material 21 via the connection body 16.
  • the first and second substrate bases 21 and 22 are reflow-heated in a state where the second substrate base member 22 is placed on the first substrate base member 21 via the connection body 16. Due to the reflow heating, the solder bumps which are the connecting bodies 16b are melted, and the first and second substrate base materials 21 and 22 are electrically connected as shown in FIG. 8B.
  • step s8 the assembly substrate in which the second substrate 22 is mounted on the first substrate 21 is cleaned. By cleaning, particles of the assembly base material, organic matter, and the like are removed.
  • step s9 a liquid thermosetting resin precursor is printed on the assembly base material of the first substrate base material 21 and the second substrate base material 22 using a metal mask. The liquid resin precursor is filled between the first substrate 21 and the second substrate 22 by printing, and the second electronic component 5 on the second substrate 22 and others. Cover the electronic components. In other words, the resin precursor is filled in a space corresponding to the first to third spaces 12 to 14.
  • step s10 the resin precursor filled or applied to the assembly base material of the first substrate base material 21 and the second substrate base material 22 is heated and cured in a batch furnace.
  • the resin precursor becomes the sealing material 2 that fills the first to third spaces 12 to 14 by thermosetting.
  • step s11 the assembled base material of the first substrate base material 21 and the second substrate base material 22 is diced. Dicing is performed along the first direction X and the second direction Y.
  • the assembly base material of the first substrate base material 21 and the second substrate base material 22 is divided into individual pieces shown in FIG. 8C by dicing. Each piece after the division becomes an electronic component package 1. As shown in FIG. 8C, the individual pieces after the division have the sealing material 2 formed on the entire surface of the first upper surface 6 of the first substrate 4.
  • Each piece after the division is configured such that the second substrate 7 is positioned between the sealing materials 2.
  • the two side portions 18 a and 18 b of the second substrate 7 correspond to a part of the slit 25.
  • the third space 14 corresponds to a space on the first substrate 21 that is located inside the slit 25 in plan view.
  • connection body 16 may be a connection body 16c in which the periphery of the connection conductor is surrounded by an insulating sleeve.
  • an insulating sleeve made of an insulating resin surrounds a substantially cylindrical connection conductor.
  • the first wiring conductor of the first substrate 21 and the second wiring conductor of the second substrate 22 may be electrically connected via the connection body 16c.
  • the connecting body 16c is disposed on the first substrate 21 in step s2, and is mounted on the first substrate 21 in step s3.
  • 9A to 9C are diagrams showing a part of the manufacturing procedure in the case of using the connection body 16c including an insulating sleeve. 9A-C correspond to FIGS. 8A-C, respectively.
  • the two side portions 18a and 18b and the two side portions 18c and 18d of the second substrate 7 do not have to be exposed from the side surface of the sealing material 2 over the entire length.
  • the third space 14 may be located over the outer periphery of the side portions 18a to 18d in plan view.
  • the sealing material 2 having such a configuration can join the first and second substrates 4 and 7 with high strength.
  • the sealing material 2 can increase the heat transfer area between the part of the first space 12 and the part of the second space 13 by the part of the third space 14. Regardless of the amount of heat of either the first electronic component 3 or the second electronic component 5, the generated heat is quickly diffused throughout the sealing material 2 in the first to third spaces 12-14.
  • the electronic component package 1 may have a film-like conductive member on the surface of the sealing material 2.
  • the film-like conductive member is formed, for example, by vapor deposition on the surface of the sealing material 2.
  • the first substrate 4 and the second substrate 7 are molded with a conductive member.
  • the conductive member of the electronic component package 1 functions as an electromagnetic shield.
  • the electronic component package 1 may have a conductive member on the whole surface or a part of the sealing material 2.
  • the electronic component package 1 may have a conductive member on a region where an electromagnetic shield is required. Since the electronic component package 1 has a conductive material on the surface of the sealing material 2, the required performance can be separated into a sealing function by a thermosetting resin and an electromagnetic shielding property by a conductive member. .
  • the sealing material 2 may be a mixed material of a thermosetting resin such as an epoxy resin and a magnetic material such as ferrite.
  • the sealing material 2 having this configuration has airtightness and electromagnetic shielding properties.
  • the second substrate base material 22 may be diced along the dividing lines 24x and 24y.
  • substrate 7 which is an individual piece is mounted in the base material 21 for 1st board
  • the present disclosure is not limited to the electronic component package 1 having the two-layer structure of the first and second substrates 4 and 7, but includes the electronic component package in a laminated structure of three or more layers.
  • the electronic component package of the present disclosure can be applied to a wireless module with an antenna.
  • An electronic component package 31 according to one of a plurality of embodiments of the present disclosure is shown in FIG.
  • the wireless module 32 is mounted on the first substrate 4
  • the antenna 33 is mounted on the second substrate 7.
  • a resonator 34 that can function as a frequency selective surface (FSS: Frequency ⁇ ⁇ Selective Surface) may be positioned between the antenna 33 and the second substrate 7.
  • the resonator 34 may be located inside or on the lower surface of the second substrate 7. 10, the same or similar components as those in the embodiment of FIGS. 1 to 3 are denoted by the same reference numerals as those in FIGS.
  • the resonator 34 may have a structure in which a plurality of unit conductors that resonate in response to an incident electromagnetic wave and reflect an electromagnetic wave having a predetermined wavelength are periodically arranged in a two-dimensional manner.
  • the unit conductor may be a metal thin film, for example.
  • the FSS can function as an artificial magnetic conductor (AMC: Artificial Magnetic Magnetic Conductor) by combining with an electrically grounded part.
  • AMC can reflect incident electromagnetic waves with substantially the same phase.
  • an antenna 33 can be located in the vicinity of the conductor surface.
  • a radio wave having a frequency close to the resonance frequency of the resonator 34 radiated from the antenna 33 can reduce and reduce the occurrence of weakening with the radio wave reflected on the conductor surface, and can radiate to the opposite side of the conductor surface.
  • the electronic component package 31 can be close to the upper surface of a flat metal battery such as a button battery.
  • the resonator 34 may be located on the upper surface of the wireless module 32 or between the first substrate 4 and the wireless module 32.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本開示の一実施形態である電子部品パッケージ１は、第１基板４と、封止材２と、第２基板７と、接続体１６とを含む。第１基板４は、第１電子部品３が搭載された第１上面６を有する。封止材２は、第１上面６の上に位置し、第１電子部品および第２電子部品を封止する。第２基板７は、第２電子部品５が搭載された第２上面１０を有し、封止材２の内部に位置する。接続体１６は、第１基板４と第２基板７とを電気的に接続する。

Description

電子部品パッケージ 関連出願の相互参照
　本出願は、２０１５年１１月１１日に出願された日本国特許出願２０１５－２２１６８４号の優先権を主張するものであり、この先の出願の開示全体をここに参照のために取り込む。
　本開示は、電子部品が搭載された電子部品実装基板を２つ以上積み重ねたＰＯＰ(Package On Package)を含む電子部品パッケージに関する。
　従来から、電子機器の高密度化に対応するために、複数の半導体パッケージを上下に積み重ねて一体的に積層したＰＯＰ(Package On Package)と呼ばれる電子部品パッケージが使用されている。このような電子部品パッケージの従来技術は、たとえば特許文献１に多層基板として記載されている。
　この従来技術の電子部品パッケージは、第１電子部品が搭載された第１基板と、第２電子部品が搭載された第２基板と、第１基板の周縁部と第２基板の周縁部とを接合して、第１基板と第２基板とを電気的に接続する接続体としての枠体とを備える。
特開２００１－２１０９５４号公報
　本開示の複数の実施形態の１つである電子部品パッケージは、第１基板と、封止材と、第２基板と、接続体とを含む。第１基板は、第１電子部品が搭載された第１面を有する。封止材は、第１面の上に位置し、第１電子部品および第２電子部品を封止する。第２基板は、第２電子部品が搭載された第２面を有し、封止材の内部に位置する。接続体は、第１基板と第２基板とを電気的に接続する。
図１は、複数の実施形態の１つに係る電子部品パッケージの断面図である。 図２は、封止材を省略した電子部品パッケージの平面図である。 図３は、図２のＢ－Ｂ線断面図である。 図４Ａは、第１基板用基材を示す平面図である。 図４Ｂは、図４Ａの第１基板用基材の上に、接続体としてインタポーザを配した状態の一例を部分拡大して示す平面図である。 図４Ｃは、図４Ａの第１基板用基材の上に、接続体としてボールバンプを配した状態の他の一例を部分拡大して示す平面図である。 図５は、第２基板用基材を示す平面図である。 図６は、電子部品パッケージの製造手順の一例を示すフローチャートである。 図７は、電子部品パッケージの製造手順の一例を示すフローチャートである。 図８Ａは、電子部品パッケージの製造手順の一例を説明するための簡略化した断面図である。 図８Ｂは、電子部品パッケージの製造手順の一例を説明するための簡略化した断面図である。 図８Ｃは、電子部品パッケージの製造手順の一例を説明するための簡略化した断面図である。 図９Ａは、複数の実施形態の他の１つに係る電子部品パッケージの製造手順を説明するための簡略化した断面図である。 図９Ｂは、複数の実施形態の他の１つに係る電子部品パッケージの製造手順を説明するための簡略化した断面図である。 図９Ｃは、複数の実施形態の他の１つに係る電子部品パッケージの製造手順を説明するための簡略化した断面図である。 図１０は、複数の実施形態の１つに係る電子部品パッケージの断面図である。
　２つ以上の電子部品を搭載した基板を、周辺部に位置する枠体とはんだバンプのみにより接合した従来の電子部品パッケージでは、上側の基板は基板の面積と比較して狭い接点または面により支えられる。本開示の電子部品パケージにおいて、上側に位置する第２基板は、下側に位置する第１基板の上に位置する柱状の封止材の内部に位置する。本開示の電子部品パケージは、第１基板と第２基板とを封止材が一体的に保持するので、枠体とはんだバンプのみで接合する電子部品パッケージより接合が強い。本願において、封止材の内部に位置するとは、封止材の側面に内接する状態で位置することも含む。以下、本開示の電子部品パッケージについて、詳細に説明する。
　図１は、電子部品パッケージ１の一実施形態を示す断面図である。図２は封止材２を省略した電子部品パッケージ１の平面図である。図１は、図２のＡ－Ａ線断面図になっている。図３は図２のＢ－Ｂ線断面図である。電子部品パッケージ１は、第１電子部品３が第１上面６に搭載された第１基板４と、第２電子部品５が第２上面１０に搭載された第２基板７とを含む。第１上面６は第１面である。第２上面１０は第２面である。第２基板７は、第１基板４上に該第１基板４の第１上面６に垂直な方向Ｚに間隔ΔＬ１をあけて実質的に平行に位置される。第２基板７は第１基板４よりも面積が小さい。第１基板４および第２基板７を、第２基板７側に離れた位置から方向Ｚの反対方向に見た平面視において、第２基板７の領域は、第１基板４の領域に含まれる。上記方向Ｚの反対方向に見た平面視において、第２基板７の周縁部は第１基板４の周縁部と部分的に一致してよい。複数の実施形態の１つにおいて、第１基板４および第２基板７は、直交する２辺を第１方向Ｘおよび第２方向Ｙとする矩形の形状を有する。第２基板７は第１基板４と第１方向Ｘの長さが等しく第２方向Ｙの長さが短い。なお、本願における「平行」とは、厳密な平行に限られず、製造上の誤差および僅かな傾きを許容する。
　第１基板４の第１上面６の上には柱状の封止材２が位置する。封止材２は、第１上面６の周縁全ての上に位置してよい。封止材２は、第１上面６の全面の上に位置してよい。なお、本願における「全面」からは、他の素子と電気的に接続する接点を除いてよい。第２基板７は、封止材２の間に位置する。第２基板７は、第１基板４に対して製造誤差等によるずれを除き実質的に平行である。電子部品パッケージ１は、第１空間１２と、第２空間１３と、第３空間１４とに一体の封止材２がある。第１空間１２は、第１基板４と第２基板７との間の空間である。第２空間１３は、第２基板７上の空間である。第３空間１４は、第２基板７が第１基板４より平面視において狭くなっている部分の外側に位置する空間としてよい。第３空間１４は、第１基板４が第２基板７より平面視において突出している領域上の空間である。封止材２は、第１基板４上の第１電子部品３及び第２基板７上の第２電子部品５を封止する。電子部品パッケージ１は、ＰＯＰ(Package On Package)と呼ばれることがある。
　第１基板４は、第１上面６の上に所定の配線パターンを成す第１接続導体を有する。第１接続導体には、第１電子部品３が接続される。第１電子部品３は、たとえばＩＣチップなどの、稼働時に発熱を伴う能動型電子部品を含む。第２基板７は、第２電子部品５が搭載される第２上面１０を有する。第２基板７は、第２上面１０の上に所定の配線パターンを成す第２配線導体を有する。第２配線導体には、第２電子部品５が接続される。第２電子部品５は、たとえばＩＣなどの稼働時に発熱を伴う能動型電子部品を含む。第１上面６、第２上面１０には、上記の第１および第２電子部品３，５の他、チップインダクタ、チップコンデンサ、ダイオード、チップ抵抗器などの各種の電子部品が実装されうる。これらの電子部品は、図１～３において、特に符号を付すこと無く長方形で簡略化して示している。本開示では、第１配線導体および第２配線導体を区別せずに配線導体とする場合がある。
　第１基板４および第２基板７の材料としては、有機絶縁材料、無機絶縁材料、及びエポキシ樹脂などの熱硬化性樹脂で無機絶縁材料を結合した複合絶縁材料からいずれか１つを個々に選択しうる。有機絶縁材料は、熱可塑性樹脂である、たとえばガラスエポキシ樹脂、ポリイミド、フッ素樹脂、ポリノルボルネンまたはベンゾシクロブテンなどを含む。無機絶縁材料は、酸化アルミニウム質焼結体、窒化アルミニウム質焼結体、炭化珪素質焼結体、窒化珪素質焼結体、ムライト質焼結体およびガラスセラミックスなどを含む。
　具体的には、上記の第１および第２電子部品３，５は、裏面側に信号用、電源用、および接地用の端子を有してよい。各端子は、第１基板４の第１上面６の第１配線導体、および第２基板７の第２上面１０の第２配線導体の一部である表面実装用電極パッドに、表面実装用導体バンプを介して電気的に接続される。本開示では、電気的かつ機械的に接続することを実装すると表記する場合がある。表面実装用導体バンプは、錫－鉛（Ｓｎ－Ｐｂ）合金または錫-銀-銅（Ｓｎ－Ａｇ－Ｃu）合金のはんだバンプ、もしくは金（Ａｕ）から成る。
　各表面実装用電極パッドは、第１基板４および第２基板７の上の配線導体、第１基板４および第２基板７の内部に位置する内部導体、第１基板４および第２基板７の表面から内部にかけて形成されたビア導体などの貫通導体、並びに後述の接続体１６の少なくとも１つを介して、それぞれ所定の回路配線に電気的に接続される。第１および第２電子部品３，５の各端子は、表面実装用電極パッドを介して対応する回路配線と電気的に接続される。他の例では、第１および第２電子部品３，５は、ボンディングワイヤによって第１基板４および第２基板７の配線導体に接続されてよい。
　上記の配線導体の材料は、たとえば、銅（Ｃｕ）、ニッケル（Ｎｉ）、金（Ａｕ）、銀（Ａｇ）などを含みうる。配線導体は、融点の低い金属材料を含みうる。融点の低い金属材料は、有機基板上の配線導体に用いうる。配線導体は、厚膜法および薄膜法などを含む金属層形成手法によって形成できる。
　第１基板４および第２基板７として、有機基板を用いうる。有機基板は、銅貼基板を含む。銅張基板は、たとえばエポキシ樹脂などの有機材料から成る基材にガラス繊維またはガラス粉末を混合したガラスエポキシ樹脂の板体の上に銅箔を有する。配線導体は、銅張基板から銅箔の一部をパターンエッチングによって除去することで形成できる。
　第１基板４および第２基板７として、無機絶縁材料を用いうる。無機絶縁材料の基板は、たとえばセラミックグリーンシート積層法、および押出し成形法などを含む基板形成手法を用いて製造しうる。無機絶縁材料は、ガラスセラミックス、アルミナ質セラミックス、および窒化アルミニウム質セラミックス等を含みうる。
　無機絶縁材料用の配線導体としては、銅、金、銀、タングステン、およびモリブデンの少なくとも一部を含む焼結体を採用しうる。配線導体の厚みは、５～５０μｍの範囲を含みうる。
　第２基板７は、第２下面１５を有する。第２下面１５は、第１基板４の第１上面６に対向する。電子部品パッケージ１は、接続体１６を含む。接続体１６は、第１基板４の第１上面６と第２基板７の第２下面１５とを機械的に接合する。接続体１６、第１基板４の第１配線導体と第２基板７の第２配線導体とを電気的に接続する。接続体１６は、インタポーザであってよい。インタポーザは、導体パターンを内部に有してよい。導体パターンは、第１基板４と第２基板７との間の電気信号を伝える。インタポーザの基材は、例えば、エポキシ樹脂等の絶縁材料であってよい。インタポーザは、第２方向Ｙに延びる角柱状であってよい。インタポーザである接続体１６は、接続体１６ａと示してよい。接続体１６は、後述する複数のはんだバンプによって実現される接続体１６ｂとしてよい。
　第１基板４および第２基板７は、矩形の板状体である。第１基板４の周縁部８は、４つの側辺部１７ａ，１７ｂ，１７ｃ，１７ｄを含む。第２基板７の周縁部９は、４つの側辺部１８ａ，１８ｂ，１８ｃ，１８ｄを含む。第２基板７は、第１基板４と比べ第２方向Ｙに短い。第２基板７の４つの側辺部１８ａ，１８ｂ，１８ｃ，１８ｄのうち、第１方向Ｘ延びる２つの側辺部１８ａ，１８ｂは、全長にわたって封止材２の内側に位置する。２つの側辺部１８ａ，１８ｂは、全長にわたって封止材２に接してよい。第２方向Ｙに延びる２つの側辺部１８ｃ，１８ｄは、封止材２の側面から露出する。第２基板７は、封止材２の側面において一部が露出している。他の実施形態では、第２基板７の１つの側辺部１８ａだけが封止材２の側面から内側に位置してよく、４つの側辺部１８ａ～１８ｄのすべてが、封止材２の側面から内側に位置してよい。
　上記の封止材２としては、絶縁性樹脂が用いられる。絶縁性樹脂は、硬化した樹脂材を含む。樹脂材は、熱硬化可能な樹脂材を含む。封止材２は、フィラーを含みうる。フィラーは、絶縁性フィラーおよび導電性フィラーを含みうる。フィラーは、熱伝導性および熱膨張率の少なくともの特性を所望の範囲に近づける際に利用しうる。熱硬化可能な樹脂材としては、例えばエポキシ系熱硬化性樹脂、ポリイミド系熱可塑性樹脂、およびビスマレイド系熱硬化性樹脂等を含む。フィラーとしては、金属、金属酸化物、金属窒化物、を含みうる。金属酸化物は、酸化アルミニウム（Ａｌ2Ｏ3）、酸化ベリリウム（ＢｅＯ）を含みうる。金属窒化物は、窒化アルミニウム（ＡｌＮ）を含む。フィラーは、炭化珪素（ＳｉＣ）、及びダイヤモンド等の炭素含有物質を含みうる。
　第２基板７の一部は、第１基板４の第１上面６の全面の上に位置する封止材２の内側に位置する。第２基板７は、第１基板４と実質的に平行となりうる。第１基板４の第１上面６と第２基板７の第２下面１５と間の第１空間１２、第２基板７の第２上面１０上の第２空間１３、第２基板７の側辺部１８ａ、１８ｂの外側部分の第３空間１４は、一体の封止材２がある。第３空間１４は、平面視において、側辺部１７ａと１８ａとの間および側辺部１７ｂと１８ｂとの間に位置する。封止材２は、第１基板４と第２基板７とを一体的に保持する。電子部品パッケージ１は、たとえば第１基板４および第２基板７間の剥離に対して高い強度をもつ。
　第２基板７は、封止材２の側面から一部が露出している。第１基板４および第２基板７は、平面視において矩形の板状体であってよい。前記第２基板７は、２つの側辺部１８ｃ，１８ｄが前記封止材２の側面に露出しているので、第２基板７上に第２電子部品５を実装する領域を広く確保できる。接続体１６は、封止材２の側面から露出している第１基板４の側辺部１７ｃ、１７ｄおよび第２基板７の側辺部１８ｃ，１８ｄに沿っている。第１基板４は、第１電子部品３を実装する領域を接続体１６の間に広く確保できる。接続体１６を第１基板４と第２基板７との間に延在する角柱状のインタポーザとした場合、第１基板４と第２基板７との間で、多数の電極間を導体で接続できる。接続体１６を大きいバンプとして形成した場合、第１基板４と第２基板７との接続抵抗を低減できる。
　第１電子部品３および第２電子部品５が、互いに連なる封止材２によって封止される。このため、第１電子部品３および第２電子部品５の一方または双方から発生した熱を、第１～第３空間１２～１４の封止材２に拡散できる。拡散した熱は、第１～第３空間１２～１４の封止材２の表面全体から大気へ放散できる。第１電子部品３および第２電子部品５の一方または双方で発生した熱を、熱伝導によって第１～第３空間１２～１４の封止材２全体に拡散できる。
　第１基板４および第２基板７は、矩形の板状体である。封止材２は、第３空間１４の部位を介して、第１空間１２の部位と第２空間１３の部位とが一体的に連なる。第１電子部品３および第２電子部品５の発熱量が異なる場合であっても、発生した熱を第１～第３空間１２～１４の全体に拡散させて、封止材２の表面全体から大気へ放散できる。
　封止材２がある第３空間１４が、側辺部１８ａ，１８ｂの外側に位置する。封止材２は、第１空間１２の部位と第２空間１３の部位とが２つの第３空間１４にある２つの部位を介して２個所で連なる。電子部品パッケージ１は、第１空間１２の封止材２と第２空間１３の封止材２との間の熱伝導性が高い。電子部品パッケージ１は、第１電子部品３および第２電子部品５の発熱量が相違しても、封止材２のうちの第１空間１２にある部位と第２空間１３にある部位とにバランスよく拡散できる。
　封止材２の一部は、側辺部１８ａ，１８ｂの外側に全長にわたっている。封止材２は、第１空間１２と第２空間１３との間の熱交換路を広く確保できる。
　封止材２が熱硬化性樹脂から成るので、第１電子部品３が搭載された第１基板４と、第２電子部品５が搭載された第２基板７とが積層された状態で、液体状の熱硬化性樹脂を印刷しうる。熱硬化性樹脂の前駆体は、第１基板４に搭載された第１電子部品３および第２基板７に搭載された第２電子部品５が覆われるように充填もしくは塗布されうる。加熱硬化によって液体状の熱硬化性樹脂の前駆体が硬化され、第１～第３空間１２～１４の間で一体的に連なる封止材２が形成されうる。第１電子部品３が第１上面６に搭載された第１基板４と、第２上面１０に第２電子部品５が搭載された第２基板７とが、封止材２によってモールドされた、気密性の高い電子部品パッケージ１を製造できる。
　インタポーザ、はんだボール等から成る接続体１６によって、第１基板４の第１上面６と第２基板７の第２下面１５とが接合している。第２基板７の第２下面１５は、第２上面１０の配線パターンと電気的に接続している。第１基板４と第２基板７とが電気的に接続される。第１基板４と第２基板７とが積層状態で機械的および電気的に接続される。接続体１６は、封止材２の側面から露出している第１基板４の側辺部１７ｃ，１７ｄ、及び第２基板７の側辺部１８ｃ，１８ｄに沿って位置する。
　図４Ａは、第１基板用基材２１を示す平面図である。第１基板用基材２１は、第１基板４となる部位を複数含む。第１基板用基材２１は、第１基板４と同じ材料である。第１基板用基材２１は、一辺の長さがたとえば７０ｍｍ、厚みがたとえば１００μｍ以上４００μｍ以下の矩形の板状体であってよい。第１基板用基材２１への部品の実装は、例えば、ＩＣその他の電子部品を第１基板用基材２１の上に載置し、リフロー加熱によって第１基板用基材２１と電子部品とをはんだが接合して行われる。
　第１基板用基材２１は、例えば、ダイシングによって複数の個片に分割される。各個片は、第１基板４に対応する。第１基板用基材２１は、複数の分割線２３ｘ、および複数の分割線２３ｙに沿って分割される。分割線２３ｘは、第１方向Ｘに沿って延びる。複数の分割線２３ｘは、各々が間隔ΔＬ２で第２方向Ｙに離れている。複数の分割線２３ｙは、間隔ΔＬ３で第１方向Ｘに離れている。分割線２３ｙは、第２方向Ｙに延びる。間隔ΔＬ２は、たとえば５．０５ｍｍであり、間隔ΔＬ３はたとえば５．３０ｍｍである。各複数の分割線２３ｘ，２３ｙの幅ｍ１，ｍ２は、たとえば０．１５ｍｍである。分割線２３ｘ，２３ｙは、一続きの溝であってよい。分割線２３ｘ、２３ｙは、所定の間隔で並ぶ穴であってよい。
　複数の実施形態の１つにおいて、第１基板用基材２１の各分割線２３ｙには、図４Ｂに示すように、接続体１６ａｗが載置される。接続体１６ａｗは、分割されてインタポーザとなる基材である。接続体１６ａｗは、分割線２３ｙに沿って分割線２３ｙを跨ぐように載置されてよい。この場合、接続体１６ａｗは、分割線２３ｙに沿って分割された後に導体パターンとなる導体を含む。接続体１６ａｗは、ダイシングによって分割線２３に沿って分割され、各電子部品パッケージ１のインタポーザである接続体１６ａとなる。
　接続体１６は、図４Ｃに示すように、基板間接続用のはんだバンプよりなる接続体１６ｂとしうる。複数の接続体１６ｂは、分割線２３ｙに沿って分割線２３ｙを挟んで並ぶ。接続体１６ｂは、分割線２３ｙのみならず分割線２３ｘに沿って並びうる。
　図５は、第２基板用基材２２を示す平面図である。第２基板用基材２２は、第２基板７と同じ材料である。第２基板用基材２２は、一辺の長さがたとえば７０ｍｍ、厚みがたとえば１００μｍ以上４００μｍ以下の矩形の板状体である。第２基板用基材２２は、複数のスリット２５を有する。第２基板用基材２２への部品の実装は、ＩＣその他の電子部品を載置して、リフロー加熱によって電子部品と第２基板用基材２２とをはんだで接合して行われる。
　第２基板用基材２２は、例えば、ダイシングによって複数の個片に分割される。各個片は、第２基板７に対応する。第２基板用基材２２は、複数の分割線２４ｘ、および複数の分割線２４ｙに沿って分割される。分割線２４ｘは、第１方向Ｘに沿って延びる。複数の分割線２４ｘは、各々が間隔ΔＬ４で第２方向Ｙに離れている。複数の分割線２４ｙは、間隔ΔＬ５で第１方向Ｘに離れている。分割線２４ｙは、第２方向Ｙに延びる。第１方向Ｘの間隔ΔＬ５は、たとえば５．３０ｍｍであり、第２方向Ｙの間隔ΔＬ４は、たとえば５．０５ｍｍである。各複数の分割線２４ｘ，２４ｙの幅ｍ３、ｍ４は、たとえば０．１５ｍｍである。分割線２４ｘ，２４ｙは、一続きの溝であってよい。分割線２４ｘ、２４ｙは、所定の間隔で並ぶ穴であってよい。
　第２基板用基材２２は、複数のスリット２５を有する。第２基板用基材２２の複数のスリット２５は、第１方向Ｘに沿って延びる。複数のスリット２５は、たとえば金型などによる打抜き加工、及びダイシング加工などの種々の加工によって実現しうる。複数のスリット２５の各々は、複数の分割線２４ｘのいずれかと連続してよい。複数のスリット２５は、第２方向Ｙに平行な幅ΔＬ６が分割線２４ｘの幅ｍ３より広い。スリット２５の幅ΔＬ６は、たとえば１．００ｍｍである。
　図６および図７は、電子部品パッケージ１の製造手順の一例を説明するためのフローチャートである。図８Ａ～図８Ｃは電子部品パッケージ１の製造手順の一例を示す簡略化した断面図である。
　ステップｓ１では、第１基板用基材２１の配線導体の上にはんだペーストを塗布する。はんだペーストは、分割後の第１基板４において第１配線導体を含む配線導体のうえに塗布される。はんだペーストは、例えば接続体１６ｂとしてのはんだバンプが形成される領域を含む領域に塗布される。はんだペーストは、例えばスクリーン印刷法などの印刷によって塗布される。ステップｓ２では、第１電子部品３およびその他の電子部品が第１配線導体の上に配置される。第１電子部品３およびその他の電子部品が上に配置されている第１基板用基材２１は、ステップｓ３においてリフロー加熱される。リフロー加熱によって、第１電子部品３およびその他の電子部品は、第１基板用基材２１の上にはんだを介して実装される。はんだペーストは、リフロー加熱によって溶融し、接続体１６ｂとしてのはんだバンプとなる。ステップｓ４では、図８Ａに示すような、第１電子部品３およびその他の電子部品、並びに接続体１６が実装された第１基板用基材２１を洗浄する。図８Ａでは、後述するダイシング（ステップｓ１１）において個片に分割される境界を一点鎖線により示している。洗浄によって、第１基板用基材２１に付着するパーティクル、有機物などが除去される。ステップｓ５では、第１電子部品３およびその他の電子部品、並びに接続体１６が実装された第１基板用基材２１を外観で検査する。
　電子部品パッケージ１の製造手順の一例では、ステップｓ１～ｓ５と並行してステップｓ２１～ｓ２５を実行する。ステップｓ２１では、複数のスリット２５を有する第２基板用基材２２の配線導体の上にはんだペーストを印刷する。はんだペーストは、分割後の第２基板７において第２上面１０の第２配線導体を含む配線導体のうえに塗布される。はんだペーストは、例えばスクリーン印刷法などの印刷によって塗布される。ステップｓ２２では、第２電子部品５およびその他の電子部品が第２配線導体の上に配置される。ステップｓ２３では、第２電子部品５およびその他の電子部品が上に配置されている第２基板用基材２２がリフロー加熱される。リフロー加熱後に、第２電子部品５およびその他の電子部品は、第２基板用基材２２の上にはんだを介して実装される。ステップｓ２４では、第２電子部品５およびその他の電子部品が実装された第２基板用基材２２を洗浄する。洗浄によって、第２基板用基材２２に付着するパーティクル、有機物などが除去される。ステップｓ２５では、洗浄後の第２基板用基材２２を外観で検査する。
　上記のステップｓ１～ｓ５において、第１電子部品３およびその他の電子部品、ならびに接続体１６が実装された第１基板用基材２１が準備される。ステップｓ２１～ｓ２５において、第２電子部品５およびその他の電子部品が実装された第２基板用基材２２が準備される。ステップｓ６では、第１基板用基材２１の上に接続体１６を介して第２基板用基材２２が配置される。ステップｓ７では、第１基板用基材２１の上に接続体１６を介して第２基板用基材２２を載せた状態で、第１，２基板用基材２１，２２をリフロー加熱する。リフロー加熱によって、接続体１６ｂであるはんだバンプが溶融して、図８Ｂに示されるように、第１，２基板用基材２１，２２を電気的に接続する。
　ステップｓ８では、第１基板用基材２１上に第２基板用基材２２が実装された組み立て基材が洗浄される。洗浄によって、組み立て基材のパーティクル、および有機物などが除去される。ステップｓ９では、第１基板用基材２１及び第２基板用基材２２の組立て基材の上から、メタルマスクを用いて液体状の熱硬化性樹脂の前駆体が印刷される。印刷によって液体状の樹脂前駆体は、第１基板用基材２１と第２基板用基材２２との間に充填されるとともに、第２基板用基材２２上の第２電子部品５およびその他の電子部品を覆う。言い換えると、樹脂前駆体は、第１～第３空間１２～１４に相当する空間に充填される。
　ステップｓ１０では、第１基板用基材２１および第２基板用基材２２の組み立て基材に充填もしくは塗布された樹脂前駆体がバッチ炉で加熱されて硬化する。樹脂前駆体は、熱硬化によって第１～第３空間１２～１４を埋める封止材２となる。ステップｓ１１では、第１基板用基材２１および第２基板用基材２２の組み立て基材をダイシングする。ダイシングは、第１方向Ｘおよび第２方向Ｙに沿って実行される。ダイシングによって、第１基板用基材２１および第２基板用基材２２の組み立て基材は、図８Ｃに示される個片に分割される。分割後の各個片は、各々が電子部品パッケージ１となる。分割後の各個片は、図８Ｃに示すように、第１基板４の第１上面６の全面の上に封止材２が形成されている。分割後の各個片は、封止材２の間に第２基板７が位置する構成となる。
　第２基板７の２つの側辺部１８ａ，１８ｂは、スリット２５の一部に相当する。第３空間１４は、平面視においてスリット２５の内側に位置する第１基板用基材２１上の空間に対応する。
　接続体１６は、接続導体の周囲を絶縁スリーブで囲んだ接続体１６ｃであってよい。接続体１６ｃは、略円柱状の接続導体の周囲を絶縁樹脂からなる絶縁スリーブが囲んでいる。第１基板用基材２１の第１配線導体と、第２基板用基材２２の第２配線導体とは、接続体１６ｃを介して電気的に接続されてよい。接続体１６ｃは、ステップｓ２で第１基板用基材２１の上に配置され、ステップｓ３で第１基板用基材２１の上に実装される。図９Ａ～Ｃは、絶縁スリーブを含む接続体１６ｃを用いる場合の製造手順の一部を示す図である。図９Ａ～Ｃは、それぞれ図８Ａ～Ｃに対応する。
　第２基板７の２つの側辺部１８ａ，１８ｂと、２つの側辺部１８ｃ，１８ｄとは、全長にわたって封止材２の側面から露出しなくてよい。言い換えれば、第３空間１４は、平面視において側辺部１８ａ～１８ｄの外周に渡り位置してよい。
　このような構成の封止材２は、第１および第２基板４，７を大きな強度で接合することができる。封止材２は、第３空間１４の部位によって第１空間１２の部位と第２空間１３の部位との間の伝熱面積を大きくできる。第１電子部品３および第２電子部品５のいずれの熱量が大きい場合であっても、発生した熱は第１～第３空間１２～１４の封止材２全体に迅速に拡散される。
　電子部品パッケージ１は、封止材２の表面に、膜状の導電性部材を有してよい。膜状の導電性部材は、例えば封止材２の表面への蒸着によって形成される。第１基板４と第２基板７とが、導電性部材によってモールドされる。電子部品パッケージ１の導電性部材は、電磁シールドとして機能する。
　電子部品パッケージ１は、封止材２の表面全体または一部の上に導電性部材を有してよい。電子部品パッケージ１は、電磁シールドが必要とされる領域の上に導電性部材を有してよい。電子部品パッケージ１は、封止材２の表面上に導電性材料を有することで、求められる性能を熱硬化性樹脂による封止機能と、導電性部材による電磁遮蔽性とに分離することができる。
　封止材２は、エポキシ樹脂などの熱硬化性樹脂とフェライトなどの磁性体材料との混合材料であってよい。この構成の封止材２は、気密性と電磁遮蔽性とを有する。
　前述のステップｓ２５の外観検査後、第２基板用基材２２を分割線２４ｘ，２４ｙでダイシングしてよい。この場合、ｓ６では、個片である第２基板７が第１基板用基材２１に載置される。
　本開示は、第１および第２基板４，７の２層構造の電子部品パッケージ１に限定されず、３層以上の積層構造に電子部品パッケージを含む。
　本開示の電子部品パッケージは、アンテナ付きの無線モジュールに適用しうる。本開示の複数の実施形態の１つに係る電子部品パッケージ３１を図１０に示す。電子部品パッケージ３１は、第１基板４に無線モジュール３２を搭載し、第２基板７にアンテナ３３を搭載する。周波数選択表面（ＦＳＳ：Frequency Selective Surface）として機能しうる共振器３４が、アンテナ３３と第２基板７との間に位置してよい。共振器３４は、第２基板７の内部もしくは下面に位置してよい。図１０において、図１～３の実施形態と同一または類似の構成要素には、図１～３と同じ参照符号を付して説明を省略する。
　共振器３４は、電磁波の入射に応じて共振し、所定の波長の電磁波を反射する複数の単位導体が２次元的に周期的に配列された構造であってよい。単位導体は、例えば、金属の薄膜であってよい。ＦＳＳは、電気的に接地された部分と組み合わせることによって、人工磁気導体（ＡＭＣ：Artificial Magnetic Conductor）として機能しうる。ＡＭＣは、入射した電磁波を略同位相で反射しうる。
　電子部品パッケージ３１は、導体面の近傍にアンテナ３３が位置しうる。アンテナ３３から放射される共振器３４の共振周波数に近い周波数を有する電波は、導体面に反射される電波と弱め合いが生じるのを低減減少し、導体面と反対側に放射しうる。例えば、電子部品パッケージ３１は、ボタン電池等の扁平な金属製の電池の上面に近接できる。共振器３４は、無線モジュール３２の上面または第１基板４と無線モジュール３２との間に位置してよい。
　なお、本発明は上述の各実施形態に限定されるものではなく、本発明の要旨を逸脱しない範囲内であれば、種々の変更が可能である。
　１　電子部品パッケージ
　２　封止材
　３　第１電子部品
　４　第１基板
　５　第２電子部品
　６　第１上面
　７　第２基板
　８　第１基板４の周縁部
　９　第２基板７の周縁部
　１０　第２上面
　１２　第１空間
　１３　第２空間
　１４　第３空間
　１５　第２下面
　１６　接続体
　１７ａ～１７ｄ；１８ａ～１８ｄ　側辺部
　２１　第１基板用基材
　２２　第２基板用基材
　２３ｘ，２３ｙ；２４ｘ，２４ｙ　分割線
　２５　スリット
　３１　電子部品パッケージ
　３２　無線モジュール
　３３　アンテナ
　３４　共振器（周波数選択表面）

Claims (9)

  1. 　第１電子部品が搭載された第１面を有する第１基板と、
    　前記第１面の上に位置する封止材であって、前記第１電子部品および第２電子部品を封止する封止材と、
    　前記第２電子部品が搭載された第２面を有する第２基板であって、前記封止材の内部に位置する第２基板と、
    　前記第１基板と前記第２基板とを電気的に接続する接続体と
    を備える電子部品パッケージ。
  2. 　前記第２基板の一部は、前記封止材の側面から露出している請求項１に記載の電子部品パッケージ。
  3. 　前記第１基板および前記第２基板は平面視において矩形の板状体であり、前記第２基板は２つの側辺部が前記封止材の側面から露出している請求項２に記載の電子部品パッケージ。
  4. 　前記接続体は、前記２つの側辺部に沿って並ぶ請求項３に記載の電子部品パッケージ。
  5. 　前記接続体は、前記２つの側辺部に沿って前記第１基板と前記第２基板との間に延在する角柱状のインタポーザを含む請求項４に記載の電子部品パッケージ。
  6. 　前記接続体は、バンプである請求項１から４の何れか一項に記載の電子部品パッケージ。
  7. 　前記接続体は、絶縁スリーブによって周囲を囲まれる接続導体を含む請求項１から４の何れか一項に記載の電子部品パッケージ。
  8. 　前記封止材は、硬化した樹脂材料からなる請求項１から７の何れか一項に記載の電子部品パッケージ。
  9. 　前記封止材は、前記樹脂材料より熱伝導性の高い絶縁性フィラーを含む請求項８に記載の電子部品パッケージ。
PCT/JP2016/083592 2015-11-11 2016-11-11 電子部品パッケージ WO2017082416A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP16864377.3A EP3376537A4 (en) 2015-11-11 2016-11-11 BOX OF ELECTRONIC COMPONENTS
JP2017550427A JPWO2017082416A1 (ja) 2015-11-11 2016-11-11 電子部品パッケージ
US15/773,987 US10388628B2 (en) 2015-11-11 2016-11-11 Electronic component package

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015-221684 2015-11-11
JP2015221684 2015-11-11

Publications (1)

Publication Number Publication Date
WO2017082416A1 true WO2017082416A1 (ja) 2017-05-18

Family

ID=58695507

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2016/083592 WO2017082416A1 (ja) 2015-11-11 2016-11-11 電子部品パッケージ

Country Status (4)

Country Link
US (1) US10388628B2 (ja)
EP (1) EP3376537A4 (ja)
JP (1) JPWO2017082416A1 (ja)
WO (1) WO2017082416A1 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102409913B1 (ko) * 2017-12-06 2022-06-16 삼성전자주식회사 솔더 리플로우 장치 및 이를 이용한 전자 장치의 제조 방법

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09180788A (ja) * 1995-12-22 1997-07-11 Nec Corp プリント基板接続用同軸端子及びプリント基板の接続構造
JP2006261387A (ja) * 2005-03-17 2006-09-28 Matsushita Electric Ind Co Ltd モジュールとその製造方法
JP2008166327A (ja) * 2006-12-27 2008-07-17 Shinko Electric Ind Co Ltd 配線基板及びその製造方法と半導体装置
JP2008311267A (ja) * 2007-06-12 2008-12-25 Taiyo Yuden Co Ltd 回路モジュールの製造方法及び回路モジュール
JP2010118369A (ja) * 2008-11-11 2010-05-27 J Devices:Kk 多層プリント配線基板用柱部品、その製造方法、及び電子部品モジュール
US20130084678A1 (en) * 2011-09-30 2013-04-04 Byeong Ho JEONG Method Of Manufacturing Package-On-Package (Pop)
WO2014097725A1 (ja) * 2012-12-18 2014-06-26 株式会社村田製作所 積層型電子装置およびその製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001210954A (ja) 2000-01-24 2001-08-03 Ibiden Co Ltd 多層基板
US6472741B1 (en) * 2001-07-14 2002-10-29 Siliconware Precision Industries Co., Ltd. Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same
TWI255536B (en) * 2005-02-02 2006-05-21 Siliconware Precision Industries Co Ltd Chip-stacked semiconductor package and fabrication method thereof
US7687899B1 (en) * 2007-08-07 2010-03-30 Amkor Technology, Inc. Dual laminate package structure with embedded elements
US8106499B2 (en) * 2009-06-20 2012-01-31 Stats Chippac Ltd. Integrated circuit packaging system with a dual substrate package and method of manufacture thereof
JP5352437B2 (ja) * 2009-11-30 2013-11-27 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8080445B1 (en) * 2010-09-07 2011-12-20 Stats Chippac, Ltd. Semiconductor device and method of forming WLP with semiconductor die embedded within penetrable encapsulant between TSV interposers
JP5951414B2 (ja) * 2012-08-29 2016-07-13 新光電気工業株式会社 電子部品内蔵基板及び電子部品内蔵基板の製造方法
JP5427305B1 (ja) * 2013-02-19 2014-02-26 株式会社フジクラ 部品内蔵基板及びその製造方法並びに実装体
KR101588947B1 (ko) * 2014-03-05 2016-01-26 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09180788A (ja) * 1995-12-22 1997-07-11 Nec Corp プリント基板接続用同軸端子及びプリント基板の接続構造
JP2006261387A (ja) * 2005-03-17 2006-09-28 Matsushita Electric Ind Co Ltd モジュールとその製造方法
JP2008166327A (ja) * 2006-12-27 2008-07-17 Shinko Electric Ind Co Ltd 配線基板及びその製造方法と半導体装置
JP2008311267A (ja) * 2007-06-12 2008-12-25 Taiyo Yuden Co Ltd 回路モジュールの製造方法及び回路モジュール
JP2010118369A (ja) * 2008-11-11 2010-05-27 J Devices:Kk 多層プリント配線基板用柱部品、その製造方法、及び電子部品モジュール
US20130084678A1 (en) * 2011-09-30 2013-04-04 Byeong Ho JEONG Method Of Manufacturing Package-On-Package (Pop)
WO2014097725A1 (ja) * 2012-12-18 2014-06-26 株式会社村田製作所 積層型電子装置およびその製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3376537A4 *

Also Published As

Publication number Publication date
US10388628B2 (en) 2019-08-20
EP3376537A4 (en) 2019-04-17
JPWO2017082416A1 (ja) 2018-06-14
EP3376537A1 (en) 2018-09-19
US20180331068A1 (en) 2018-11-15

Similar Documents

Publication Publication Date Title
JP5823043B2 (ja) 電子素子搭載用基板、電子装置および撮像モジュール
JP6096812B2 (ja) 電子素子搭載用パッケージ、電子装置および撮像モジュール
US20060043562A1 (en) Circuit device and manufacture method for circuit device
JP5518086B2 (ja) 素子収納用パッケージおよび実装構造体
WO2007114224A1 (ja) 回路モジュール及び無線通信機器、並びに回路モジュールの製造方法
TW200945546A (en) Semiconductor device
CN107993985B (zh) 电子部件搭载用基板、电子装置以及电子模块
JP6140834B2 (ja) 配線基板および電子装置
US10985098B2 (en) Electronic component mounting substrate, electronic device, and electronic module
JP6626735B2 (ja) 電子部品搭載用基板、電子装置および電子モジュール
JP7075810B2 (ja) 電子部品収納用パッケージ、電子装置、および電子モジュール
WO2017082416A1 (ja) 電子部品パッケージ
JP2021005674A (ja) 電子部品モジュール、電子部品ユニット、および、電子部品モジュールの製造方法
CN108028232B (zh) 布线基板、电子装置以及电子模块
US20150187676A1 (en) Electronic component module
WO2019208577A1 (ja) 放熱基板および電子装置
JP6989292B2 (ja) 電子素子実装用基板、電子装置および電子モジュール
JP2007042848A (ja) 配線基板、電気素子装置並びに複合基板
JP7299121B2 (ja) 回路基板、電子部品および電子モジュール
JP6747901B2 (ja) 電子素子搭載用基板および電子装置
JP7433766B2 (ja) 回路基板、電子部品および電子モジュール
JP2017174872A (ja) 半導体素子収納用パッケージおよび半導体装置
JP6680634B2 (ja) 半導体素子実装用基板および半導体装置
JP6465387B2 (ja) 電子部品
JP2006185977A (ja) 配線基板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16864377

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2017550427

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 15773987

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2016864377

Country of ref document: EP