WO2017081798A1 - 半導体装置、半導体検出器並びにそれらの製造方法、半導体チップまたは基板 - Google Patents

半導体装置、半導体検出器並びにそれらの製造方法、半導体チップまたは基板 Download PDF

Info

Publication number
WO2017081798A1
WO2017081798A1 PCT/JP2015/081891 JP2015081891W WO2017081798A1 WO 2017081798 A1 WO2017081798 A1 WO 2017081798A1 JP 2015081891 W JP2015081891 W JP 2015081891W WO 2017081798 A1 WO2017081798 A1 WO 2017081798A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
substrate
semiconductor device
cylindrical
semiconductor
Prior art date
Application number
PCT/JP2015/081891
Other languages
English (en)
French (fr)
Inventor
弘之 岸原
吉牟田　利典
敏 徳田
和田　幸久
元吉　真
Original Assignee
株式会社島津製作所
東北マイクロテック株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社島津製作所, 東北マイクロテック株式会社 filed Critical 株式会社島津製作所
Priority to US15/775,538 priority Critical patent/US10468365B2/en
Priority to PCT/JP2015/081891 priority patent/WO2017081798A1/ja
Priority to JP2017549943A priority patent/JP6430658B2/ja
Publication of WO2017081798A1 publication Critical patent/WO2017081798A1/ja

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14632—Wafer-level processed structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11472—Profile of the lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13011—Shape comprising apertures or cavities, e.g. hollow bump
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13118—Zinc [Zn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16057—Shape in side view
    • H01L2224/16059—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/1607—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16148—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81897—Mechanical interlocking, e.g. anchoring, hook and loop-type fastening or the like
    • H01L2224/81898—Press-fitting, i.e. pushing the parts together and fastening by friction, e.g. by compression of one part against the other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81897—Mechanical interlocking, e.g. anchoring, hook and loop-type fastening or the like
    • H01L2224/81898—Press-fitting, i.e. pushing the parts together and fastening by friction, e.g. by compression of one part against the other
    • H01L2224/81899—Press-fitting, i.e. pushing the parts together and fastening by friction, e.g. by compression of one part against the other using resilient parts in the bump connector or in the bonding area

Definitions

  • the present invention relates to a semiconductor device, a semiconductor detector, a manufacturing method thereof, a semiconductor chip or a substrate used in the medical field, the industrial field, and the nuclear field.
  • flip chip bonding in which the electrodes of the semiconductor chip and the electrodes on the signal readout substrate face each other and are electrically connected via conductive bumps (bump electrodes), has a structure as shown in FIG. is there.
  • This structure includes a signal readout substrate 101, a semiconductor chip 102, a pixel electrode 103, a conductive bump 104, and an insulating layer 105.
  • the signal readout substrate 101 is a signal readout substrate such as a CMOS integrated circuit in which the pixel electrodes 103 are arranged in a two-dimensional matrix, for example. Note that a substrate represented by a counter substrate or the like may be used instead of the semiconductor chip.
  • the pixel electrode 103 is formed on the signal readout substrate 101.
  • the conductive bump 104 is formed on the semiconductor chip 102 as a counter pixel electrode at a position facing the pixel electrode 103.
  • the flip chip bonding shown in FIG. 7 is used for a photodetector and a radiation detector, detects light and radiation, and takes out a signal obtained by detection.
  • flip-chip bonding includes adhesive bonding methods such as conductive resin bonding, which uses organic materials, and anisotropic conductive member bonding.
  • the present invention can also be applied to the case where both substrates are used as bonding targets (see, for example, Patent Document 1).
  • the conventional flip chip connection has the following problems. That is, if the pitch of the electrodes (corresponding to the pixel pitch) is 50 ⁇ m or more, connection is possible without any problem. However, if the pitch is 20 ⁇ m or less, the bump size becomes fine, and a uniform bump is formed and connected. There is a problem that it becomes difficult.
  • the present invention has been made in view of such circumstances, and an object thereof is to provide a semiconductor device, a semiconductor detector, a manufacturing method thereof, a semiconductor chip, or a substrate that can be reliably connected. .
  • the present invention has the following configuration.
  • a first electrode is formed on one semiconductor chip or substrate
  • a second electrode is formed on the other semiconductor chip or substrate at a position facing the first electrode
  • a cylindrical electrode is formed on the second electrode, and the first electrode of the one semiconductor chip or substrate and the cylindrical electrode of the other semiconductor chip or substrate are mechanically and electrically connected to each other. It is structured to be connected.
  • the cylindrical electrode has a cylindrical shape, the pressure applied to the semiconductor chip or the substrate can be reduced because the bonding area is smaller than that of the conventional bump-shaped bump electrode. Further, since the bonding area is reduced, the diameter of the electrode can be formed with good reproducibility, and the connection can be reliably performed.
  • the cylindrical electrode is directed inward so that an inner diameter and an outer diameter on the side connected to the first electrode gradually decrease with respect to an inner diameter and an outer diameter on the second electrode side. Is a curved tube.
  • the side of the cylindrical electrode that is connected to the first electrode is slightly crushed inward, so that contact can be made more reliably.
  • the second electrode and the cylindrical electrode are integrally formed of the same material.
  • the manufacturing process can be simplified, and a reliable electrical connection can be maintained without a problem of separation between the second electrode and the cylindrical electrode.
  • a plurality of the second electrodes and the cylindrical electrodes are formed in association with one of the first electrodes.
  • the cylindrical electrode when the height of the cylindrical electrode is t and the diameter of the cylindrical electrode is d, the condition of t / d ⁇ 1/2 is satisfied. With this configuration, the cylindrical electrode can be reliably formed.
  • a semiconductor detector has the structure of the semiconductor device described above, and any one of the semiconductor chips or the substrate detects light or radiation, and any signal obtained by detection is detected. It is structured to be taken out from the other semiconductor chip or substrate.
  • a method of manufacturing a semiconductor device includes a step of forming a second electrode on the other semiconductor chip or substrate at a position opposite to the first electrode formed on one semiconductor chip or substrate.
  • a cylindrical electrode forming step including a step of forming a cylindrical electrode on the second electrode.
  • the step of forming the second electrode and the step of forming the cylindrical electrode include a step of applying a resist, a step of exposing the resist to form an opening, and the opening The step of depositing a portion to be the second electrode on the bottom surface of the opening and depositing the portion to be the cylindrical electrode on the inner wall of the opening and removing the resist Process.
  • the opening is curved inward so that the diameter of the opening connected to the first electrode gradually decreases with respect to the diameter of the second electrode.
  • the step of forming the first electrode on the one semiconductor chip or substrate, the first electrode formed on the one semiconductor chip or substrate, and the other semiconductor chip or substrate An electrode contact step of aligning and bonding the electrodes of both the semiconductor chip or the substrate so that the cylindrical electrodes formed on each other are in contact with each other; and the first electrode and the cylindrical electrode At least one is provided with an electrode joining step in which both electrodes are joined to each other mechanically and electrically by applying pressure, heat or ultrasonic energy.
  • the vapor deposition is sputter vapor deposition.
  • the cylindrical electrode is cylindrical, the diameter of the electrode is also formed with high reproducibility as the junction area is reduced. Connection can be made reliably.
  • SEM scanning electron microscope
  • FIG. 1 is a schematic cross-sectional view of a semiconductor detector (radiation detector) according to the embodiment.
  • FIG. 2 is a specific example of a signal readout substrate and a counter substrate of the semiconductor detector (radiation detector) according to the embodiment.
  • FIG. 3 is a schematic cross-sectional view showing a configuration, and FIG. 3 is an equivalent circuit per unit pixel of a signal readout substrate of a semiconductor detector (radiation detector) according to the embodiment.
  • the semiconductor detector is used as a radiation detector.
  • the counter pixel electrode and the wall bump electrode are not shown.
  • the radiation detector includes a signal readout substrate 1 and an opposing substrate 2 disposed so as to face the signal readout substrate 1.
  • the signal readout substrate 1 includes each pixel electrode 11 (corresponding to a first electrode) arranged in a two-dimensional matrix and a pixel arrangement layer for arranging them.
  • the counter substrate 2 is formed by stacking a common electrode 21 and a photoelectric conversion semiconductor layer 23 in this order. The surface of the counter substrate 2 on the photoelectric conversion semiconductor layer 23 side is electrically connected to each pixel electrode 11 of the signal readout substrate 1 for each pixel.
  • the pixel electrode 11 and the counter substrate 2 of the signal readout substrate 1 are formed by a counter pixel electrode 33 (corresponding to a second electrode) and a wall bump electrode 34 (corresponding to a cylindrical electrode) formed by sputter deposition described later.
  • the photoelectric conversion semiconductor layer 23 is bonded to face each other.
  • the signal readout substrate 1 is formed of a glass substrate. On the signal readout substrate 1, in addition to the pixel electrode 11 described above, a pixel capacitor 12 and a switching transistor 13 are formed in a two-dimensional matrix, and a scanning line 14 (see FIG. 3) and a signal readout line 15 (see FIG. 3). Pattern) is formed vertically and horizontally in the row and column directions.
  • the reference electrode 12 a of the pixel capacitor 12 and the gate electrode 13 a of the switching transistor 13 are stacked on the signal readout substrate 1 and covered with an interlayer insulating film 31.
  • the capacitor electrode 12b of the pixel capacitor 12 is stacked on the interlayer insulating film 31 so as to face the reference electrode 12a with the interlayer insulating film 31 interposed therebetween, and the source electrode 13b and the drain electrode 13c of the switching transistor 13 are stacked. Then, except for the portion where the pixel electrode 11 exists, it is covered with the sealing material 32.
  • the capacitor electrode 12b and the source electrode 13b are electrically connected to each other.
  • the capacitor electrode 12b and the source electrode 13b may be integrally formed simultaneously.
  • the reference electrode 13a is grounded.
  • plasma SiN is used for the interlayer insulating film 31.
  • the scanning line 14 is electrically connected to the gate electrode 13a of the switching transistor 13 (see FIG. 2), and the signal readout line 15 is connected to the drain electrode 13c of the switching transistor 13 (see FIG. 2). ) Is electrically connected.
  • the scanning line 14 extends in the row direction of each pixel, and the signal readout line 15 extends in the column direction of each pixel.
  • the scanning line 14 and the signal readout line 15 are orthogonal to each other.
  • Reference numeral 23 in FIG. 3 is an equivalent circuit of the photoelectric conversion semiconductor layer.
  • the pixel capacitor 12, the switching transistor 13, and the interlayer insulating film 31 including the scanning line 14 and the signal readout line 15 are patterned as a pixel array layer on the surface of the signal readout substrate 1 using a semiconductor thin film manufacturing technique or a fine processing technique. Is formed.
  • the photoelectric conversion semiconductor layer 23 is formed of CdTe (cadmium telluride), ZnTe (zinc telluride), CdZnTe (cadmium zinc telluride), GaAs (gallium arsenide), or the like.
  • the pixel electrode 11 of the signal readout substrate 1 and the photoelectric conversion semiconductor layer 23 of the counter substrate 2 are bonded to face each other.
  • Au gold
  • Cu copper
  • Al aluminum
  • Ni nickel
  • In indium
  • Pb lead
  • Zn zinc
  • the pixel electrode 11 of the signal readout substrate 1 and the photoelectric conversion semiconductor layer 23 of the counter substrate 2 Adhere to each other.
  • each pixel electrode 11 corresponds to each pixel, by converting the signal charges read corresponding to the pixel electrode 11 into pixel values, the pixel values corresponding to the pixels are arranged two-dimensionally.
  • a two-dimensional image (a radiation image having a two-dimensional distribution) can be acquired.
  • FIG. 4 is a schematic cross-sectional view illustrating a process of forming the counter pixel electrode and the wall bump electrode according to the embodiment. Note that illustration of the photoelectric conversion semiconductor layer is omitted in FIG.
  • FIG. 4 shows a process in the case of forming a wall bump electrode of Au (gold) having a diameter: ⁇ 3 ⁇ m and a height: 3 ⁇ m.
  • a resist R having a thickness of 3 ⁇ m is applied to the common electrode 21 (hereinafter, collectively referred to as “support substrate”) on which the photoelectric conversion semiconductor layer 23 (see FIGS. 1 and 2) is formed. Apply.
  • the resist R is exposed to form an opening O having a diameter of ⁇ 3 ⁇ m.
  • a resist is selected so that the upper part of the opening O is narrower than the lower part.
  • the counter pixel electrode 33 is deposited on the bottom surface in O, and the others are not deposited on the bottom surface in the opening O, and most of them are attached to the inner wall of the opening O to form side walls.
  • the cylindrical electrode of the side wall is formed on the counter pixel electrode 33 so as to adhere to the inner wall of the opening O.
  • this cylindrical electrode is referred to as a “wall bump electrode”.
  • an Au layer M is formed on the resist R as shown in FIG.
  • the shape of the wall bump electrode 34 shown in FIG. For example, when the shape of the opening O is substantially cylindrical, the wall bump electrode 34 is also substantially cylindrical, and when the shape of the opening O is substantially rectangular, the wall bump electrode 34 is also substantially rectangular. It becomes.
  • the shapes of the opening O and the wall bump electrode 34 are not particularly limited.
  • the shape of the opening O is directed inward so that the diameter of the side connected to the pixel electrode 11 (upper side in the figure) gradually decreases with respect to the diameter of the counter pixel electrode 33 side (lower side in the figure). It is curved. That is, the opening O is narrower on the upper side than on the lower side. Therefore, the wall bump electrode 34 is formed in a cylindrical shape curved inward so that the inner diameter and outer diameter on the side connected to the pixel electrode 11 gradually decrease with respect to the inner diameter and outer diameter on the counter pixel electrode 33 side. Is done.
  • a radiation detector having a structure as shown in FIG. 4D is formed. That is, the counter pixel electrode 33 and the wall bump electrode 34 are integrally formed of Au which is the same material. As shown in FIG. 1, the pixel electrode 11 of the signal readout substrate 1 and the photoelectric conversion semiconductor layer 23 of the counter substrate 2 are bonded to each other so that the pixel electrode 11 of the signal readout substrate 1 as shown in FIG. 1 is bonded. Thus, a radiation detector having a structure in which the wall bump electrode 34 of the counter substrate 2 is mechanically and electrically connected to each other is formed.
  • both electrodes are applied by applying pressure, heat, or ultrasonic energy to at least one of the pixel electrode 11 and the wall bump electrode 34. 11 and 34 are joined together and mechanically and electrically connected.
  • the wall bump electrode 34 is slightly crushed inward on the side in contact with the pixel electrode 11, so that the inner wall of the cylinder is on the inner side. It becomes the structure bent in.
  • the wall bump electrodes 34 as shown in FIG. 4D can be formed uniformly. Further, the height of the wall bump electrode 34 is substantially determined by the resist thickness.
  • FIG. 5 shows a scanning electron microscope (SEM: Scanning Electron Microscope) photograph in which an Au wall bump electrode having a pitch of 20 ⁇ m, an opening diameter of 3 ⁇ m, and a height of 3 ⁇ m is actually formed.
  • 5A is a plane SEM having a magnification of 500 times
  • FIG. 5B is a plane SEM having a magnification of 4000 times
  • FIG. 5C is a cross-sectional SEM having a magnification of 7000 times.
  • the wall bump electrode is formed with good reproducibility, and as described above, the height of the wall bump electrode is almost determined by the resist thickness. In the case of FIG. 5, the height variation is about 0.2 ⁇ m. It is.
  • Examples of the material of the wall bump electrode including the counter pixel electrode include Cu, Al, Ni and the like as described above in addition to Au described in FIG.
  • a relatively soft semiconductor such as CdTe, In, Pb, Zn, etc. as described above can be used as soft bump materials.
  • the aspect ratio t / d preferably satisfies the condition of t / d ⁇ 1/2.
  • the resist thickness ( ⁇ bump height) t is low, or the bump diameter d is large, and it is difficult to maintain the shape of the wall bump electrode. Accordingly, if the condition of t / d ⁇ 1/2 is satisfied, the higher t / d is more preferable. However, if t / d is too high, the wall bump electrode is not formed on the counter pixel electrode, or the counter pixel electrode itself is not formed.
  • the resist thickness ( ⁇ bump height) t is not too high.
  • the above range is more preferable. Note that if the condition of t / d ⁇ 1/2 is satisfied, the specific range of a suitable resist thickness ( ⁇ bump height) t varies depending on the size of the bump diameter d.
  • the wall bump electrode 34 is cylindrical, so that the bonding area is smaller than that of the conventional bump-shaped bump electrode, so that the semiconductor chip or the substrate In this embodiment, the pressure applied to the signal readout substrate 1 can be reduced. Further, since the bonding area is reduced, the diameter of the electrode can be formed with good reproducibility, and the connection can be reliably performed.
  • the side of the wall bump electrode 34 that is in contact with the pixel electrode 11 is slightly crushed inward, so that the contact can be made more reliably.
  • the counter pixel electrode 33 and the wall bump electrode 34 are integrally formed of the same material. In this case, the manufacturing process can be simplified, and a reliable electrical connection can be maintained without a problem of peeling between the counter pixel electrode 33 and the wall bump electrode 34.
  • the radiation detector according to the present embodiment has the structure shown in FIG. 1 described above, and one of the semiconductor chips or the substrate (the counter substrate 2 in the present embodiment) detects and detects the radiation.
  • the obtained signal is structured so as to be taken out from one of the other semiconductor chips or the substrate (in this embodiment, the signal reading substrate 1).
  • the pixel electrode 11, the counter pixel electrode 33, and the wall bump electrode 34 are arranged one-dimensionally or two-dimensionally (two-dimensional in this embodiment) so that the pixel pitch is less than 50 ⁇ m (in this embodiment, 20 ⁇ m).
  • one counter pixel electrode 33 and a wall bump electrode 34 are formed in one pixel electrode.
  • the manufacturing method of the radiation detector in the process of FIG. 4 corresponding to the cylindrical electrode forming process, it is formed on one semiconductor chip or the substrate (in this embodiment, the signal readout substrate 1).
  • a plurality of pixel electrodes 11 are formed on one semiconductor chip or substrate (signal reading substrate 1 in the present embodiment).
  • the electrode contact step the pixel electrode 11 formed on one semiconductor chip or substrate (signal readout substrate 1) and the wall bump electrode 34 formed on the other semiconductor chip or substrate (counter substrate 2 in this embodiment).
  • the electrodes (electrodes 11 and 34 in this embodiment) of both semiconductor chips or substrates (substrates 1 and 2 in this embodiment) are aligned and bonded together.
  • the electrode joining step by applying pressure, heat or ultrasonic energy to at least one of the pixel electrode 11 and the wall bump electrode 34, both the electrodes 11 and 34 are joined to each other and mechanical / electrical. Connect.
  • the present invention is not limited to the above embodiment, and can be modified as follows.
  • the semiconductor detector is used as a radiation detector, but may be used as a photodetector for detecting light.
  • one of the semiconductor chips or the substrate detects light and is applied to a photodetector having a structure in which a signal obtained by the detection is extracted from the other semiconductor chip or substrate.
  • the semiconductor device is used for a radiation detector, but it is not necessarily used for a semiconductor detector such as a radiation detector or a photodetector.
  • a semiconductor detector such as a radiation detector or a photodetector.
  • applications other than semiconductor detectors such as the above-described flip chip bonding may be used.
  • the target for forming the counter pixel electrode and the cylindrical electrode (wall bump electrode) is the substrate (the counter substrate 2 in the embodiment), and the target for forming the pixel electrode is the substrate (the embodiment).
  • a semiconductor chip may be used as a bonding target instead of the substrate.
  • one of the bonding targets may be a substrate and the other of the bonding targets may be a semiconductor chip.
  • the semiconductor chip is made of a compound semiconductor, and the material of the compound semiconductor includes CdTe, ZnTe, CdZnTe, GaAs, etc., as in the photoelectric conversion semiconductor layer of the above-described embodiment.
  • the semiconductor chip / substrate forming the counter pixel electrode and the cylindrical electrode detects radiation and light, and forms a pixel electrode from the detected signal. Although it was taken out from the semiconductor chip / substrate, it may be reversed. In other words, the semiconductor chip / substrate forming the pixel electrode detects radiation and light, and signals detected are taken out from the semiconductor chip / substrate forming the counter pixel electrode and the cylindrical electrode (wall bump electrode). Also good.
  • the pixel electrode, the counter pixel electrode, and the cylindrical electrode (wall bump electrode) are two-dimensionally arranged so that the pixel pitch is less than 50 ⁇ m (in the embodiment, 20 ⁇ m).
  • the present invention can also be applied to a semiconductor device having a structure in which a pixel electrode, a counter pixel electrode, and a cylindrical electrode (wall bump electrode) are arranged one-dimensionally.
  • one counter pixel electrode and a cylindrical electrode are formed in one pixel electrode.
  • a plurality of pixels are provided in one pixel electrode.
  • the counter pixel electrode and the cylindrical electrode (wall bump electrode) may be formed. That is, a plurality of second electrodes (opposite pixel electrode 33 in the embodiment) and cylindrical electrodes (wall bump electrodes) are formed in association with one first electrode (pixel electrode 11 in the embodiment).
  • An example in which three opposing pixel electrodes and wall bump electrodes are formed in one pixel electrode is shown in the schematic plan view of FIG.
  • the counter pixel electrode and the cylindrical electrode are formed by sputtering vapor deposition, but the wall bump electrode may be formed by vapor deposition other than sputtering vapor deposition.
  • the wall bump electrode may be formed by vapor deposition other than sputtering vapor deposition.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Measurement Of Radiation (AREA)
  • Wire Bonding (AREA)

Abstract

　放射線検出器の製造方法では、信号読出し基板に形成された複数の画素電極に対向した位置に、対向基板２に対向画素電極３３を形成し、さらにその上にウォールバンプ電極３４を形成する。そのために、レジストＲを塗布して、レジストＲに露光して開口部Ｏを形成する。開口部ＯにＡｕのスパッタ蒸着を行うと、Ａｕの一部のみが開口部Ｏ内の底面に対向画素電極３３として堆積され、それ以外は開口部Ｏ内の底面に堆積されず、ほとんどが開口部Ｏの内壁に付着してウォールバンプ電極３４が形成される。ウォールバンプ電極３４が筒状であるので、従来のバンプ形状のバンプ電極と比べて接合面積が小さくなる分、信号読出し基板にかける圧力を下げることができる。また、接合面積が小さくなる分、電極の径も再現性よく形成することができ、接続を確実に行うことができる。

Description

半導体装置、半導体検出器並びにそれらの製造方法、半導体チップまたは基板
　この発明は、医療分野、工業分野、さらには原子力分野等に用いられる半導体装置、半導体検出器並びにそれらの製造方法、半導体チップまたは基板に関する。
　半導体チップの電極と信号読出し基板上の電極とを向かい合わせにして、導電性バンプ（バンプ電極）を介して両者を電気的に接続する、いわゆる「フリップチップボンディング」は図７のような構造である。この構造は、信号読出し基板１０１、半導体チップ１０２、画素電極１０３、導電性バンプ１０４、および絶縁層１０５を含む。
　信号読出し基板１０１は、例えば画素電極１０３を２次元マトリックス状に配置したＣＭＯＳ集積回路等の信号読出し基板である。なお、半導体チップの替わりに対向基板などに代表される基板を用いてもよい。画素電極１０３は信号読出し基板１０１に形成されている。導電性バンプ１０４は、画素電極１０３に対向した位置に対向画素電極として半導体チップ１０２に形成されている。
　図７に示すフリップチップボンディングは光検出器や放射線検出器に用いられ、光や放射線を検出し、検出されて得られた信号を取り出す。なお、フリップチップボンディングは、はんだバンプや金バンプなどを用いた金属接合方式の他に、有機材料を用いた接合である導電性樹脂接合や、異方性導電部材接合などの接着接合方式もある。フリップチップボンディング以外に、接合の対象として基板を両方用いる場合にも適用することができる（例えば、特許文献１参照）。
国際公開第ＷＯ２０１４／００６８１２号
　しかしながら、従来のフリップチップ接続の場合には、以下のような問題点がある。すなわち、（画素ピッチに一致する）電極のピッチが５０μｍ以上であれば問題なく接続可能であるが、当該ピッチが２０μｍ以下になるとバンプサイズも微細となり、均一なバンプを形成して接続するのが困難になってくるという問題がある。
　この発明は、このような事情に鑑みてなされたものであって、接続を確実に行うことができる半導体装置、半導体検出器並びにそれらの製造方法、半導体チップまたは基板を提供することを目的とする。
　この発明は、このような目的を達成するために、次のような構成をとる。
　本発明の好ましい実施形態による半導体装置は、一方の半導体チップまたは基板に第１の電極が形成され、他方の半導体チップまたは基板に前記第１の電極に対向する位置に第２の電極、および前記第２の電極の上に筒状電極が形成され、前記一方の半導体チップまたは基板の前記第１の電極と、前記他方の半導体チップまたは基板の前記筒状電極とが互いに機械的・電気的に接続されるよう構造されている。
　筒状電極が筒状であるので、従来のバンプ形状のバンプ電極と比べて接合面積が小さくなる分、半導体チップまたは基板にかける圧力を下げることができる。また、接合面積が小さくなる分、電極の径も再現性よく形成することができ、接続を確実に行うことができる。
　好ましい実施形態においては、前記筒状電極は、前記第１の電極に接続される側の内径および外径が、前記第２の電極側の内径および外径に対して漸減するように内側に向けて湾曲した筒状である。第１の電極と筒状電極とが接続される際に、筒状電極の第１の電極に接続される側が内側に向けて若干押しつぶされるので、より確実に接触させることができる。
　好ましい実施形態においては、前記第２の電極および前記筒状電極が同一材料により一体形成されている。この場合、製造工程を簡素化することができるとともに、第２の電極と筒状電極との剥離の問題もなく、確実な電気的接続を維持することができる。
　好ましい実施形態において、１つの前記第１の電極に対応付けて、複数の前記第２の電極および前記筒状電極が形成される。
　好ましい実施形態においては、前記筒状電極の高さをｔ、前記筒状電極の径をｄとしたとき、ｔ／ｄ≧１／２の条件を満足する。この構成により、確実に筒状電極が形成され得る。
　本発明の好ましい実施形態による半導体検出器は、上述した半導体装置の構造を有し、いずれか一方の前記半導体チップまたは基板が、光または放射線を検出し、検出されて得られた信号を、いずれか他方の前記半導体チップまたは基板から取り出すよう構造されている。
　本発明の好ましい実施形態による半導体装置の製造方法は、一方の半導体チップまたは基板に形成された第１の電極に対向する位置に、他方の半導体チップまたは基板に第２の電極を形成する工程と、前記第２の電極の上に筒状電極を形成する工程とを含む筒状電極形成工程を備えるものである。
　好ましい実施形態においては、前記第２の電極を形成する工程および前記筒状電極を形成する工程は、レジストを塗布する工程と、前記レジストに露光して開口部を形成する工程と、前記開口部に蒸着を行うことにより、前記開口部の底面に前記第２の電極となる部分が堆積され、前記開口部の内壁に前記筒状電極となる部分が堆積される工程と、前記レジストを除去する工程とを含む。
　好ましい実施形態においては、前記開口部が、前記第１の電極に接続される側の径が、前記第２の電極側の径に対して漸減するように内側に向けて湾曲している。
　好ましい実施形態においては、前記一方の半導体チップまたは基板に前記第１の電極を形成する工程と、前記一方の半導体チップまたは基板に形成された前記第１の電極と、前記他方の半導体チップまたは基板に形成された前記筒状電極とが互いに接触するように、両方の前記半導体チップまたは基板の各電極の位置合わせを行って貼り合わせる電極接触工程と、前記第１の電極および前記筒状電極の少なくとも一方に、圧力、熱または超音波のエネルギーを加えることにより、両方の電極を互いに接合して機械的・電気的に接続する電極接合工程とを備える。
　好ましい実施形態においては、前記蒸着がスパッタ蒸着である。
　この発明に係る半導体装置、半導体検出器並びにそれらの製造方法、半導体チップまたは基板によれば、筒状電極が筒状であるので、接合面積が小さくなる分、電極の径も再現性よく形成することができ、接続を確実に行うことができる。
実施例に係る半導体検出器（放射線検出器）の概略断面図である。 実施例に係る半導体検出器（放射線検出器）の信号読出し基板および対向基板の具体的な構成を示した概略断面図である。 実施例に係る半導体検出器（放射線検出器）の信号読出し基板の単位画素当たりの等価回路である。 実施例に係る対向画素電極およびウォールバンプ電極を形成する工程を示した概略断面図である。 Ａｕ（金）のウォールバンプ電極を形成した走査型電子顕微鏡（ＳＥＭ）写真であり、（ａ）は倍率が５００倍の平面ＳＥＭ、（ｂ）は倍率が４０００倍の平面ＳＥＭ、（ｃ）は倍率が７０００倍の断面ＳＥＭである。 １つの画素電極内に３つのウォールバンプ電極を形成した例の概略平面図である。 フリップチップ接続構造の概略図である。
　以下、図面を参照してこの発明の実施例を説明する。図１は、実施例に係る半導体検出器（放射線検出器）の概略断面図であり、図２は、実施例に係る半導体検出器（放射線検出器）の信号読出し基板および対向基板の具体的な構成を示した概略断面図であり、図３は、実施例に係る半導体検出器（放射線検出器）の信号読出し基板の単位画素当たりの等価回路である。本実施例では、半導体検出器は、放射線検出器として用いられる。なお、図２では対向画素電極およびウォールバンプ電極の図示を省略する。
　放射線検出器は、図１～図３に示すように、信号読出し基板１と、信号読出し基板１に対向配置した対向基板２とを備えている。信号読出し基板１は、２次元マトリックス状に配置された各々の画素電極１１（第１の電極に相当）およびそれらを配列する画素配列層を含んで構成されている。一方、対向基板２は、共通電極２１，光電変換半導体層２３の順に積層形成されて構成されている。対向基板２の光電変換半導体層２３側の面が画素毎に信号読出し基板１の画素電極１１毎に電気的に接続されている。具体的には、後述するスパッタ蒸着によって形成された対向画素電極３３（第２の電極に相当）およびウォールバンプ電極３４（筒状電極に相当）により信号読出し基板１の画素電極１１と対向基板２の光電変換半導体層２３とを互いに対向させて貼り合わせる。
　信号読出し基板１はガラス基板で形成されている。信号読出し基板１には、上述の画素電極１１の他に、画素容量１２，スイッチングトランジスタ１３が２次元マトリックス状に形成され、走査線１４（図３を参照）および信号読出線１５（図３を参照）が行および列方向にそれぞれ縦横にパターン形成されている。
　具体的には、図２に示すように、信号読出し基板１上に画素容量１２の基準電極１２ａおよびスイッチングトランジスタ１３のゲート電極１３ａが積層形成され層間絶縁膜３１で覆われている。その層間絶縁膜３１に、画素容量１２の容量電極１２ｂが、層間絶縁膜３１を介在させて基準電極１２ａに対向するように積層形成され、スイッチングトランジスタ１３のソース電極１３ｂおよびドレイン電極１３ｃが積層形成され、画素電極１１が存在する部分を除いて封止材料３２で覆われている。なお、容量電極１２ｂとソース電極１３ｂとは相互に電気的に接続される。図２に示すように、容量電極１２ｂおよびソース電極１３ｂを一体的に同時形成すればよい。基準電極１３ａは接地されている。層間絶縁膜３１には、例えばプラズマＳｉＮが使用される。
　図３に示すように、走査線１４は、スイッチングトランジスタ１３のゲート電極１３ａ（図２を参照）に電気的に接続され、信号読出線１５は、スイッチングトランジスタ１３のドレイン電極１３ｃ（図２を参照）に電気的に接続されている。走査線１４は、各々の画素の行方向にそれぞれ延びており、信号読出線１５は、各々の画素の列方向にそれぞれ延びている。走査線１４および信号読出線１５は互いに直交している。図３の符号２３は、光電変換半導体層の等価回路である。これら走査線１４や信号読出線１５を含めて、画素容量１２、スイッチングトランジスタ１３および層間絶縁膜３１は、半導体薄膜製造技術や微細加工技術を用いて信号読出し基板１の表面に画素配列層としてパターン形成されている。
　光電変換半導体層２３は、ＣｄＴｅ（テルル化カドミウム），ＺｎＴｅ（テルル化亜鉛），ＣｄＺｎＴｅ（テルル化カドミウム亜鉛），ＧａＡｓ（ガリウムヒ素）等で形成される。
　上述したように、信号読出し基板１の画素電極１１と対向基板２の光電変換半導体層２３とは、互いに対向させて貼り合わされる。層間絶縁膜３１で覆われていない箇所の画素電極１１に、Ａｕ（金），Ｃｕ（銅），Ａｌ（アルミニウム），Ｎｉ（ニッケル），Ｉｎ（インジウム），Ｐｂ（鉛），Ｚｎ（亜鉛）のいずれかを含んだ材料をスパッタ蒸着することにより形成された対向画素電極３３およびウォールバンプ電極３４を接続することにより、信号読出し基板１の画素電極１１と対向基板２の光電変換半導体層２３とを互いに対向させて貼り合わせる。
　放射線検出器の動作を、図１～図３を参照して説明する。共通電極２１にバイアス電圧を印加した状態で、放射線（例えばＸ線）が入射することにより光電変換半導体層２３で電子－正孔対キャリアが生成され、画素容量１２に一旦蓄積される。必要なタイミングで走査線１４を駆動させることで、当該走査線１４に接続されたスイッチングトランジスタ１３がＯＮ状態に移行し、画素容量１２に蓄積された電子－正孔対キャリアが信号電荷として読み出され、スイッチングトランジスタ１３に接続された信号読出線１５を介して後段の信号収集回路（図示省略）に読み出される。
　各々の画素電極１１は各々の画素にそれぞれ対応しているので、画素電極１１に対応して読み出された信号電荷を画素値に変換することで、画素に応じた画素値を２次元に並べて２次元画像（２次元分布を有した放射線画像）を取得することができる。
　放射線検出器の製造方法について、図４を参照して説明する。図４は、実施例に係る対向画素電極およびウォールバンプ電極を形成する工程を示した概略断面図である。なお、図４では光電変換半導体層の図示を省略する。
　例えば、直径：φ３μｍ、高さ：３μｍのＡｕ（金）のウォールバンプ電極を形成する場合の工程を図４に示す。図４（ａ）に示すように、光電変換半導体層２３（図１および図２を参照）が形成された共通電極２１（以下、「支持基板」と総称する）に厚みが３μｍのレジストＲを塗布する。そして、図４（ｂ）に示すようにレジストＲに露光して、直径：φ３μｍの開口部Ｏを形成する。このとき、開口部Ｏの上部が下部よりも狭まるようなレジストを選択する。
　スパッタリングのＡｕソースとレジストＲとが近接しているので、図４（ｂ）の開口部ＯにＡｕのスパッタ蒸着を行うと、図４（ｃ）に示すようにＡｕの一部のみが開口部Ｏ内の底面に対向画素電極３３として堆積され、それ以外は開口部Ｏ内の底面に堆積されず、ほとんどが開口部Ｏの内壁に付着してサイドウォール（側壁）となる。このように、対向画素電極３３の上に開口部Ｏの内壁に付着してサイドウォールの筒状電極が形成される。以下、この筒状電極を「ウォールバンプ電極」と呼ぶ。なお、開口部Ｏ以外では、図４（ｃ）に示すようにＡｕの層ＭがレジストＲ上に形成される。
　開口部Ｏの形状にしたがって、図４（ｃ）に示すウォールバンプ電極３４の形状が決定される。例えば、開口部Ｏの形状が略円筒状の場合には、ウォールバンプ電極３４も略円筒形状となり、開口部Ｏの形状が略角筒状の場合には、ウォールバンプ電極３４も略角筒形状となる。開口部Ｏやウォールバンプ電極３４の形状は、特に限定されない。本実施例では、開口部Ｏの形状は、画素電極１１に接続される側（図示上側）の径が対向画素電極３３側（図示下側）の径に対して漸減するように内側に向けて湾曲している。つまり、開口部Ｏは、上側が下側よりも狭くなっている。したがって、ウォールバンプ電極３４は、画素電極１１に接続される側の内径および外径が、対向画素電極３３側の内径および外径に対して漸減するように内側に向けて湾曲した筒状に形成される。
　続いて、図４（ｃ）のＡｕの層ＭやレジストＲを除去することにより、図４（ｄ）に示すような構造の放射線検出器が形成される。すなわち、対向画素電極３３およびウォールバンプ電極３４が同一材料であるＡｕによって一体的に形成される。図１に示すように、信号読出し基板１の画素電極１１と対向基板２の光電変換半導体層２３とを互いに対向させて貼り合わせることにより、図１に示すような信号読出し基板１の画素電極１１と、対向基板２のウォールバンプ電極３４とが互いに機械的・電気的に接続された構造の放射線検出器が形成される。
　なお、両方の基板１，２を互いに対向させて貼り合わせる際には、画素電極１１，ウォールバンプ電極３４のいずれか少なくとも一方に、圧力，熱または超音波のエネルギーを加えることにより、両方の電極１１，３４を互いに接合して機械的・電気的に接続する。両方の基板１，２を互いに対向させて貼り合わせることにより、図１に示すように、ウォールバンプ電極３４は、画素電極１１に接触する側が内側に向けて若干押しつぶされるので、筒の内壁が内側に折り曲げられた構造となる。
　仮にサイドウォールではなく、開口部に通常のバンプを形成するには、スパッタ蒸着ではなく、（基板とソースとの間の距離を長くして成膜速度が遅い）ロングスローの蒸着装置を使用しなければならず、蒸着の効率が格段に下がる。スパッタ蒸着以外の通常の蒸着法では、ソースは基板の中央に設置され、基板とソースとを近接させて蒸着を行うと指向性が強く、端部において斜めに堆積される、あるいは堆積されない箇所が存在するからである。したがって、指向性を弱め通常のバンプを一様に形成するには、ロングスローの蒸着装置を採用しなければならなくなる。また、バンプの高さのバラツキも生じやすくなる。
　これに対して、スパッタ蒸着を採用することにより、図４（ｄ）に示すようなウォールバンプ電極３４を一様に形成することができる。また、ウォールバンプ電極３４の高さは、レジスト厚でほぼ決定される。
　実際に、ピッチ：２０μｍ、開口径：３μｍ、高さ：３μｍのＡｕのウォールバンプ電極を形成した走査型電子顕微鏡(SEM: Scanning Electron Microscope) 写真を図５に示す。図５（ａ）は、倍率が５００倍の平面ＳＥＭであり、図５（ｂ）は、倍率が４０００倍の平面ＳＥＭであり、図５（ｃ）は、倍率が７０００倍の断面ＳＥＭである。図５に示すように、ウォールバンプ電極が再現性よく形成され、上述したようにウォールバンプ電極の高さはレジスト厚でほぼ決まるので、図５の場合には高さのバラツキは０．２μｍ程度である。
　対向画素電極を含んだウォールバンプ電極の材料として、図５で述べたＡｕの他に、上述したようなＣｕ，Ａｌ，Ｎｉ等が挙げられる。また、ＣｄＴｅ等のように比較的軟らかい半導体を接続するには、軟らかいバンプ材料として、上述したようなＩｎ，Ｐｂ，Ｚｎ等も使用することができる。また、これらの混合物でウォールバンプ電極を形成してもよい。
　実際に、機械的・電気的に接合させるには、上述したように圧力や熱や超音波のエネルギーを加えて接合する。通常の柱状バンプに比べて接合面積は小さくなるが、その分、接合の際にかける全体の圧力を下げることができる。
　レジスト厚（≒バンプ高さ）をｔとし、バンプの直径（バンプ径）をｄとしたとき、アスペクト比ｔ／ｄはｔ／ｄ≧１／２の条件を満足するのが好ましい。ｔ／ｄ＜１／２の場合には、レジスト厚（≒バンプ高さ）ｔが低く、あるいはバンプ径ｄが大きくなり、ウォールバンプ電極の形状を維持するのが難しくなる。したがって、ｔ／ｄ≧１／２の条件を満足するならばｔ／ｄは高ければ高いほどより好ましい。ただし、ｔ／ｄが高過ぎると、ウォールバンプ電極が対向画素電極の上に形成されなくなる、あるいは対向画素電極そのものが形成されなくなる。よって、レジスト厚（≒バンプ高さ）ｔは高過ぎず、例えばバンプ径ｄが３μｍの場合には、通常、レジスト厚（≒バンプ高さ）ｔは３μｍ以下で１．５μｍ（＝ｄ／２）以上の範囲がより好ましい。なお、ｔ／ｄ≧１／２の条件を満足するならば、バンプ径ｄの大きさに応じて好適なレジスト厚（≒バンプ高さ）ｔの具体的な範囲は変わることに留意されたい。
　上述の構成を備えた本実施例に係る放射線検出器によれば、ウォールバンプ電極３４が筒状であるので、従来のバンプ形状のバンプ電極と比べて接合面積が小さくなる分、半導体チップまたは基板（本実施例では信号読出し基板１）にかける圧力を下げることができる。また、接合面積が小さくなる分、電極の径も再現性よく形成することができ、接続を確実に行うことができる。
　画素電極１１とウォールバンプ電極３４とが接続される際に、ウォールバンプ電極３４は、画素電極１１に接触する側が内側に向けて若干押しつぶされるので、より確実に接触させることができる。また、対向画素電極３３およびウォールバンプ電極３４が同一材料により一体形成されている。この場合、製造工程を簡素化することができるとともに、対向画素電極３３とウォールバンプ電極３４との剥離の問題もなく、確実な電気的接続を維持することができる。
　また、本実施例に係る放射線検出器は、上述した図１の構造を有し、いずれか一方の半導体チップまたは基板（本実施例では対向基板２）が、放射線を検出し、検出されて得られた信号を、いずれか他方の半導体チップまたは基板（本実施例では信号読出し基板１）から取り出すよう構造されている。
　画素ピッチが５０μｍ未満（本実施例では２０μｍ）になるように、画素電極１１，対向画素電極３３およびウォールバンプ電極３４が１次元もしくは２次元（本実施例では２次元）に配置されている。本実施例では、１つの画素電極内に１つの対向画素電極３３およびウォールバンプ電極３４が形成されている。
　また、本実施例に係る放射線検出器の製造方法によれば、筒状電極形成工程に相当する図４の工程では、一方の半導体チップまたは基板（本実施例では信号読出し基板１）に形成された複数の画素電極１１に対向する位置に、他方の半導体チップまたは基板（本実施例では対向基板２）に対向画素電極３３を形成する工程と、対向画素電極３３の上にウォールバンプ電極３４を形成する工程とを含む。
　本実施例に係る放射線検出器の製造方法では、第１の電極を形成する工程では、一方の半導体チップまたは基板（本実施例では信号読出し基板１）に複数の画素電極１１を形成する。そして、電極接触工程では、一方の半導体チップまたは基板（信号読出し基板１）に形成された画素電極１１、他方の半導体チップまたは基板（本実施例では対向基板２）に形成されたウォールバンプ電極３４が互いに接触するように、両方の半導体チップまたは基板（本実施例では基板１，２）の各電極（本実施例では電極１１，３４）の位置合わせを行って貼り合わせる。さらに、電極接合工程では、画素電極１１，ウォールバンプ電極３４のいずれか少なくとも一方に、圧力，熱または超音波のエネルギーを加えることにより、両方の電極１１，３４を互いに接合して機械的・電気的に接続する。
　この発明は、上記実施形態に限られることはなく、下記のように変形実施することができる。
　（１）上述した実施例では、半導体検出器は、放射線検出器として用いられていたが、光を検出する光検出器として用いられてもよい。具体的には、いずれか一方の半導体チップまたは基板が、光を検出し、検出されて得られた信号を、いずれか他方の半導体チップまたは基板から取り出す構造の光検出器に適用する。
　（２）上述した実施例では、半導体装置は放射線検出器に用いられていたが、必ずしも放射線検出器や光検出器などの半導体検出器に用いられる必要はない。例えば、上述したフリップチップボンディングのように半導体検出器以外の用途でもよい。
　（３）上述した実施例では、対向画素電極や筒状電極（ウォールバンプ電極）を形成する対象は基板（実施例では対向基板２）であるとともに、画素電極を形成する対象は基板（実施例では信号読出し基板１）であったが、接合の対象として基板の替わりに半導体チップを用いてもよい。例えば、上述したフリップチップボンディングのように、接合の対象の一方を基板として、接合の対象の他方を半導体チップとしてもよい。また、接合の対象として半導体チップを両方用いてもよい。半導体チップは化合物半導体で構成し、上述した実施例の光電変換半導体層と同様に、化合物半導体の材料として、ＣｄＴｅ，ＺｎＴｅ，ＣｄＺｎＴｅ，ＧａＡｓ等が挙げられる。
　（４）上述した実施例では、対向画素電極や筒状電極（ウォールバンプ電極）を形成する半導体チップ／基板が放射線や光を検出し、検出されて得られた信号を、画素電極を形成する半導体チップ／基板から取り出したが、逆でもよい。つまり、画素電極を形成する半導体チップ／基板が放射線や光を検出し、検出されて得られた信号を、対向画素電極や筒状電極（ウォールバンプ電極）を形成する半導体チップ／基板から取り出してもよい。
　（５）上述した実施例では、画素ピッチが５０μｍ未満（実施例では２０μｍ）になるように、画素電極，対向画素電極および筒状電極（ウォールバンプ電極）が２次元に配置されていたが、画素電極，対向画素電極および筒状電極（ウォールバンプ電極）が１次元に配置された構造の半導体装置にも適用することができる。
　（６）上述した実施例では、１つの画素電極内に１つの対向画素電極および筒状電極（ウォールバンプ電極）が形成されていたが、接合面積を大きくするために１つの画素電極内に複数の対向画素電極および筒状電極（ウォールバンプ電極）を形成してもよい。つまり、１つの第１の電極（実施例では画素電極１１）に対応付けて、複数の第２の電極（実施例では対向画素電極３３）および筒状電極（ウォールバンプ電極）が形成される。１つの画素電極内に３つの対向画素電極およびウォールバンプ電極を形成した例を図６の概略平面図に示す。
　（７）上述した実施例では、スパッタ蒸着によって対向画素電極および筒状電極（ウォールバンプ電極）を形成したが、スパッタ蒸着以外の蒸着でもウォールバンプ電極を形成してもよい。ソースを基板の中央に設置すると、基板とソースとを近接させて蒸着を行えば、上述したように端部において斜めに堆積される、あるいは堆積されない箇所が存在する恐れがある。そこで、ソースを基板の全面にわたって設置して、基板とソースとを近接させて蒸着を行えば、指向性を弱め、かつ成膜速度が速い状態で、スパッタ蒸着以外の蒸着でもウォールバンプ電極を一様に形成することが可能である。
　１　…　信号読出し基板
　１１　…　画素電極
　２　…　対向基板
　３３　…　対向画素電極
　３４　…　ウォールバンプ電極

Claims (12)

  1. 　一方の半導体チップまたは基板に第１の電極が形成され、
    　他方の半導体チップまたは基板に前記第１の電極に対向する位置に第２の電極、および前記第２の電極の上に筒状電極が形成され、
    　前記一方の半導体チップまたは基板の前記第１の電極と、前記他方の半導体チップまたは基板の前記筒状電極とが互いに機械的・電気的に接続されるよう構造されている、半導体装置。
  2. 　請求項１に記載の半導体装置において、
    　前記筒状電極は、前記第１の電極に接続される側の内径および外径が、前記第２の電極側の内径および外径に対して漸減するように内側に向けて湾曲した筒状である、半導体装置。
  3. 　請求項１に記載の半導体装置において、
    　前記第２の電極および前記筒状電極が同一材料により一体形成されている、半導体装置。
  4. 　請求項１に記載の半導体装置において、
    　１つの前記第１の電極に対応付けて、複数の前記第２の電極および前記筒状電極が形成される、半導体装置。
  5. 　請求項１に記載の半導体装置において、
    　前記筒状電極の高さをｔ、前記筒状電極の径をｄとしたとき、ｔ／ｄ≧１／２の条件を満足する、半導体装置。
  6. 　請求項１から請求項５のいずれかに記載の半導体装置の構造を有し、
    　いずれか一方の前記半導体チップまたは基板が、光または放射線を検出し、検出されて得られた信号を、いずれか他方の前記半導体チップまたは基板から取り出すよう構造されている、半導体検出器。
  7. 　一方の半導体チップまたは基板に形成された第１の電極に対向する位置に、他方の半導体チップまたは基板に第２の電極を形成する工程と、前記第２の電極の上に筒状電極を形成する工程とを含む筒状電極形成工程
    　を備える、半導体装置の製造方法。
  8. 　請求項７に記載の半導体装置の製造方法において、
    　前記第２の電極を形成する工程および前記筒状電極を形成する工程は、
    　レジストを塗布する工程と、
    　前記レジストに露光して開口部を形成する工程と、
    　前記開口部に蒸着を行うことにより、前記開口部の底面に前記第２の電極となる部分が堆積され、前記開口部の内壁に前記筒状電極となる部分が堆積される工程と、
    　前記レジストを除去する工程とを含む、半導体装置の製造方法。
  9. 　請求項８に記載の半導体装置の製造方法において、
    　前記開口部が、前記第１の電極に接続される側の径が、前記第２の電極側の径に対して漸減するように内側に向けて湾曲している、半導体装置の製造方法。
  10. 　請求項７に記載の半導体装置の製造方法において、
    　前記一方の半導体チップまたは基板に前記第１の電極を形成する工程と、
    　前記一方の半導体チップまたは基板に形成された前記第１の電極と、前記他方の半導体チップまたは基板に形成された前記筒状電極とが互いに接触するように、両方の前記半導体チップまたは基板の各電極の位置合わせを行って貼り合わせる電極接触工程と、
    　前記第１の電極および前記筒状電極の少なくとも一方に、圧力、熱または超音波のエネルギーを加えることにより、両方の電極を互いに接合して機械的・電気的に接続する電極接合工程と
    　を備える、半導体装置の製造方法。
  11. 　請求項８に記載の半導体装置の製造方法において、
    　前記蒸着がスパッタ蒸着である、半導体装置の製造方法。
  12. 　第１の電極が形成された他の半導体チップまたは基板に接続される、半導体チップまたは基板であって、
    　前記前記第１の電極に対向する位置に第２の電極が形成され、
    　前記第２の電極の上に筒状電極がさらに形成されており、
    　前記筒状電極が、前記第１の電極と機械的・電気的に接続されるよう構造されている、半導体チップまたは基板。
PCT/JP2015/081891 2015-11-12 2015-11-12 半導体装置、半導体検出器並びにそれらの製造方法、半導体チップまたは基板 WO2017081798A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US15/775,538 US10468365B2 (en) 2015-11-12 2015-11-12 Semiconductor device and semiconductor detector, methods for manufacturing same, and semiconductor chip or substrate
PCT/JP2015/081891 WO2017081798A1 (ja) 2015-11-12 2015-11-12 半導体装置、半導体検出器並びにそれらの製造方法、半導体チップまたは基板
JP2017549943A JP6430658B2 (ja) 2015-11-12 2015-11-12 半導体装置、半導体検出器並びにそれらの製造方法、半導体チップまたは基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2015/081891 WO2017081798A1 (ja) 2015-11-12 2015-11-12 半導体装置、半導体検出器並びにそれらの製造方法、半導体チップまたは基板

Publications (1)

Publication Number Publication Date
WO2017081798A1 true WO2017081798A1 (ja) 2017-05-18

Family

ID=58694864

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2015/081891 WO2017081798A1 (ja) 2015-11-12 2015-11-12 半導体装置、半導体検出器並びにそれらの製造方法、半導体チップまたは基板

Country Status (3)

Country Link
US (1) US10468365B2 (ja)
JP (1) JP6430658B2 (ja)
WO (1) WO2017081798A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10115695B1 (en) 2017-04-28 2018-10-30 Tohoku-Microtec Co., Ltd Solid-state imaging device
WO2020105432A1 (ja) * 2018-11-21 2020-05-28 東北マイクロテック株式会社 積層型半導体装置及びこれに用いる複数のチップ
EP3926673A1 (en) 2020-06-17 2021-12-22 Tohoku-Microtec Co., Ltd Semiconductor device with repair bumps with walls of a hard material biting into parent bumps with walls of a soft material

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI429066B (zh) * 2005-06-02 2014-03-01 Sony Corp Semiconductor image sensor module and manufacturing method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02271634A (ja) * 1989-04-13 1990-11-06 Sony Corp 多層配線形成方法およびこれに用いる真空蒸着装置
JPH11260848A (ja) * 1998-03-10 1999-09-24 Nippon Hoso Kyokai <Nhk> 電極形成方法
JP2003298012A (ja) * 2002-01-30 2003-10-17 Nippon Hoso Kyokai <Nhk> 半導体装置およびその製造方法
JP2005019429A (ja) * 2003-06-23 2005-01-20 Seiko Epson Corp 半導体チップの接続方法、半導体チップ
JP2008130992A (ja) * 2006-11-24 2008-06-05 Fujitsu Ltd 実装構造体とその製造方法および半導体装置とその製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130116643A (ko) * 2012-04-16 2013-10-24 에스케이하이닉스 주식회사 범프를 갖는 기판, 반도체칩, 및 반도체 패키지와, 그 제조방법
JP2015165185A (ja) 2012-07-04 2015-09-17 株式会社島津製作所 放射線二次元検出器
JP6456232B2 (ja) * 2015-04-30 2019-01-23 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02271634A (ja) * 1989-04-13 1990-11-06 Sony Corp 多層配線形成方法およびこれに用いる真空蒸着装置
JPH11260848A (ja) * 1998-03-10 1999-09-24 Nippon Hoso Kyokai <Nhk> 電極形成方法
JP2003298012A (ja) * 2002-01-30 2003-10-17 Nippon Hoso Kyokai <Nhk> 半導体装置およびその製造方法
JP2005019429A (ja) * 2003-06-23 2005-01-20 Seiko Epson Corp 半導体チップの接続方法、半導体チップ
JP2008130992A (ja) * 2006-11-24 2008-06-05 Fujitsu Ltd 実装構造体とその製造方法および半導体装置とその製造方法

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10115695B1 (en) 2017-04-28 2018-10-30 Tohoku-Microtec Co., Ltd Solid-state imaging device
EP3396715A1 (en) 2017-04-28 2018-10-31 Tohoku-microtec Co., Ltd. Solid-state imaging device
WO2020105432A1 (ja) * 2018-11-21 2020-05-28 東北マイクロテック株式会社 積層型半導体装置及びこれに用いる複数のチップ
JPWO2020105432A1 (ja) * 2018-11-21 2021-09-02 東北マイクロテック株式会社 積層型半導体装置及びこれに用いる複数のチップ
JP7097639B2 (ja) 2018-11-21 2022-07-08 東北マイクロテック株式会社 積層型半導体装置及びこれに用いる複数のチップ
US11495565B2 (en) 2018-11-21 2022-11-08 Tohoku-Microtec Co., Ltd. Stacked semiconductor device and multiple chips used therein
EP3926673A1 (en) 2020-06-17 2021-12-22 Tohoku-Microtec Co., Ltd Semiconductor device with repair bumps with walls of a hard material biting into parent bumps with walls of a soft material
US11462668B2 (en) 2020-06-17 2022-10-04 Tohoku-Microtec Co., Ltd. Stacked semiconductor device, and set of onboard-components, body and jointing-elements to be used in the stacked semiconductor device

Also Published As

Publication number Publication date
JP6430658B2 (ja) 2018-11-28
JPWO2017081798A1 (ja) 2018-08-30
US20180331060A1 (en) 2018-11-15
US10468365B2 (en) 2019-11-05

Similar Documents

Publication Publication Date Title
JP6430658B2 (ja) 半導体装置、半導体検出器並びにそれらの製造方法、半導体チップまたは基板
US6933505B2 (en) Low temperature, bump-bonded radiation imaging device
KR102626766B1 (ko) 이면 입사형 고체 촬상 소자
JP2001242255A (ja) 放射線検出器および放射線撮像装置
JP5798181B2 (ja) コリメータ結合構造及びコリメータ結合方法
US9279730B2 (en) Device having a membrane structure for detecting thermal radiation, and method for production thereof
CA2482279C (en) Radiation detector
JPH06350068A (ja) 半導体エネルギー線検出器の製造方法
US20200243586A1 (en) Image sensor and image-capturing device
JP2006504257A (ja) 半導体基板上における接点の形成
WO1998057376A1 (en) Interconnection technique for hybrid integrated devices
US8809923B2 (en) Backside illuminated imaging sensor having a carrier substrate and a redistribution layer
CN112385025B (zh) 层叠型半导体装置及用于其的多个芯片
JP3537401B2 (ja) 電磁波撮像装置およびその製造方法
JP2017157755A (ja) 光検出器及び光検出器の製造方法
JP2002303676A (ja) 放射線検出素子および放射線検出素子の製造方法
KR101486250B1 (ko) 이미지센서와 그 제조방법
US20090206265A1 (en) Electron Bombarded Image Sensor Array Device and Its Manufacturing Method
JP2017092419A (ja) 半導体検出器
JP6544440B2 (ja) 半導体検出器
US20240194707A1 (en) Enhanced area getter architecture for wafer-level vacuum packaged uncooled focal plane array
US20230176237A1 (en) X-ray imaging device
JP2014211383A (ja) 放射線検出器
EP4191675A1 (fr) Dispositif d&#39;imagerie a rayons x
TW202332027A (zh) 光感測裝置以及製造光感測裝置的方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15908318

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2017549943

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 15775538

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15908318

Country of ref document: EP

Kind code of ref document: A1