WO2017077729A1 - Module à semi-conducteur et son procédé de fabrication - Google Patents
Module à semi-conducteur et son procédé de fabrication Download PDFInfo
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- WO2017077729A1 WO2017077729A1 PCT/JP2016/066618 JP2016066618W WO2017077729A1 WO 2017077729 A1 WO2017077729 A1 WO 2017077729A1 JP 2016066618 W JP2016066618 W JP 2016066618W WO 2017077729 A1 WO2017077729 A1 WO 2017077729A1
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Definitions
- the present invention relates to a semiconductor module and a manufacturing method thereof, and more particularly to a power module and a manufacturing method thereof.
- a conventional power module includes a power semiconductor element and a substrate member.
- the electrode on the back surface of the power semiconductor element is bonded to the substrate member using a bonding member such as solder.
- the electrode on the surface of the power semiconductor element is bonded to a wiring member such as a wire. Thereby, wiring of a power semiconductor element is performed.
- the power semiconductor element generates heat.
- each member which comprises a power module differs in a linear expansion coefficient. Therefore, during operation of the power module, thermal stress is generated due to the heat generated by the power semiconductor element and the difference in the linear expansion coefficient of each member constituting the power module.
- a crack may occur at the joint between the power semiconductor element and the substrate member due to the thermal stress. When such a crack occurs, the thermal resistance directly under the power semiconductor element increases. As a result, the electrical characteristics of the power module deteriorate.
- Patent Document 1 and Patent Document 2 disclose a structure in which a joint portion between a power semiconductor element back electrode and a substrate member is divided into a plurality of portions. Such a structure can disperse the thermal stress generated at the joint between the power semiconductor element and the substrate member. As a result, the occurrence of cracks at the joint is suppressed.
- a load and ultrasonic vibration are applied in a state where the wiring member such as a wire is in contact with the electrode on the surface of the power semiconductor element.
- the application of the load and ultrasonic vibration may cause damage such as cracking in the power semiconductor element.
- the present invention has been made in view of such problems of the prior art. That is, the present invention relates to a semiconductor module that can reduce thermal stress generated at the junction between the back electrode of the semiconductor element and the substrate member, and suppress damage to the semiconductor element that occurs when the wiring member is bonded to the front electrode of the semiconductor element. It aims at providing the manufacturing method.
- the semiconductor module according to the present invention includes a substrate member, a semiconductor element having a surface electrode and a back electrode, an element bonding member for bonding the back electrode and the substrate member, and a wiring member bonded to the surface electrode. Between the back electrode and the substrate member, there is a bonding region where the gap region and the element bonding member are disposed, and the front electrode and the wiring member are bonded on the bonding region in a plan view.
- the semiconductor module of the present invention it is possible to reduce thermal stress generated at the joint between the back electrode of the semiconductor element and the substrate member and to suppress damage to the semiconductor element that occurs when the front electrode of the semiconductor element and the wiring member are joined. it can.
- FIG. 1A is a cross-sectional view illustrating an example of the structure of the power module according to the first embodiment.
- the power module according to the first embodiment mainly includes a power semiconductor element 1, a substrate member 2, an element bonding member 3, a heat radiating plate 4, a heat radiating plate bonding member 5, a case 6, and a wiring member 7. And a sealing member 8.
- the power semiconductor element 1 includes, for example, an insulated gate bipolar transistor (IGBT), a free wheel diode (FWD), a metal oxide semiconductor field effect transistor (MOSFET). Etc.
- IGBT insulated gate bipolar transistor
- FWD free wheel diode
- MOSFET metal oxide semiconductor field effect transistor
- Etc the type of the power semiconductor element 1 is not limited to these. 1A and 1B, the number of power semiconductor elements 1 is one, but the number of power semiconductor elements 1 may be plural.
- the power semiconductor element 1 has a front surface 1a and a back surface 1b.
- a surface electrode 11 is provided on the surface 1 a of the power semiconductor element 1.
- a back electrode 12 is provided on the back surface 1 b of the power semiconductor element 1.
- the surface electrode 11 is preferably provided on a bonding region 3a (see FIG. 2) of the element bonding member 3 described later in plan view.
- the substrate member 2 is, for example, a ceramic substrate.
- alumina (Aluminum Oxide) or aluminum nitride (Aluminum Nitride) is used as a material for the ceramic substrate.
- the material of the ceramic substrate is not limited to this.
- the substrate member 2 has a front surface 2a and a back surface 2b.
- a first circuit pattern 21 and a second circuit pattern 22 are provided on the surface 2 a of the substrate member 2.
- a metal pattern 23 is provided on the back surface 2 b of the substrate member 2.
- the material used for the first circuit pattern 21 and the second circuit pattern 22 is not limited to this.
- the material used for the first circuit pattern 21 and the second circuit pattern 22 may be any material that can be bonded to the substrate member 2 by a direct bonding method or an active metal bonding method.
- the material used for the first circuit pattern 21 and the second circuit pattern 22 may be a material having high electrical conductivity.
- the direct bonding method is a method in which the first circuit pattern 21, the second circuit pattern 22, and the substrate member 2 are bonded by direct reaction.
- the active metal bonding method the first circuit pattern 21, the second circuit pattern 22 and the substrate member 2 are bonded with a brazing material to which an active metal such as titanium (Ti) or zirconium (Zr) is added. Is the method.
- Cu is used for the metal pattern 23.
- the material used for the metal pattern 23 is not limited to this. If the material used for the metal pattern 23 can be bonded to the substrate member 2 by the direct bonding method or the active metal bonding method and can be bonded via the heat radiation plate 4 and the heat radiation plate bonding member 5. Good.
- the material constituting the metal pattern 23 is preferably a material having good electrical conductivity.
- the substrate member 2 not only a ceramic substrate but also a lead frame can be used, for example. In this case, it is not necessary to provide the first circuit pattern 21 and the second circuit pattern on the substrate member 2.
- the element bonding member 3 is provided between the back electrode 12 of the power semiconductor element 1 and the first circuit pattern 21 of the substrate member 2. Thereby, the back surface electrode 12 and the board
- the element bonding member 3 for example, a high-temperature solder containing lead (Pb) and tin (Sn) is used.
- the material used for the element bonding member 3 is not limited to this.
- a material used for the element bonding member 3 for example, an Ag nanoparticle paste or a conductive adhesive containing Ag particles and an epoxy resin can be used.
- FIG. 2 is a top view of the joining member in the power module according to the first embodiment.
- region 3a is arrange
- the back electrode 12 of the power semiconductor element 1 is bonded to the first circuit pattern 21 by the element bonding member 3 in the bonding region 3a, but is bonded to the first circuit pattern 21 in the gap region 3b.
- a portion corresponding to a portion where the surface electrode 11 of the power semiconductor element 1 and the wiring member 7 are joined is indicated by a wiring region 13 in FIG.
- Each of the bonding regions 3a including the wiring region 13 preferably has a length L of about 1.0 mm and a width W of about 0.5 mm.
- the element bonding member 3 has a plurality of divided bonding regions 3 a, but is not limited thereto.
- region 3a should just be arrange
- a plurality of joining regions 3a having equal dimensions are arranged.
- the arrangement of the joining region 3a is not limited to such an arrangement.
- the bonding region 3a can be appropriately selected according to the arrangement of the wiring region 13, the desired thermal resistance, and the allowable thermal stress.
- FIG. 3A is a top view showing a first modification of the arrangement of the element bonding members.
- the junction region 3a including the wiring region 13 is divided and formed.
- the junction region 3a that does not include the wiring region 13 is formed continuously. From a different point of view, the area of the junction region 3 a that does not include the wiring region 13 is larger than the area of the junction region 3 a that includes the wiring region 13.
- FIG. 3B is a top view showing a second modification of the arrangement of the element bonding members.
- the junction region 3a including the wiring region 13 is divided and formed.
- the junction region 3 a that does not include the wiring region 13 is formed by being divided more finely than the junction region 3 a that includes the wiring region 13.
- FIG. 3C is a top view showing a third modification of the arrangement of the element bonding members.
- the bonding region 3a is continuously formed in a spiral shape while forming the void region 3b.
- the heat sink 4 has a front surface 4a and a back surface 4b.
- the heat radiating plate 4 radiates heat generated during operation of the power module from the back surface 4b to the outside. Therefore, the heat sink 4 is made of a material having good thermal conductivity.
- a material of the heat sink 4 for example, a composite material of silicon carbide (SiC) and Al (Al—SiC) is used.
- the surface 4 a of the heat radiating plate 4 is joined to the metal pattern 23 of the substrate member 2 by the heat radiating plate joining member 5.
- high temperature solder containing Pb and Sn is used.
- the material used for the heat sink joining member 5 is not limited to this.
- a conductive adhesive containing Ag nanoparticle paste or Ag particles and an epoxy resin can be used.
- Case 6 is made of an insulating material with high heat resistance.
- polyphenylene sulfide Polyphenylene Sulfide
- polybutylene terephthalate Polybutylene Terephthaete
- the case 6 and the heat sink 4 constitute a power module housing.
- the heat sink 4 is provided on the lower surface of the case 6, but the case 6 may surround the outer peripheral portion of the heat sink 4.
- the shape of the case 6 is not limited to these. It is only necessary that the heat generated from the heat radiating plate 4 can be released to the outside by exposing the back surface 4b of the heat radiating plate 4 to the outside.
- the case 6 has a terminal 61.
- the terminal 61 includes an outer end 61a and an inner end 61b.
- the wiring member 7 connects the surface electrode 11 of the power semiconductor element 1 and the second circuit pattern 22 of the substrate member 2. Another wiring member 7 connects the second circuit pattern 22 of the board member 2 and the inner end 61 b of the terminal 61.
- a wire 7a is used as the wiring member 7, for example.
- the wire 7a is made of, for example, an alloy mainly composed of Al, Cu, or the like.
- the diameter of the wire 7a is preferably smaller than the length L and the width W of the bonding region 3a. Specifically, the diameter of the wire 7a is preferably 300 ⁇ m or more and 400 ⁇ m or less.
- the sealing member 8 seals the power semiconductor element 1, the substrate member 2, and the wiring member 7.
- the sealing resin 8 a is filled inside the casing of the power module configured by the heat radiating plate 4 and the case 6.
- a silicon resin is used as the sealing resin 8a.
- the material used for the sealing resin 8a is not limited to this.
- the sealing resin 8a urethane resin, epoxy resin, polyimide resin, polyamide resin, polyamideimide resin, acrylic resin, rubber material, or the like can be used.
- the sealing member 8 may be formed of a plurality of sealing resins 8a.
- the sealing member 8 may be formed by overlapping an epoxy resin on a gel-like silicon resin.
- the manufacturing process of the power module according to the first embodiment includes a preparation process S1, an element bonding process S2, a wiring member bonding process S3, and a resin sealing process S4.
- the preparation step S1 the power semiconductor element 1 having the front electrode 11 and the back electrode 12 is prepared. Moreover, the board
- a heat radiating plate bonding member 5 is supplied on the surface 4 a of the heat radiating plate 4.
- the element bonding member 3 is supplied on the first circuit pattern 21.
- the element bonding member 3 is supplied only to a region corresponding to the bonding region 3 a on the first circuit pattern 21.
- the substrate member 2 is placed so that the metal pattern 23 is in contact with the supplied heat sink joining member 5.
- the power semiconductor element 1 is placed so that the back electrode 12 is in contact with the supplied element bonding member 3.
- the heat radiating plate 4, the heat radiating plate bonding member 5, the element bonding member 3, the substrate member 2, and the power semiconductor element 1 are put into a heating furnace such as a reflow furnace.
- the heat sink 4 and the metal pattern 23 are joined by melting or sintering the heat sink joining member 5.
- the element bonding member 3 is melted or sintered, the first circuit pattern 21 and the back electrode 12 are bonded in the bonding region 3a. After completion of such joining, a case 6 is attached to the heat sink 4.
- the element bonding member 3 is supplied onto the first circuit pattern 21.
- the element bonding member 3 may be supplied to the back electrode 12 side by a method such as pre-coating the back electrode 12. .
- the wiring member joining step S3 One end of the wire 7a is placed in the wiring region 13 (see FIG. 2) on the surface electrode 11.
- the wiring region 13 refers to a region where the wiring member 7 and the surface electrode are joined or joined.
- the wiring region 13 is disposed so as to be above the bonding region 3a of the element bonding member 3 in plan view. That is, in the plan view, the wiring region 13 overlaps with the bonding region 3a and has a positional relationship that is included in the bonding region 3a. Further, as shown in FIG. 2, the wiring region 13 is preferably not located on the gap region 3b in plan view, but only on the joining region 3a. In this state, a load and ultrasonic vibration are applied to one end of the wire 7a.
- the wire 7a is joined to the surface electrode 11.
- the bonding region 3a of the element bonding member 3 is obtained by X-ray transmission observation and ultrasonic flaw inspection before wire bonding. You may confirm the position.
- the other end of the wire 7a is joined to the second circuit pattern 22 by the same method.
- another wire 7 a is joined to the second circuit pattern 22 and the inner end 61 b of the terminal 61 by the same method.
- the sealing resin 8 a is filled in the inside of the casing constituted by the heat radiating plate 4 and the case 6. Thereby, the power semiconductor element 1, the substrate member 2, the element bonding member 3, the heat sink 4, the heat sink bonding member 5, and the wiring member 7 are covered with the sealing resin 8a. In this state, the sealing resin 8a is cured by performing a heat treatment in a heat treatment furnace. From the above, the power module according to the first embodiment is manufactured.
- FIG. 1B is a cross-sectional view of a power module according to a modification of the first embodiment.
- an organic material filled with a ceramic filler is used as the substrate member 2.
- an epoxy resin, a polyimide resin, a cyanate resin, or the like is used as such an organic material.
- ceramic filler alumina, aluminum nitride, boron nitride or the like is used.
- the manufacturing method of the substrate member 2 is as follows. First, an organic material filled with a ceramic filler is applied on the heat sink 4. Thereafter, the heat sink 4 coated with the organic material filled with the ceramic filler is heat-treated. Thereby, the board
- the back electrode 12 of the power semiconductor element 1 and the substrate member 2 are joined by the element joining member 3 in the joining region 3a.
- substrate member 2 are not joined in the space
- the wiring member 7 is bonded to the surface electrode 11 of the power semiconductor element 1 on the bonding region 3a, the load generated in the gap region 3b is reduced by applying a load at the time of bonding and ultrasonic vibration. be able to. Therefore, damage of the power semiconductor element 1 can be prevented at the time of bonding.
- FIG. 4 is a cross-sectional view of a power module according to the second embodiment.
- the power module according to the second embodiment is similar to the power module according to the first embodiment in that the power semiconductor element 1, the substrate member 2, the element bonding member 3, and the heat sink. 4, a terminal 61, a wiring member 7, and a sealing member 8.
- the power module according to the second embodiment is different from the power module according to the first embodiment in that the case 6 is not provided and the resin mold 8b is used as the sealing member 8. .
- the resin mold 8 b covers the power semiconductor element 1, the substrate member 2, the element bonding member 3, the heat sink 4, the terminal 61, and the wiring member 7. However, the external end 61a of the terminal 61 and the back surface 4b of the heat sink 4 are exposed to the outside.
- a thermosetting resin is used as the resin mold 8b.
- an epoxy resin can be used as the material of the resin mold 8b.
- the power module manufacturing method according to the second embodiment is the same as the power module manufacturing method according to the first embodiment with respect to the preparation step S1, the element bonding step S2, and the wiring member bonding step S3.
- a molding step S5 is performed instead of the resin sealing step S4.
- transfer molding is performed as the molding step S5.
- a mold is prepared. A cavity having the same shape as that of the resin mold 8b is provided in the mold. In addition, the mold is provided with a liner communicating with the cavity. Subsequently, the power module in which the preparation step S1, the element bonding step S2, and the wiring member bonding step S3 are completed is placed in the cavity of the mold. Thereafter, the molten thermosetting resin is injected into the cavity through the runner. And after injection
- the resin mold 8b is formed by the process as described above.
- the power module according to the second embodiment can be resin-sealed using a low-cost resin sealing process such as transfer molding. Therefore, according to the second embodiment, the manufacturing cost can be reduced as compared with the first embodiment. Moreover, the resin sealing process such as transfer molding can more firmly seal the power module. Therefore, according to the second embodiment, compared to the first embodiment, it is possible to improve the reliability of the bonding between the wiring member 7 and the front surface electrode 11 and the bonding between the substrate member 2 and the back surface electrode 12.
- FIG. 5A is a cross-sectional view of a power module according to the third embodiment.
- the power module according to the third embodiment is similar to the power module according to the first embodiment in that the power semiconductor element 1, the substrate member 2, the element joining member 3, and the heat sink. 4, a heat radiating plate bonding member 5, a case 6, a terminal 61, a wiring member 7, and a sealing member 8.
- the power module according to the second embodiment is different from the power module according to the first embodiment in that a plate-like wiring member 7 b is used as the wiring member 7.
- the plate-like wiring member 7b may be an inner end 61b of the terminal 61.
- FIG. 5B is a cross-sectional view of a modification of the power module according to the third embodiment.
- Such a modified example is the same as the structure of the power module shown in FIG. 5A except that an organic material filled with a ceramic filler is used as the substrate member 2 as shown in FIG. 5B.
- the plate-like wiring member 7 b is joined to the surface electrode 11 of the power semiconductor element 1.
- the plate-like wiring member 7b is made of, for example, an alloy mainly composed of Al, Cu or the like.
- the region (wiring region 13) where the plate-like wiring member 7b and the surface electrode 11 are joined is on the joining region 3a in plan view. 5A and 5B, the plate-like wiring member 7b is directly joined to the surface electrode 11, but another member may be inserted between the plate-like wiring member 7b and the surface electrode 11. .
- FIG. 6 is a top view of the element bonding member 3 in the power module according to the third embodiment. Similar to the power module according to the first embodiment, a bonding region 3 a and a gap region 3 b exist between the back electrode 12 and the element bonding member 3. However, the plate-like wiring member 7b has a larger area (wiring region 13) joined to the surface electrode 11 than the wire 7a. Therefore, in the third embodiment, it is preferable that the area of the junction region 3a including the wiring region 13 is larger than that in the first embodiment. More specifically, the width W of the bonding region 3a is preferably about 0.8 mm, and the length L is preferably about 0.8 mm.
- the power module manufacturing method according to the third embodiment is the same as the power module manufacturing method according to the first embodiment with respect to the preparation step S1, the element bonding step S2, and the resin sealing step S4.
- the method for manufacturing the power module according to the third embodiment is different from the method for manufacturing the power module according to the first embodiment with respect to the wiring member joining step S3. Therefore, the difference regarding wiring member joining process S3 is demonstrated.
- the plate-like wiring member 7b is bonded to the surface electrode 11 by, for example, an ultrasonic bonding method.
- the plate-like wiring member 7 b is disposed on the surface electrode 11.
- the joining tool T is pressed against the plate-like wiring member 7b.
- This joining tool has an uneven shape at the tip.
- the joining tool T applies a load and ultrasonic vibration to the plate-like wiring member 7b.
- the plate-like wiring member 7 b is joined to the surface electrode 11.
- it is preferable that the location where the joining tool T applies a load and ultrasonic vibration to the plate-like wiring member 7b is on the joining region 3a of the element joining member 3 in plan view.
- FIG. 7 is a cross-sectional view of a power module according to the fourth embodiment.
- the power module according to the fourth embodiment is similar to the power module according to the first embodiment in that the power semiconductor element 1, the substrate member 2, the element joining member 3, and the heat sink 4 and a terminal 61 are provided.
- the inner end 61b of the terminal 61 is such that the wiring member 7 is a plate-like wiring member 7b, and the resin mold 8b instead of the case 6 and the sealing member 8 is used. Is different from the power module according to the first embodiment. These points are the same as those of the power modules according to the second and third embodiments.
- the manufacturing cost can be reduced as compared with the first embodiment, and the reliability of the bonding between the wiring member 7 and the front electrode 11 and the bonding between the substrate member 2 and the back electrode 12 is improved. Performance can be improved, and a large current can be achieved.
- the power semiconductor element 1 is used as the semiconductor element.
- a semiconductor element other than the power semiconductor element can be used instead of the power semiconductor element 1.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
L'invention concerne un module à semi-conducteur qui peut réduire la contrainte thermique provoquée sur une partie de liaison entre une électrode arrière d'un élément semi-conducteur et un élément substrat, et qui peut empêcher l'endommagement de l'élément semi-conducteur provoqué lorsqu'une électrode avant de l'élément semi-conducteur est connectée à un élément de câblage ; son procédé de fabrication. Le module à semi-conducteur selon la présente invention est pourvu : d'un élément substrat (2) ; d'un élément semi-conducteur (1) ayant une électrode avant (11) et une électrode arrière (12) ; d'un élément de connexion d'élément (3) connectant l'électrode arrière (12) et l'élément substrat (2) ; d'un élément de câblage (7) connecté à l'électrode avant (11). Une zone de connexion (3a), dans laquelle sont disposés une zone d'espacement (3b) et l'élément de connexion d'élément, est présente entre l'électrode arrière (12) et l'élément substrat (2), et l'électrode avant (11) et l'élément de câblage (7) sont connectés l'un à l'autre au-dessus de la zone de connexion (3a) en vue plane.
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Cited By (1)
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EP3611761A1 (fr) * | 2018-08-13 | 2020-02-19 | Heraeus Deutschland GmbH & Co KG | Procédé et substrat métallique destinés à contacter un semi-conducteur de puissance par un moyen de contact avec au moins une zone sans le moyen de contact comme structure réductrice de contraintes |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08274228A (ja) * | 1995-03-29 | 1996-10-18 | Origin Electric Co Ltd | 半導体搭載基板、電力用半導体装置及び電子回路装置 |
JP2008283024A (ja) * | 2007-05-11 | 2008-11-20 | Spansion Llc | 半導体装置及びその製造方法 |
JP2013026361A (ja) * | 2011-07-20 | 2013-02-04 | Panasonic Corp | 半導体装置及び半導体装置の製造方法 |
JP2014078616A (ja) * | 2012-10-11 | 2014-05-01 | Mitsubishi Electric Corp | 電力用半導体装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4766479A (en) * | 1986-10-14 | 1988-08-23 | Hughes Aircraft Company | Low resistance electrical interconnection for synchronous rectifiers |
US20030141103A1 (en) * | 2002-01-31 | 2003-07-31 | Ng Wee Lee | PCB solder pad geometry including patterns improving solder coverage |
JP2008270469A (ja) * | 2007-04-19 | 2008-11-06 | Mitsubishi Electric Corp | パワーモジュール及びその製造方法 |
WO2011132670A1 (fr) * | 2010-04-19 | 2011-10-27 | 本田技研工業株式会社 | Procédé de soudure de fils pour dispositif à semi-conducteur de puissance |
DE102011078582A1 (de) * | 2011-07-04 | 2013-01-10 | Robert Bosch Gmbh | Verfahren zum Herstellen von strukturierten Sinterschichten und Halbleiterbauelement mit strukturierter Sinterschicht |
JP6083109B2 (ja) * | 2012-01-18 | 2017-02-22 | 富士電機株式会社 | 半導体装置 |
JP6146007B2 (ja) * | 2012-03-30 | 2017-06-14 | 三菱マテリアル株式会社 | 接合体の製造方法、パワーモジュールの製造方法、パワーモジュール用基板及びパワーモジュール |
-
2016
- 2016-06-03 JP JP2016563002A patent/JPWO2017077729A1/ja active Pending
- 2016-06-03 WO PCT/JP2016/066618 patent/WO2017077729A1/fr active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08274228A (ja) * | 1995-03-29 | 1996-10-18 | Origin Electric Co Ltd | 半導体搭載基板、電力用半導体装置及び電子回路装置 |
JP2008283024A (ja) * | 2007-05-11 | 2008-11-20 | Spansion Llc | 半導体装置及びその製造方法 |
JP2013026361A (ja) * | 2011-07-20 | 2013-02-04 | Panasonic Corp | 半導体装置及び半導体装置の製造方法 |
JP2014078616A (ja) * | 2012-10-11 | 2014-05-01 | Mitsubishi Electric Corp | 電力用半導体装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3611761A1 (fr) * | 2018-08-13 | 2020-02-19 | Heraeus Deutschland GmbH & Co KG | Procédé et substrat métallique destinés à contacter un semi-conducteur de puissance par un moyen de contact avec au moins une zone sans le moyen de contact comme structure réductrice de contraintes |
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