WO2017071181A1 - 一种全包围栅结构的制备方法 - Google Patents

一种全包围栅结构的制备方法 Download PDF

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WO2017071181A1
WO2017071181A1 PCT/CN2016/082308 CN2016082308W WO2017071181A1 WO 2017071181 A1 WO2017071181 A1 WO 2017071181A1 CN 2016082308 W CN2016082308 W CN 2016082308W WO 2017071181 A1 WO2017071181 A1 WO 2017071181A1
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layer
gate
fin
enclosed
gate structure
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PCT/CN2016/082308
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English (en)
French (fr)
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黄仁东
钟旻
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上海集成电路研发中心有限公司
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Priority to US15/765,490 priority Critical patent/US10388765B2/en
Publication of WO2017071181A1 publication Critical patent/WO2017071181A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates

Definitions

  • the invention belongs to the technical field of semiconductor integrated circuit manufacturing processes, and in particular relates to a method for preparing a full-enclosed gate structure.
  • the semiconductor integrated circuit (IC) industry has experienced rapid development.
  • the functional density ie, the number of interconnected devices per chip area
  • the geometry ie, the smallest device or interconnect that can be fabricated using a fabrication process
  • the advantage of this scaled down process is increased productivity and reduced associated costs. At the same time, this scale-down process also increases the complexity of processing and manufacturing ICs.
  • FinFET effect tube
  • a FinFET device is a multi-gate MOS device. According to the number of gates, the FinFET can be divided into a dual-gate FinFET, a tri-gate FinFET, and a four-sided controlled full-enclosed gate. (Gate-all-around) FinFET.
  • the double-gate FinFET has two gates respectively located on two sides of the fin body (Fin), and can independently control the channel current of the fin body.
  • dual-gate FinFETs are commonly used in core logic circuits that require low leakage current.
  • the tri-gate FinFET has three gates, one on each side of the fin and one on the top of the fin.
  • the gate and the Fin are separated from the substrate by an insulating layer underneath.
  • the Fin structure of the tri-gate FinFET is formed on SOI (Silicon On Insulator), and is directly obtained directly from the silicon substrate.
  • SOI Silicon On Insulator
  • the advantage of the tri-gate FinFET is that since the three sides of the fin body are controlled by the gate, the carriers in the active region can be better controlled than the conventional MOS structure, thereby providing a larger driving current, thereby improving Device performance.
  • Currently widely used FinFET devices are basically three-sided controlled three-gate FinFETs.
  • the fully-enclosed gate structure can more effectively improve the gate control capability and suppress the short channel effect.
  • the current full-enclosed gate structure basically adopts a suspended gate structure, and the formation method thereof is mainly:
  • a planar process is used to form the required active regions; then, the lower portion is hollowed out to form a floating gate by various schemes; then, a gate dielectric is formed by oxidation; finally, polysilicon is deposited to form a control gate.
  • the active region direction is a full-enclosed gate structure perpendicular to the surface of the silicon wafer, and the fabrication process is more complicated.
  • the technical problem to be solved by the present invention is to provide a method for preparing a fully enclosed gate structure with simple, reliable and low cost, and to ensure device performance, so that the formed fully enclosed gate can effectively control the channel from four sides. And obtaining the required device characteristics, the method of the invention is simple, and can be compatible with the existing integrated circuit planar process, and solves the problems of complicated process and high cost existing in the prior art.
  • the present invention provides a method for fabricating a fully-enclosed gate structure for fabricating a FinFET device, comprising the steps of:
  • Step S01 providing a semiconductor substrate, forming a composite layer on the semiconductor substrate, and patterning the composite layer, wherein the composite layer includes a dielectric layer, a buried gate layer, and sequentially from bottom to top.
  • Barrier layer
  • Step S02 forming a sidewall spacer around the composite layer, then growing an epitaxial layer around the sidewall spacer, and planarizing the epitaxial layer to make the upper surface of the barrier layer, the upper surface of the sidewall spacer, and the epitaxial layer The upper surface of the layer is flush;
  • Step S03 removing the barrier layer, and depositing a first high-k dielectric layer equal to its thickness
  • Step S04 growing a fin layer, patterning the fin layer and exposing the buried gate layer to form a fin structure
  • Step S05 forming a dielectric isolation layer on the epitaxial layer
  • Step S06 forming a second high-K dielectric layer on the sidewall and the top of the fin structure
  • Step S07 growing a second gate layer, and patterning the second gate layer to form a cross And a gate structure surrounding the fin structure.
  • step S03 the following steps are specifically included:
  • Step S031 removing the barrier layer by a wet etching process or a dry etching process
  • Step S032 depositing a first high-k dielectric layer thicker than the barrier layer
  • Step S033 removing the first high-k dielectric layer on the sidewall and the surface of the epitaxial layer.
  • the method specifically includes the following steps:
  • Step S071 growing a second gate layer, and the second gate layer covers the fin structure
  • Step S072 planarizing the second gate layer
  • Step S073 etching the second gate layer by photolithography and etching to form a gate structure.
  • the buried gate layer is connected to the second gate layer and the fin structure is enclosed.
  • a fin layer is formed by a bonding process, and the material of the fin layer is the same as the material of the semiconductor substrate.
  • the buried gate layer and the second gate layer are doped polysilicon.
  • the dielectric layer is silicon oxide, silicon nitride or silicon oxynitride
  • the barrier layer is silicon nitride or silicon carbonitride.
  • the material of the epitaxial layer is the same as the material of the semiconductor substrate.
  • the material of the first high K dielectric layer and the second high K dielectric layer is cerium oxide.
  • the fin structure has a strip shape, a strip shape or a rectangular block shape.
  • the present invention provides a method for preparing a fully-enclosed gate structure, first forming a buried gate layer on a semiconductor substrate, then forming an epitaxial layer in the non-embedded gate layer region, and planarizing The buried gate layer is level, then a fin structure is formed over it, and finally a straddle and a package are formed
  • the gate structure of the fin structure, the gate structure in the present invention effectively controls the channel from all sides in the form of full envelopment, and the width of the channel is increased compared to the double gate structure and the triple gate structure, thereby The effective area of the channel is improved.
  • the invention solves the problems of complicated process and high cost in the prior art while ensuring the required device characteristics, has the advantages of simple method, can be compatible with the existing integrated circuit plane process, has low cost, is easy to implement, etc. advantage.
  • FIG. 1 is a schematic flow chart of a method for preparing a full-enclosed gate structure according to the present invention
  • FIGS. 2a-2j are schematic diagrams showing the side structure of a fully enclosed gate structure in the present invention.
  • 3a-3j are schematic top plan views showing the formation of a fully enclosed gate structure in the present invention.
  • FIG. 4 is a schematic perspective view of a full-enclosed gate structure of the present invention.
  • Figure 5 is a schematic cross-sectional view showing the structure of a fully enclosed gate structure in the present invention.
  • FIG. 1 is a schematic flow chart of a method for fabricating a full-enclosed gate structure according to the present invention
  • FIGS. 2a-2j are schematic views showing a side structure of a full-enclosed gate structure in the present invention
  • FIGS. 3a-3j are top views of forming a fully-enclosed gate structure in the present invention.
  • 4 is a schematic perspective view of a full-enclosed gate structure of the present invention
  • FIG. 5 is a schematic cross-sectional view of the full-enclosed gate structure of the present invention.
  • the present invention provides a method for fabricating a fully-enclosed gate structure for fabricating a FinFET device, comprising the steps of:
  • Step S01 a semiconductor substrate 100 is provided, a composite layer is formed on the semiconductor substrate 100, and the composite layer is patterned.
  • the composite layer includes a dielectric layer 201, a buried gate layer 202, and a barrier layer in this order from bottom to top. 203 (as shown in Figure 2a and Figure 3a).
  • the semiconductor substrate 100 provided in this step may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium silicon substrate, gallium arsenide, or the like, and may be any type known in the electronic field.
  • a method known in the art forms a composite layer on a semiconductor substrate and patterns it.
  • the composite layer is etched by photolithography and etching processes.
  • the dielectric layer 201 is preferably silicon oxide, silicon nitride or nitrogen.
  • the silicon oxide, the barrier layer 203 is preferably silicon nitride or silicon carbonitride, and the buried gate layer 202 is preferably doped polysilicon.
  • Step S02 forming a sidewall spacer 204 around the composite layer, then growing the epitaxial layer 205 around the sidewall spacer 204, and planarizing the epitaxial layer 205 to make the upper surface of the barrier layer 203 and the upper surface of the sidewall spacer 204 And the upper surface of the epitaxial layer 205 is flush (as in Figures 2b, 2c and Figures 3b, 3c).
  • the sidewall spacer 204 may be formed by an epitaxial growth process.
  • the sidewall spacer 204 is preferably a pure silicon layer or a doped silicon layer.
  • an epitaxial layer 205 is formed around the sidewall spacer 204.
  • the material of the epitaxial layer 205 is preferably compared with the semiconductor substrate 100. The materials are the same.
  • step S03 the barrier layer 203 is removed, and a first high-k dielectric layer 206 equal to its thickness is deposited (as shown in FIGS. 2d, 2e and 3d, 3e).
  • the step includes the following sub-steps: step S031, removing the barrier layer 203 by a wet etching process or a dry etching process; step S032, depositing a first high-k dielectric layer 206 thicker than the barrier layer 203; Step S033, removing the first high-k dielectric layer 206 on the surface of the sidewall spacer 204 and the epitaxial layer 205, wherein the material of the first high-k dielectric layer 206 is preferably hafnium oxide.
  • step S04 the fin layer 301 is grown, the fin layer 301 is patterned and the buried gate layer 202 is exposed to form a fin structure 303 (as shown in FIGS. 2f, 2g and FIGS. 3f, 3g).
  • the fin layer 301 is preferably formed by a bonding process, wherein the material of the fin layer 301 is the same as the material of the semiconductor substrate 100, and then the fin layer 301 is applied by photolithography and etching processes.
  • the first high K dielectric layer 206 is patterned and portions of the first high K dielectric layer 206, the sidewall spacers 204, and the epitaxial layer 205 outside the pattern regions are removed, while the buried gate layer 202 is exposed.
  • step S05 a dielectric isolation layer 303 is formed on the epitaxial layer 205 (as shown in FIG. 2h and FIG. 3h).
  • a dielectric isolation layer 303 is formed on the epitaxial layer by a method known in the art to isolate the subsequent gate and the semiconductor substrate.
  • Step S06 forming a second high-k dielectric layer 304 on the sidewalls and top of the fin structure 302 (as shown in Figures 2i and 3i).
  • the second high-k dielectric layer 304 may be first deposited on the known structure, and then the second high-k dielectric layer 304 other than the fin structure 302 is removed, that is, only the sidewall of the fin structure 302 is retained. And a second high K dielectric layer 304 at the top, wherein the material of the second high K dielectric layer 304 is preferably hafnium oxide.
  • Step S07 growing a second gate layer 305, and patterning the second gate layer 305 to form a gate structure 306 that spans and surrounds the fin structure (as shown in FIGS. 2j and 3j).
  • the step includes the following sub-steps: step S071, growing the second gate layer 305, and the second gate layer 305 covers the fin structure 302; step S072, planarizing the second gate layer 305; step S073,
  • the second gate layer 305 is etched by photolithography and etching to form a gate
  • the pole structure 306, wherein the second gate layer 305 is preferably doped polysilicon.
  • the present invention provides a buried gate layer 202 in a fully-enclosed gate structure connected to the second gate layer 305 and surrounding the fin structure 302, wherein the fin structure 302
  • the shape is preferably a strip shape, a strip shape or a rectangular block shape which increases the width of the channel so that the effective area of the channel is improved.
  • the present invention provides a method for fabricating a fully-enclosed gate structure by first forming a buried gate layer 202 on a semiconductor substrate 100, then forming an epitaxial layer 205 in a region of the non-embedded gate layer, and planarizing The buried gate layer 202 is level, and then a fin structure 300 is formed thereon, and finally a gate structure 306 is formed across and surrounding the fin structure.
  • the gate structure in the present invention is effectively controlled from four sides in a fully enclosed form.
  • the channel compared to the dual gate structure and the triple gate structure, increases the width of the channel so that the effective area of the channel is improved.
  • the invention solves the problems of complicated process and high cost in the prior art while ensuring the required device characteristics, has the advantages of simple method, can be compatible with the existing integrated circuit plane process, has low cost, is easy to implement, etc. advantage.

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Abstract

一种全包围栅结构的制备方法，包括提供一半导体衬底（100），在半导体衬底（100）上形成复合层，并对复合层进行图形化，复合层从下往上依次包括介质层（201）、掩埋栅极层（202）以及阻隔层（203）；在复合层四周形成侧墙（204），然后在侧墙（204）的四周生长外延层（205），并对外延层（205）平坦化，以使阻隔层（203）的上表面、侧墙（204）的上表面以及外延层（205）的上表面相平齐；去除阻隔层（203），并淀积与其等厚的第一高K介质层（206）；生长鳍片层（301），形成鳍片结构（302）；在外延层（205）上形成介质隔离层（303）；在鳍片结构（302）的侧壁以及顶部形成第二高K介质层（304）；生长第二栅极层（305），形成横跨及包围所述鳍片结构（302）的栅极结构（306）。栅极结构（306）以全包围的形式从四面有效地控制沟道，相比于双栅极结构以及三栅极结构，增加了沟道的宽度从而使得沟道的有效面积得到提升。

Description

一种全包围栅结构的制备方法 技术领域
本发明属于半导体集成电路制造工艺技术领域，具体的，涉及一种全包围栅结构的制备方法。
技术背景
半导体集成电路(IC)工业经历了迅速的发展。在IC的发展过程中，通常增大了功能密度(即每个芯片区域的互连器件的数量)，而减小了几何尺寸(即使用制造工艺可以制造的最小器件或互连线)。这种按比例缩小的工艺优点在于提高了生产效率并且降低了相关费用。同时，这种按比例缩小的工艺也增加了处理和制造IC的复杂性。
在寻求更高的器件密度、更高的性能以及更低的费用的过程中，随着集成电路工艺持续发展到纳米技术工艺节点，一些制造厂商已经开始考虑如何从平面CMOS晶体管向三维鳍式场效应管(FinFET)器件结构的过渡问题。与平面晶体管相比，FinFET器件由于改进了对沟道的控制，从而减小了短沟道效应。
制造和设计中的挑战推动了FinFET器件的发展。目前，FinFET已出现在20nm技术代的应用中。尽管现有的FinFET器件以及制造FinFET器件的方法已大体上满足了其预期目的，但并不是在所有方面都能够完全令人满意。
FinFET器件是一种多栅MOS器件。按照栅极数目的不同，可以将FinFET划分为双栅FinFET、三栅FinFET以及可四面控制的全包围栅 (Gate-all-around)FinFET。
其中，双栅FinFET具有两个栅极，分别位于鳍体(Fin)的两侧，可以分别独立控制鳍体的沟道电流。在实际应用中，双栅FinFET常用于要求具有低漏电流的核心逻辑电路。
三栅FinFET具有三个栅极，鳍体的两侧面各有一个栅极，另外一个栅极在鳍体的顶部。栅极及Fin(鳍)通过其下方的绝缘层与衬底相隔离。三栅FinFET的Fin结构有的是在SOI(Silicon On Insulator，绝缘体上硅)上形成的，有的是直接从硅衬底上直接得到。三栅FinFET的好处是，由于鳍体的三个侧面都受到栅极的控制，所以比传统的MOS结构能更好地控制有源区中的载流子，提供更大的驱动电流，因而提高了器件性能。目前广泛应用的FinFET器件，基本上是三面控制的三栅FinFET。
随着对器件性能不断提出的更高要求，催生了四面控制的全包围栅结构。全包围栅结构能更加有效地提高栅极控制能力、抑制短沟道效应。
目前的全包围栅结构基本上都是采用悬栅结构，其形成方法主要是：
首先，采用平面工艺形成所需要的有源区；然后，采用各种方案将其下部掏空，形成悬栅；接着，氧化形成栅介质；最后，淀积多晶硅，形成控制栅极。
也有采用垂直形式的栅结构来实现四面控制的FinFET器件，即有源区方向是垂直于硅片表面方向的全包围栅结构，其制作过程就更为复杂了。
由此可见，上述形成全包围栅结构的工艺非常复杂，且成本高昂，制约了FinFET器件向低成本、高效率生产的迅速发展。因此，如何提供一种工艺简单、可靠、低成本的全包围栅极结构的制备方法，并保证器件性能，是 本领域技术人员亟待解决的技术问题之一。
发明概要
本发明所要解决的技术问题是提供一种工艺简单、可靠、低成本的全包围栅极结构的制备方法，并保证器件性能，使形成的全包围形式的栅极能从四面有效地控制沟道，并得到所需要的器件特性，本发明方法简便，可与现有的集成电路平面工艺相兼容，解决了现有技术存在的工艺复杂、成本高的问题。
为了解决上述技术问题，本发明提供了一种全包围栅结构的制备方法，用于制作FinFET器件，包括以下步骤：
步骤S01，提供一半导体衬底，在所述半导体衬底上形成复合层，并对所述复合层进行图形化，其中，所述复合层从下往上依次包括介质层、掩埋栅极层以及阻隔层；
步骤S02，在所述复合层四周形成侧墙，然后所述侧墙的四周生长外延层，并对所述外延层平坦化，以使所述阻隔层的上表面、侧墙的上表面以及外延层的上表面相平齐；
步骤S03，去除所述阻隔层，并淀积与其等厚的第一高K介质层；
步骤S04，生长鳍片层，对所述鳍片层进行图形化并暴露出掩埋栅极层，以形成鳍片结构；
步骤S05，在所述外延层上形成介质隔离层；
步骤S06，在所述鳍片结构的侧壁以及顶部形成第二高K介质层；
步骤S07，生长第二栅极层，对所述第二栅极层进行图形化，形成横跨 及包围所述鳍片结构的栅极结构。
优选的，所述步骤S03中，具体包括以下步骤：
步骤S031，采用湿法刻蚀工艺或干法刻蚀工艺去除所述阻隔层；
步骤S032，淀积与所述阻隔层等厚的第一高K介质层；
步骤S033，去除所述侧墙和外延层表面的第一高K介质层。
优选的，所述步骤S07中，具体包括以下步骤：
步骤S071，生长第二栅极层，且第二栅极层覆盖所述鳍片结构；
步骤S072，对所述第二栅极层平坦化；
步骤S073，采用光刻以及刻蚀工艺对所述第二栅极层进行刻蚀，以形成栅极结构。
优选的，所述掩埋栅极层与第二栅极层相连，并将所述鳍片结构合围。
优选的，所述步骤S04中，采用键合工艺形成鳍片层，所述鳍片层的材料与半导体衬底的材料相同。
优选的，所述掩埋栅极层与第二栅极层为掺杂的多晶硅。
优选的，所述步骤S01中，所述介质层为氧化硅、氮化硅或氮氧化硅，所述阻隔层为氮化硅或碳氮化硅。
优选的，所述步骤S02中，所述外延层的材料与半导体衬底的材料相同。
优选的，所述第一高K介质层以及第二高K介质层的材料为二氧化铪。
优选的，所述鳍片结构的形状为条状、带状或矩形块状。
与现有的方案相比，本发明提供了一种全包围栅结构的制备方法，首先在半导体衬底上形成掩埋栅极层，然后在非掩埋栅极层区域形成外延层，并平坦化与掩埋栅极层相平，接着在其上方形成鳍片结构，最后形成横跨及包 围鳍片结构的栅极结构，本发明中的栅极结构以全包围的形式从四面有效地控制沟道，相比于双栅极结构以及三栅极结构，增加了沟道的宽度从而使得沟道的有效面积得到提升。本发明在保证所需要的器件特性的同时，解决了现有技术存在的工艺复杂、成本高的问题，具有方法简便，可与现有的集成电路平面工艺相兼容，具有成本低、易于实施等优点。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明中全包围栅结构的制备方法的流程示意图
图2a-2j是本发明中形成全包围栅结构的侧面结构示意图
图3a-3j是本发明中形成全包围栅结构的俯视结构示意图
图4是本发明中全包围栅结构的立体结构示意图
图5是本发明中全包围栅结构的剖面结构示意图
发明内容
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明的实施方式作进一步地详细描述。本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
上述及其它技术特征和有益效果，将结合实施例及附图对本发明的全包围栅结构的制备方法进行详细说明。图1是本发明中全包围栅结构的制备方法的流程示意图；图2a-2j是本发明中形成全包围栅结构的侧面结构示意图；图3a-3j是本发明中形成全包围栅结构的俯视结构示意图；图4是本发明中全包围栅结构的立体结构示意图；图5是本发明中全包围栅结构的剖面结构示意图。
如图1所示,本发明提供了一种全包围栅结构的制备方法，用于制作FinFET器件，包括以下步骤：
步骤S01，提供一半导体衬底100，在半导体衬底100上形成复合层，并对复合层进行图形化，其中，复合层从下往上依次包括介质层201、掩埋栅极层202以及阻隔层203(如图2a以及图3a)。
具体的，本步骤中提供的半导体衬底100可以为体硅衬底、绝缘体上硅(SOI)衬底、锗硅衬底、砷化镓等,可以是电子领域中已知的任何类型，采用业界已知方法在半导体衬底上形成复合层，并对其图形化，优选采用光刻和刻蚀工艺对复合层进刻蚀，具体的，介质层201优选为氧化硅、氮化硅或氮氧化硅，阻隔层203优选为氮化硅或碳氮化硅，掩埋栅极层202优选为掺杂的多晶硅。
步骤S02，在复合层四周形成侧墙204，然后所述侧墙204的四周生长外延层205，并对所述外延层205平坦化，以使阻隔层203的上表面、侧墙204的上表面以及外延层205的上表面相平齐(如图2b、2c以及图3b、3c)。
具体的，可采用外延生长工艺形成侧墙204，侧墙204优选为纯硅层或者掺杂硅层，接着在侧墙204的四周形成外延层205，外延层205的材料优选与半导体衬底100的材料相同。
步骤S03，去除所述阻隔层203，并淀积与其等厚的第一高K介质层206(如图2d、2e以及图3d、3e)。
具体的，本步骤包括以下分步骤：步骤S031，采用湿法刻蚀工艺或干法刻蚀工艺去除阻隔层203；步骤S032，淀积与阻隔层203等厚的第一高K介质层206；步骤S033，去除侧墙204和外延层205表面的第一高K介质层206，其中，第一高K介质层206的材料优选为二氧化铪。
步骤S04，生长鳍片层301，对所述鳍片层301进行图形化并暴露出掩埋栅极层202，以形成鳍片结构303(如图2f、2g以及图3f、3g)。
具体的，本步骤中，优选采用键合工艺形成鳍片层301，其中，鳍片层301的材料与半导体衬底100的材料相同，接着，采用光刻和刻蚀工艺对鳍片层301以及第一高K介质层206进行图形化，并去除图形区以外的部分第一高K介质层206、侧墙204和外延层205，同时，暴露出掩埋栅极层202。
步骤S05，在所述外延层205上形成介质隔离层303(如图2h以及图3h)。
具体的，本步骤中，采用业界已知方法在外延层上形成介质隔离层303，以隔离后续栅极和半导体衬底。
步骤S06，在所述鳍片结构302的侧壁以及顶部形成第二高K介质层304(如图2i以及图3i)。
具体的，本步骤中，可首先在已知结构上淀积第二高K介质层304，然后去除鳍片结构302以外的第二高K介质层304，即仅保留鳍片结构302的侧壁以及顶部的第二高K介质层304，其中，第二高K介质层304的材料优选为二氧化铪。
步骤S07，生长第二栅极层305，对所述第二栅极层305进行图形化，形成横跨及包围所述鳍片结构的栅极结构306(如图2j以及图3j)。
具体的，本步骤包括以下分步骤：步骤S071，生长第二栅极层305，且第二栅极层305覆盖鳍片结构302；步骤S072，对第二栅极层305平坦化；步骤S073，采用光刻以及刻蚀工艺对第二栅极层305进行刻蚀，以形成栅 极结构306，其中，第二栅极层305优选为掺杂的多晶硅。
如图4、5所示,本发明提供了一种全包围栅结构中的掩埋栅极层202与第二栅极层305相连，并将所述鳍片结构302合围，其中，鳍片结构302的形状优选为条状、带状或矩形块状，该结构增加了沟道的宽度从而使得沟道的有效面积得到提升。
综上所述，本发明提供了一种全包围栅结构的制备方法，首先在半导体衬底100上形成掩埋栅极层202，然后在非掩埋栅极层区域形成外延层205，并平坦化与掩埋栅极层202相平，接着在其上方形成鳍片结构300，最后形成横跨及包围鳍片结构的栅极结构306，本发明中的栅极结构以全包围的形式从四面有效地控制沟道，相比于双栅极结构以及三栅极结构，增加了沟道的宽度从而使得沟道的有效面积得到提升。本发明在保证所需要的器件特性的同时，解决了现有技术存在的工艺复杂、成本高的问题，具有方法简便，可与现有的集成电路平面工艺相兼容，具有成本低、易于实施等优点。
上述说明示出并描述了本发明的若干优选实施例，但如前所述，应当理解本发明并非局限于本文所披露的形式，不应看作是对其他实施例的排除，而可用于各种其他组合、修改和环境，并能够在本文所述发明构想范围内，通过上述教导或相关领域的技术或知识进行改动。而本领域人员所进行的改动和变化不脱离本发明的精神和范围，则都应在本发明所附权利要求的保护范围内。

Claims (10)

  1. 一种全包围栅结构的制备方法，用于制作FinFET器件，其特征在于，包括以下步骤：
    步骤S01，提供一半导体衬底，在所述半导体衬底上形成复合层，并对所述复合层进行图形化，其中，所述复合层从下往上依次包括介质层、掩埋栅极层以及阻隔层；
    步骤S02，在所述复合层四周形成侧墙，然后所述侧墙的四周生长外延层，并对所述外延层平坦化，以使所述阻隔层的上表面、侧墙的上表面以及外延层的上表面相平齐；
    步骤S03，去除所述阻隔层，并淀积与其等厚的第一高K介质层；
    步骤S04，生长鳍片层，对所述鳍片层进行图形化并暴露出掩埋栅极层，以形成鳍片结构；
    步骤S05，在所述外延层上形成介质隔离层；
    步骤S06，在所述鳍片结构的侧壁以及顶部形成第二高K介质层；
    步骤S07，生长第二栅极层，对所述第二栅极层进行图形化，形成横跨及包围所述鳍片结构的栅极结构。
  2. 根据权利要求1所述的全包围栅结构的制备方法，其特征在于，所述步骤S03中，具体包括以下步骤：
    步骤S031，采用湿法刻蚀工艺或干法刻蚀工艺去除所述阻隔层；
    步骤S032，淀积与所述阻隔层等厚的第一高K介质层；
    步骤S033，去除所述侧墙和外延层表面的第一高K介质层。
  3. 根据权利要求1所述的全包围栅结构的制备方法，其特征在于，所述步骤S07中，具体包括以下步骤：
    步骤S071，生长第二栅极层，且第二栅极层覆盖所述鳍片结构；
    步骤S072，对所述第二栅极层平坦化；
    步骤S073，采用光刻以及刻蚀工艺对所述第二栅极层进行刻蚀，以形 成栅极结构。
  4. 根据权利要求1所述的全包围栅结构的制备方法，其特征在于，所述掩埋栅极层与第二栅极层相连，并将所述鳍片结构合围。
  5. 根据权利要求1所述的全包围栅结构的制备方法，其特征在于，所述步骤S04中，采用键合工艺形成鳍片层，所述鳍片层的材料与半导体衬底的材料相同。
  6. 根据权利要求1所述的全包围栅结构的制备方法，其特征在于，所述掩埋栅极层与第二栅极层为掺杂的多晶硅。
  7. 根据权利要求1所述的全包围栅结构的制备方法，其特征在于，所述步骤S01中，所述介质层为氧化硅、氮化硅或氮氧化硅，所述阻隔层为氮化硅或碳氮化硅。
  8. 根据权利要求1所述的全包围栅结构的制备方法，其特征在于，所述步骤S02中，所述外延层的材料与半导体衬底的材料相同。
  9. 根据权利要求1所述的全包围栅结构的制备方法，其特征在于，所述第一高K介质层以及第二高K介质层的材料为二氧化铪。
  10. 根据权利要求1～9任一所述的全包围栅结构的制备方法，其特征在于，所述鳍片结构的形状为条状、带状或矩形块状。
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