200919587 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種矽覆絕緣裝置及其製作方法，詳〜 之，係關於一種假閘極全環繞矽覆絕緣裝置及其製作方 法。 【先前技術】 根據國際半導體技術藍圖（ITRS)之評估，傳統金氧半場 f 效電晶體（M〇SFET)在尺寸持續微縮的影響下所造成的短 f 通道效應已面臨極大的挑戰。其中學者提出一些解決方 案’例如使用矽覆絕緣（SOI)、超薄本體（Ultra thin b〇dy ; UTB)和high-k閘極介電層（如八丨2〇3、Hf〇2等等）來解決最嚴 重的漏電流問題；使用雙閘極材料、金屬閘極、多層閘極 工程或鰭狀（Fin)閘極來控制閘極臨界門檻電壓（Thresh〇id Voltage)隨著通道長度縮小而捲曲向下（r〇11_〇ff)和汲極引 致能障下降（DIBL)效應。但使用這些解決方法同時會延伸 〇 一連串的問題（Issues)，例如使用SOI將面臨浮體（Floating body effect)與屈膝效應（Kink Effec〇、自我加熱效應和單 拴走火效應（Single latch up);使用UTB雖然鬆弛漏電流問 題和壓抑超短通道效應，但同時將面臨源/汲極串接電阻 增大而降低電流驅動能力、及本體平坦化不均而造成臨界 ' 門檻電壓變動過大之更大問題。 因為傳統M0SFET太多的寄生？]^接面電容，這使得元件 切換速度和高頻響應速度變慢，也造成源/極漏電流過 问。使用SOI或UTB固然可以降低寄生pN接面電容，其未 123800.doc 200919587 來的實用性當然不容置疑，巾面臨的串接電阻過高問題已 有不少解決方案，如提高或加深源/汲極厚度或加入矽化 金屬來提高導電率和降低歐姆接觸（中華民國專利申請號 第090108868號、美國專利第6,825,535號、第mm] η 號）。SOI所造成浮體效應的抑制亦有對策（如美國專利第 6,686,629號、第M37,375號），如在本體下方形成一矽化 鍺磊晶使電荷經由表面效應而復合，避免本體電位上升。 抑制短通道效應造成漏電流的方法中’最常用的技術如淺 佈植源/汲極〇^〇)技術或使用超陡峭接面（如美國專利第 6,465,847號）或暈圈（Hal〇)離子植入（如美國專利第 6,936,278號)來抑制空乏區的㈣，但有#於成本和複雜 度的考量我們更希望有—些實際的㈣，如減少製程步 驟、降低光罩和離子佈植使用次數等等。 ο 此外’決定元件性能的臨界門檻電壓 更顯重要。未來，環繞式閘極（Gate all ，可改善本體與周圍絕緣層之間的邊際 ’但製作困難度將大為提高。然而可以 美的電荷耦合效應 效應和耗損的功率 同時解決上述問題的其實並 件結構來作改變以及一些自 的性能和降低製程複雜度。 在尺寸微縮情狀下 around)將具有更完 不多見，根本上必須考慮從元 我對準的機制來同時增加元件 因此，有必要提供一種創新且且推牛 钔祈/、進步性的假閘極全環繞 矽覆絕緣裝置及其製作方法，以解決上述問題。 【發明内容】 本發明之目的在於提供— 種假閘極全環繞⑪覆絕緣裝 123800.doc 200919587 置。該假閘極全環繞矽覆絕緣裝置包括：一基板、一下間 極氧化侧壁、一下閘極介電層、一導電半導體層、一上閘 極介電層、一上閘極、一邊襯、一氧化保護層及一電極 組。該基板具有一下閘極，該下閘極具有一第一端及一第 . 二端，該第一端及該第二端係沿一第一方向之相對二端。 該下閘極氧化側壁覆蓋該下閘極之侧面。該下閘極介電層 覆蓋該下閘極及該下閘極氧化側壁，其具有一接觸窗，該 Q 接觸窗形成於該下閘極之該第一端之周緣上方相對位置， 以顯露出部分該下閘極。該導電半導體層具有一本體、一 源極及一汲極，該本體大致形成於該下閘極介電層之中間 部分上，該源極及該汲極形成於該本體沿著一第二方向之 二側邊，該第二方向大致垂直該第一方向。該上閘極介電 層沿該第一方向覆蓋該下閘極上方相對位置之該下閘極介 電層、該本體之一頂面及該本體之二側面，二側面係垂直 該第一方向。該上閘極沿該第一方向覆蓋該下閘極介電 u 層、該接觸窗及該上閘極介電層。該邊襯形成於該上閘極 介電層及該上閘極之二相對侧面，該二相對側面係垂直於 該第二方向。該氧化保護層覆蓋該源極、該汲極、該邊襯 及該上閘極，其具有一第一貫孔、一第二貫孔及一第三貫 孔’該帛一貫⑶、該第二貫孔及該第三貫孔分別形成於該 接觸窗、該源極及該汲極之上方相對位置，以分別顯露部 分該上閘極、部分該源極及部分該汲極。該電極組具有一 第一電極、一第二電極及一第三電極，分別設置於該第一 貫孔、該第二貫孔及該第三貫孔内，以分別電性連接該上 123800.doc 200919587 閘極、該源極及該沒極。 本發明之另一目的在於提供一種假閘極全環繞矽覆絕緣 裝置之製作方法，其包括以下步驟：⑷提供一基板，該基 ' &具有—τ閘極’該下閘極具有—第-端及-第二端，該 . [端及該第二端係沿-第-方向之相對二端；⑻形成一 下閘極氧化側壁，其覆蓋該下閘極之側面；（C)形成一下閘 極介電層，其覆蓋該下間極及該下間極氧化側壁；⑷形成 〇 —導電半導體層，其具有-第-部分、—第二部分及一第 三部分，該第一部分大致形成於該下閘極介電層之中間部 刀上該第一部分及該第三部分形成於該第一部分沿著一 第-方向之二側邊，該第二方向大致垂直該第一方向·⑷ 成一上閘極介電層，其覆蓋該導電半導體層及該下閘極介 電層；⑴形成-接觸窗，該接觸窗係貫穿該上閘極介電層 及該下閘極介電層，且形成於該下閘極之該第一端之周緣 上方相對位置，以顯露出部分該下問極；⑷形成—上間 〇 極’其覆蓋該接觸窗、顯露之該下閘極、該下閘極介電層 及該上閘極介電層；（h)沿該第一方向移除部分該上閘極及 邛刀該上閘極介電層，未移除之該上閘極及該上閘極介電 S ”有相同見度且位於該下閘極上方之相對位置，其中該 上閘極沿該第一方向覆蓋該下閘極介電層、該接觸窗、該 下閘極及該上閘極介電層；⑴形成一邊襯，其覆蓋該上閉 極介電層及該上閘極之二相對側面，該二相對側面係垂直 於該第一方向，⑴進行一離子佈植步驟，於該導電半導體 層之該第一部分、該第二部分及該第三部分相對應地形成 123800.doc 200919587 -本體一源極及-沒極；（k)形成—氧化保護層，其覆蓋 該源極、該汲極、該邊概及該上閘極，其具有一第一貫 孔、一第二貫孔及一第三貫孔，該第一貫孔、該第二貫孔 - a該第三貫孔分別形成於該接觸窗、該源極及該汲極之上 - 丨相對位置’以分別顯露部分該上閘極、部分該源極及部 分該汲極；及⑴形成一電極組，其具有一第一電極、一第 一電極及一第二電極，分別設置於該第一貫孔、該第二貫 〇 A及該第三貫孔内’以分別電性連接該上閘極、該源極及 該沒極。 本發明之該半導體裝置之該上閘極及該下閘極互相接 觸，且連結於同一電極（該第一電極），使得該半導體裝置 之該上閘極及該下閘極環繞於該導電半導體層之該本體之 上方、下方及二側，以形成一近乎全環繞式閘極之結構。 藉此，本發明之該半導體裝置可克服上閘極與下閘極間之 耦合電容問題，故本發明之該半導體裝置具有較傳統矽覆 。 絕緣金屬氧化物半導體元件（SOI MOSFET)或鰭式場效電 晶體（FinFET)較大的電流驅動和次臨界轉換特性。 【實施方法】 參考圖1A至5B，其顯示本發明假閘極全環繞矽覆絕緣 裝置之製作方法。其中，圖1A、2A、3A、4八及从顯示沿 一第一方向之剖面圖；圖1B、2B、3B、4B及5B顯示沿一 第一方向之剖面圖。配合參考圖1A至2B，首先提供一基 板10，该基板1 〇具有一下閘極丨丨，該下閘極丨丨具有一第一 端ui及一第二端112，該第一端ln及該第二端112係沿一 123800.doc •10· 200919587 第一方向之相對二端。 該基板ίο可經由以下步驟製作而成。配合參考圖⑽ 1B，首先提供—承载板1G1，該承載板1G1可為—石夕基板。 . 接著，形成—埋入氧化層102於該承載板101上，其中，該 士里入氧化層102係利用低壓化^氣相沉積（LPCVD)或電衆 輔助化學氣相沈積（PECVD)方法形成。接著，利用低麼化 學氣相沉積方法形成一半導體層1〇3，其覆蓋該埋入氧化 〇 層102。再配合參考圖1A至2B，利用光學微影技術或電子 束直寫技術形成該半導體層103，以形成該下閘極u。 較佳地，在形成該下閘極U之後，另進行載子摻雜及高 溫熱退火（Thermal annealing)之步驟，使該下閘極u具有 導電性。在本實施例中，載子摻雜技術可為中電流離子佈 植（Ion Implantation)或尚溫熱驅入（in_situ)技術，且離子佈 植能量及劑量需視該下閘極n之厚度而定。其中，若摻雜 之載子為磷（P)或砷（As)，該下閘極11為1^型半導體；若摻 (J 雜之載子為硼（B)，該下閘極π為P型半導體。 要注意的是，該基板10亦可直接選用一般矽基板、矽覆 絕緣（soi)基板、鍺覆絕緣（G〇I)基板、玻璃、石英、鑽 石、塑膠或其他單層絕緣基板。若該基板1〇係為矽覆絕緣 基板，則該下閘極11係為單晶矽。 配合參考圖3A至4B，形成一下閘極氧化側壁2〇，該下 閘極氧化側壁2〇覆蓋該下閘極丨丨之侧面。在本實施例中， 該下閘極氧化側壁20係經由以下步驟製作而成。配合參考 圖3A及3B，形成一下閘極氧化層2〇1，其覆蓋該下閘極 123800.doc 200919587 Η。再配合參考圖3Α·，移除部分該下間極氧化層2〇ι 至顯露出該下間㈣之頂面，以形成該下閘極氧化側壁 2〇。較佳地’該下閘極氧化層加係以錢化學氣相沉積 或電漿辅助化學氣相沈積方法形成’利用化學機械研磨 (CMP)技術移除部分之該下閘極氧化層2()1，使該下間極氧 化側壁20之厚度與該下閘極u之厚度相同。 Ο 配合參考圖5A及5B，形成一下閉極介電層扣，該下間 極介電層30覆蓋該下閘極"及該下閘極氧化側壁。要注 意的是’若該下閘極U係為一多晶石夕層，該下閉極介電層 3〇係以低壓化學氣相沉積方法形成。然而，若該下閑極η 係為單晶石夕層，該下問極介電層3〇可利用低壓化學氣相沉 積方法或乾式熱氧化技術形成。200919587 IX. Description of the Invention: [Technical Field] The present invention relates to a coating insulation device and a method of fabricating the same, and more particularly to a false gate full-circumferential insulation device and a method of fabricating the same. [Prior Art] According to the evaluation of the International Semiconductor Technology Blueprint (ITRS), the short f-channel effect caused by the traditional gold oxide half-field effect transistor (M〇SFET) under the influence of continuous shrinkage has faced great challenges. Some scholars have proposed some solutions 'such as using SOI, Ultra thin b〇dy (UBT) and high-k gate dielectric layers (such as gossip 2〇3, Hf〇2, etc.) ) to solve the most serious leakage current problem; use double gate material, metal gate, multi-layer gate engineering or fin (Fin) gate to control gate threshold threshold voltage (Thresh〇id Voltage) with channel length reduction The curling downward (r〇11_〇ff) and the bungee lead to the energy barrier reduction (DIBL) effect. But using these solutions will also extend a series of problems (Issues), such as using the SOI to face the floating body effect and knee-knee effect (Kink Effec〇, self-heating effect and single latch up effect). UTB uses the relaxation leakage current problem and suppresses the ultra-short channel effect, but at the same time, it will face the increase of the source/drain series resistance, reduce the current drive capability, and the uneven planarization of the body, resulting in a critical threshold voltage that is too large. Problem. Because the traditional MOSFET has too many parasitic ?]^ junction capacitance, which makes the component switching speed and high-frequency response slower, and also causes source/pole leakage current. The use of SOI or UTB can reduce the parasitic pN junction. The practicality of the capacitor, which is not 123800.doc 200919587, is of course unquestionable. There are many solutions to the problem of excessive series resistance of the towel, such as increasing or deepening the source/dip thickness or adding deuterated metal to improve the conductivity and Reduce ohmic contact (Republic of China Patent Application No. 090108868, US Patent No. 6,825,535, mm] η). There are countermeasures for suppression (such as U.S. Patent No. 6,686,629, No. M37,375), such as forming a bismuth telluride epitaxy under the body to recombine the charge via surface effects, thereby avoiding the rise of the bulk potential. In the method of 'the most commonly used techniques such as shallow cloth source / bungee 〇 ^ 〇) technology or use ultra-steep junction (such as US Patent No. 6,465,847) or halo (Hal〇) ion implantation (such as the US patent 6,936,278) to suppress the (40) of the depletion zone, but there are considerations in terms of cost and complexity. We would like to have some practical (4), such as reducing the number of process steps, reducing the number of times the mask and ion implantation are used. ο Furthermore, the critical threshold voltage that determines component performance is more important. In the future, the surrounding gate (Gate all can improve the margin between the body and the surrounding insulation layer), but the difficulty of fabrication will be greatly improved. However, the beautiful charge-coupled effect effect and the power loss can simultaneously solve the above problems. Structure to change and some self-performance and reduce process complexity. Under the size of the miniature situation around) will be more rare, fundamentally must consider the mechanism of the meta-I alignment to increase the components at the same time, therefore, it is necessary to provide An innovative and sturdy, sturdy gated full-circumferential insulation device and its manufacturing method to solve the above problems. SUMMARY OF THE INVENTION The object of the present invention is to provide a false gate full-around 11-covered insulating package 123800.doc 200919587. The dummy gate full-covering insulating device comprises: a substrate, a lower electrode oxidized sidewall, a lower gate dielectric layer, a conductive semiconductor layer, an upper gate dielectric layer, an upper gate, a side lining, An oxidation protective layer and an electrode group. The substrate has a lower gate, the lower gate has a first end and a second end, and the first end and the second end are opposite ends of a first direction. The lower gate oxide sidewall covers the side of the lower gate. The lower gate dielectric layer covers the lower gate and the lower gate oxide sidewall, and has a contact window, and the Q contact window is formed at a relative position above the periphery of the first end of the lower gate to reveal Part of the lower gate. The conductive semiconductor layer has a body, a source and a drain. The body is formed substantially on a middle portion of the lower gate dielectric layer. The source and the drain are formed on the body along a second direction. The second side is substantially perpendicular to the first direction. The upper gate dielectric layer covers the lower gate dielectric layer at a relative position above the lower gate, the top surface of the body and the two sides of the body along the first direction, and the two sides are perpendicular to the first direction . The upper gate covers the lower gate dielectric layer, the contact window and the upper gate dielectric layer along the first direction. The edge liner is formed on the upper side of the upper gate dielectric layer and the upper gate, and the two opposite sides are perpendicular to the second direction. The oxidized protective layer covers the source, the drain, the edge lining and the upper gate, and has a first through hole, a second through hole and a third through hole. The 帛 consistent (3), the second The through hole and the third through hole are respectively formed at opposite positions of the contact window, the source and the drain to respectively expose a portion of the upper gate, a portion of the source and a portion of the drain. The electrode group has a first electrode, a second electrode and a third electrode, respectively disposed in the first through hole, the second through hole and the third through hole, respectively, to electrically connect the upper 123800. Doc 200919587 Gate, the source and the pole. Another object of the present invention is to provide a method for fabricating a false gate full-wrap insulating device, comprising the steps of: (4) providing a substrate having a -τ gate and the lower gate having - - terminal and - second end, the [end and the second end are along the opposite ends of the - direction - (8) forming a gate oxide oxidation sidewall covering the side of the lower gate; (C) forming a a gate dielectric layer covering the lower interpole and the lower interpole oxidation sidewall; (4) forming a germanium-conductive semiconductor layer having a -part portion, a second portion and a third portion, the first portion being substantially formed The first portion and the third portion are formed on the middle portion of the lower gate dielectric layer on the side of the first portion along a first direction, the second direction being substantially perpendicular to the first direction (4) An upper gate dielectric layer covering the conductive semiconductor layer and the lower gate dielectric layer; (1) forming a contact window through the upper gate dielectric layer and the lower gate dielectric layer, and Forming a relative position above the circumference of the first end of the lower gate to a portion of the lower electrode; (4) forming an upper drain ' covering the contact window, the exposed lower gate, the lower gate dielectric layer, and the upper gate dielectric layer; (h) along the first Removing a portion of the upper gate and the upper gate dielectric layer in a direction, the unselected upper gate and the upper gate dielectric S" have the same visibility and are located above the lower gate a position, wherein the upper gate covers the lower gate dielectric layer, the contact window, the lower gate and the upper gate dielectric layer along the first direction; (1) forming a side liner covering the upper closed polarity And an opposite side of the upper layer, wherein the two opposite sides are perpendicular to the first direction, (1) performing an ion implantation step on the first portion, the second portion, and the third portion of the conductive semiconductor layer A portion correspondingly forms 123800.doc 200919587 - a body-source and a finite electrode; (k) forming an oxidized protective layer covering the source, the drain, the side and the upper gate, having a a first through hole, a second through hole and a third through hole, the first through hole, the second through hole - a the third through hole respectively Forming on the contact window, the source and the drain - a relative position 'to expose a portion of the upper gate, a portion of the source and a portion of the drain; and (1) forming an electrode group having a first An electrode, a first electrode and a second electrode are respectively disposed in the first through hole, the second through hole A and the third through hole to electrically connect the upper gate and the source respectively The upper gate and the lower gate of the semiconductor device of the present invention are in contact with each other and are connected to the same electrode (the first electrode) such that the upper gate and the lower gate of the semiconductor device are surrounded The structure of the conductive semiconductor layer is formed above, below and on both sides to form a nearly full-wrap gate. Thereby, the semiconductor device of the present invention can overcome the coupling capacitance between the upper gate and the lower gate. The problem is that the semiconductor device of the present invention has a more conventional coating. Insulated metal oxide semiconductor devices (SOI MOSFETs) or fin field effect transistors (FinFETs) have large current drive and subcritical switching characteristics. [Embodiment] Referring to Figures 1A to 5B, there is shown a method of fabricating a false gate full-wrap insulating device of the present invention. 1A, 2A, 3A, 4B and a cross-sectional view taken along a first direction; Figs. 1B, 2B, 3B, 4B and 5B show cross-sectional views along a first direction. Referring to FIGS. 1A to 2B, a substrate 10 is first provided, the substrate 1 has a lower gate 丨丨, the lower gate 丨丨 has a first end ui and a second end 112, the first end ln and the The second end 112 is along the opposite ends of a first direction of 123800.doc •10·200919587. The substrate ίο can be fabricated through the following steps. With reference to the reference diagram (10) 1B, a carrier board 1G1 is first provided, and the carrier board 1G1 can be a Shishi substrate. Next, a buried oxide layer 102 is formed on the carrier plate 101, wherein the oxide oxide layer 102 is formed by a low pressure vapor deposition (LPCVD) or a plasma assisted chemical vapor deposition (PECVD) method. . Next, a semiconductor layer 1 〇 3 is formed by a low chemical vapor deposition method, which covers the buried ruthenium oxide layer 102. Referring again to Figures 1A through 2B, the semiconductor layer 103 is formed by optical lithography or electron beam direct writing to form the lower gate u. Preferably, after the lower gate U is formed, a step of carrier doping and thermal annealing is performed to make the lower gate u conductive. In this embodiment, the carrier doping technique may be a medium current ion implantation (Ion Implantation) or a thermal inrush (in_situ) technique, and the ion implantation energy and the dose are determined according to the thickness of the lower gate n. set. Wherein, if the doped carrier is phosphorus (P) or arsenic (As), the lower gate 11 is a semiconductor of the type 1; if the carrier of the mixed impurity is boron (B), the lower gate π is P-type semiconductor. It should be noted that the substrate 10 can also be directly selected from a general germanium substrate, a soon substrate, a germanium-insulated (G〇I) substrate, glass, quartz, diamond, plastic or other single-layer insulation. If the substrate 1 is a covered insulating substrate, the lower gate 11 is a single crystal germanium. Referring to FIGS. 3A to 4B, a lower gate oxide sidewall 2〇 is formed, and the lower gate oxide sidewall 2〇 Covering the side surface of the lower gate electrode. In the embodiment, the lower gate oxide sidewall 20 is formed through the following steps. Referring to FIGS. 3A and 3B, a gate oxide layer 2〇1 is formed, which is covered. The lower gate 123800.doc 200919587 Η. With reference to FIG. 3Α, a portion of the lower interpole oxide layer 2〇ι is removed to reveal the top surface of the lower (4) to form the lower gate oxide sidewall 2〇 Preferably, the lower gate oxide layer is formed by a chemical vapor deposition or a plasma assisted chemical vapor deposition method. A portion of the lower gate oxide layer 2()1 is removed by a chemical mechanical polishing (CMP) technique such that the thickness of the lower interpole oxidation sidewall 20 is the same as the thickness of the lower gate u. 配合 Refer to FIGS. 5A and 5B. Forming a closed-cell dielectric layer buckle, the lower inter-electrode layer 30 covering the lower gate " and the lower gate oxidation sidewall. It should be noted that if the lower gate U is a polycrystalline stone The lower closed dielectric layer 3 is formed by a low pressure chemical vapor deposition method. However, if the lower idle pole η is a single crystal layer, the lower dielectric layer 3 can be utilized with a low voltage. Formed by chemical vapor deposition or dry thermal oxidation techniques.
配合參考圖6Α及6Β，形成一導電半導體層4〇， 第邛刀4〇1、一第二部分4〇2及一第三部分4〇3 部分401大致形成於該下閘極介電層3〇之中間部 其具有 ，該第 分上， 該第=部分4〇2及該第三部分4〇3形成於該第一部分々Μ沿 著-第二方向之二側邊，該第二方向大致垂直該第一： 向。 在本實施例中，該導電半導體層4〇係以低壓化學氣相沉 積、常壓化學氣相沉積(APCVD)或電漿輔助化學氣相沈積 技術形成，其中，該導電半導體層4〇可為多晶矽 (P〇lyS1llcon)或非晶石夕（amorph〇us siHc〇n)。較佳地，本發 明利用高溫回火方法進行固相再結晶成長（spc)或利用準 分子雷射回火（ELA)方法進行再結晶，以改善該導電半導 123800.doc -12- 200919587 體層40之品質及減少該導電半導體層⑽之缺陷。 在本實施例中，在形成該導電半導體層4〇步驟之後，另 包括-第-熱退火之步驟，該第一熱退火步驟係利用快速 * 升温熱退火（RTA)技術或利用高溫爐管退火（furnace - anneal)。較佳地，該第一熱退火步驟之退火溫度係介於 8〇(TC至95CTC，該第—熱退火步驟之退火時間係介於丨分 鐘至30分鐘之間。 〇 配合參考圖7A及7B，形成一上閘極介電層5〇，較佳 地，該上閘極介電層50係以低壓化學氣相沉積#法或乾式 熱氧化技術形成。該上閘極介電層5〇覆蓋該導電半導體層 40及該下閘極介電層3〇。配合參考圖8入及8B，形成一接 觸窗，該接觸窗31係貫穿該上閘極介電層5〇及該下間極 介電層30,且形成於該下閘極n之該第一端lu之周緣上 方相對位置，以顯露出部分該下閘極丨丨。在本實施例中， 該接觸窗3 1係經由以下步驟製作而成。首先，利用微影製 Ij ㈣義-光罩。接著，以㈣方法形成該接觸窗3 1。較佳 地，該微影製程係為光學微影技術或電子束微影技術 beam)。較佳地，該光學微影技術係使用i_line、g_Hne或深 紫外光（DUV)。 配合參考圖9A及9B，形成一上閘極6〇 ,其覆蓋該接觸 窗31、顯露之該下閘極丨丨、該下閘極介電層3〇及該上閘極 介電層50。配合參考圖1〇A及1〇B，沿該第一方向移除部 分該上閘極60及部分該上閘極介電層50，未移除之該上閘 極6〇及該上閘極介電層5〇具有相同寬度且位於該下閘極^ 1238⑻.doc -13- 200919587 上方之相對位置，其中該上閘極60沿該第一方向覆蓋該下 閘極介電層30、該接觸窗31、該下閘極11及該上閘極介電 層50。在本實施例中，該上閘極60係以低壓化學氣相沉積 或電漿輔助化學氣相沈積方法形成多晶矽層。較佳地，該 上閘極60係利用中電流離子佈植或高溫熱驅入技術進行摻 雜步驟。 配&多考圖11A及11B，形成一邊概（side-well spacer) 7〇，該邊襯70覆蓋該上閘極介電層5〇及該上閘極6〇之二相 對侧面，該二相對側面係垂直於該第二方向。在本實施例 中，該邊襯70係利用低壓化學氣相沉積方法地毯式成長一 層二氧化矽層或氮化矽層，再利用自我對準方法蝕刻該二 氧化石夕層或該氮化石夕層而成。 配合參考圖11A、11B及12A、12B，進行一離子佈植步 驟，於該導電半導體層4〇之該第一部分4〇1、該第二部分 402及該第三部分403相對應地形成一本體41、一源極42及 一沒極4 3。 在本實施例中，其係以該上閘極7〇作為自我對準之硬式 遮罩，利用離子佈植方法形成該本體41、該源極42及該汲 極43。在該離子佈植步驟之後，另包括一第二熱退火步 驟，該第二熱退火步驟係、利用快速升溫熱退火技術或利用 瞬間升溫熱退火（spike anneal)。其中，該第二熱退火步驟 之退火溫度係介於^^(:至丨丨⑻它之間，該第二熱退火步 驟之退火時間係介於〇 · 2秒至3 〇秒之間。 配合參考圖13A及13B，形成一氧化保護層8〇 ,該氧化 123800.doc -14- 200919587 保濩層80覆蓋該源極42、該汲極43、該邊襯70及該上閘極 60該氧化保護層具有一第一貫孔$ 1、一第二貫孔μ及 一第二貫孔83，該第一貫孔81、該第二貫孔82及該第三貫 ' 孔83分別形成於該接觸窗31、該源極42及該汲極43之上方 相對位置，以分別顯露部分該上閘極6〇、部分該源極42及 部分該汲極43。 在本實施例中，該氧化保護層8〇係利用電漿輔助化學氣 q 相沉積或旋塗式塗佈法（Spin-〇n Dielectric ; SOD)形成， 該第一貫孔81、該第二貫孔82及該第三貫孔83係利用光學 微影技術或電子束直寫技術所形成。 接著’形成一電極組90，該電極組90具有一第一電極 91、一第二電極92及一第三電極93，分別設置於該第一貫 孔8 1、該第二貫孔82及該第三貫孔83内，以分別電性連接 該上閘極60、該源極42及該沒極43。 在本實施例中，該電極組90係經由以下步驟製作而成。 〇 首先，形成一金屬層，該金屬層覆蓋該氧化保護層80、該 第一貫孔81、該第二貫孔82及該第三貫孔83。接著，移除 部分該金屬層，以形成該電極組9〇。較佳地，該金屬層係 • 利用物理氣相沉積（PVD)方法形成，或者該金屬層亦可利 用賤鑛（sputtering)或蒸鍍（evap0rati〇n)方法形成。其中， 該第一電極91、該第二電極92及該第三電極93係利用光學 微影技術或電子束直寫技術定義其結構及形狀。 再參考圖13A及13B，其顯示本發明假閘極全環繞矽覆 絕緣裝置。該假閘極全環繞矽覆絕緣裝置1包括：一基板 123800.doc •15· 200919587 、一下閘極氧化側壁20、一下閘極介電層3〇、一導電半 導體層40、—上閘極介電層50、一上閘極60、一邊襯7〇、 一氧化保護層80及一電極組90。 該基板10具有一下閘極U，該下閘極U具有—第—端 Π1及一第二端112，該第一端U1及該第二端112係沿—第 一方向之相對二端。其中，該基板10可為一般矽基板、矽 覆絕緣基板、鍺覆絕緣基板、玻璃、石英、鑽石、塑膠或 其他單層絕緣基板。要注意的是，依據摻雜之載子之= 同，該下閘極11可為N型半導體（摻雜之載子為磷或砷）或p 型半導體（摻雜之載子為硼）。 該下閘極氧化側壁20覆蓋該下閘極丨丨之側面。較佳地， 該下閘極11厚度為50奈米至2〇〇奈米。較佳地，該下閘極 氧化側壁20之材質係選自由二氧化矽（Si〇2)、氮化矽 (Si3N4)、氧氮氧（ONO)、氧化鋁（Al2〇3)或矽化碳（sic)。 該下閘極介電層30覆蓋該下閘極丨丨及該下閘極氧化側壁 20該下閘極介電層30具有一接觸窗31，該接觸窗31形成 於》亥下閘極11之該第一端丨丨丨之周緣上方相對位置，以顯 路出部分該下閘極11。較佳地，該下閘極介電層3〇之材質 係選自由二氧化矽、氮化矽、氧化钽、氧化铪 (HGO)、氧化锆（Zr〇2)或等效厚度〇 5奈米至5〇奈米之設定 问”電常數值介電材料。在本實施例中，該設定高介電常 數值大於10。 „亥導电半導體層40具有—本體41、一源極42及一汲極 43，該本體41大致形成於該下閘極介電層3〇之中間部分 123800.doc -16- 200919587 上，該源極42及該汲極43形成於該本體“沿著一第二方向 之二側邊，該第二方向大致垂直該第一方向。其中，該導 電半導體層40可為多晶石夕（p〇lysinc〇n)或非晶石夕（am〇啡_ slnc〇n)。該導電半導體層40係選自由第四族、m々族材 料或其所組成之群之單層或多層結構。較佳地，該導電半 導體層40之厚度係為〇·5奈米至1〇〇奈米。 該上閘極介電層5〇沿該第—方向覆蓋該下閘極η上方相 對位置之該下間極介電層3G、該第—部分術之—頂面及 該第-部分401之二側面’二側面係垂直該第一方向。較 佳地，該上閘極介電㈣之㈣係選自由二氧切、氮化 石夕、氧化组、氧化給（Hf2〇)、氧化錯或等效厚度〇5奈米至 50奈米之設定高介電常數值介電材料。在本實施例中，該 設定高介電常數值大於1〇。 該上閑極60沿該第-方向覆蓋該下閘極介電⑽、該接 觸窗31及該上問極介電層5〇。較佳地，該上閘極60之厚度 為50不米至200奈米。其中，該上閘極6〇係為一多晶矽 層，且該上閘極60可為N型半導體或？型半導體。較佳地， 該多曰曰石夕層係為成長單層或多層之中能隙金屬 或金屬石夕化物（silicide)。該邊襯7〇形成於該上間極介電層 5〇及該上閘極60之二相對側面，該二相對側面係垂直於該 第一方向。 〜氧化保濩層8〇覆蓋該源極42、該汲極43、該邊襯及 :上閘極60。該氧化保護層⑽具有—第—貫㈣、一第二 貫孔82及-第三貫孔83。該第一貫孔81、該第二貫孔82及 123800.doc •17- 200919587 該第三貫孔83分別形成於該接觸窗3丨、該源極42及該汲極 43之上方相對位置’以分別顯露部分該上閘極6〇、部分該 源極42及部分該汲極43。較佳地，該氧化保護層8〇係為二 氧化矽、磷矽玻璃（PSG)、硼磷矽玻璃（BPSG)、氟矽玻璃 (Fluorinated Silicate Glass ; FSG)、鑽石（Diamond)或其他 低介電係數之材質。 該電極組90具有一第一電極91、一第二電極92及一第三 電極93，分別設置於該第一貫孔81、該第二貫孔82及該第 三貫孔83内，以分別電性連接該上閘極6〇、該源極42及該 汲極43。較佳地，該電極組9〇係為鋁（A1)、銅（Cu)或鋁矽 銅合金（Al-Si-Cu)。 本發明之假閘極全環繞矽覆絕緣裝置及其製作方法中， 該半導體裝置1之該上閘極60及該下閘極丨丨互相接觸，且 連結於同一電極（該第一電極91)，使得該半導體裝置i之該 上閘極60及該下閘丨丨極環繞於該導電半導體層4〇之該本體 41之上方、下方及一側，以形成一近乎全環繞式閘極之結 構。藉此，本發明之該半導體裝置i可克服上閘極與下閘 極間之耦合電容問題，故本發明之該半導體裝置丨具有較 傳統矽覆絕緣金屬氧化物半導體元件（s〇I m〇sfet)或鰭 式场效電晶體（Fin FET)較大的電流驅動和次臨界轉換特 性。 惟上述實施例僅為說明本創作之原理及其功效，而非用 以限制本創作。因此，習於此技術之人士對上述實施例進 行修改及變化仍不脫本創作之精神。本創作之權利範圍應 123800.doc -18- 200919587 如後述之申請專利範圍所列。 【圖式簡單說明】 圖1A及1B顯示本發明之基板示意圖； ' 圖2A及2B顯示本發明於該基板形成一下閘極之示意 圖； 圖3A及3B顯示本發明形成一下閘極氧化層覆蓋該下閘 極之示意圖； ^ 圖4 A及4B顯示本發明形成一下閘極氧化側壁之示意 園， 圖5Α及5Β顯示本發明形成一下閘極介電層之示意圖； 圖6A及6B顯示本發明形成一導電半導體層之示意圖； 圖7A及7B顯示本發明形成一上閘極介電層之示意圖； 圖8A及8B顯示本發明形成一接觸窗之示意圖； 圖9A及9B顯示本發明形成一上閘極之示意圖； 圖10A及10B顯示本發明移除部分該上閘極及部分該上 〇 閘極介電層之示意圖； 圖11A及11B顯不本發明形成一邊概之示意圖； 圖12A及12B顯示本發明於該導電半導體層進行一離子 . 佈植步驟，以形成一本體、一源極及一汲極之示意圖；及 圖13A及13B顯示本發明假閘極全環繞矽覆絕緣裝置之 示意圖。 【主要元件符號說明】 1 本發明假閘極全環繞矽覆絕緣裝置 1〇 基板 123800.doc -19- 200919587 11 下閘極 20 下閘極氧化側壁 30 下閘極介電層 31 接觸窗 40 導電半導體層 41 本體 42 源極 43 汲極 50 上閘極介電層 60 上閘極 70 邊襯 80 氧化保護層 81 第一貫孔 82 第二貫孔 83 第三貫孔 90 電極組 91 第一電極 92 第二電極 93 第三電極 111 第一端 112 第二端 401 第一部分 402 第二部分 403 第三部分 123800.doc -20Referring to FIGS. 6A and 6B, a conductive semiconductor layer 4?, a first trowel 4?1, a second portion 4?2, and a third portion 4?3 portion 401 are formed substantially on the lower gate dielectric layer 3. The middle portion of the crucible has, on the first portion, the first portion 4〇2 and the third portion 4〇3 are formed on the two sides of the first portion 々Μ along the second direction, the second direction is substantially Vertical first: toward. In this embodiment, the conductive semiconductor layer 4 is formed by low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition (APCVD) or plasma assisted chemical vapor deposition, wherein the conductive semiconductor layer 4 Polycrystalline germanium (P〇lyS1llcon) or amorphous austenite (amorph〇us siHc〇n). Preferably, the present invention utilizes a high temperature tempering method for solid phase recrystallization growth (spc) or recrystallization by excimer laser tempering (ELA) to improve the conductive semiconducting layer 123800.doc -12-200919587 40 quality and reduce the defects of the conductive semiconductor layer (10). In this embodiment, after the step of forming the conductive semiconductor layer 4, a step of - a first thermal annealing step is performed, which is performed by using a rapid* thermal annealing (RTA) technique or using a high temperature furnace tube annealing. (furnace - anneal). Preferably, the annealing temperature of the first thermal annealing step is between 8 〇 and TC to 95 CTC, and the annealing time of the first thermal annealing step is between 丨 minute and 30 minutes. 〇 参考 参考 参考 7 参考 参考 参考 参考An upper gate dielectric layer 5 is formed. Preferably, the upper gate dielectric layer 50 is formed by a low pressure chemical vapor deposition method or a dry thermal oxidation technique. The upper gate dielectric layer 5 is covered. The conductive semiconductor layer 40 and the lower gate dielectric layer 3 are formed. Referring to FIG. 8 and 8B, a contact window is formed. The contact window 31 extends through the upper gate dielectric layer 5 and the lower gate dielectric. The electrical layer 30 is formed at a relative position above the periphery of the first end lu of the lower gate n to expose a portion of the lower gate 丨丨. In this embodiment, the contact window 31 is subjected to the following steps. First, the lithography Ij (four) sense-mask is used. Then, the contact window 31 is formed by the method of (4). Preferably, the lithography process is optical lithography or electron beam lithography. ). Preferably, the optical lithography technique uses i_line, g_Hne or deep ultraviolet light (DUV). Referring to Figures 9A and 9B, an upper gate 6A is formed which covers the contact window 31, the exposed lower gate electrode, the lower gate dielectric layer 3A, and the upper gate dielectric layer 50. Referring to FIGS. 1A and 1B, a portion of the upper gate 60 and a portion of the upper gate dielectric layer 50 are removed along the first direction, and the upper gate 6〇 and the upper gate are not removed. The dielectric layer 5 has the same width and is located at a position above the lower gate 1238 (8).doc -13 - 200919587, wherein the upper gate 60 covers the lower gate dielectric layer 30 along the first direction, the contact Window 31, the lower gate 11 and the upper gate dielectric layer 50. In the present embodiment, the upper gate 60 is formed of a polycrystalline germanium layer by a low pressure chemical vapor deposition or a plasma assisted chemical vapor deposition method. Preferably, the upper gate 60 is subjected to a doping step using a medium current ion implantation or a high temperature thermal drive technique. And a plurality of side-well spacers 7A and 11B, the side liner 70 covering the upper side of the upper gate dielectric layer 5 and the upper gate 6〇, the two The opposite sides are perpendicular to the second direction. In this embodiment, the edge liner 70 is formed by a low pressure chemical vapor deposition method to grow a layer of ruthenium dioxide or tantalum nitride by a low pressure chemical vapor deposition method, and then etching the dioxide layer or the nitrite by a self-alignment method. Layered. Referring to FIGS. 11A, 11B and 12A, 12B, an ion implantation step is performed to form a body corresponding to the first portion 4?1, the second portion 402, and the third portion 403 of the conductive semiconductor layer 4? 41. One source 42 and one pole 4 3 . In the present embodiment, the upper gate 7A is used as a self-aligned hard mask, and the body 41, the source electrode 42, and the anode 43 are formed by ion implantation. After the ion implantation step, a second thermal annealing step is further included, which utilizes a rapid thermal annealing technique or a spike anneal. The annealing temperature of the second thermal annealing step is between ^^(: to 丨丨(8), and the annealing time of the second thermal annealing step is between 〇·2 seconds and 3 〇 seconds. Referring to FIGS. 13A and 13B, an oxidized protective layer 8 is formed, and the oxidized layer 123800.doc -14-200919587 protects the source 42 , the drain 43 , the edge liner 70 and the upper gate 60 from oxidation. The protective layer has a first through hole $1, a second through hole μ and a second through hole 83. The first through hole 81, the second through hole 82 and the third through hole 83 are respectively formed in the hole. The contact window 31, the source 42 and the upper position of the drain 43 respectively expose a portion of the upper gate 6 〇, a portion of the source 42 and a portion of the drain 43. In this embodiment, the oxidation protection The layer 8 is formed by a plasma-assisted chemical gas q-phase deposition or a spin-on coating (SOD), the first through hole 81, the second through hole 82, and the third through hole. The 83 series is formed by an optical lithography technique or an electron beam direct writing technique. Next, an electrode group 90 is formed, the electrode group 90 having a first electrode 91 and a second electrode. 92 and a third electrode 93 are respectively disposed in the first through hole 8 1 , the second through hole 82 and the third through hole 83 to electrically connect the upper gate 60 and the source 42 respectively In the present embodiment, the electrode group 90 is fabricated through the following steps: First, a metal layer is formed, the metal layer covering the oxidation protection layer 80, the first through hole 81, the first a through hole 82 and the third through hole 83. Then, a portion of the metal layer is removed to form the electrode group 9. Preferably, the metal layer is formed by a physical vapor deposition (PVD) method, or The metal layer may also be formed by a sputtering or vapor deposition method, wherein the first electrode 91, the second electrode 92, and the third electrode 93 utilize optical lithography or electron beam. The direct writing technique defines its structure and shape. Referring again to Figures 13A and 13B, there is shown a false gate full-wrap insulating device of the present invention. The false gate full-wrap insulating device 1 comprises: a substrate 123800.doc • 15 · 200919587, the next gate oxide sidewall 20, the lower gate dielectric layer 3〇, a guide a semiconductor layer 40, an upper gate dielectric layer 50, an upper gate 60, a side liner 7, an oxidation protection layer 80, and an electrode group 90. The substrate 10 has a lower gate U, and the lower gate U has - a first end U1 and a second end 112, the first end U1 and the second end 112 are along the opposite ends of the first direction. The substrate 10 can be a general germanium substrate, a covered insulating substrate, Covering the insulating substrate, glass, quartz, diamond, plastic or other single-layer insulating substrate. It should be noted that the lower gate 11 can be an N-type semiconductor (doped carrier) according to the doping carrier. It is a phosphorus or arsenic or a p-type semiconductor (the doped carrier is boron). The lower gate oxide sidewall 20 covers the side of the lower gate. Preferably, the lower gate 11 has a thickness of 50 nm to 2 nm. Preferably, the material of the lower gate oxide sidewall 20 is selected from the group consisting of cerium oxide (Si〇2), cerium nitride (Si3N4), oxynitride (ONO), aluminum oxide (Al2〇3) or deuterated carbon ( Sic). The lower gate dielectric layer 30 covers the lower gate electrode and the lower gate oxide sidewall 20. The lower gate dielectric layer 30 has a contact window 31 formed on the lower gate 11 A relative position above the circumference of the first end turns to reveal a portion of the lower gate 11. Preferably, the material of the lower gate dielectric layer 3 is selected from the group consisting of ceria, tantalum nitride, hafnium oxide, hafnium oxide (HGO), zirconium oxide (Zr〇2) or equivalent thickness of 奈5 nm. In the case of the setting of 5 nanometers, "electric constant value dielectric material. In the present embodiment, the set high dielectric constant value is greater than 10. The conductive semiconductor layer 40 has a body 41, a source 42 and a The body 41 is formed substantially in the middle portion 123800.doc -16 - 200919587 of the lower gate dielectric layer 3, and the source 42 and the drain 43 are formed on the body "along a second The second direction of the direction is substantially perpendicular to the first direction. The conductive semiconductor layer 40 may be a polycrystalline spine or an amorphous alum (am 〇 sl 〇 slnc〇n The conductive semiconductor layer 40 is selected from a single layer or a multilayer structure of a group of Group 4, m々 materials or a group thereof. Preferably, the thickness of the conductive semiconductor layer 40 is 〇·5 nm to 1 〇〇 nanometer. The upper gate dielectric layer 5 覆盖 covers the lower interposer dielectric layer 3G at a relative position above the lower gate η along the first direction, the first The top surface and the second side of the first portion 401 are perpendicular to the first direction. Preferably, the upper gate dielectric (four) is selected from the group consisting of dioxin, nitriding, and oxidation. a high dielectric constant value dielectric material set in the group, oxidized (Hf2 〇), oxidized or equivalent thickness 〇 5 nm to 50 nm. In the present embodiment, the set high dielectric constant value is greater than 1 〇. The upper idler 60 covers the lower gate dielectric (10), the contact window 31 and the upper dielectric layer 5〇 along the first direction. Preferably, the upper gate 60 has a thickness of 50 mm. Up to 200 nm, wherein the upper gate 6 is a polysilicon layer, and the upper gate 60 can be an N-type semiconductor or a ?-type semiconductor. Preferably, the polysilicon layer is a growth sheet a layer or a plurality of layers of a gap metal or a metal silicide. The edge liner 7 is formed on the opposite side of the upper interposer dielectric layer 5 and the upper gate 60, the opposite sides being perpendicular In the first direction, the oxidized protective layer 8 〇 covers the source 42 , the drain 43 , the lining and the upper gate 60. The oxidized protective layer (10) has — a fourth through hole 82 and a third through hole 83. The first through hole 81, the second through hole 82, and 123800.doc • 17-200919587 are formed in the contact The window 3, the source 42 and the upper position of the drain 43 are respectively exposed to partially expose the upper gate 6 〇, the portion of the source 42 and a portion of the drain 43. Preferably, the oxidized protective layer 8 The lanthanide is cerium oxide, phosphoric bismuth glass (PSG), borophosphoquinone glass (BPSG), fluorinated glass (FSG), diamond (Diamond) or other low dielectric constant materials. The electrode assembly 90 has a first electrode 91, a second electrode 92, and a third electrode 93. The first electrode 91, the second through hole 82, and the third through hole 83 are respectively disposed in the first through hole 91, respectively. The upper gate 6 〇, the source 42 and the drain 43 are electrically connected. Preferably, the electrode group 9 is aluminum (A1), copper (Cu) or aluminum beryllium copper alloy (Al-Si-Cu). In the dummy gate full-surrounding and covering insulating device of the present invention, the upper gate 60 and the lower gate electrode of the semiconductor device 1 are in contact with each other and are connected to the same electrode (the first electrode 91) The upper gate 60 and the lower gate of the semiconductor device i surround the upper, lower and side sides of the body 41 of the conductive semiconductor layer 4 to form a structure of a nearly full-wrap gate. . Thereby, the semiconductor device i of the present invention can overcome the coupling capacitance problem between the upper gate and the lower gate, so the semiconductor device of the present invention has a more conventional overlying insulating metal oxide semiconductor device (s〇I m〇). Sfet) or fin field effect transistor (Fin FET) with large current drive and sub-critical switching characteristics. However, the above embodiments are merely illustrative of the principles and functions of the present invention and are not intended to limit the present invention. Therefore, those skilled in the art can modify and change the above embodiments without departing from the spirit of the present invention. The scope of the rights of this creation shall be 123800.doc -18- 200919587 as listed in the scope of the patent application described later. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A and FIG. 1B are schematic diagrams showing a substrate of the present invention; FIG. 2A and FIG. 2B are diagrams showing the present invention for forming a lower gate on the substrate; FIGS. 3A and 3B are views showing the formation of a gate oxide layer of the present invention. FIG. 4A and FIG. 4B show schematic views of the present invention forming a gate oxide sidewall, and FIGS. 5A and 5B show a schematic diagram of forming a gate dielectric layer of the present invention; FIGS. 6A and 6B show the formation of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 7A and Figure 7B show a schematic diagram of an upper gate dielectric layer of the present invention; Figures 8A and 8B show a schematic diagram of a contact window of the present invention; Figures 9A and 9B show the present invention forming a gate. 10A and 10B are schematic views showing the removal of a portion of the upper gate and a portion of the upper gate dielectric layer of the present invention; and FIGS. 11A and 11B show a schematic diagram of the present invention; FIGS. 12A and 12B show The present invention performs an ion implantation step on the conductive semiconductor layer to form a schematic diagram of a body, a source and a drain; and FIGS. 13A and 13B show the dummy gate full-circle insulation device of the present invention. Schematic diagram. [Main component symbol description] 1 The present invention is a false gate full-circle insulation device 1〇 substrate 123800.doc -19- 200919587 11 lower gate 20 lower gate oxidation sidewall 30 lower gate dielectric layer 31 contact window 40 conductive Semiconductor layer 41 body 42 source 43 drain 50 upper gate dielectric layer 60 upper gate 70 side liner 80 oxide protective layer 81 first through hole 82 second through hole 83 third through hole 90 electrode group 91 first electrode 92 second electrode 93 third electrode 111 first end 112 second end 401 first part 402 second part 403 third part 123800.doc -20