KR20090081603A - Method of fabricating self-aligned three dimensional transistor - Google Patents

Abstract

A method for fabricating a self aligned three dimensional transistor is provided to limit the height of a gate by using a mask layer as a planarization stop layer in a planarization process. A mask having a shape of a source forming area, a drain forming area, and a channel forming area is formed on a substrate including a silicon layer on a first insulating layer. The silicon layer is patterned by the mask. The mask is etched on the channel forming area. An undercut is formed in the lower part of the channel forming area. A nano wire channel(118) is formed by thermally oxidizing the channel forming area. A gate oxide layer(160) is formed on the nano wire channel. A gate material covering the mask is deposited on the substrate. A gate is formed by planarizing the gate material using the mask as a CMP stop layer. The mask is removed. A source(115') and a drain(117') are formed by irradiating the impurity from the substrate.

Description

Method of fabricating self-aligned three dimensional transistor

The present invention relates to a method of manufacturing self-alignment of a three-dimensional transistor, and more particularly, to a method of manufacturing by aligning the three-dimensional gate on the nanowire channel.

Metal oxide semiconductor field effect transistors (MOSFETs), which are unit devices of highly integrated logic circuits, are being scaled down to improve performance and integration. As the scaling down of the MOSFET progresses, the distance between the source and the drain becomes shorter, resulting in a short channel effect, a phenomenon in which a drain field modulates a gate field applied to a channel. This lowers the channel controllability of the gate. This phenomenon is manifested by electrical characteristics such as punch-through, drain-induced barrier lowering (DIBL), and threshold voltage roll-off.

The short channel effect (SCE) is severe in transistors with very short gate lengths, eg gate lengths of less than 50 nm, which can undermine the switching function, which is the basic function of transistors. To solve this problem, channel doping, ultra-shallow junction, gate dielectric thinning, etc. are used. However, there are limitations such as random doping problem and gate leakage.

Various three-dimensional multiple gate transistors have been proposed to solve this problem. FinFETs with double gates, tri-gate transistors, and gate-all-around transistors are examples, all of which control the channel on multiple sides of the channel, resulting in gate controllability. ) Increases.

In particular, the short channel transistor is a nanowire having a small diameter of a channel, and in manufacturing such a transistor, gate controllability may be reduced due to misalignment of the gate. In addition, when the gate width is narrower than the channel width, the channel may be broken during the patterning of the gate. In addition, it is difficult to fabricate the gate so that it is aligned across the source and drain, and it is difficult to limit the height of the gate by the planarization process.

The present invention provides a manufacturing method for easily defining the height of the gate while self-aligning the position of the gate on the channel in manufacturing a short channel transistor having a nanowire channel.

Self-aligned manufacturing method of the three-dimensional transistor according to an embodiment of the present invention:

Forming a mask having a shape of a source forming region, a drain forming region, and a channel forming region on a substrate having a silicon layer on the first insulating layer;

Patterning the silicon layer with the mask;

Etching the mask on the channel forming region and forming an undercut under the channel forming region;

A fourth step of thermally oxidizing the channel forming region to form a nanowire channel;

A fifth step of forming a gate oxide layer on the nanowire channel;

Depositing a gate material overlying the mask on the substrate;

A seventh step of forming a gate by planarizing the gate material using the mask as a stop layer;

An eighth step of removing the mask; And

And a ninth step of forming a source and a drain by irradiating impurities from the substrate.

According to the invention, the mask,

A second insulating layer on the silicon layer and a silicon nitride layer on the second insulating layer.

The second step may include forming a third insulating layer on a side of the mask;

Forming a photoresist exposing a region corresponding to the channel formation region on the substrate; And

And etching the third insulating layer exposed to the photoresist.

The third insulating layer forming step is:

Forming the third insulating layer covering the substrate; And

And planarizing the third insulating layer to expose an upper surface of the mask.

Exposing the upper surface of the mask,

And forming a second silicon nitride layer on the third insulating layer and the mask.

The etching of the third insulating layer may include etching the second silicon nitride layer exposed to the photoresist.

The masks of the seventh and eighth steps may include the second silicon nitride layer.

According to the invention, the third step,

Etching side surfaces of the exposed second insulating layer.

The fourth step may include forming an oxide sacrificial layer on the surface of the channel region by heat-treating the substrate or by electrochemical method; And

And removing the oxide sacrificial layer.

The sixth step may be depositing polysilicon.

According to the present invention, the fourth step,

And forming and removing an oxide sacrificial layer on surfaces of the source forming region and the drain region exposed by the undercut and the side etching.

The fifth step includes forming a gate oxide film on the exposed surfaces of the source forming region and the drain region,

In the sixth step, the gate material is formed to overlap the source forming region and the drain forming region.

According to the present invention, the ninth step may include: irradiating impurities from the substrate at low concentration to form a low doped drain (LDD) region in the source region and the drain region in contact with the channel; And

Irradiating impurities at a high concentration on the substrate to form a source and a drain.

According to the present invention, the source and drain forming step,

Forming a third silicon nitride layer on the substrate; And

Dry etching the third silicon nitride layer to form spacers on both sides of the gate.

Hereinafter, a method of manufacturing self-alignment of a 3D transistor according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. In this process, the thicknesses of layers or regions illustrated in the drawings are exaggerated for clarity.

1A to 1J are diagrams illustrating a step-by-step method of manufacturing a self-alignment of a 3D transistor according to an exemplary embodiment of the present invention.

Referring to FIG. 1A, a substrate 110 having a silicon layer 114 formed on an insulating layer 112, for example, a silicon oxide layer, is prepared. The silicon layer 114 is a layer consisting of a source, a drain, and a channel. Silicon layer 114 is formed approximately 20-100 nm in height. The insulating layer 112 may be formed to a thickness of 140 nm. The substrate 110 may be an SOI substrate.

Subsequently, the mask layer 120 is formed on the silicon layer 114. The mask layer 120 may be a buffer layer 122 and a silicon nitride layer 124 on the silicon layer 114. The buffer layer 122 may be made of silicon oxide. The buffer layer 122 may be formed to be approximately 15 nm thick, and the silicon nitride layer 124 may be formed to be 200 nm thick.

Referring to FIG. 1B, the mask layer 120 is patterned to form a source region, a channel region, and a drain region. Subsequently, the silicon layer 114 is dry etched using the patterned mask layer 120 to form the source forming part 115, the channel forming part 116, and the drain forming part 117. The channel forming portion 116 is fin-shaped, the width (W) may be formed of 5 ~ 50 nm.

Referring to FIG. 1C, an insulating layer (not shown) covering the patterned portion on the substrate 110 is deposited in the resultant of FIG. 1B. The insulating layer may be formed of silicon oxide to a thickness of approximately 500 nm.

Next, the insulating layer is planarized by a chemical mechanical polishing (CMP) process to expose the patterned silicon nitride layer 124. An insulating layer 130 is formed on side surfaces of the patterned layers 114, 122, and 124.

Referring to FIG. 1D, a second silicon nitride layer 140 is deposited to a thickness of about 100 nm onto the substrate 110. The second silicon nitride layer 140 prevents etching of the insulating layer 130 in an etching process which will be described later. Subsequently, after the photoresist 150 is formed on the substrate 110, the photoresist 150 is patterned to expose a region corresponding to the channel formation region 116. Subsequently, the second silicon nitride layer 140 and the insulating layer 130 exposed to the photoresist 150 are sequentially dry-etched. In FIG. 1D, for convenience, structures at both ends of the drain formation region and the source formation region are shown.

FIG. 1E is a cross-sectional view taken along the line A-A of FIG. 1D. Referring to FIG. 1E, after the silicon nitride layer 124 of FIG. 1D on the channel forming region 116 is dry etched, the exposed region is wet etched to form an undercut under the channel forming portion 116. At this time, the upper portion 122A of the source forming region 115 and the drain forming region 117 connected to the channel forming portion 116 is also partially etched. Accordingly, the channel forming portion 116 is suspended between the source forming portion 115 and the drain forming portion 117, so that the channel forming portion 116 is exposed up and down. The structure of the channel forming portion 116 enables the formation of nanowires and, furthermore, the three-dimensional gate structure.

Referring to FIG. 1F, the substrate 110 is dry oxidized to oxidize a portion of the source forming portion 115 and the drain forming portion 117 exposed by the side surface etching and the surface of the channel forming portion 116. Reference numeral 116 'is a thermally oxidized portion. The dry oxidation may be heat treated at about 875 to 950 ° C. for about 5 to 10 hours to form an oxide film 116 ′ having a thickness of about 1 to 5 nm. The oxide layer 116 ′ may be formed by an electrochemical method.

Subsequently, when the oxide layer 116 ′ is removed by wet etching, the nanowire channel 118 is formed. Subsequently, the gate oxide layer 160 is formed in the source formation region 115 and the drain formation region 117 of the channel 118 and the exposed region. The gate oxide layer 160 may be formed of silicon oxide having a thickness of 3 to 4 nm.

Referring to FIG. 1G, polysilicon 170 is formed on the substrate 110 to a thickness of about 400 nm by chemical vapor deposition. The impurities may be doped into the polysilicon 170 in-situ or implanted into the polysilicon 170 in a separate process later. In this process, polysilicon 170 is formed surrounding the channel 118. In addition, since the polysilicon 170 is formed by filling up to the side-etched portion 122A and the undercut portion of the insulating layer 122, the portions 170A and 170B of the polysilicon 170 may include the source forming portion 115 and It is formed to overlap with the drain forming portion 117. This in turn causes the gate to be formed to overlap the source and drain.

Referring to FIG. 1H, the polysilicon 170 is planarized by a CMP process using the silicon nitride layer 140 as a CMP stop layer to form a gate 172. Silicon nitride layers 124 and 140 define the height of gate 172. Therefore, according to the present invention, it is easy to adjust the height of the gate 172.

Referring to FIG. 1I, a second insulating layer (see 130 of FIG. 1D) and silicon nitride layers 140 and 124 are selectively removed on the substrate 110, respectively. Such a process may use a dry etching process. Subsequently, when the dopant is doped at a low concentration, for example, 10 ¹⁵ atoms / cm ³ , from above the substrate 110, the source formation region 115 and the drain formation region 117 are disposed below the portion 170A of the gate 172. Low doped drain (LDD) 180 is formed. Such formation of the LDD region 180 may be easily formed by the portion 170A of the present invention. In particular, the LDD region 180 may be doped at a predetermined angle to form the LDD region 180. This LDD region plays a role in improving short channel effects and reducing hot carriers by controlling the field strength within the junction.

Referring to FIG. 1J, after depositing a silicon nitride layer (not shown) on the substrate 110 to a predetermined thickness, anisotropic etching is performed to form spacers 190 on both sides of the gate 172. Impurities are then implanted from the substrate 110 at a high concentration, such as 10 ¹⁵ atoms / cm ³ , to form source 115 ′ and drain 117 ′. Although the spacer forming process is for effectively implanting the region except for the LDD region 180, the source and the drain may be formed by implanting at a high concentration without forming the spacer in the process of FIG. 1I.

According to the method of manufacturing a transistor according to an embodiment of the present invention, the gate is formed after the channel is formed so that the gate is automatically aligned on the channel without a separate patterning process. In addition, the gate forming process is a planarization process without an etching process, and in the planarization process, since the mask layer is used as the planarization stop layer, it is easy to limit the gate height. In addition, the gate controllability of the transistor can be improved because the gate is automatically aligned to overlap the source and drain.

Although the present invention has been described with reference to the embodiments with reference to the drawings, this is merely exemplary, it will be understood by those skilled in the art that various modifications and equivalent embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined only by the appended claims.

1A to 1J are diagrams illustrating a step-by-step method of manufacturing a self-alignment of a 3D transistor according to an exemplary embodiment of the present invention.

Claims (12)

Forming a mask having a shape of a source forming region, a drain forming region, and a channel forming region on a substrate having a silicon layer on the first insulating layer; Patterning the silicon layer with the mask; Etching the mask on the channel forming region and forming an undercut under the channel forming region; A fourth step of thermally oxidizing the channel forming region to form a nanowire channel; A fifth step of forming a gate oxide layer on the nanowire channel; Depositing a gate material overlying the mask on the substrate; A seventh step of forming a gate by planarizing the gate material using the mask as a CMP stop layer; An eighth step of removing the mask; And a ninth step of forming a source and a drain by irradiating impurities from the substrate. The method of claim 1, wherein the mask, And a second insulating layer on the silicon layer and a silicon nitride layer on the second insulating layer. The method of claim 2, wherein the second step, Forming a third insulating layer on the side of the mask; Forming a photoresist exposing a region corresponding to the channel formation region on the substrate; And And etching the third insulating layer exposed to the photoresist. The method of claim 3, wherein the third insulating layer forming step: Forming the third insulating layer covering the substrate; And And planarizing the third insulating layer to expose the top surface of the mask. The method of claim 4, wherein the exposing the upper surface of the mask, And forming a second silicon nitride layer on the third insulating layer and the mask. The etching of the third insulating layer may include etching the second silicon nitride layer exposed to the photoresist. And the mask of the seventh and eighth steps comprises the second silicon nitride layer. The method of claim 4 or 5, wherein the third step, A method of manufacturing a self-alignment of a three-dimensional transistor comprising etching the exposed side of the second insulating layer. The method of claim 6, wherein the fourth step, Heat-treating the substrate or forming an oxide sacrificial layer on the surface of the channel region by an electrochemical method; And Removing the oxide sacrificial layer; Self-aligning manufacturing method of a three-dimensional transistor further comprising. The method of claim 6, wherein the fourth step and the fifth step, Forming a gate oxide layer on a surface of the channel region by thermal oxidation or an electrochemical method, wherein the channel region is the channel. The method of claim 1, wherein the sixth step is Self-aligned manufacturing method of a three-dimensional transistor for depositing polysilicon. The method of claim 7, wherein the fourth step, And forming and removing an oxide sacrificial layer on surfaces of the source forming region and the drain region exposed by the undercut and the side etching. The fifth step includes forming a gate oxide film on the exposed surfaces of the source forming region and the drain region, The sixth step may include forming the gate material overlapping the source forming region and the drain forming region. The method of claim 1, wherein the ninth step is Irradiating impurities on the substrate at low concentration to form a low doped drain (LDD) region in the source region and the drain region in contact with the channel; And Irradiating impurities at a high concentration on the substrate to form a source and a drain. The method of claim 11, wherein the source and drain forming step, Forming a third silicon nitride layer on the substrate; And dry etching the third silicon nitride layer to form spacers on both sides of the gate.

Images