KR101208969B1 - Single electron transistor with extended channel using work-function difference and fabrication method of the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single-electron transistor and a process method thereof, and more particularly, to have a recessed channel, thereby minimizing the MOSFET component current acting as a leakage current and controlling the quantum dot. The operating temperature can be increased by minimizing the capacitance value, and both side gates are formed of a material having a work function difference from the recessed channel, thereby tunneling the channel with a work function difference without applying a conventional bias. The present invention relates to a single-electron transistor having an extended recess channel using a work function difference that allows a barrier to be formed, and a process method thereof.

Description

SINGLE ELECTRON TRANSISTOR WITH EXTENDED CHANNEL USING WORK-FUNCTION DIFFERENCE AND FABRICATION METHOD OF THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single-electron transistor and a process method thereof, and more particularly, to have a recessed channel, thereby minimizing the MOSFET component current acting as a leakage current and controlling the quantum dot. The operating temperature can be increased by minimizing the capacitance value, and both side gates are formed of a material having a work function difference from the recessed channel, thereby tunneling the channel with a work function difference without applying a conventional bias. The present invention relates to a single-electron transistor having an extended recess channel using a work function difference that allows a barrier to be formed, and a process method thereof.

The single-electron transistor is basically a source / drain, a quantum dot (QD), two tunneling barriers formed between the source / drain and the quantum dot, and a gate for independently controlling the potential of the quantum dot, as shown in FIG. 1A. It is composed.

With this configuration, the following two conditions must be satisfied to obtain the characteristics of the single-electron transistor, as shown in FIG. 1B.

First, the size of the quantum dot is small enough that the capacitance C in the quantum dot must satisfy the condition of the following equation (1).

[Equation 1]

q ² / C? k _B T

In Equation 1, q ² / C is charging energy required for one electron to enter a quantum dot, and k _B T is thermal energy at temperature T.

Second, it is necessary to make the coupling between the source / drain and the quantum dot weakly so that the tunneling resistance R _T between the two is larger than the lowest tunneling resistance R _{T, min} as in Equation 2.

[Equation 2]

R _T ? h / q ² (= R _{T, min} )

Process methods of single-electron transistors capable of satisfying the above two conditions have been studied in various ways. Among them, a side gate (or dual) which electrically induces a tunneling barrier forming a quantum dot and can be controlled by a structural parameter of the device. Single-electron transistors with dual gate structures have attracted more attention.

However, the side gate single-electron transistor that has been studied so far has a problem that it is difficult to put practical use due to the non-ideal characteristics due to the alignment problem between the control gate and the side gate, the side gate and the source / drain region.

For example, the conventional side gate single electron transistor shown in FIG. 2A has non-ideal electrical characteristics due to parasitic MOSFET components.

That is, as shown in the ① and ③ portions of FIG. 2A, the source / drain regions are not immediately adjacent to the tunneling barrier but underlap a certain distance, so that the ONO layer (TEOS / Si ₃ N ₄ / TEOS) and the control on top are located. Due to the series MOSFET component generated by the gate and the parallel MOSFET component generated because the control gate covers the side gate (side wall gate) forming an electrical barrier, as shown in part 2 of FIG. As the current is completely cut off, and as the control gate voltage increases, the height of the electrical barrier decreases, reducing the peak-to-valley-current-ratio (PVCR) between peak and valley currents. The problem is that the single electron current decreases and the MOSFET current (which acts as a leakage current in the single electron transistor) increases (see Fig. 2b).

FIG. 2B is a simulation result diagram showing that the height of the potential barrier to be fixed by the sidewall gate in the conventional side gate single-electron transistor is changed by the voltage of the control gate.

In addition, the conventional side gate single-electron transistor is the largest obstacle to commercialization is observed only at cryogenic temperatures even if there is a single-electron tunneling phenomenon, as shown in FIG.

In order to solve the above problems, a single electron transistor having the structure of FIG. 3 is proposed, and Korean Patent Application No. 10-2006-0135357 (self-aligned dual gate single electron transistor and a method of manufacturing the same) has been filed by the same applicant. There is a bar.

In FIG. 3, 110 is a buried oxide film (BOX), 122a is a source region, 124b is a drain region, 126 is a channel region, 140b is a control gate, 170 is a sidewall gate insulating film, 180a and 180b is a sidewall gate (side gate), and 190a And 190b are insulating film sidewall spacers.

However, since the patent application is a single-electron transistor having a planar channel structure, there is a problem that there is a certain limit in reducing the MOSFET component current acting as a leakage current.

In addition, the conventional side gate single-electron transistor is to form a tunneling barrier electrically by applying a separate bias to the side gate, there is a problem that increases the coupling (coupling) between the quantum dot and the side gate to increase the capacitance of the quantum dot, side The need for additional connection terminals for biasing the gate requires complexity in terms of circuit applications, and the parasitic MOSFETs are formed on both sides of the quantum dots due to the bias applied to the side gate and the side gate. As the bias increases, the MOSFET component current also increases.

Accordingly, the present invention fundamentally solves the problems of the conventional side gate single-electron transistor by forming a side gate having a recessed channel and a material having a work function difference from the channel region, thereby affecting the quantum dot. It is an object of the present invention to provide a single-electron transistor having an extended channel using a work function difference that can increase the operating temperature by minimizing the capacitance value of the control gate.

In order to achieve the above object, the single-electron transistor having an extended channel using a work function difference according to the present invention comprises a silicon layer vertically dug to have a channel region recessed on the buried oxide film of the SOI substrate; A first gate insulating film formed on the channel region; First and second side gates spaced at a predetermined distance in a channel direction from both edge surfaces of the channel region with the first gate insulating layer interposed therebetween; And a control gate formed on the buried oxide layer with a second gate insulating layer interposed therebetween, wherein the first and second side gates are formed of a material having a work function difference from the recessed channel region. And the second gate insulating film is formed on the first gate insulating film on the channel region between the side gates, and the third gate insulating film is further formed on both sidewalls of the second gate insulating film on the channel region between the side gates. It is done.

In addition, the process of the single-electron transistor having an extended channel using the work function difference according to the present invention is deposited on at least one hard mask material layer having a different etching rate on the SOI substrate, and on top of the material layer for the hard mask Forming a fine pattern after applying the first insulating material; A second step of forming a mix and match pattern for forming a source / drain and fin-shaped channel through an etching process after coating the photoresist on the entire surface of the substrate; A hard mask is formed by etching the hard mask material layer using the mix-and-match pattern as a mask, and a source / drain pad and a fin-shaped channel region are formed by etching the silicon layer of the SOI substrate using the hard mask. With three steps; Depositing and planarizing a field oxide film over the entire surface of the substrate; Depositing a second insulating material on the entire surface of the planarized substrate, applying a second photosensitive film on the second insulating material, and forming a second photoresist pattern for forming a recess channel through an etching process; ; A sixth step of sequentially etching the second insulating material and the field oxide film using the second photoresist pattern as a mask to expose the fin-shaped channel region; A seventh step of forming a recessed channel region by etching the fin-shaped channel region by using the second photoresist pattern as a mask; An eighth step of removing the second photoresist pattern and forming a first gate insulating film on the recessed channel region by a thermal oxidation process; Depositing sidewall gate material having a work function difference from the recessed channel region over the substrate, and anisotropically etching to form first and second sidewall gates on both sidewalls of the recessed channel region; A tenth step of forming a second gate insulating film on each sidewall gate; An eleventh step of depositing and planarizing a control gate material over the substrate to expose the second insulating material, and then removing the exposed second insulating material to form a control gate; A first doped layer having a low junction to partially overlap an upper portion of the first and second sidewall gates in the fin-shaped channel region and the source / drain pad adjacent to the control gate through impurity ion implantation on the entire surface of the substrate; Characterized in that it comprises a twelfth step of forming each.

The present invention provides a recessed channel, and by forming a side gate of a material having a work function difference from the channel region, the tunneling barrier is naturally formed in the channel length direction, so that an additional connection terminal is required for conventional bias application. In addition to eliminating the complexity of the circuit, the channel length can be extended to significantly reduce the MOSFET current acting as a leakage current, and the width of the silicon fin where the quantum dots are formed by thermal oxidation and sidewall processes. And the length can be reduced, and the distance to the control gate can be increased by the first gate insulating film, the second gate insulating film, and / or the third gate insulating film. The effect of increasing the operating temperature by minimizing the capacitance value have.

1A and 1B are basic structural diagrams and ideal operating characteristics diagrams of single-electron transistors, respectively.
2A is a structural cross-sectional view of a conventional side gate single electron transistor.
FIG. 2B is a simulation result diagram showing that the height of the potential barrier to be fixed by the sidewall gate in FIG. 2A is changed by the voltage of the control gate.
3 is a structural cross-sectional view of Korean Patent Application No. 10-2006-0135357 for solving the problems of the structure of FIG.
FIG. 4 is a simulation result diagram showing a tunneling barrier formed according to a work function difference of a single-electron transistor according to the present invention.
FIG. 5 is a simulation result diagram illustrating a tunneling barrier formed by applying a bias to a conventional side gate to prepare a result of FIG. 4.
FIG. 6 is a simulation result diagram illustrating a tunneling barrier formed according to a bias of a control gate in a state of Vsg = 0 V when the single-electron transistor according to the present invention is formed of an n-type control gate and a p-type side gate.
FIG. 7 is a simulation result diagram illustrating a tunneling barrier formed according to a bias of a control gate in a state where a bias is applied to a conventional side gate (Vsg = −1 V) in order to prepare the result of FIG. 6.
FIG. 8 illustrates tunneling according to the bias of the control gate in the state of Vsg = 0 V when the single-electron transistor according to the present invention is formed of an n-type silicon substrate, a p-type source / drain, a p-type control gate and an n-type side gate (SHT). The simulation results show how the barrier is formed.
9 is a cross-sectional view showing a simulation structure and parameters used to grasp the electrical characteristics of the single-electron transistor according to the present invention.
10 to 35 are perspective views illustrating a manufacturing process of a single electron transistor according to the present invention.
36 and 37 are cross-sectional views taken along lines AA and BB of FIG. 35, respectively.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

[Example of Structure]

The structure according to the present invention is basically perpendicular to the channel region 19 recessed on the buried oxide film 2 on the sub silicon layer 1 of the SOI substrate, as shown in FIGS. 35, 36 and 37. Excavated active silicon layers 14, 14a, 16, 18a, 18b; A first gate insulating film 80 formed on the channel region; First and second side gates 92 formed at a predetermined distance apart from each other on a side surface of the channel region with the first gate insulating layer interposed therebetween; And a control gate 66a formed on the investment oxide layer with a second gate insulating layer 82 interposed therebetween, wherein the first and second side gates 92 are recessed channels. It is formed of a material having a work function difference from the region 19.

Here, in the active silicon layer, as shown by reference numeral 14 in FIG. 24, sources / drains are formed on both sides with recessed channel regions interposed therebetween, and as shown in FIG. 36, the source / drain 18a and 18b. ) Is connected to the shallow doping region 16 formed on both sides of the vertical fin.

By the above configuration, the channel length can be significantly increased as compared with the conventional planar structure, as shown by reference numeral 19 of FIG. 36, and it is easy to form the potential barrier by the side gate 92, as well as the leakage current in the single-electron transistor. This has the advantage of dramatically reducing the MOSFET current component.

In addition, the tunneling barrier formed in the channel length direction by the first and second side gates 92 formed of a material having a work function difference from the channel region 19 recessed on both sides of the control gate 66a is more reliably. Since it is possible to form a high voltage, it is not necessary to apply a bias to the side gate to form a tunneling barrier as in the prior art, which greatly reduces the complexity of the circuit and greatly reduces the MOSFET current component generated by applying the bias. There is this.

More specifically, the active silicon layers 14, 14a, 16, 18a, and 18b of the SOI substrate may be p-type, and the source / drain 18a and 18b may be n-type impurity doped layers in order to have the latter advantage. The control gate 66a may be an n-type doped silicon-based material (eg, polycrystalline silicon, amorphous silicon, or the like), and the first and second side gates 92 may be formed in the recessed channel region ( 19) (i.e., a material having a work function difference from that of a p-type active silicon layer not ion-implanted when forming a source / drain), a single electron transistor (SET) having electrons as a carrier can be implemented.

Here, the material having a work function difference from the recessed channel region 19 may be any one selected from a metal, a metal silicide, and a p-type doped silicon-based material, but is not limited thereto. That is, any material having a work function difference from the recessed channel region 19 may be used.

On the other hand, the type of each configuration is changed, that is, the active silicon layers 14, 14a, 16, 18a, and 18b of the SOI substrate are n-type, and the source / drain 18a and 18b are p-type impurity doping layers. The control gate 66a is a p-type doped silicon-based material, and the first and second side gates 92 are not implanted with the recessed channel region 19 (ie, source / drain formation). A single hole transistor (SHT) using a hole as a carrier may be implemented using a material having a work function difference from an n-type active silicon layer).

Here, the material having a work function difference from the recessed channel region 19 may be any one selected from metals, metal silicides, and n-type doped silicon-based materials, but is not limited thereto. That is, any material having a work function difference from the recessed channel region 19 may be used.

The metal silicide may be any one selected from TiSi ₂ , IrSi ₃ , Ni ₂ Si, and Pt ₂ Si.

It can be seen from FIG. 4 that the height of the tunneling barrier may be formed differently according to the work function difference of each metal silicide. FIG. 4 shows the simulation results using SILVACO tools after Lcg = 10nm, Lsg = 20nm, t _COX = 10nm, t _SOX = 5nm as the simulation parameters in the structure of FIG. 9. In FIG. 4, W = 4.53eV represents TiSi ₂ , W = 4.68eV represents IrSi ₃ , W = 4.96eV represents Ni ₂ Si, and W = 5.17eV represents Pt ₂ Si.

Although no bias is applied to the side gate from FIG. 4, when the side gate is formed of a material having a work function difference from the channel region, the height of the tunneling barrier may be formed differently according to the work function difference. have. This can be seen that similar to the tunneling barrier appearance according to the voltage applied to the control gate in a state where a bias is applied to the conventional side gate as shown in FIG.

In particular, the tunneling barrier height of the single-electron transistor according to the present embodiment has the largest work function difference when the control gate and the side gates formed on both sides thereof are formed of n-type polysilicon and p-type polysilicon, respectively. It can be seen that the tunneling barrier is formed as the simulation result of.

FIG. 6 shows a tunneling barrier formed according to the bias of the control gate in the state of Vsg = 0 V with the single-electron transistor according to the present embodiment. As a result, the bias of the control gate can be applied with a difference of 1V or more. It can be seen that room temperature operation is sufficiently possible.

6 shows a profile almost identical to that of FIG. 7 showing a tunneling barrier formed according to the bias of the control gate while the bias is applied to the conventional side gate (Vsg = -1 V).

When the type of each configuration is changed in the configuration of a single electron transistor (SET) configuration according to the present embodiment, as described above, a single hole transistor (SHT) having a hole as a carrier may also be implemented.

Simulation results thereof are also shown in FIG. 8. That is, FIG. 8 shows the single-electron transistor according to the present embodiment when the single-electron transistor is formed as a single hole transistor (SHT) using an n-type substrate, a p-type source / drain, a p-type control gate, and an n-type side gate. The tunneling barrier is formed by the bias of the control gate.

Meanwhile, when the second gate insulating layer 82 is formed on the side gate 92 in FIG. 27, the second gate insulating layer 80 may also be formed on the first gate insulating layer 80 on the channel region between the side gates 92. 82a) is preferably formed such that the distance between the quantum dot formed in the channel region and the control gate 66a is increased.

More preferably, as shown in FIG. 28, the third gate insulating layer 84 is further formed on both sidewalls of the second gate insulating layer 82a on the channel region between the side gates 92 so that the side gates 92 are disposed between the side gates 92. The distance from the control gate 66a formed to surround the channel region may be greater.

In addition, both sides of the recessed channel region are surrounded by the field oxide layer 64 as shown in FIG. 24, and as shown in FIG. 26, each side gate is formed on both sides of the channel region and the field oxide layer 64 and the buried oxide layer ( It is formed by the side wall gate 92 on both edge surfaces formed by 2).

In the accompanying drawings, the channel region between the sidewall gates 92 is shown long, but this is illustrated for convenience of showing the respective structures. In the actual device structure, the channel region between the sidewall gates 92 is minimized so that the portion contacting the control gate 66a is as small as possible. . This can reduce the channel region in contact with the control gate 66a by adjusting the width of the sidewall gate 92.

With the above configuration, the operating temperature of the single-electron transistor can be increased by minimizing the capacitance value of the control gate 66a which affects the quantum dot.

EXAMPLES ABOUT PROCESS METHOD

A method of manufacturing a single electron transistor according to an embodiment of the above structure will be described with reference to FIGS. 10 to 37.

First, as shown in FIGS. 10 and 11, one or more hard mask material layers 20 and 30 having different etching rates are deposited on the silicon layer 10 of the SOI substrate, and a first layer is formed on the hard mask material layer. After applying the insulating material 40, a fine pattern 42 is formed (first step).

Here, as shown in FIG. 10, the hard mask material layer may be formed by sequentially depositing an oxide layer 20 and a silicon-based material layer (eg, a polycrystalline silicon layer or an amorphous silicon layer 30).

In addition, the first insulating material 40 is preferably a negative photoresist film (negative PR) for the e-beam fine pattern, but may be a positive photosensitive film ZEP.

When using the electron, as shown in FIG. 10, only the portion exposed to the e-beam remains, and as illustrated in FIG. 11, the fine pattern 42 may be formed.

Next, as shown in FIGS. 12 and 13, after the photosensitive film 50 is applied to the entire surface of the substrate, a mix and match pattern 42 for forming a source / drain and fin-shaped channel through a known photolithography process is performed. , 52) (second step).

14 to 16, the hard mask material layers 20 and 30 are etched using the mix and match patterns 42 and 52 as masks to form hard masks 22 and 32, and the hard masks The silicon layer 10 of the SOI substrate is etched with a mask to form a source / drain pad and a fin-shaped channel region as shown by reference numeral 18 of FIG. 16 (third step).

Here, when the hard mask material layer is sequentially deposited with the oxide layer 20 and the silicon-based material layer 30 as shown in FIG. 10, the etching of the hard mask material layer in the third step is shown in FIG. 14. 15, the silicon-based material layer 30 and the oxide layer 20 are sequentially etched, and as shown in FIG. 16, the oxide layer etched with the mix-n-match pattern is used as the hard mask 22. The silicon layer 10 of the SOI substrate is etched to form source / drain pad and fin-shaped channel regions as shown by reference numeral 12.

That is, when the silicon-based material layer 30 is etched using the mix and match patterns 42 and 52 as a mask, and then the oxide layer 20 is etched, a mix made of a photosensitive film and a first insulating material (eg, HSQ). The n-match masks 42 and 52 are also etched and removed, and when the silicon layer 10 of the SOI substrate is etched, the oxide layer is used as the hard mask 22.

Next, as shown in FIGS. 17 and 18, the field oxide film 60 is deposited and planarized on the entire surface of the substrate using TEOS or the like (fourth step).

In this case, as shown in FIG. 18, it is preferable to stop the planarization process before the active silicon layer 12 is etched so that a portion of the oxide layer hard mask remains (see reference numeral 24).

Subsequently, as shown in FIGS. 19 and 20, a second insulating material 70 is deposited on the entire surface of the planarized substrate, a second photosensitive film 44 is coated on the second insulating material, and then a known etching process is performed. A second photoresist pattern 44a for forming a recess channel is formed (fifth step).

Here, the second insulating material 70 is preferably formed sufficiently high of nitride, and the second photosensitive film 44 is coated with a ZEP material (positive PR) using a spin coater, and then e By removing the irradiated portion using -beam lithography, it is preferable to narrow the width of the open portion (the portion irradiated with the e-beam) so that the channel region in contact with the control gate is made smaller later (of course, in this case, HSQ May be used as an e-beam photosensitive film).

The open portion (the portion irradiated by the two beams) is further reduced by forming a side gate (side wall gate) after the recess channel is formed later.

Next, as shown in FIGS. 21 and 22, the second insulating material 70 and the field oxide layer 62 are sequentially etched using the second photoresist pattern 44a as a mask to form the channel region 12a of the fin shape. (Step 6).

Next, as illustrated in FIG. 23, the fin-shaped channel region 12a is etched using the second photoresist pattern 44a as a mask to form a recessed channel region 14a (seventh step).

Next, as shown in FIG. 24, the second photoresist layer pattern 44a is removed and a first gate insulating layer 80 is formed on the recessed channel region 14a through a thermal oxidation process (step 8). ).

In this way, an oxide film is formed on the exposed silicon layer 14a of the recessed channel region with the first gate insulating film 80, and the width (thickness) of the silicon fin can be reduced by corrosion oxidation. The advantage is that the distance can be increased while reducing the area of the silicon pins in contact.

Then, as shown in FIGS. 25 and 26, the sidewall gate material 90 having a work function difference from the recessed channel region 14a is deposited on the entire surface of the substrate, and anisotropically etched to form the recessed channel region ( 14a) First and second sidewall gates 92 are formed on both sidewalls (ninth step).

At this time, it is preferable that the width of the first and second sidewall gates 92 is sufficiently adjusted to adjust the sidewall process so that the recessed channel regions 14a and 80 are only slightly exposed (exaggerated in the drawing). In addition, when the active silicon layer 12 is p-type, the sidewall gate material 90 may be used as a metal, a metal silicide, or a silicon-based material doped with a p-type, and the active silicon layer 12 may be n-type. In this case, it is preferable to use the metal, the metal silicide, or the n-type silicon-based material.

Next, as shown in FIG. 27, a second gate insulating layer 82 is formed on each sidewall gate (step 10).

Although the second gate insulating layer 82 may be formed by a thermal oxidation process, the second gate insulating layer 82 may be formed on the channel region 80 exposed between the sidewall gates using MTO equipment.

Further, as shown in FIG. 28, a third gate insulating film sidewall is formed on the sidewall of the second gate insulating film 82a on the channel region 80 exposed between the sidewall gates by anisotropic etching and deposition of an insulating film such as TEOS. By further proceeding to form 84, the operating temperature of the single-electron transistor can be further increased by increasing the distance between the quantum dot and the control gate as much as possible (see FIG. 37).

Thereafter, as shown in FIGS. 29 to 31, the gate material 66 is again deposited and planarized on the entire surface of the substrate to expose the second insulating material 72, and then the exposed second insulating material 66 is removed. The control gate 66a is formed (11th step).

Here, when the second insulating material 72 is nitride, when the planarization process is performed with a known CMP, the nitride acts as an etch stopper.

34, a shallow doping layer is formed on the fin-shaped channel region adjacent to the control gate 66a and the control gate 66a and the source / drain pad 14 by implanting impurity ions into the entire surface of the substrate. Each of 16 is formed (12th step).
Here, as shown in FIG. 36, the shallow doping layer 16 refers to a doping layer having a low junction so as to partially overlap with an upper portion of the first and second side gates 92.

The impurity ion implantation is preferably implanted with another type of impurity when a silicon-based material doped with p-type or n-type impurity is used as the side gate material.

In the case where the remaining oxide film hard mask 26 in FIG. 31 is thick, the oxide film hard mask 26 is removed as shown in FIG. 32, and the doping sacrificial oxide film 86 is again shown in FIG. 33. 88), then proceed to step 12 above.

As shown in FIG. 36, which is a cross-sectional view along line AA of FIG. 35, by forming the shallow doping layer 16, there is an effect of further extending the length of the channel 19 vertically.

However, since the shallow doping layer 16 has a shallow junction, the source / drain pad regions 18a and 18b for the source / drain contact have a deeper junction depth than the shallow doping layer 16. It is desirable to form a deep doping layer.

As shown in FIG. 35, after the twelfth step, a field oxide film is further deposited on the entire surface of the substrate using TEOS, and then anisotropically etched to form oxide sidewalls 68 on both sides of the control gate 66a, and then doping. This can be achieved by further increasing the energy to proceed with the impurity ion implantation process.

Here, in the impurity ion implantation process, when a silicon-based material doped with a p-type or n-type impurity is used as the side gate material, ion implantation with other types of impurities is preferable.

In FIG. 35, a cross-sectional view along line BB is shown in FIG. 37. According to FIG. 37, the distance between the control gate 66a in the silicon fin 14a, which is a channel region in which the quantum dots are formed, is formed on the first gate insulating film 80, the second gate insulating film 82a, and the third gate insulating film 84. It can be seen that it can be enlarged by.

Other processes and non-described parts follow a general CMOS process, and thus a detailed description thereof will be omitted.

10, 12, 14, 16, 18: active silicon layer of SOI substrate
20, 22: oxide layer 30, 32: silicon-based material layer
40, 42: first insulating material 44, 44a: second photosensitive film
50, 52: photosensitive films 60, 62, 64, 64a, 68: field oxide films
66, 66a: control gate 70, 72: second insulating material
80: first gate insulating film 82, 82a: second gate insulating film
84: third gate insulating film 90, 92: side gate (side wall gate)

Claims (16)

delete delete A silicon layer vertically dug to have a channel region recessed on the buried oxide film of the SOI substrate;
A first gate insulating film formed on the channel region;
First and second side gates spaced at a predetermined distance in a channel direction from both edge surfaces of the channel region with the first gate insulating layer interposed therebetween;
A control gate formed on the buried oxide film with a second gate insulating film interposed therebetween,
The first and second side gates are formed of a material having a work function difference from the recessed channel region.
The second gate insulating film is also formed on the first gate insulating film on the channel region between the side gates,
And a third gate insulating film is further formed on both sidewalls of the second gate insulating film on the channel region between the side gates.
The method of claim 3, wherein
The silicon layer has the recessed channel region in a vertical fin shape, and sources / drains are formed on both sides of the channel region.
And the source / drain is connected to a doped region having a low junction on both sides of the vertical fin so as to partially overlap with an upper portion of the respective side gates.
The method of claim 4, wherein
Both sides of the recessed channel region are surrounded by a field oxide layer,
Wherein each side gate is formed as a sidewall gate on both edges of the channel region and on both edges of the field oxide film and the buried oxide film, wherein the side gates are extended.
The method of claim 5, wherein
The SOI substrate is a p-type substrate,
The source / drain is an n-type impurity doped layer, respectively
The control gate is an n-type doped silicon-based material,
Wherein each side gate is formed of any one selected from a metal, a metal silicide, and a p-type doped silicon-based material.
The method according to claim 6,
The metal silicide is a single electron transistor having an extended channel using a work function difference, characterized in that any one selected from TiSi ₂ , IrSi ₃ , Ni ₂ Si and Pt ₂ Si.
The method of claim 5, wherein
The SOI substrate is an n-type substrate,
The source / drain is a p-type impurity doped layer, respectively
The control gate is a p-type doped silicon-based material,
Wherein each side gate is formed of any one selected from a metal, a metal silicide, and an n-type doped silicon-based material.
The method of claim 8,
The metal silicide is a single electron transistor having an extended channel using a work function difference, characterized in that any one selected from TiSi ₂ , IrSi ₃ , Ni ₂ Si and Pt ₂ Si.
Depositing at least one hard mask material layer having different etching rates on the SOI substrate, and forming a fine pattern after applying the first insulating material on the hard mask material layer;
A second step of forming a mix and match pattern for forming a source / drain and fin-shaped channel through an etching process after coating the photoresist on the entire surface of the substrate;
A hard mask is formed by etching the hard mask material layer using the mix-and-match pattern as a mask, and a source / drain pad and a fin-shaped channel region are formed by etching the silicon layer of the SOI substrate using the hard mask. With three steps;
Depositing and planarizing a field oxide film over the entire surface of the substrate;
Depositing a second insulating material on the entire surface of the planarized substrate, applying a second photosensitive film on the second insulating material, and forming a second photoresist pattern for forming a recess channel through an etching process; ;
A sixth step of sequentially etching the second insulating material and the field oxide film using the second photoresist pattern as a mask to expose the fin-shaped channel region;
A seventh step of forming a recessed channel region by etching the fin-shaped channel region by using the second photoresist pattern as a mask;
An eighth step of removing the second photoresist pattern and forming a first gate insulating film on the recessed channel region by a thermal oxidation process;
Depositing sidewall gate material having a work function difference from the recessed channel region over the substrate, and anisotropically etching to form first and second sidewall gates on both sidewalls of the recessed channel region;
A tenth step of forming a second gate insulating film on each sidewall gate;
An eleventh step of depositing and planarizing a control gate material over the substrate to expose the second insulating material, and then removing the exposed second insulating material to form a control gate;
A first doped layer having a low junction to partially overlap an upper portion of the first and second sidewall gates in the fin-shaped channel region adjacent to the control gate and the source / drain pads by implanting impurity ions into the entire surface of the substrate; And a twelfth step of forming each of them.
11. The method of claim 10,
The second gate insulating film of the tenth step is also formed on the channel region exposed between the sidewall gates,
Between the tenth step and the eleventh step, a process of forming a third gate insulating film sidewall on the sidewalls of the second gate insulating film on the channel region exposed between the sidewall gates by deposition and anisotropic etching of the insulating film is further performed. Process for the single-electron transistor having an extended channel using a work function difference, characterized in that.
11. The method of claim 10,
The hard mask material layer is formed by sequentially depositing an oxide layer and a silicon-based material layer.
In the etching of the hard mask material layer of the third step, the silicon layer of the SOI substrate is etched by sequentially etching the silicon-based material layer and the oxide layer and using the oxide layer etched in the mix-n-match pattern as a hard mask. And a channel region having a source / drain pad and a pin shape to form an extended channel using a work function difference.
13. The method of claim 12,
The silicon-based material layer is polycrystalline silicon or amorphous silicon,
The first insulating material and the second photosensitive film are HSQ or ZEP,
And the second insulating material is nitride. 2. The method of claim 1, wherein the second insulating material is nitride.
The method according to any one of claims 10 to 13,
After the twelfth step, a field oxide film is further deposited on the entire surface of the substrate, and anisotropically etched to form oxide sidewalls on both sides of the control gate. The method of claim 1, further comprising forming a second doped layer having a deep junction depth.
15. The method of claim 14,
The SOI substrate is a p-type substrate,
The control gate material is n-type doped polycrystalline silicon or amorphous silicon,
The sidewall gate material is any one selected from metal, metal silicide and p-doped polycrystalline silicon or amorphous silicon,
And the impurity ion implantation is performed using n-type impurities.
15. The method of claim 14,
The SOI substrate is an n-type substrate,
The control gate material is p-type polycrystalline silicon or amorphous silicon,
The sidewall gate material is any one selected from metal, metal silicide and n-type doped polycrystalline silicon or amorphous silicon,
And the impurity ion implantation is performed using a p-type impurity.

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