1355691 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種矽覆絕緣裝置及其製作方法，詳言 之，係關於一種假閘極全環繞矽覆絕緣裝置及其製作方 法。 【先前技術】 根據國際半導體技術藍圖（ITRS)之評估，傳統金氧半場 效電晶體（MOSFET)在尺寸持續微縮的影響下所造成的短 通道效應已面臨極大的挑戰。其中學者提出一些解決方 案，例如使用矽覆絕緣（SOI)、超薄本體（Ultra thin body ; UTB)和high-k閘極介電層（如Al2〇3、Hf02等等）來解決最嚴 重的漏電流問題；使用雙閘極材料、金屬閘極、多層閘極 工程或鰭狀（Fin)閘極來控制閘極臨界門檻電壓（Threshold Voltage)隨著通道長度縮小而捲曲向下（roll-off)和汲極引 致能障下降（DIBL)效應。但使用這些解決方法同時會延伸 一連串的問題（Issues)，例如使用SOI將面臨浮體（Floating body effect)與屈膝效應（Kink Effect)、自我加熱效應和單 拴走火效應（Single latch up);使用UTB雖然鬆弛漏電流問 題和壓抑超短通道效應，但同時將面臨源/汲極串接電阻 增大而降低電流驅動能力、及本體平坦化不均而造成臨界 門檻電壓變動過大之更大問題。 因為傳統MOSFET太多的寄生PN接面電容，草使得元件 切換速度和高頻響應速度變慢，也造成Jf、漏電流過 - ----、/ 高。使用SOI或UTB固然可以降低寄生PN接面電容，其未 123800.doc 1355691 來的實用性當然不容置疑，而面臨的串接電阻過高問題已 有不少解決方案，如提高或加深源/汲極厚度或加入矽化 • 金屬來提高導電率和降低歐姆接觸（中華民國專利申請號 . 第 090108868 號、美國專利第 ό，825,535 號、第 6117 712 ' 號）。S01所造成浮體效應的抑制亦有對策（如美國專利第 6,686,629號、第6,437,375號），如在本體下方形成—石夕化 鍺磊晶使電荷經由表面效應而復合，避免本體電位上升。 • ㈣短通道效應造成漏電流的方法中，最常用的技術如淺 佈植源/汲極（LDD)技術或使用超陡峭接面（如美國專利第 6’465,847號）或暈圈（Hal〇)離子植入（如美國專利第 6,936,278號)來抑制空乏區的擴散’但有鑒於成本和複雜 度的考量我們更希望有一些實際的對策，如減少製程步 驟、降低光罩和離子佈植使用次數等等。 此外/夫疋7G件性能的自界門|電壓在尺寸微縮情狀下 更顯重要。未來’環繞式閘極（Gate州ar〇und)將具有更完 象 4的電荷麵合效應，可改善本體與周圍絕緣層之間的邊際 效應和耗損的功#，但製作困難度將 同時解決上述問題的其實並不多見，根本上必須考慮從元 件結構來作改變以及一些自我對準的機制來同時增加元件 的性能和降低製程複雜度。 ^ ® & ’有必要提供-種創新且具進步，性的假閘極全環繞 • _覆絕緣裝置及其製作方法，以解決上述問題。 【發明内容】 本發明之目的在於提供一種假開極全環繞矽覆絕緣裝 123800.doc 1355691 置。該假閘極全環繞矽覆絕緣裝置包括：一基板、一下閘 極氧化側壁、-下閘極介電層、一導電半導體層、一上間 .· 極介電層、-上閘極、-邊襯、-氧化保護層及一電極 .，组。該基板具有—下閘極’該下閘極具有-第-端及一第 .* 二端’該第-端及該第二端係沿一第一方向之相對二端。 該下閘極氧化侧壁覆蓋該下閘極之側面。該下間極介電層 覆蓋該下間極及該下閘極氧化側壁，其具有一接觸窗，該 # 接觸窗形成於該下閘極之該第一端之周緣上方相對位置， 以顯露出部分該下閘極》該導電半導體層具有一本體、一 源極及一汲極，該本體大致形成於該下閘極介電層之中間 部分上，該源極及該汲極形成於該本體沿著一第二方向之 二側邊，該第二方向大致垂直該第一方向。該上閘極介電 層沿該第一方向覆蓋該下閘極上方相對位置之該下閘極介 電層、該本體之一頂面及該本體之二側面，二側面係垂直 該第一方向。該上間極沿該第一方向覆蓋該下閘極介電 瞻 I、該接觸窗及該上閘極介電層。該邊襯形成於該上間極 介電層及該上閘極之二相對側面，該二相對側面係垂直於 該第二方向。該氧化保護層覆蓋該源極、該汲極、該邊襯 及該上閘極，其具有一第一貫孔、一第二貫孔及一第三貫 孔，該第一貫孔、該第二貫孔及該第三貫孔分別形成於該 - 接觸窗、該源極及該汲極之上方相對位置，以分別顯露部 • 分該上閘極、部分該源極及部分該汲極。該電極組具有一 第一電極、一第二電極及一第三電極，分別設置於該第一 貫孔該第二貫孔及該第三貫孔内，以分別電性連接該上 123800.doc 1355691 閘極、該源極及該汲極。 本發明之另-目的在於提供一種假閘極全環繞妙覆絕緣 . 冑置之製作方法’其包括以下步驟：U)提供-基板，該基 • 板具有一下閘極，該下閘極具有一第一端及一第二端，^ . 帛-端及該第二端係沿-第-方向之相對二端；(b)形成一 下閘極氧化側壁，其覆蓋該下閘極之側面；⑷形成—下閉 極”電層’其覆蓋該下閘極及該下閘極氧化側壁；⑷形成 • _導電半導體層’其具有-第-部分、-第二部分及一第 二部分，該第一部分大致形成於該下閘極介電層之中間部 分上，該第二部分及該第三部分形成於該第一部分沿著一 第二方向之二側邊，該第二方向大致垂直該第一方向；⑷ 成一上閘極介電層，其覆蓋該導電半導體層及該下閘極介 電層；（f)形成-接觸窗，該接觸窗係貫穿該上閘極介電層 及該下閘極介電層，且形成於該下閘極之該第一端之周緣 上方相對位置，以顯露出部分該下閘極；（g)形成一上閘 極’其覆蓋該接觸窗、顯露之該下閘極、該下間極介電層 及該上閘極介電層；⑻沿該第—方向移除部分該上間極及 部分該上閉極介電層，未移除之該上閘極及該上閘極介電 層具有相同寬度且位於該下閘極上方之相對位置，其中該 上閘極沿該第一方向覆蓋該下閘極介電層、該接觸窗、該 ^ 下閘極及該上閘極介電層；⑴形成一邊襯，其覆蓋該上閘 * 極"電層及該上閘極之二相對側面，該二相對側面係垂直 於該第二方向；⑴進行一離子佈植步驟，於該導電半導體 層之該第-部分 '該第二部分及該第三部分相對應地形成 123800.doc 1355691 一本體、一源極及一沒極；（k)形成一氧化保護層，其覆蓋 該源極、該汲極、該邊襯及該上閘極，其具有一第一貫 孔、一第二貫孔及一第三貫孔，該第一貫孔、該第二貫孔 及該第三貫孔分別形成於該接觸窗、該源極及該汲極之上 方相對位置，以分別顯露部分該上閘極、部分該源極及部 分該汲極；及（1)形成一電極組’其具有一第一電極、一第 一電極及一第三電極，分別設置於該第一貫孔、該第二貫1355691 IX. Description of the Invention: [Technical Field] The present invention relates to a coating insulation device and a method of fabricating the same, and more particularly to a false gate full-circumferential insulation device and a method of fabricating the same. [Prior Art] According to the evaluation of the International Semiconductor Technology Blueprint (ITRS), the short-channel effect caused by the traditional metal oxide half-effect transistor (MOSFET) under the influence of continuous shrinkage has been greatly challenged. Some scholars have proposed solutions such as using SOI, Ultra thin body (UBT) and high-k gate dielectric layers (such as Al2〇3, Hf02, etc.) to solve the most serious problems. Leakage current problem; use double gate material, metal gate, multi-layer gate engineering or fin (Fin) gate to control threshold threshold voltage (Threshold Voltage) curl down as channel length shrinks (roll-off And bungee-induced energy loss (DIBL) effects. But using these solutions will also extend a series of problems (Issues), such as using the SOI will face the floating body effect and Kink Effect, self-heating effect and single latch up effect; use Although the UTB relaxes the leakage current problem and suppresses the ultra-short channel effect, it will face the problem that the source/drain series resistance increases, the current drive capability is reduced, and the body flatness is uneven, causing the threshold voltage to fluctuate too much. Because of the parasitic PN junction capacitance of the traditional MOSFET, the grass makes the component switching speed and the high-frequency response slower, which also causes Jf and leakage current to be over--, // high. Although the use of SOI or UTB can reduce the parasitic PN junction capacitance, its practicality is not unquestionable, and there are many solutions to the problem of excessive series resistance, such as raising or deepening the source/汲. Extreme thickness or addition of bismuth metal to increase conductivity and reduce ohmic contact (Republic of China Patent Application No. 090108868, US Patent No. 825,535, No. 6117 712 '). There is also a countermeasure against the suppression of the floating body effect caused by S01 (e.g., U.S. Patent No. 6,686,629, No. 6,437,375), for example, forming under the body--Shi Xihua 锗 epitaxial crystal causes the charge to recombine via the surface effect, thereby avoiding the rise of the bulk potential. • (iv) Among the methods of causing leakage current due to short-channel effects, the most commonly used techniques are shallow-planted/drain-drain (LDD) techniques or the use of ultra-steep junctions (eg, US Patent No. 6 '465,847) or halo (Hal〇) Ion implantation (such as US Patent No. 6,936,278) to suppress the diffusion of depletion zones. But given the cost and complexity considerations, we would like to have some practical countermeasures, such as reducing process steps, reducing masks and ion implantation. The number of times and so on. In addition, the self-border gate of the 7G piece performance is more important in the size of the miniature situation. In the future, the wraparound gate (Gate State ar〇und) will have a more complete charge surface effect, which can improve the marginal effect and wear and tear between the body and the surrounding insulation layer, but the difficulty of production will be solved at the same time. The above problems are rare. It is fundamentally necessary to consider changes from component structures and some self-alignment mechanisms to simultaneously increase component performance and reduce process complexity. ^ ® & ‘It is necessary to provide an innovative and progressive, full-featured false gate full surround • _ over-insulation device and its fabrication method to solve the above problems. SUMMARY OF THE INVENTION It is an object of the present invention to provide a false open-pole full-wrap insulating device 123800.doc 1355691. The dummy gate full-covering insulating device comprises: a substrate, a lower gate oxide sidewall, a lower gate dielectric layer, a conductive semiconductor layer, an upper layer, an extremely dielectric layer, an upper gate, and Side lining, - oxidized protective layer and an electrode., group. The substrate has a lower gate. The lower gate has a first end and a second end. The first end and the second end are opposite ends of a first direction. The lower gate oxide sidewall covers the side of the lower gate. The lower interposer covers the lower interpole and the lower gate oxide sidewall, and has a contact window formed at a relative position above the periphery of the first end of the lower gate to reveal a portion of the lower gate: the conductive semiconductor layer has a body, a source, and a drain, the body is formed substantially on a middle portion of the lower gate dielectric layer, and the source and the drain are formed on the body The second direction is substantially perpendicular to the first direction along two sides of a second direction. The upper gate dielectric layer covers the lower gate dielectric layer at a relative position above the lower gate, the top surface of the body and the two sides of the body along the first direction, and the two sides are perpendicular to the first direction . The upper pole covers the lower gate dielectric I, the contact window and the upper gate dielectric layer along the first direction. The edge liner is formed on the opposite side of the upper interposer dielectric layer and the upper gate, and the two opposite sides are perpendicular to the second direction. The oxidized protective layer covers the source, the drain, the edge lining and the upper gate, and has a first through hole, a second through hole and a third through hole, the first through hole, the first through hole The two through holes and the third through holes are respectively formed at the relative positions of the contact window, the source, and the drain to respectively expose the upper gate, the portion of the source, and a portion of the drain. The electrode group has a first electrode, a second electrode and a third electrode, respectively disposed in the first through hole and the third through hole, to electrically connect the upper 123800.doc 1355691 Gate, the source and the bungee. Another object of the present invention is to provide a false gate full-surround insulation. The method of manufacturing the device includes the steps of: U) providing a substrate having a lower gate, the lower gate having a a first end and a second end, the 帛-end and the second end are opposite ends of the -th direction; (b) forming a lower gate oxidation sidewall covering the side of the lower gate; (4) Forming a lower-electrode "electric layer" covering the lower gate and the lower gate oxide sidewall; (4) forming a conductive semiconductor layer having a - portion - a second portion and a second portion a portion is formed substantially on a middle portion of the lower gate dielectric layer, the second portion and the third portion are formed on the two sides of the first portion along a second direction, the second direction being substantially perpendicular to the first portion Direction (4) forming an upper gate dielectric layer covering the conductive semiconductor layer and the lower gate dielectric layer; (f) forming a contact window through the upper gate dielectric layer and the lower gate a dielectric layer formed at a relative position above a circumference of the first end of the lower gate to Forming a portion of the lower gate; (g) forming an upper gate 'which covers the contact window, the exposed lower gate, the lower interlayer dielectric layer, and the upper gate dielectric layer; (8) along the first - removing a portion of the upper interpole and a portion of the upper closed dielectric layer, the unselected upper gate and the upper gate dielectric layer having the same width and opposite positions above the lower gate, wherein The upper gate covers the lower gate dielectric layer, the contact window, the lower gate and the upper gate dielectric layer along the first direction; (1) forming a side liner covering the upper gate* And an opposite side of the upper layer of the upper gate, wherein the two opposite sides are perpendicular to the second direction; (1) performing an ion implantation step on the first portion of the conductive semiconductor layer and the second portion The three portions correspondingly form 123800.doc 1355691 a body, a source and a immersion; (k) forming an oxidized protective layer covering the source, the drain, the edge liner and the upper gate, The first through hole, the second through hole and the third through hole, the first through hole, the second through hole and the third through The holes are respectively formed at the relative positions of the contact window, the source and the drain to respectively expose a portion of the upper gate, a portion of the source and a portion of the drain; and (1) form an electrode group having a first electrode, a first electrode and a third electrode are respectively disposed on the first through hole and the second through hole
孔及該第三貫孔内’以分別電性連接該上閘極、該源極及 該沒極。The hole and the third through hole are electrically connected to the upper gate, the source and the gate.
本發明之該半導體裝置之該上閘極及該下閘極互相接 觸，且連結於同一電極（該第一電極），使得該半導體裝置 之該上閘極及該下閘極環繞於該導電半導體層之該本體之 上方、下方及二侧，以形成一近乎全環繞式閘極之結構。 藉此，本發明之該半導體裝置可克服上閘極與下閘極間之 耦合電容問題，故本發明之該半導體裝置具有較傳統矽覆 絕緣金屬氧化物半導體元件（S〇I M〇SFET)或鰭式場效電 晶體（FinFET)較大的電流驅動和次臨界轉換特性。 【實施方法】 參考圖1A至5B，其顯示本發明假閘極全環繞矽覆絕緣 裝置之製作方法。其中’圖1A、2A、3A、4A&5A顯示沿 -第二方向之剖面圖；圖1B、2B、3B、4BA5B顯示沿— 第一方向之剖面圖。配合參考圖丨八至⑼，首先提供—基 板10,該基板10具有一下開極u，該下閉極丨丨具有一第: 端111及-第二端112 ’該第一端lu及該第二端112係沿— 123800.doc •10· 1355691 第一方向之相對二端。 該基板10可經由以下步驟製作而成。配合參考圖丨八及 1B，首先提供一承載板101，該承載板1〇1可為一矽基板。 接著，形成一埋入氧化層102於該承載板1〇1上，其中，該 埋入氧化層102係利用低壓化學氣相沉積（LpcvD)或電漿 辅助化學氣相沈積(PECVD)方法形成。接著，利用低壓化 學氣相沉積方法形成一半導體層1〇3,其覆蓋該埋入氧化 層102 »再配合參考圖以至邛，利用光學微影技術或電子 束直寫技術形成該半導體層103，以形成該下間極u。 較佳地，在形成該下閘極U之後’另進行載子摻雜及高 溫熱退火（Thermal annealing)之步驟，使該下閘極n具有 導電性。在本實施例中，載子摻雜技術可為中電流離子佈 植（Ion Implantation)或高溫熱驅入（in_situ)技術且離子佈 植能量及劑量需視該下閘極U之厚度而定。其中，若摻雜 之载子為磷（P)或砷（As)，該下閘極丨丨為^^型半導體；若摻 雜之載子為领（B) ’該下閘極11為p型半導體。 要注意的是，該基板10亦可直接選用一般矽基板、矽覆 絕緣（SOI)基板、鍺覆絕緣（G0I)基板、玻璃、石英、鑽 石、塑膠或其他單層絕緣基板。若該基板1〇係為矽覆絕緣 基板，則該下閘極11係為單晶矽。 配合參考圖3A至4B，形成一下閘極氧化側壁2〇，該下 間極氧化側壁20覆蓋該下閘極U之側面。在本實施例中， 該下閘極氧化側壁2〇係經由以下步驟製作而成。配合參考 圖3A及3B，形成一下閘極氧化層2〇1 ,其覆蓋該下閘極 123800.doc -11 · 1355691 i顧Γ^ 3Α至4B，移除部分該下間極氧化層則 20::該下間極11之頂面，以形成該下間極氧化側壁 2=地’該下間極氧化層2〇1係以低塵化學氣相沉積 ^㈣助化學氣相沈積方法形成’利用化學機械研磨 )技術移除部分之該下閘極氧化層2(H，使該下間極氧 化側壁20之厚度與該下閘極&厚度相同。 配合參考圖5Α及5Β，形成一下間極介電層如，該下間 極介電層30覆蓋該下閘極u及該下閘極氧化側壁。要注 意的是’若該下閘仙係為一多晶石夕層，該下間極介電声 3〇係以低Μ化學氣相沉積方法形成。“，若該下間極^ 係為單晶石夕層，該下閑極介電層3〇可利用低廢化學氣相沉 積方法或乾式熱氧化技術形成。 配合參考圖6Α及6Β，形成一導電半導體層4〇,其具有 一第一部分401、一第二部分4〇2及一第三部分4〇3，該第 一部分401大致形成於該下閘極介電層3〇之中間部分上， 該第二部分402及該第三部分4〇3形成於該第一部分4〇丨沿 著一第二方向之二侧邊，該第二方向大致垂直該第一方 向0 在本實施例中，該導電半導體層4〇係以低壓化學氣相沉 積、常壓化學氣相沉積（APCVD)或電漿輔助化學氣相沈積 技術形成，其中，該導電半導體層4〇可為多晶矽 (polysilicon)或非晶石夕（amorph〇us silicon)。較佳地，本發 明利用尚溫回火方法進行固相再結晶成長（spc)或利用準 分子雷射回火（ELA)方法進行再結晶，以改善該導電半導 123800.doc -12- 1355691 體層40之品質及減少該導電半導體層仞之缺陷。 在本實施例中，在形成該導電半導體層^驟之隻另 :括：第一熱退火之步驟，該第-熱退火步驟係利用快速 升溫熱退火Ο技術或利用高溫爐管退火一 酬⑽。較佳地，該第—熱退火步驟之退火溫度係介於 800 C至950 C，該第-熱退火步驟之退火時間係介於1分 鐘至3 0分鐘之間。The upper gate and the lower gate of the semiconductor device of the present invention are in contact with each other and are connected to the same electrode (the first electrode) such that the upper gate and the lower gate of the semiconductor device surround the conductive semiconductor The upper, lower and opposite sides of the body of the layer form a structure of a nearly full wrap gate. Thereby, the semiconductor device of the present invention can overcome the coupling capacitance problem between the upper gate and the lower gate, so the semiconductor device of the present invention has a more conventional overlying insulating metal oxide semiconductor device (S〇IM〇SFET) or The fin field effect transistor (FinFET) has large current drive and sub-critical switching characteristics. [Embodiment] Referring to Figures 1A to 5B, there is shown a method of fabricating a false gate full-wrap insulating device of the present invention. 1A, 2A, 3A, 4A & 5A show a cross-sectional view along the second direction; Figs. 1B, 2B, 3B, 4BA5B show a cross-sectional view along the first direction. With reference to FIGS. 8-8, a substrate 10 is first provided, the substrate 10 has a lower opening u, and the lower closing pole has a first end 111 and a second end 112 'the first end lu and the first The two ends of the 112 series are - 123800.doc • 10· 1355691 the opposite ends of the first direction. The substrate 10 can be fabricated through the following steps. Referring to Figures 8 and 1B, a carrier board 101 is first provided, and the carrier board 101 can be a substrate. Next, a buried oxide layer 102 is formed on the carrier substrate 101, wherein the buried oxide layer 102 is formed by a low pressure chemical vapor deposition (LpcvD) or a plasma assisted chemical vapor deposition (PECVD) method. Next, a semiconductor layer 1〇3 is formed by a low-pressure chemical vapor deposition method, and the buried oxide layer 102 is covered, and then the reference layer is used to form the semiconductor layer 103 by optical lithography or electron beam direct writing. To form the lower interpole u. Preferably, after the formation of the lower gate U, a step of carrier doping and thermal annealing is performed to make the lower gate n conductive. In this embodiment, the carrier doping technique may be a medium current ion implantation (Ion Implantation) or a high temperature thermal drive (in_situ) technique, and the ion implantation energy and dose are determined according to the thickness of the lower gate U. . Wherein, if the doped carrier is phosphorus (P) or arsenic (As), the lower gate electrode is a ^^ type semiconductor; if the doped carrier is a collar (B) 'the lower gate 11 is p Type semiconductor. It should be noted that the substrate 10 can also be directly selected from a general germanium substrate, a silicon-on-insulator (SOI) substrate, a germanium-insulated (G0I) substrate, glass, quartz, diamond, plastic or other single-layer insulating substrate. When the substrate 1 is a blanket insulating substrate, the lower gate 11 is a single crystal germanium. Referring to Figures 3A through 4B, a lower gate oxide sidewall 2 is formed which covers the side of the lower gate U. In this embodiment, the lower gate oxide sidewall 2 is fabricated through the following steps. Referring to FIGS. 3A and 3B, a gate oxide layer 2〇1 is formed, which covers the lower gate 123800.doc -11 · 1355691 i Γ Α 3 Α to 4B, and removes part of the lower electrode oxide layer 20: : the top surface of the lower interpole 11 to form the lower interpole oxidation sidewall 2 = ground 'the lower interpole oxide layer 2 〇 1 is formed by low-dust chemical vapor deposition ^ (four) assisted chemical vapor deposition method The chemical mechanical polishing process removes a portion of the lower gate oxide layer 2 (H such that the thickness of the lower interpole oxide sidewall 20 is the same as the thickness of the lower gate & the reference is shown in FIGS. 5 and 5 to form a lower interpole. a dielectric layer, for example, the lower interposer dielectric layer 30 covers the lower gate u and the lower gate oxide sidewall. It is noted that if the lower gate is a polycrystalline layer, the lower interpole The dielectric acoustic lanthanum is formed by a low-lying chemical vapor deposition method. "If the lower electrode is a single crystal layer, the lower dielectric layer 3 〇 can utilize a low-waste chemical vapor deposition method. Or a dry thermal oxidation technique is formed. Referring to FIGS. 6A and 6B, a conductive semiconductor layer 4 is formed, which has a first portion 401 and a second portion 4. 2 and a third portion 4〇3, the first portion 401 is formed substantially on a middle portion of the lower gate dielectric layer 3〇, and the second portion 402 and the third portion 4〇3 are formed in the first portion 4 The second side of the second direction is substantially perpendicular to the first direction. In the embodiment, the conductive semiconductor layer 4 is deposited by low pressure chemical vapor deposition and atmospheric pressure chemical vapor deposition. Formed by (APCVD) or plasma-assisted chemical vapor deposition, wherein the conductive semiconductor layer 4 can be polysilicon or amorph〇us silicon. Preferably, the present invention utilizes a warm temperature back. The fire method performs solid phase recrystallization growth (spc) or recrystallization by excimer laser tempering (ELA) method to improve the quality of the conductive semiconductor layer 40800.doc -12-1355691 and reduce the conductive semiconductor layer. In the present embodiment, in forming the conductive semiconductor layer, only the first thermal annealing step is performed, and the first thermal annealing step is performed by using a rapid heating annealing technique or a high temperature furnace. The tube is annealed (10). Preferably, the tube - based thermal annealing step annealing temperature of between 800 C to 950 C, the second - based thermal annealing step annealing time of between 1 minute to 30 minutes.
配合參考圖7 A及7 B，形成一上閘極介電層5 〇，較佳 地’該上閘極介電層5〇係以低屡化學氣相沉積方法或乾式 熱氧化技術形成。該上閘極介電層5G覆蓋該導電半導體層 40及該下㈣介電層3Ge配合參考圖8a&8b，形成一^ 觸窗31 ’該接觸窗31係貫穿該上閘極介電層5〇及該下閉極 介電層30 ’且形成於該下閘極"之該第一端⑴之周緣上 方相對位置’以顯露出部分該下間極u。在本實施例中， 該，觸窗31係經由以下步驟製作而成。首先，利用微影製 程疋義《罩。接著，以钱刻方法形成該接觸窗Μ。較佳 地該微衫製程係為光學微影技術或電子束微影技術（卜 )較佳地，該光學微影技術係使用Mine、g_line或深 紫外光（DUV)。 < 配口參考圖9A及9B ’形成-上閘極6〇，其覆蓋該接觸 窗31、顯露之該下閘極11、該下閘極介電層3〇及該上間極 ”電層50。配合參考圖1〇A及1〇B，沿該第一方向移除部 为該上閘極60及部分該上閘極介電層50，未移除之該上閘 極60及該上閘極介電層5〇具有相同寬度且位於該下閘極u 123800.doc 13 1355691 上方之相對位置，其中該上閘極60沿該第一方向覆蓋該下 閘極介電層30、該接觸窗31、該下閘極1〗及該上閘極介電 層50。在本實施例中，該上閘極6〇係以低壓化學氣相沉積 或電漿辅助化學氣相沈積方法形成多晶矽層。較佳地，該 上閘極60係利用中電流離子佈植或高溫熱驅入技術進行摻 雜步驟。 配合參考圖11A及11B ’形成一邊襯（side_well spaee〇 ’該邊襯70覆蓋該上閘極介電層50及該上閘極6〇之二相 對侧面’該二相對侧面係垂直於該第二方向。在本實施例 中’該邊襯70係利用低壓化學氣相沉積方法地毯式成長一 層二氧化石夕層或氮化石夕層，再利用自我對準方法姓刻該二 ，氧化矽層或該氮化矽層而成》 配合參考圖11A、11B及12A、12B，進行一離子佈植步 驟’於該導電半導體層40之該第一部分401、該第二部分 402及該第三部分4〇3相對應地形成一本體41、一源極42及 一汲極43。 在本實施例中’其係以該上閘極70作為自我對準之硬式 遮罩’利用離子佈植方法形成該本體41、該源極42及該汲 極43。在該離子佈植步驟之後，另包括一第二熱退火步 驟’該第二熱退火步驟係利用快速升溫熱退火技術或利用 瞬間升溫熱退火（spike anneal)。其中，該第二熱退火步驟 之退火溫度係介於800°C至ll〇〇°C之間，該第二熱退火步 驟之退火時間係介於0.2秒至30秒之間。 配合參考圖13A及13B，形成一氧化保護層80，該氧化 123800.doc -14- 1355691 保4層80覆蓋該源極42、該沒極43、該邊襯及該上間極 6一〇。該氧化保護層80具有一第一貫孔81、一第二貫孔82及 第一貝孔83，該第一貫孔81、該第二貫孔82及該第三貫 孔83刀別形成於該接觸窗3丨、該源極42及該汲極之上方 相對位置，以分別顯露部分該上閘極6〇、部分該源極及 部分該沒極43。 在本實施例中，該氧化保護層80係利用電槳輔助化學氣 相沉積或旋塗式塗佈法（Spin-on Dielectric ; SOD)形成， 該第一貫孔81、該第二貫孔82及該第三貫孔83係利用光學 微影技術或電子束直寫技術所形成。 接著，形成一電極組90，該電極組90具有一第一電極 91、一第二電極92及一第三電極93，分別設置於該第一貫 孔81、該第二貫孔82及該第三貫孔83内，以分別電性連接 該上閘極60、該源極42及該汲極43。 在本實施例中’該電極組90係經由以下步驟製作而成。 首先’形成一金屬層，該金屬層覆蓋該氧化保護層8〇、該 第一貫孔81、該第二貫孔82及該第三貫孔83。接著，移除 部分該金屬層，以形成該電極組90。較佳地，該金屬層係 利用物理氣相沉積（PVD)方法形成，或者該金屬層亦可利 用賤鍵（sputtering)或蒸鐘（evaporation)方法形成。其中， 該第一電極91、該第二電極92及該第三電極93係利用光學 微影技術或電子束直寫技術定義其結構及形狀。 再參考圖13 A及13B ’其顯示本發明假閘極全環繞石夕覆 絕緣裝置。該假閘極全環繞矽覆絕緣裝置1包括：一基板 123800.doc •15- 1355691 10、一下閘極氧化側壁20、一下閘極介電層30、一導電半 導體層40、一上閘極介電層5〇、一上閘極6〇、一邊襯7〇、 一氧化保護層80及一電極組9〇。 該基板10具有一下閘極11，該下閘極11具有一第一端 - U1及一第二端112，該第一端111及該第二端112係沿一第 一方向之相對二端。其中，該基板1〇可為一般矽基板、矽 覆絕緣基板、鍺覆絕緣基板、玻璃、石英、鑽石、塑膠或 • 其他單層絕緣基板。要注意的是，依據摻雜之載子之不 同，該下閘極11可為N型半導體（摻雜之載子為磷或砷）或卩 型半導體（摻雜之載子為爛）。 該下閘極氧化側壁20覆蓋該下閘極u之側面。較佳地， 該下閘極11厚度為50奈米至200奈米。較佳地，該下閘極 氧化側壁20之材質係選自由二氧化矽（si〇2)、氮化矽 (Sl3N4)、氧氮氧（ON〇)、氧化铭（Al2〇3)或石夕化碳（沉）。 該下閘極介電層3G覆蓋該下閘極u及該下閘極氧化側壁 籲 2G〇該下閘極介電層3〇具有_接觸窗31，該接觸窗形成 於該下閘極11之該第一端i i!之周緣上方相對位置，以顯 路出部分該下閘極11。較佳地，該下閘極介電層3〇之材質 係選自由二氧化矽、氮化矽、氧化鈕（Ta2〇5)、氧化铪 (HGO)、氧化鍅（Zr〇2)或等效厚度〇 5奈书至％奈米之設定 ' 冑介電常數值介電材料。在本實施例中，該設；t高介電常 ^ 數值大於10。 該導電半導體層40具有—本體41、—源極42及一汲極 43，該本體41大致形成於該下閘極介電層3〇之中間部分 123800.doc •16- 1355691 上，該源極42及該汲極43形成於該本體41沿著一第二方向 之一側邊’該第一方向大致垂直該第一方向。其中，該導 電半導體層40可為多晶矽（p〇iysiiic〇n)或非晶矽（am〇rph〇us silicon)。該導電半導體層係選自由第四族、v族材 料或其所組成之群之單層或多層結構。較佳地，該導電半 導體層40之厚度係為〇 5奈米至ι〇〇奈米。 該上閘極介電層5 0沿該第一方向覆蓋該下閘極丨丨上方相 對位置之該下閘極介電層3〇、該第一部分4〇1之一頂面及 該第一部分401之二側面，二側面係垂直該第一方向。較 佳地，該上閘極介電層50之材質係選自由二氧化矽、氮化 矽、氧化鈕、氧化铪（Hf2〇)、氧化锆或等效厚度〇 5奈米至 5〇奈米之設定高介電常數值介電材料。在本實施例中該 設定高介電常數值大於10。 該上閘極60沿該第一方向覆蓋該下閘極介電層3〇、該接 觸窗31及該上閘極介電層5〇。較佳地，該上閘極6〇之厚度 為50奈米至200奈米。其中，該上閘極6〇係為一多晶矽 層，且該上閘極60可為N型半導體或P型半導體。較佳地， 該夕b曰矽層係為成長單層或多層之中能隙（Mid_Ga…金屬 或金屬矽化物（silicidep該邊襯7〇形成於該上閘極介電層 5〇及該上閘極60之二相對側面，該二相對側面係垂直於該 第二方向。 該氧化保濩層80覆蓋該源極42、該汲極43、該邊襯70及 該上閘極60。該氧化保護層8〇具有一第一貫孔以、一第二 貫孔82及一第三貫孔83。該第一貫孔81、該第二貫孔以及 123800.doc -17· 1355691 該第三貫孔83分別形成於該接觸窗3 1、該源極42及該汲極 43之上方相對位置，以分別顯露部分該上閘極6〇、部分該 源極42及部分該汲極43。較佳地，該氧化保護層80係為二 氧化矽、磷矽玻璃（PSG)、硼磷矽玻璃（BPSG)、氟矽玻璃 (Fluorinated Silicate Glass ; FSG)、鑽石（Diamond)或其他 低介電係數之材質。 該電極組90具有一第一電極91、一第二電極92及一第三 電極93，分別設置於該第一貫孔81、該第二貫孔82及該第 三貫孔83内，以分別電性連接該上閘極6〇、該源極42及該 汲極43。較佳地，該電極組90係為鋁（A1)、銅（Cu)或鋁矽 銅合金（Al-Si-Cu)。 本發明之假閘極全環繞矽覆絕緣裝置及其製作方法中， 該半導體裝置1之該上閘極60及該下閘極n互相接觸，且 連結於同一電極（該第一電極91)，使得該半導體裝置丨之該 上閘極60及該下閘11極環繞於該導電半導體層4〇之該本體 41之上方、下方及二側，以形成一近乎全環繞式閘極之結 構。藉此，本發明之該半導體裝置〗可克服上閘極與下閘 極間之耦合電容問題，故本發明之該半導體裝置丨具有較 傳統矽覆絕緣金屬氧化物半導體元件（s〇I m〇sfet)或鰭 式場效電晶體（Fin FET)較大的電流驅動和次臨界轉換特 性。 惟上述實施例僅為說明本創作之原理及其功效，而非用 以限制本創作。心，f於此技術之人士對上述實施例進 行修改及變化仍不脫本創作之精神。本創作之權利範圍應 123800.doc -18- 1355691 如後述之申請專利範圍所列。 【圖式簡單說明】 . 圖1A及1B顯示本發明之基板示意圖； 圖2A及2B顯示本發明於該基板形成—下閘極之示意 * 囬 · • 圆， 圖3A及3B顯示本發明形成一下閘極氧化層覆蓋該下閘 極之示意圖； % 圖4 A及4B顯示本發明形成一下閘極氧化侧壁之示意 团 · 園， 圖5A及5B顯示本發明形成一下閘極介電層之示意圖； 圖6A及6B顯示本發明形成一導電半導體層之示意圖； 圖7A及7B顯示本發明形成一上閘極介電層之示意圖； 圖8A及8B顯示本發明形成一接觸窗之示意圖； 圖9A及9B顯示本發明形成一上閘極之示意圖； 圖10A及10B顯示本發明移除部分該上閘極及部分該上 ® 閘極介電層之示意圖； 圖11A及11B顯示本發明形成一邊襯之示意圖； 圖12A及12B顯示本發明於該導電半導體層進行—離子 佈植步驟’以形成一本體、一源極及一汲極之示意. 圖13A及13B顯示本發明假閘極全環繞矽覆絕緣裝置之 - 示意圖。 . 【主要元件符號說明】 1 本發明假閘極全環繞矽覆絕緣裝置 10 基板 123800.doc •19- 1355691Referring to Figures 7A and 7B, an upper gate dielectric layer 5 is formed, preferably the upper gate dielectric layer 5 is formed by a low chemical vapor deposition method or a dry thermal oxidation technique. The upper gate dielectric layer 5G covers the conductive semiconductor layer 40 and the lower (four) dielectric layer 3Ge. Referring to FIG. 8a & 8b, a contact window 31 is formed. The contact window 31 extends through the upper gate dielectric layer 5. And the lower closed dielectric layer 30' is formed at a relative position above the periphery of the first end (1) of the lower gate to expose a portion of the lower interpole u. In the present embodiment, the touch window 31 is fabricated through the following steps. First, use the lithography process to "cover." Next, the contact window is formed by a money engraving method. Preferably, the micro-shirting process is an optical lithography technique or an electron beam lithography technique. Preferably, the optical lithography technique uses Mine, g_line or deep ultraviolet light (DUV). < Porting Referring to Figures 9A and 9B' forming-upper gate 6A, covering the contact window 31, the exposed lower gate 11, the lower gate dielectric layer 3, and the upper interlayer "electric layer" 50. Referring to FIGS. 1A and 1B, the first direction removing portion is the upper gate 60 and a portion of the upper gate dielectric layer 50, and the upper gate 60 and the upper portion are not removed. The gate dielectric layer 5 has the same width and is located above the lower gate u 123800.doc 13 1355691, wherein the upper gate 60 covers the lower gate dielectric layer 30 along the first direction, the contact The window 31, the lower gate 1 and the upper gate dielectric layer 50. In the embodiment, the upper gate 6 is formed by a low pressure chemical vapor deposition or a plasma assisted chemical vapor deposition method to form a polysilicon layer. Preferably, the upper gate 60 is doped by a medium current ion implantation or a high temperature thermal drive technique. The side liner is formed by referring to FIGS. 11A and 11B' (side_well spaee〇' The upper side of the upper gate dielectric layer 50 and the upper side of the upper gate 6' are opposite to the second direction. In this embodiment The side lining 70 is formed by a low pressure chemical vapor deposition method using a low-temperature chemical vapor deposition method to grow a layer of a cerium oxide layer or a layer of nitriding stone, and then using a self-alignment method to name the ruthenium oxide layer or the tantalum nitride layer. Referring to FIGS. 11A, 11B and 12A, 12B, an ion implantation step is performed to form a body 41 corresponding to the first portion 401, the second portion 402, and the third portion 4〇3 of the conductive semiconductor layer 40. a source 42 and a drain 43. In the present embodiment, the upper gate 70 is used as a self-aligned hard mask to form the body 41, the source 42 and the ion implant method. a drain 43. After the ion implantation step, a second thermal annealing step is further included. The second thermal annealing step utilizes a rapid thermal annealing technique or a spike anneal. The annealing temperature of the second thermal annealing step is between 800 ° C and 11 ° C, and the annealing time of the second thermal annealing step is between 0.2 seconds and 30 seconds. Referring to FIGS. 13A and 13B, Forming an oxidation protective layer 80, the oxidation 123800.doc -14- 135569 The protective layer 80 has a first through hole 81, a second through hole 82 and a first portion. The protective layer 80 has a first through hole 81 and a second through hole 82. The first through hole 81, the second through hole 82 and the third through hole 83 are formed at opposite positions of the contact window 3, the source 42 and the drain to respectively reveal A portion of the upper gate 6〇, a portion of the source, and a portion of the gate 43. In the embodiment, the oxidized protective layer 80 is electrically padded by chemical vapor deposition or spin coating (Spin-on). Dielectric; SOD) is formed, and the first through hole 81, the second through hole 82, and the third through hole 83 are formed by optical lithography or electron beam direct writing. Then, an electrode group 90 is formed. The electrode group 90 has a first electrode 91, a second electrode 92, and a third electrode 93. The first through hole 81, the second through hole 82, and the first The upper via 86 is electrically connected to the upper gate 60, the source 42 and the drain 43 respectively. In the present embodiment, the electrode group 90 is produced through the following steps. First, a metal layer is formed which covers the oxidation protection layer 8A, the first continuous hole 81, the second through hole 82, and the third through hole 83. Next, a portion of the metal layer is removed to form the electrode group 90. Preferably, the metal layer is formed by a physical vapor deposition (PVD) method, or the metal layer may be formed by a sputtering or evaporation method. The first electrode 91, the second electrode 92, and the third electrode 93 define the structure and shape thereof by optical lithography or electron beam direct writing. Referring again to Figures 13A and 13B', there is shown a false gate full-wound insulation device of the present invention. The dummy gate full-around insulating device 1 comprises: a substrate 123800.doc • 15-1355691 10, a lower gate oxide sidewall 20, a lower gate dielectric layer 30, a conductive semiconductor layer 40, and an upper gate dielectric layer. The electric layer 5 〇, an upper gate 6 〇, a side lining 7 〇, an oxidized protective layer 80 and an electrode group 9 〇. The substrate 10 has a lower gate 11 having a first end - U1 and a second end 112. The first end 111 and the second end 112 are opposite ends of the first direction. The substrate 1 can be a general germanium substrate, a covered insulating substrate, a covered insulating substrate, glass, quartz, diamond, plastic or other single-layer insulating substrate. It is to be noted that the lower gate 11 may be an N-type semiconductor (the doped carrier is phosphorus or arsenic) or a 卩-type semiconductor (the doped carrier is rotten) depending on the doped carrier. The lower gate oxide sidewall 20 covers the side of the lower gate u. Preferably, the lower gate 11 has a thickness of 50 nm to 200 nm. Preferably, the material of the lower gate oxide sidewall 20 is selected from the group consisting of cerium oxide (si〇2), cerium nitride (Sl3N4), oxynitride (ON〇), oxidized ing (Al2〇3) or Shixi Carbon (sink). The lower gate dielectric layer 3G covers the lower gate u and the lower gate oxide sidewall 2G. The lower gate dielectric layer 3 has a contact window 31 formed on the lower gate 11 The relative position above the circumference of the first end ii! is to show a portion of the lower gate 11. Preferably, the material of the lower gate dielectric layer 3 is selected from the group consisting of cerium oxide, cerium nitride, oxidized button (Ta 2 〇 5), cerium oxide (HGO), cerium oxide (Zr 〇 2) or equivalent. The thickness is 〇5N to the setting of %N' 胄 dielectric constant value dielectric material. In this embodiment, the setting of the high dielectric constant is greater than 10. The conductive semiconductor layer 40 has a body 41, a source 42 and a drain 43. The body 41 is formed substantially on the middle portion 123800.doc • 16-1355691 of the lower gate dielectric layer. 42 and the drain 43 are formed on the side of the body 41 along a second direction, the first direction being substantially perpendicular to the first direction. The conductive semiconductor layer 40 may be polycrystalline germanium or amorphous germanium (am〇rph〇us silicon). The conductive semiconductor layer is selected from a single layer or a multilayer structure of a group of Group 4 or Group V materials or a group thereof. Preferably, the thickness of the conductive semiconductor layer 40 is from 〇 5 nm to ι 〇〇. The upper gate dielectric layer 50 covers the lower gate dielectric layer 3 at the opposite position of the lower gate electrode along the first direction, the top surface of the first portion 4〇1, and the first portion 401 On the two sides, the two sides are perpendicular to the first direction. Preferably, the material of the upper gate dielectric layer 50 is selected from the group consisting of ceria, tantalum nitride, oxidized knob, hafnium oxide (Hf2〇), zirconia or equivalent thickness 〇5 nm to 5 Å nm. The dielectric material is set to a high dielectric constant value. In the present embodiment, the high dielectric constant value is set to be greater than 10. The upper gate 60 covers the lower gate dielectric layer 3, the contact window 31 and the upper gate dielectric layer 5A along the first direction. Preferably, the upper gate 6〇 has a thickness of 50 nm to 200 nm. The upper gate 6 is a polysilicon layer, and the upper gate 60 can be an N-type semiconductor or a P-type semiconductor. Preferably, the 曰矽b曰矽 layer is a growth single layer or a plurality of interlayer energy gaps (Mid_Ga...metal or metal bismuth (silicidep lining 7 〇 is formed on the upper gate dielectric layer 5 〇 and thereon) The opposite sides of the gate 60 are perpendicular to the second direction. The oxide layer 80 covers the source 42, the drain 43, the edge liner 70 and the upper gate 60. The oxidation The protective layer 8 has a first through hole, a second through hole 82 and a third through hole 83. The first through hole 81, the second through hole and the 123800.doc -17· 1355691 the third through The holes 83 are respectively formed at the opposite positions of the contact window 31, the source 42 and the drain 43 to respectively expose a portion of the upper gate 6〇, a portion of the source 42 and a portion of the drain 43. Preferably, the holes 43 are formed. The oxidized protective layer 80 is cerium oxide, phosphoric bismuth glass (PSG), borophosphoquinone glass (BPSG), Fluorinated Silicate Glass (FSG), diamond (Diamond) or other low dielectric constant. The electrode group 90 has a first electrode 91, a second electrode 92 and a third electrode 93, respectively disposed on the first through hole 81, The second through hole 82 and the third through hole 83 are electrically connected to the upper gate 6 〇, the source 42 and the drain 43. Preferably, the electrode group 90 is aluminum (A1). Copper (Cu) or aluminum beryllium copper alloy (Al-Si-Cu). In the false gate full-wrap insulating device of the present invention and the manufacturing method thereof, the upper gate 60 and the lower portion of the semiconductor device 1 The gates n are in contact with each other and are connected to the same electrode (the first electrode 91) such that the upper gate 60 and the lower gate 11 of the semiconductor device are surrounded by the body 41 of the conductive semiconductor layer 4 , the lower side and the two sides to form a structure of a nearly full-wrap gate. Thereby, the semiconductor device of the present invention can overcome the coupling capacitance problem between the upper gate and the lower gate, so the semiconductor device of the present invention丨 has larger current drive and sub-critical switching characteristics than conventional overlying insulating metal oxide semiconductor devices (s〇I m〇sfet) or fin field effect transistors (Fin FETs). However, the above examples are only illustrative of the creation. The principle and its efficacy, not to limit the creation. Modifications and changes to the above-described embodiments are not inconsistent with the spirit of the present invention. The scope of the present invention should be in accordance with the scope of the patent application described below. [Simplified Schematic] Figure 1A and 1B show 2A and 2B are schematic diagrams showing the formation of a lower gate of the substrate in the present invention, and FIGS. 3A and 3B are diagrams showing the formation of a lower gate oxide layer covering the lower gate of the present invention; 4A and 4B show a schematic diagram of the present invention forming a gate oxide sidewall, and FIGS. 5A and 5B are schematic views showing the formation of a gate dielectric layer of the present invention; FIGS. 6A and 6B show the formation of a conductive semiconductor of the present invention. 7A and 7B are schematic views showing the formation of an upper gate dielectric layer of the present invention; Figs. 8A and 8B are views showing the formation of a contact window of the present invention; and Figs. 9A and 9B are views showing the formation of an upper gate of the present invention. 10A and 10B are schematic views showing the removal of a portion of the upper gate and a portion of the upper gate dielectric layer of the present invention; FIGS. 11A and 11B are views showing a side liner of the present invention; and FIGS. 12A and 12B show the present invention. The conductive semiconductor layer - ion implantation step 'to form a main body, a source and a drain of a schematic 13A and 13B show false gate electrode of the present invention means the whole surrounding silicon insulating coating - Fig. [Description of main component symbols] 1 The false gate full-circle insulation device of the present invention 10 substrate 123800.doc •19- 1355691
11 下閘極 20 下閘極氧化侧壁 30 下閘極介電層 31 接觸窗 40 導電半導體層 41 本體 42 源極 43 汲極 50 上閘極介電層 60 上閘極 70 邊襯 80 氧化保護層 81 第一貫孔 82 第二貫孔 83 第三貫孔 90 電極組 91 第一電極 92 第二電極 93 第三電極 111 第一端 112 第二端 401 第一部分 402 第二部分 403 第三部分 123800.doc -20-11 lower gate 20 lower gate oxide sidewall 30 lower gate dielectric layer 31 contact window 40 conductive semiconductor layer 41 body 42 source 43 drain 50 upper gate dielectric layer 60 upper gate 70 side liner 80 oxidation protection Layer 81 First Consistent Hole 82 Second Through Hole 83 Third Through Hole 90 Electrode Group 91 First Electrode 92 Second Electrode 93 Third Electrode 111 First End 112 Second End 401 First Part 402 Second Part 403 Part III 123800.doc -20-