WO2017070868A1 - N型tft的制作方法 - Google Patents

N型tft的制作方法 Download PDF

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Publication number
WO2017070868A1
WO2017070868A1 PCT/CN2015/093109 CN2015093109W WO2017070868A1 WO 2017070868 A1 WO2017070868 A1 WO 2017070868A1 CN 2015093109 W CN2015093109 W CN 2015093109W WO 2017070868 A1 WO2017070868 A1 WO 2017070868A1
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layer
region
polysilicon layer
fabricating
gate
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French (fr)
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胡国仁
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Wuhan China Star Optoelectronics Technology Co Ltd
TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US14/892,572 priority Critical patent/US9698177B1/en
Publication of WO2017070868A1 publication Critical patent/WO2017070868A1/zh
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    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H10D86/0227—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials using structural arrangements to control crystal growth, e.g. placement of grain filters
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    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
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    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
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Definitions

  • the present invention relates to a semiconductor fabrication process, and more particularly to a method of fabricating an N-type TFT.
  • the flat panel display device has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the conventional flat panel display device mainly includes a liquid crystal display (LCD), an organic light emitting display (OLED), and the like.
  • TFTs Thin Film Transistors
  • the TFT can be classified into two types: an N-type TFT (electrons are carriers) and a P-type TFT (with holes as carriers).
  • the leakage current of the N-type TFT is large.
  • a lightly doped drain (LDD) is usually disposed on both sides of the channel of the semiconductor layer in the N-type TFT. Reduce leakage current through LDD.
  • a conventional method of fabricating an N-type TFT having an LDD structure includes the following steps:
  • Step 1 as shown in FIG. 1 , a substrate 100 is provided, a light shielding layer is deposited on the substrate 100 , and the light shielding layer is patterned to obtain an integral light shielding strip 210 .
  • Step 2 As shown in FIG. 2, a buffer layer 200 and an amorphous silicon layer are sequentially deposited on the integral light-shielding strip 210 and the substrate 100, and the amorphous silicon layer is subjected to dehydrogenation treatment using excimer laser annealing. The process converts the amorphous silicon layer into a polysilicon layer 300.
  • the grain size in the polysilicon layer 300 obtained through the step 2 is substantially uniform.
  • Step 3 as shown in FIG. 4, a photoresist layer 400' is coated on the polysilicon layer 300, and the photoresist layer 400' is exposed and developed by a yellow light process to expose two of the polysilicon layers 300.
  • the end region, the photoresist layer 400 ′ is used as a occlusion layer for the N-type heavily doping of the two end regions of the polysilicon layer 300, and then the photoresist layer 400 ′ is removed;
  • Step 4 depositing a gate insulating layer 400 on the polysilicon layer 300;
  • Step 5 depositing a gate on the gate insulating layer 400.
  • the electric film is patterned and patterned to obtain a gate conductive layer 500.
  • the length of the gate conductive layer 500 is smaller than the length of the photoresist layer 400' in the above step 3 to expose the undoped portion of the above step 3.
  • the polysilicon layer 300 is further N-type lightly doped with the gate conductive layer 500 as a shielding layer to obtain an N-type heavily doped region 310, an N-type lightly doped region 320, and a channel region 330.
  • the N-type lightly doped region 320 constitutes an LDD.
  • Step 6 Continue the subsequent general semiconductor process, such as depositing an interlayer insulating layer and etching the interlayer insulating layer to form a contact hole with the gate insulating layer 400, depositing and etching a metal layer to form a source, a drain, a gate, etc., and finally An N-type TFT having an LDD structure is obtained.
  • the above conventional method for fabricating an N-type TFT having an LDD structure requires a photomask to define a heavily doped region and a lightly doped region, and requires two ion doping, a plurality of process steps, and a high cost, and Since the heavily doped region and the lightly doped region often have deviations in the alignment of the yellow light, the uniformity of the TFT is affected.
  • Another method for fabricating an N-type TFT having an LDD structure is to use a halftone mask to etch the gate twice in succession, and to perform N-type heavily doping with the first etched gate as a shielding layer.
  • the N-type light doping is performed by using the gate after the second etching as a shielding layer to form an LDD.
  • Figure 8 shows the relationship between the resistivity of polysilicon and the doping concentration for different grain sizes. From this figure, it can be seen that polysilicon of different grain sizes have different resistivities at the same doping concentration. Specifically, at the same doping concentration, the smaller the polycrystalline silicon grains, the larger the resistivity. Therefore, at the same doping concentration, the effect equivalent to the LDD structure can be achieved by controlling the size of the polycrystalline silicon crystal grains.
  • An object of the present invention is to provide a method for fabricating an N-type TFT, which has different resistivity characteristics of polycrystalline silicon having different grain sizes at the same doping concentration, and can achieve an effect equivalent to an LDD structure by only one ion doping. , saving process time and manufacturing costs.
  • the present invention provides a method for fabricating an N-type TFT, comprising the following steps:
  • Step 1 Providing a substrate, depositing a light shielding layer on the substrate, and performing grid pattern processing on the light shielding layer to obtain a plurality of independent light shielding blocks spaced apart from each other;
  • Step 2 sequentially depositing a buffer layer and an amorphous silicon layer on the plurality of independent light blocking blocks and the substrate, and crystallizing the amorphous silicon layer into a polysilicon layer;
  • the polycrystalline silicon layer has a smallest crystal grain corresponding to the first region of the plurality of independent light blocking blocks, and the crystal grain corresponding to the second region spaced between each adjacent two independent light blocking blocks is the largest, and the remaining The crystallites of the third region are moderate;
  • Step 3 depositing a gate insulating layer on the polysilicon layer
  • Step 4 depositing a conductive film on the gate insulating layer and performing patterning treatment to obtain a gate conductive layer;
  • the gate conductive layer is located directly above the plurality of mutually spaced independent light blocking blocks, and a third region and a portion of the first region of the polysilicon layer are exposed on both sides thereof;
  • Step 5 performing the N-type ion doping on the polysilicon layer with the gate conductive layer as a shielding layer, and the resistivity of the third region of the polysilicon layer after being doped by the N-type ions is smaller than the polysilicon layer A portion of the first region is doped with an N-type ion, and a portion of the first region of the polysilicon layer is doped with an N-type ion and is equivalent to a lightly doped drain region.
  • the manufacturing method of the N-type TFT further includes:
  • Step 6 depositing an interlayer insulating layer on the gate conductive layer and the gate insulating layer, and patterning the interlayer insulating layer and the gate insulating layer to form a portion exposing the gate conductive layer a first contact hole of the surface, and a second contact hole and a third contact hole respectively exposing a part of the surface of the third region of the polysilicon layer doped by the N-type ions on both sides of the gate conductive layer;
  • Step 7 Depositing and patterning a metal layer on the interlayer insulating layer to form a gate electrode contacting the gate conductive layer via a first contact hole, respectively contacting the N-type via the second contact hole and the third contact hole The source and the drain of the third region of the polysilicon layer after ion doping.
  • the substrate is a glass substrate or a plastic substrate.
  • the amorphous silicon layer is crystallized and converted into a polysilicon layer by dehydrogenation treatment of the amorphous silicon layer by an excimer laser annealing process.
  • the number of the plurality of independent light blocking blocks spaced apart from each other is three or more.
  • the material of the light shielding layer in the step 1 is metal.
  • the buffer layer, the gate insulating layer, and the material of the interlayer insulating layer are silicon oxide, silicon nitride, or a combination of the two; the gate conductive layer, the gate, the source, and the drain are made of a material A stack combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the fabrication method of the N-type TFT is suitable for fabricating an AMLCD, an AMOLED, and a flexible display device.
  • the invention also provides a method for fabricating an N-type TFT, comprising the following steps:
  • Step 1 Providing a substrate, depositing a light shielding layer on the substrate, and performing grid pattern processing on the light shielding layer to obtain a plurality of independent light shielding blocks spaced apart from each other;
  • Step 2 sequentially depositing a buffer layer and an amorphous silicon layer on the plurality of independent light blocking blocks and the substrate, and crystallizing the amorphous silicon layer into a polysilicon layer;
  • the polysilicon layer has the smallest crystal grain corresponding to the first region of the plurality of independent light blocking blocks, The crystal grain in the second region which is spaced between each adjacent two independent light blocking blocks is the largest, and the crystal grains in the remaining third region are moderate;
  • Step 3 depositing a gate insulating layer on the polysilicon layer
  • Step 4 depositing a conductive film on the gate insulating layer and performing patterning treatment to obtain a gate conductive layer;
  • the gate conductive layer is located directly above the plurality of mutually spaced independent light blocking blocks, and a third region and a portion of the first region of the polysilicon layer are exposed on both sides thereof;
  • Step 5 performing the N-type ion doping on the polysilicon layer with the gate conductive layer as a shielding layer, and the resistivity of the third region of the polysilicon layer after being doped by the N-type ions is smaller than the polysilicon layer a portion of the first region is doped with an N-type ion, and a portion of the first region of the polysilicon layer is equivalent to a lightly doped drain region after being doped with an N-type ion;
  • Step 6 depositing an interlayer insulating layer on the gate conductive layer and the gate insulating layer, and patterning the interlayer insulating layer and the gate insulating layer to form a portion exposing the gate conductive layer a first contact hole of the surface, and a second contact hole and a third contact hole respectively exposing a part of the surface of the third region of the polysilicon layer doped by the N-type ions on both sides of the gate conductive layer;
  • Step 7 Depositing and patterning a metal layer on the interlayer insulating layer to form a gate electrode contacting the gate conductive layer via a first contact hole, respectively contacting the N-type via the second contact hole and the third contact hole a source and a drain of the third region of the polysilicon layer after ion doping;
  • the substrate is a glass substrate or a plastic substrate
  • step 2 the amorphous silicon layer is crystallized and converted into a polysilicon layer by dehydrogenation treatment of the amorphous silicon layer by an excimer laser annealing process.
  • the method for fabricating an N-type TFT provided by the present invention controls the formation of crystallographic differences in different regions of the polysilicon layer by grid-like patterning of the light-shielding layer, so that crystal grains of different regions of the polysilicon layer are formed.
  • FIG. 1 is a schematic view of a conventional step 1 of a method of fabricating an N-type TFT having an LDD structure
  • FIG. 2 is a schematic diagram of a conventional step 2 of a method of fabricating an N-type TFT having an LDD structure
  • FIG. 3 is a top plan view of the polysilicon layer of FIG. 2;
  • FIG. 4 is a schematic diagram of a conventional step 3 of a method of fabricating an N-type TFT having an LDD structure
  • FIG. 5 is a schematic diagram of a conventional step 4 of a method of fabricating an N-type TFT having an LDD structure
  • FIG. 6 is a schematic diagram of a conventional step 5 of a method of fabricating an N-type TFT having an LDD structure
  • Figure 7 is a top plan view of Figure 6;
  • FIG. 8 is a schematic diagram showing relationship between polysilicon resistivity and doping concentration of different grain sizes
  • FIG. 9 is a flow chart showing a method of fabricating an N-type TFT according to the present invention.
  • step 1 is a schematic diagram of step 1 of a method of fabricating an N-type TFT of the present invention
  • step 2 is a schematic diagram of step 2 of a method for fabricating an N-type TFT of the present invention
  • Figure 12 is a top plan view of the polysilicon layer of Figure 11;
  • FIG. 13 is a schematic diagram of step 3 of the method for fabricating an N-type TFT of the present invention.
  • step 4 is a schematic diagram of step 4 of a method of fabricating an N-type TFT of the present invention.
  • Figure 15 is a top plan view of Figure 14;
  • Figure 16 is a schematic view showing the step 5 of the method for fabricating the N-type TFT of the present invention.
  • 17 is a schematic view showing the step 6 of the method for fabricating the N-type TFT of the present invention.
  • Figure 18 is a schematic view showing the seventh step of the method of fabricating the N-type TFT of the present invention.
  • the present invention provides a method for fabricating an N-type TFT, including the following steps:
  • Step 1 as shown in FIG. 10, a substrate 10 is provided, a light shielding layer is deposited on the substrate 10, and the light shielding layer is patterned in a grid pattern to obtain a plurality of independent light shielding blocks 21 spaced apart from each other.
  • the substrate 10 is a glass substrate or a plastic substrate.
  • the material of the light shielding layer is metal.
  • the number of the plurality of mutually spaced independent light blocking blocks 21 is three or more. As shown in FIG. 10, the three spaced apart independent light blocking blocks 21 form two spaces.
  • Step 2 As shown in FIG. 11, a buffer layer 30 and an amorphous silicon layer are sequentially deposited on the plurality of independent light blocking blocks 21 and the substrate 10, and the amorphous silicon layer is subjected to dehydrogenation treatment using excimer laser annealing. The process crystallization of the amorphous silicon layer into a polysilicon layer 40.
  • the polycrystalline silicon layer 40 Due to the existence of the plurality of mutually spaced independent light blocking blocks 21, in the process of crystallization and conversion into the polysilicon layer 40, the temperature of different regions is different, and different regions of the polysilicon layer 40 form crystallization differences. Thereby, the crystal grain sizes of different regions of the polysilicon layer 40 are different.
  • the polycrystalline silicon layer 40 has the smallest crystal grain corresponding to the first region 41 of the plurality of independent light blocking blocks 21, and corresponds to the second region 42 spaced between each adjacent two independent light blocking blocks 21. The crystal grains are the largest, and the remaining third region 43 has a moderate crystal grain size.
  • the material of the buffer layer 30 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of the two.
  • Step 3 As shown in FIG. 13, a gate insulating layer 50 is deposited on the polysilicon layer 40.
  • the material of the gate insulating layer 50 is SiOx, SiNx, or a combination of the two.
  • Step 4 as shown in FIG. 14 and FIG. 15, a conductive film is deposited on the gate insulating layer 50 and patterned to obtain a gate conductive layer 60.
  • the gate conductive layer 60 is located directly above the plurality of mutually spaced independent light blocking blocks 21, and the third region 43 and the partial first region 41 of the polysilicon layer 40 are exposed on both sides thereof.
  • the material of the gate conductive layer 60 is a stack combination of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu).
  • Step 5 As shown in FIG. 16, the polysilicon layer 40 is doped with N-type ions by using the gate conductive layer 60 as a shielding layer.
  • the third region 43 of the polysilicon layer 40 that is not blocked by the gate conductive layer 60 is doped with the same concentration of N-type ions as the portion of the first region 41, but due to the polysilicon in the third region 43
  • the crystal grain is larger than the crystal grain of the polysilicon in the first region 41, and the polysilicon layer 40 is the same as the polysilicon layer having a smaller resistivity at the same doping concentration as shown in FIG.
  • the resistivity of the three regions 43 after being doped by the N-type ions is smaller than the resistivity of the portion of the first region 41 of the polysilicon layer 40 after being doped by the N-type ions, so that a portion of the first region 41 of the polysilicon layer 40 is N.
  • the third region 43 of the polysilicon layer 40 is equivalent to the N-type heavily doped region after the N-type ion doping, and the second region not doped with the N-type ion. 42 and the remaining portion of the first region 41 constitute a channel region.
  • Step 7 as shown in FIG. 18, depositing and patterning a metal layer on the interlayer insulating layer 70, forming a gate electrode 81 contacting the gate conductive layer 60 via the first contact hole 71, respectively via a second contact
  • the hole 72 and the third contact hole 73 contact the source 82 and the drain 83 of the third region 43 of the polysilicon layer 40 doped by the N-type ions.
  • the crystallization difference is formed in different regions of the polysilicon layer by performing a grid-like patterning process on the light-shielding layer, so that the crystal grain sizes of different regions of the polysilicon layer are different, and further Only by one ion doping process, different regions of the polysilicon layer have different resistivities due to different grain sizes under the same doping concentration, achieving the same effect as the LDD structure, enabling the TFT to have lower leakage current and High reliability; at the same time, since only one ion implantation is required, the process time and manufacturing cost can be saved, the damage of the polysilicon layer can be reduced, and the activation time can be shortened, which is beneficial to the manufacture of the flexible display.

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Abstract

提供一种N型薄膜晶体管（TFT）的制作方法，通过对遮光层进行栅格状图案化处理来控制多晶硅层的不同区域形成结晶差异，使得多晶硅层不同区域的结晶晶粒大小不同，进而仅通过一次离子掺杂制程使得多晶硅不同区域在掺杂浓度相同的条件下由于晶粒大小不同而产生的电阻率不同，实现等同于轻掺杂漏区结构的效果，使TFT具有较低的漏电流和较高的可靠性；能够节省制成时间和制造成本，减小多晶硅层的损伤，缩短活化时间，有利于柔性显示器的制作。

Description

N型TFT的制作方法 技术领域
本发明涉及半导体制作工艺，尤其涉及一种N型TFT的制作方法。
背景技术
平板显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平板显示装置主要包括液晶显示装置(Liquid Crystal Display，LCD)及有机电致发光显示装置(Organic Light Emitting Display，OLED)等。
薄膜晶体管(Thin Film Transistor，TFT)是平板显示装置的重要组成部分，可形成在玻璃基板或塑料基板上，通常作为开关器件和驱动器件用在诸如LCD、OLED等显示装置上。
按照TFT形成电流时载流子的不同，TFT可分为以N型TFT(以电子为载流子)、与P型TFT(以空穴为载流子)两大类。
其中，N型TFT的漏电流较大，为了提高N型TFT的可靠性，现有技术通常在N型TFT内半导体层的沟道两侧设置轻掺杂漏区(Lightly Doped Drain，LDD)，通过LDD来降低漏电流。
传统的制作具有LDD结构的N型TFT的方法包括以下步骤：
步骤1、如图1所示，提供一基板100，在所述基板100上沉积一遮光层(Light shielding Layer)，对所述遮光层进行图案化处理，得到一整体式遮光条210。
步骤2、如图2所示，在所述整体式遮光条210及基板100上依次沉积缓冲层200和一非晶硅层，对所述非晶硅层进行脱氢处理，采用准分子激光退火制程将所述非晶硅层转化为多晶硅层300。
如图3所示，经该步骤2获得的多晶硅层300内的晶粒大小基本均匀一致。
步骤3、如图4所示，在多晶硅层300上涂布一光阻层400’，采用一道黄光制程对所述光阻层400’进行曝光、显影，暴露出所述多晶硅层300的两端区域，以所述光阻层400’为遮挡层对多晶硅层300的两端区域进行一次N型重掺杂，然后去除所述光阻层400’；
步骤4、如图5所示，在所述多晶硅层300上沉积栅极绝缘层400；
步骤5、如图6、图7所示，在所述栅极绝缘层400上沉积一层栅极导 电薄膜并进行图案化处理，得到栅极导电层500，该栅极导电层500的长度要小于上述步骤3中光阻层400’的长度，以暴露出上述步骤3中未被掺杂的部分多晶硅层300，再以该栅极导电层500为遮挡层进行一次N型轻掺杂，得到N型重掺杂区310、N型轻掺杂区320、及沟道区330。
所述N型轻掺杂区320即构成LDD。
步骤6、继续后续通用的半导体制程，如沉积层间绝缘层并蚀刻层间绝缘层与栅极绝缘层400形成接触孔，沉积并蚀刻金属层形成源极、漏极、栅极等，最终制得具有LDD结构的N型TFT。
上述传统的制作具有LDD结构的N型TFT的方法，分别需要一道光罩来定义重掺杂区与轻掺杂区，而且需要进行两次离子掺杂，制程步骤较多，成本较高，且由于重掺杂区与轻掺杂区在黄光对位方面常常出现偏差，会影响到TFT的均匀性。
现有的制作具有LDD结构的N型TFT的另一种方法是利用一道半色调光罩对栅极先后进行两次蚀刻，以第一次蚀刻后的栅极为遮挡层来进行N型重掺杂，以第二次蚀刻后的栅极为遮挡层来进行N型轻掺杂，从而形成LDD。这种方法虽然可以节省一道光罩，但两次蚀刻的均匀性不易控制。
图8所示为不同晶粒大小的多晶硅电阻率与掺杂浓度的关系，由此图可看出在相同的掺杂浓度下，不同晶粒大小的多晶硅具有不同的电阻率。具体地，在相同的掺杂浓度下，多晶硅晶粒越小电阻率越大。因此，在相同的掺杂浓度下，可以通过控制多晶硅晶粒的大小来实现等同于LDD结构的效果。
发明内容
本发明的目的在于提供一种N型TFT的制作方法，利用相同掺杂浓度下不同晶粒大小的多晶硅具有不同的电阻率的特性，只需一次离子掺杂就能够实现等同于LDD结构的效果，节省制程时间与制造成本。
为实现上述目的，本发明提供一种N型TFT的制作方法，包括以下步骤：
步骤1、提供一基板，在所述基板上沉积一遮光层，对所述遮光层进行栅格状图案化处理，得到多个相互间隔的独立遮光块；
步骤2、在所述多个独立遮光块及基板上依次沉积缓冲层和非晶硅层，并使所述非晶硅层结晶、转化为多晶硅层；
所述多晶硅层对应于多个独立遮光块的第一区域的结晶晶粒最小，对应于每相邻两个独立遮光块之间间隔的第二区域的结晶晶粒最大，剩余的 第三区域的结晶晶粒适中；
步骤3、在所述多晶硅层上沉积栅极绝缘层；
步骤4、在所述栅极绝缘层上沉积一层导电薄膜并进行图案化处理，得到栅极导电层；
所述栅极导电层位于所述多个相互间隔的独立遮光块的正上方，其两侧均暴露出所述多晶硅层的第三区域与部分第一区域；
步骤5、以所述栅极导电层为遮挡层，对所述多晶硅层进行一次N型离子掺杂，所述多晶硅层的第三区域经N型离子掺杂后的电阻率小于所述多晶硅层的部分第一区域经N型离子掺杂后的电阻率，所述多晶硅层的部分第一区域经N型离子掺杂后等同于轻掺杂漏区。
所述N型TFT的制作方法，还包括：
步骤6、在所述栅极导电层和栅极绝缘层上沉积一层间绝缘层，对所述层间绝缘层与栅极绝缘层进行图案化处理，形成暴露出所述栅极导电层部分表面的第一接触孔、及分别于所述栅极导电层两侧暴露出经N型离子掺杂后的多晶硅层第三区域的部分表面的第二接触孔、与第三接触孔；
步骤7、在所述层间绝缘层上沉积并图案化金属层，形成经由第一接触孔接触所述栅极导电层的栅极、分别经由第二接触孔、第三接触孔接触经N型离子掺杂后的多晶硅层第三区域的源极与漏极。
所述基板为玻璃基板或塑料基板。
所述步骤2通过对所述非晶硅层进行脱氢处理，采用准分子激光退火制程使所述非晶硅层结晶、转化为多晶硅层。
所述多个相互间隔的独立遮光块的数量为3个或3个以上。
所述步骤1中的遮光层的材料为金属。
所述缓冲层、栅极绝缘层、与层间绝缘层的材料为氧化硅、氮化硅、或二者的组合；所述栅极导电层、栅极、源极、与漏极的材料为钼、钛、铝、铜中的一种或几种的堆栈组合。
所述N型TFT的制作方法适用于制作AMLCD、AMOLED、及柔性显示器件。
本发明还提供一种N型TFT的制作方法，包括以下步骤：
步骤1、提供一基板，在所述基板上沉积一遮光层，对所述遮光层进行栅格状图案化处理，得到多个相互间隔的独立遮光块；
步骤2、在所述多个独立遮光块及基板上依次沉积缓冲层和非晶硅层，并使所述非晶硅层结晶、转化为多晶硅层；
所述多晶硅层对应于多个独立遮光块的第一区域的结晶晶粒最小，对 应于每相邻两个独立遮光块之间间隔的第二区域的结晶晶粒最大，剩余的第三区域的结晶晶粒适中；
步骤3、在所述多晶硅层上沉积栅极绝缘层；
步骤4、在所述栅极绝缘层上沉积一层导电薄膜并进行图案化处理，得到栅极导电层；
所述栅极导电层位于所述多个相互间隔的独立遮光块的正上方，其两侧均暴露出所述多晶硅层的第三区域与部分第一区域；
步骤5、以所述栅极导电层为遮挡层，对所述多晶硅层进行一次N型离子掺杂，所述多晶硅层的第三区域经N型离子掺杂后的电阻率小于所述多晶硅层的部分第一区域经N型离子掺杂后的电阻率，所述多晶硅层的部分第一区域经N型离子掺杂后等同于轻掺杂漏区；
还包括：
步骤6、在所述栅极导电层和栅极绝缘层上沉积一层间绝缘层，对所述层间绝缘层与栅极绝缘层进行图案化处理，形成暴露出所述栅极导电层部分表面的第一接触孔、及分别于所述栅极导电层两侧暴露出经N型离子掺杂后的多晶硅层第三区域的部分表面的第二接触孔、与第三接触孔；
步骤7、在所述层间绝缘层上沉积并图案化金属层，形成经由第一接触孔接触所述栅极导电层的栅极、分别经由第二接触孔、第三接触孔接触经N型离子掺杂后的多晶硅层第三区域的源极与漏极；
其中，所述基板为玻璃基板或塑料基板；
其中，所述步骤2通过对所述非晶硅层进行脱氢处理，采用准分子激光退火制程使所述非晶硅层结晶、转化为多晶硅层。
本发明的有益效果：本发明提供的一种N型TFT的制作方法，通过对遮光层进行栅格状图案化处理来控制多晶硅层的不同区域形成结晶差异，使得多晶硅层不同区域的结晶晶粒大小不同，进而仅通过一次离子掺杂制程使得多晶硅层不同区域在掺杂浓度相同的条件下由于晶粒大小不同而产生电阻率不同，实现等同于LDD结构的效果，能够使TFT具有较低的漏电流和较高的可靠性；同时由于只需要一次离子注入，能够节省制程时间和制造成本，减少多晶硅层的损伤，缩短活化时间，有利于柔性显示器的制作。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发 明加以限制。
附图中，
图1为传统的制作具有LDD结构的N型TFT的方法的步骤1的示意图；
图2为传统的制作具有LDD结构的N型TFT的方法的步骤2的示意图；
图3为图2中多晶硅层的俯视示意图；
图4为传统的制作具有LDD结构的N型TFT的方法的步骤3的示意图；
图5为传统的制作具有LDD结构的N型TFT的方法的步骤4的示意图；
图6为传统的制作具有LDD结构的N型TFT的方法的步骤5的示意图；
图7为图6的俯视示意图；
图8为不同晶粒大小的多晶硅电阻率与掺杂浓度的关系示意图；
图9为本发明N型TFT的制作方法的流程图；
图10为本发明的N型TFT的制作方法的步骤1的示意图；
图11为本发明的N型TFT的制作方法的步骤2的示意图；
图12为图11中多晶硅层的俯视示意图；
图13为本发明的N型TFT的制作方法的步骤3的示意图；
图14为本发明的N型TFT的制作方法的步骤4的示意图；
图15为图14的俯视示意图；
图16为本发明的N型TFT的制作方法的步骤5的示意图；
图17为本发明的N型TFT的制作方法的步骤6的示意图；
图18为本发明的N型TFT的制作方法的步骤7的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图9，本发明提供一种N型TFT的制作方法，包括以下步骤：
步骤1、如图10所示，提供一基板10，在所述基板10上沉积一遮光层，对所述遮光层进行栅格状图案化处理，得到多个相互间隔的独立遮光块21。
具体地，所述基板10为玻璃基板或塑料基板。
所述遮光层的材料为金属。优选的，所述多个相互间隔的独立遮光块21的数量为3个或3个以上，如图10所示，该3个相互间隔的独立遮光块21之间形成2处间隔。
步骤2、如图11所示，在所述多个独立遮光块21及基板10上依次沉积缓冲层30和非晶硅层，对所述非晶硅层进行脱氢处理，采用准分子激光退火制程使所述非晶硅层结晶、转化为多晶硅层40。
由于所述多个相互间隔的独立遮光块21的存在，所述非晶硅层在结晶、转化为多晶硅层40的过程中，不同区域的温度存在差异，多晶硅层40的不同区域形成结晶差异，从而使得多晶硅层40不同区域的结晶晶粒大小不同。结合图11与图12，所述多晶硅层40对应于多个独立遮光块21的第一区域41的结晶晶粒最小，对应于每相邻两个独立遮光块21之间间隔的第二区域42的结晶晶粒最大，剩余的第三区域43的结晶晶粒适中。
具体地，所述缓冲层30的材料为氧化硅(SiOx)、氮化硅(SiNx)、或二者的组合。
步骤3、如图13所示，在所述多晶硅层40上沉积栅极绝缘层50。
具体地，所述栅极绝缘层50的材料为SiOx、SiNx、或二者的组合。
步骤4、如图14、图15所示，在所述栅极绝缘层50上沉积一层导电薄膜并进行图案化处理，得到栅极导电层60。
所述栅极导电层60位于所述多个相互间隔的独立遮光块21的正上方，其两侧均暴露出所述多晶硅层40的第三区域43与部分第一区域41。
具体地，所述栅极导电层60的材料为钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或几种的堆栈组合。
步骤5、如图16所示，以所述栅极导电层60为遮挡层，对所述多晶硅层40进行一次N型离子掺杂。
该步骤5中，未被所述栅极导电层60遮挡的多晶硅层40的第三区域43与部分第一区域41进行了相同浓度的N型离子掺杂，但由于第三区域43内多晶硅的结晶晶粒大于第一区域41内多晶硅的结晶晶粒，根据图8所示的在相同的掺杂浓度下，多晶硅晶粒越小电阻率越大的这一特性，所述多晶硅层40的第三区域43经N型离子掺杂后的电阻率小于所述多晶硅层40的部分第一区域41经N型离子掺杂后的电阻率，从而所述多晶硅层40的部分第一区域41经N型离子掺杂后等同于轻掺杂漏区，所述多晶硅层40的第三区域43经N型离子掺杂后等同于N型重掺杂区，未经N型离子掺杂的第二区域42与其余部分第一区域41构成沟道区。
步骤6、如图17所示，在所述栅极导电层60和栅极绝缘层50上沉积 一层间绝缘层70，对所述层间绝缘层70与栅极绝缘层50进行图案化处理，形成暴露出所述栅极导电层60部分表面的第一接触孔71、及分别于所述栅极导电层60两侧暴露出经N型离子掺杂后的多晶硅层40第三区域43的部分表面的第二接触孔72、与第三接触孔73。
具体地，所述层间绝缘层70的材料为SiOx、SiNx、或二者的组合。
步骤7、如图18所示，在所述层间绝缘层70上沉积并图案化金属层，形成经由第一接触孔71接触所述栅极导电层60的栅极81、分别经由第二接触孔72、第三接触孔73接触经N型离子掺杂后的多晶硅层40第三区域43的源极82与漏极83。
具体地，所述栅极81、源极82、与漏极83的材料为Mo、Ti、Al、Cu中的一种或几种的堆栈组合。
由上述方法制作的N型TFT具有等同于LDD效果的结构，能够使TFT具有较低的漏电流和较高的可靠性；同时该方法由于只需要一次离子注入，能够节省制程时间和制造成本，减少多晶硅层的损伤，缩短活化时间。
本发明的N型TFT的制作方法适用于制作AMLCD、AMOLED、及柔性显示器件。
综上所述，本发明的N型TFT的制作方法，通过对遮光层进行栅格状图案化处理来控制多晶硅层的不同区域形成结晶差异，使得多晶硅层不同区域的结晶晶粒大小不同，进而仅通过一次离子掺杂制程使得多晶硅层不同区域在掺杂浓度相同的条件下由于晶粒大小不同而产生电阻率不同，实现等同于LDD结构的效果，能够使TFT具有较低的漏电流和较高的可靠性；同时由于只需要一次离子注入，能够节省制程时间和制造成本，减少多晶硅层的损伤，缩短活化时间，有利于柔性显示器的制作。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (13)

  1. 一种N型TFT的制作方法，包括以下步骤：
    步骤1、提供一基板，在所述基板上沉积一遮光层，对所述遮光层进行栅格状图案化处理，得到多个相互间隔的独立遮光块；
    步骤2、在所述多个独立遮光块及基板上依次沉积缓冲层和非晶硅层，并使所述非晶硅层结晶、转化为多晶硅层；
    所述多晶硅层对应于多个独立遮光块的第一区域的结晶晶粒最小，对应于每相邻两个独立遮光块之间间隔的第二区域的结晶晶粒最大，剩余的第三区域的结晶晶粒适中；
    步骤3、在所述多晶硅层上沉积栅极绝缘层；
    步骤4、在所述栅极绝缘层上沉积一层导电薄膜并进行图案化处理，得到栅极导电层；
    所述栅极导电层位于所述多个相互间隔的独立遮光块的正上方，其两侧均暴露出所述多晶硅层的第三区域与部分第一区域；
    步骤5、以所述栅极导电层为遮挡层，对所述多晶硅层进行一次N型离子掺杂，所述多晶硅层的第三区域经N型离子掺杂后的电阻率小于所述多晶硅层的部分第一区域经N型离子掺杂后的电阻率，所述多晶硅层的部分第一区域经N型离子掺杂后等同于轻掺杂漏区。
  2. 如权利要求1所述的N型TFT的制作方法，还包括：
    步骤6、在所述栅极导电层和栅极绝缘层上沉积一层间绝缘层，对所述层间绝缘层与栅极绝缘层进行图案化处理，形成暴露出所述栅极导电层部分表面的第一接触孔、及分别于所述栅极导电层两侧暴露出经N型离子掺杂后的多晶硅层第三区域的部分表面的第二接触孔、与第三接触孔；
    步骤7、在所述层间绝缘层上沉积并图案化金属层，形成经由第一接触孔接触所述栅极导电层的栅极、分别经由第二接触孔、第三接触孔接触经N型离子掺杂后的多晶硅层第三区域的源极与漏极。
  3. 如权利要求1所述的N型TFT的制作方法，其中，所述基板为玻璃基板或塑料基板。
  4. 如权利要求1所述的N型TFT的制作方法，其中，所述步骤2通过对所述非晶硅层进行脱氢处理，采用准分子激光退火制程使所述非晶硅层结晶、转化为多晶硅层。
  5. 如权利要求1所述的N型TFT的制作方法，其中，所述多个相互 间隔的独立遮光块的数量为3个或3个以上。
  6. 如权利要求1所述的N型TFT的制作方法，其中，所述步骤1中的遮光层的材料为金属。
  7. 如权利要求1所述的N型TFT的制作方法，其中，所述缓冲层、栅极绝缘层、与层间绝缘层的材料为氧化硅、氮化硅、或二者的组合；所述栅极导电层、栅极、源极、与漏极的材料为钼、钛、铝、铜中的一种或几种的堆栈组合。
  8. 如权利要求1所述的N型TFT的制作方法，其中，适用于制作AMLCD、AMOLED、及柔性显示器件。
  9. 一种N型TFT的制作方法，包括以下步骤：
    步骤1、提供一基板，在所述基板上沉积一遮光层，对所述遮光层进行栅格状图案化处理，得到多个相互间隔的独立遮光块；
    步骤2、在所述多个独立遮光块及基板上依次沉积缓冲层和非晶硅层，并使所述非晶硅层结晶、转化为多晶硅层；
    所述多晶硅层对应于多个独立遮光块的第一区域的结晶晶粒最小，对应于每相邻两个独立遮光块之间间隔的第二区域的结晶晶粒最大，剩余的第三区域的结晶晶粒适中；
    步骤3、在所述多晶硅层上沉积栅极绝缘层；
    步骤4、在所述栅极绝缘层上沉积一层导电薄膜并进行图案化处理，得到栅极导电层；
    所述栅极导电层位于所述多个相互间隔的独立遮光块的正上方，其两侧均暴露出所述多晶硅层的第三区域与部分第一区域；
    步骤5、以所述栅极导电层为遮挡层，对所述多晶硅层进行一次N型离子掺杂，所述多晶硅层的第三区域经N型离子掺杂后的电阻率小于所述多晶硅层的部分第一区域经N型离子掺杂后的电阻率，所述多晶硅层的部分第一区域经N型离子掺杂后等同于轻掺杂漏区；
    还包括：
    步骤6、在所述栅极导电层和栅极绝缘层上沉积一层间绝缘层，对所述层间绝缘层与栅极绝缘层进行图案化处理，形成暴露出所述栅极导电层部分表面的第一接触孔、及分别于所述栅极导电层两侧暴露出经N型离子掺杂后的多晶硅层第三区域的部分表面的第二接触孔、与第三接触孔；
    步骤7、在所述层间绝缘层上沉积并图案化金属层，形成经由第一接触孔接触所述栅极导电层的栅极、分别经由第二接触孔、第三接触孔接触经N型离子掺杂后的多晶硅层第三区域的源极与漏极；
    其中，所述基板为玻璃基板或塑料基板；
    其中，所述步骤2通过对所述非晶硅层进行脱氢处理，采用准分子激光退火制程使所述非晶硅层结晶、转化为多晶硅层。
  10. 如权利要求9所述的N型TFT的制作方法，其中，所述多个相互间隔的独立遮光块的数量为3个或3个以上。
  11. 如权利要求9所述的N型TFT的制作方法，其中，所述步骤1中的遮光层的材料为金属。
  12. 如权利要求9所述的N型TFT的制作方法，其中，所述缓冲层、栅极绝缘层、与层间绝缘层的材料为氧化硅、氮化硅、或二者的组合；所述栅极导电层、栅极、源极、与漏极的材料为钼、钛、铝、铜中的一种或几种的堆栈组合。
  13. 如权利要求9所述的N型TFT的制作方法，其中，适用于制作AMLCD、AMOLED、及柔性显示器件。
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