Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
  • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
  • H01L21/2251—Diffusion into or out of group IV semiconductors
  • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
  • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
  • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
  • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
  • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
  • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
  • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
  • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
  • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
  • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
  • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L29/41725—Source or drain electrodes for field effect devices
  • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
  • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
  • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
  • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
  • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
  • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants

Definitions

• Embodiments described herein generally relate to doping of three dimensional (3D) structures formed on a substrate. More specifically, embodiments described herein relate to conformal doping in 3D silicon structures using conformal dopant deposition processes.
• Three dimensional (3D) transistors such as fin field-effect transistors (FinFETs) are promising candidates to extend complimentary metal-oxide semiconductor (CMOS) scaling.
• CMOS complementary metal-oxide semiconductor
• Such FinFET transistors generally provide for improved electrostatic control (i.e. short channel effects) and lower sensitivity to random dopant fluctuations.
• electrostatic control i.e. short channel effects
• implementation challenges and process complexity issues exist in the integration of FinFETs at advanced technology dimensions.
• one challenge of FinFET integration is dopant concentration in 3D silicon containing device structures.
• dopant concentration in 3D silicon containing device structures As a result of the lack of a body or back gate bias in fully depleted (i.e. no mobile carriers) FinFET device structures, complicated workfunction engineering is often necessary to achieve workable threshold voltages for undoped FinFETs.
• dopant concentration and dopant distribution within the FinFET structures present additional challenges in 3D device structure manufacturing processes.
• a substrate processing method includes depositing a conformal boron-carbon-nitrogen containing film on a three dimensional structure formed on a substrate.
• the three dimensional structure may be a FinFET device and the three dimensional structure and the film may be annealed to diffuse the boron into the three dimensional structure to dope the FinFET device.
• a substrate processing method includes forming silicon containing three dimensional structures of a substrate and exposing the three dimensional structures to one or more dopant containing precursors and one or more carrier gases.
• a conformal film may be deposited on the three dimensional structures and the conformal film may include a dopant and at least one non-dopant material selected from the group consisting of carbon and nitrogen.
• the three dimensional structures and the conformal film may be annealed to diffuse the dopant from the conformal film into the three dimensional structures.
• a substrate processing method includes positioning a substrate having three dimensional structures formed thereon in a processing region of a film deposition chamber and exposing the three dimensional structures to one or more dopant containing precursors and one or more carrier gases.
• a conformal film may be deposited on the three dimensional structures and the conformal film may include a dopant and at least one non-dopant material selected from the group consisting of carbon and nitrogen.
• the substrate may be transferred to a thermal processing chamber and the three dimensional structures and the conformal film may be annealed to diffuse the dopant from the conformal film into the three dimensional structures.
• Figure 1 illustrates a schematic, cross-sectional view of a substrate having three dimensional (3D) structures formed thereon according to one embodiment described herein.
• Figure 2 illustrates operations of a method for performing a conformal film deposition and doping process according to embodiments described herein.
• Embodiments described herein generally relate to doping of three dimensional (3D) structures on a substrate.
• a conformal dopant containing film may be deposited over the 3D structures.
• Suitable dopants that may be incorporated in the film may include boron, phosphorous, and other suitable dopants.
• the film may be subsequently annealed to diffuse the dopants into the 3D structures.
• Figure 1 illustrates a schematic, cross-sectional view of a substrate 100 having three dimensional (3D) structures 104 formed thereon according to one embodiment described herein.
• the substrate 100 includes the 3D structures 104 which extend from a base material layer 102.
• the base material layer 102 may be silicon containing material, such as pure silicon or doped silicon.
• the base material layer 102 may be an insulator material, such as oxides, nitrides, or the like.
• the substrate 100 may be a silicon-on-insulator substrate.
• the embodiments described herein are generally made with reference to a 300 mm circular substrate, however, it is contemplated that various other substrate dimensions may benefit from the embodiments described herein.
• the 3D structures 104 may be formed on the base material layer 102 by various patterning and etching processes. Generally, the 3D structures are formed with dimensions suitable for implementation as fin field-effect transistors (FinFETs) in complimentary metal-oxide semiconductor (CMOS) transistors, however, other transistor types may also benefit from the embodiments described herein. It is contemplated that the 3D structures may be suitable for and may have dimensions commensurate for utilization in current technology nodes and advanced technology nodes, such as a sub-10 nm node.
• FinFETs fin field-effect transistors
• CMOS complimentary metal-oxide semiconductor
• the 3D structures 104 may be the same material as the base material layer 102 or a material different from the base material layer 102. In one embodiment, the 3D structures 104 may be formed from silicon. In other embodiments, the 3D structures may include multiple materials, such as silicon and one or more dopants.
• the 3D structures 104 extend from the base material layer 102 and are spaced apart by trenches 1 16.
• the 3D structures include a top surface 108 and sidewalls 106 which extend between the top surface 108 and a bottom surface 1 10 of the trenches 1 16.
• a conformal film 1 12 is deposited over the 3D structures 104 and the base material layer 102.
• the conformal film 1 12 generally maintains a constant or substantially constant thickness regardless of the region where the conformal film 1 12 is deposited.
• the conformal film 1 12 may be deposited with greater than about 70% conformity, greater than about 80% conformity, greater than about 90% conformity, greater than about 95% conformity or greater than about 98% conformity.
• a thickness 1 14 of the conformal film 1 12 may be maintained adjacent the top surface 108, the sidewalls 106, and the bottom surface 1 10 such that the thickness is predominantly equal across about 70% of the conformal film 1 12.
• the thickness 1 14 may be between about 10 nm and about 100 nm, depending on the 3D structure dimensions and desired doping characteristics.
• the conformal film 1 12 may be deposited by various deposition techniques, such as chemical vapor deposition (CVD) or plasma based deposition techniques.
• the conformal film 1 12 may be deposited by a thermal CVD technique.
• a thermal precursor vaporization apparatus may be coupled to a suitably configured film deposition chamber to prepare various precursors prior to deposition. Temperatures utilized by the thermal precursor vaporization apparatus may be between about 70°C and about 150°C, depending on the precursor utilized.
• the conformal film 1 12 may be deposited by a plasma enhanced chemical vapor deposition (PECVD) deposition technique.
• PECVD plasma enhanced chemical vapor deposition
• the plasma may be generated by a remote plasma source or may be generated inside a processing chamber.
• the conformal film 1 12 may be deposited by a hybrid thermal/plasma deposition technique.
• a suitable apparatus for depositing the conformal film 1 12 is the PRODUCER ® chamber, available from Applied Materials, Inc., Santa Clara, CA. It is contemplated that suitably configured chambers from other manufacturers may also be utilized to perform the conformal film deposition according to the embodiments described herein.
• Figure 2 illustrates operations of a method 200 for performing a conformal film deposition and doping process according to embodiments described herein.
• a conformal dopant containing film may be deposited on 3D structures formed on a substrate. The film may be deposited utilizing suitable processing conditions configured to provide for conformity as described above.
• the dopant containing conformal film may be deposited on a substrate which is positioned in a processing region of a film deposition chamber.
• the dopant containing conformal film may include dopants and non-dopant materials in certain embodiments. Suitable dopants species include boron, phosphorous, arsenic, antimony, aluminum, and gallium, among others. Non-dopant materials include carbon, nitrogen, silicon, and oxygen, among others. Generally, the dopants in the conformal film will be diffused into the 3D structures during subsequent processing operations while the non-dopant materials will not diffuse into the 3D structures.
• a boron-carbon-nitrogen film may be deposited on the 3D structures.
• a boron containing precursor such as dimethylamine borane
• the boron containing precursor may be heated prior to entry into the processing region of the film deposition chamber.
• the non-dopant materials carbon and nitrogen may also be exposed to the 3D features.
• a suitable carbon containing precursor may be a hydrocarbon containing material, such as propene, and a suitable nitrogen containing precursor may be ammonia or the like.
• the flow rates of the precursors may be varied to influence the conformal film compositional profile.
• various carrier gases such as argon, nitrogen, hydrogen, and helium, among others, may be provided to the processing volume of the film deposition chamber along with the precursors.
• One or more carrier gases may be provided to the film deposition chamber at a rate of between about 100 seem to about 20,000 seem.
• a partial pressure of the dopant precursor relative to the carrier gas may be between about 10 Pascal to about 1000 Pascal.
• a temperature of the film deposition chamber may be maintained between about 200°C and about 650°C during the conformal film deposition process.
• a pressure of the film deposition chamber may be maintained between about 100 mTorr and about 100 Torr during the conformal film deposition process. It is believed that precursor flow rates, chamber temperatures, and chamber pressures may be configured to influence the conformity of the dopant containing film to provide a degree of conformity suitable for subsequent doping of the 3D structures.
• the 3D structures may be annealed to diffuse the dopant form the dopant containing conformal film into the 3D structures.
• the substrate may be transferred from the film deposition chamber to an annealing chamber, such as a rapid thermal processing chamber. Rapid thermal processing may utilize various electromagnetic energy sources to anneal the substrate. For example, radiant heating, laser annealing, or combinations thereof may be utilized to drive the dopants from the conformal film into the 3D structures.
• suitable apparatus for performing the annealing process include the VANTAGE ® ASTRATM tool, VANTAGE ® RADIANCE ® PLUS tool, VANTAGE ® VULCANTM tool, all available from Applied Materials, Inc., Santa Clara, CA. It is contemplated that suitably configured annealing apparatus from other manufacturers may also be used to perform the annealing process described herein.
• the annealing process may be performed at a temperature of between about 700°C and about 1 100°C, such as between about 850°C and about 1050°C.
• the annealing process is generally configured to quickly heat the materials disposed on the substrate in a repetitive manner. Temperature cycling may be performed on the millisecond scale to second scale and it is believed that the annealing not only causes the dopant to diffuse from the conformal film in to the 3D structures, but may also volatilize non-dopant materials of the conformal film to prevent diffusion of the non-dopant materials into the 3D structures.
• dopant diffusion into the 3D structures may progress in a controlled manner such that dopant distribution within the 3D structures is predominantly uniform.
• the dopant diffuses into the 3D structures from multiple directions (i.e. sidewalls and top surfaces) and the depth of diffusion may be controlled by the annealing process.
• the boron concentration in the 3D structures (post anneal) may be between about 2.5 x 10 21 atoms/cm 3 and about 3.5 x 10 21 atoms/cm 3 .
• the carbon and nitrogen concentration in the 3D structures may be less than about 5.0 x 10 18 atoms/cm 3 , such as less than about 5.0 x 10 17 atoms/cm 3 .
• the concentration of carbon and nitrogen may be about 0 atoms/cm 3 or another negligible concentration which does not significantly affect device functionality (i.e. threshold voltage) of the 3D structures.
• any remaining portions of the dopant depleted conformal film may be removed from the substrate and the 3D structures.
• Various etching processes such as wet etching or dry plasma etching processes, having chemistries selected to preferentially remove the conformal film may be utilized to remove the conformal film.
• the 3D structures may be doped with desirable dopant species and the 3D structures may be suitable for subsequent device structure fabrication processes.

Landscapes

• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Ceramic Engineering (AREA)
• Chemical & Material Sciences (AREA)
• Chemical Kinetics & Catalysis (AREA)
• Plasma & Fusion (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Chemical Vapour Deposition (AREA)
• Formation Of Insulating Films (AREA)

Priority Applications (3)

Applications Claiming Priority (4)

Publications (1)

Family

ID=58517783

Family Applications (1)

Country Status (5)

Cited By (1)

Families Citing this family (6)

Citations (5)

Family Cites Families (12)

• 2015
  • 2015-12-08 US US14/961,920 patent/US9640400B1/en active Active
• 2016
  • 2016-08-26 CN CN201680050010.3A patent/CN107949918B/zh active Active
  • 2016-08-26 WO PCT/US2016/048950 patent/WO2017065880A1/en active Application Filing
  • 2016-08-26 JP JP2018519368A patent/JP6847104B2/ja active Active
  • 2016-08-26 KR KR1020187008874A patent/KR102608805B1/ko active IP Right Grant

Patent Citations (5)

Also Published As

Similar Documents

Legal Events