CN107949918B - 使用保形掺杂物沉积的3D Si结构中的保形掺杂 - Google Patents

使用保形掺杂物沉积的3D Si结构中的保形掺杂 Download PDF

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CN107949918B
CN107949918B CN201680050010.3A CN201680050010A CN107949918B CN 107949918 B CN107949918 B CN 107949918B CN 201680050010 A CN201680050010 A CN 201680050010A CN 107949918 B CN107949918 B CN 107949918B
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程睿
A·B·玛里克
S·冈迪科塔
P·曼纳
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Abstract

本文中所述的实施方式总体涉及对基板上的三维(3D)结构的掺杂。在一个实施方式中，保形的含掺杂物膜可沉积在3D结构上方。可结合在膜中的合适的掺杂物可以包括硼、磷、和其他合适的掺杂物。随后可使膜退火以将掺杂物扩散至3D结构中。

Description

使用保形掺杂物沉积的3D Si结构中的保形掺杂
背景
技术领域
本文中所述的实施方式总体涉及对基板上形成的三维(3D)结构的掺杂。更具体地，本文中所述的实施方式涉及使用保形掺杂物沉积工艺的3D硅结构中的保形掺杂。
背景技术
三维(3D)晶体管，诸如鳍式场效晶体管(FinFET)，是用于扩大互补金属氧化物半导体(CMOS)规模的有前景的候选。此类FinFET晶体管一般提供改良的静电控制(即，短沟道效应)和较低的对随机掺杂波动的敏感性。然而，实现方式挑战和工艺的复杂性问题存在于在先进技术尺寸的FinFET的集成中。
例如，FinFET集成的一个挑战是3D含硅器件结构中的掺杂物浓度。由于在全耗尽型(即，无移动载流子)FinFET器件结构中缺乏本体或背栅极偏置，为了实现用于未掺杂FinFET的可工作的阈值电压，复杂的功函数工程常常是必须的。除了阈值电压的复杂性之外，在3D器件结构制造工艺中，FinFET结构内的掺杂物浓度和掺杂物分布带来额外挑战。
当前FinFET掺杂工艺利用成角度的离子注入方案或视线沉积方案。在成角度的离子注入方案中，难以控制掺杂物浓度和分布特异性并且在处理顺序中实现此类系统是昂贵的。另外，用于进行掺杂操作的额外设备会不利地影响产量。视线方案可以用于在FinFET上沉积掺杂物膜，但是FinFET的3D结构阻止合适的膜沉积特性(即，在3D结构的侧壁上的沉积)，这不利地影响FinFET结构内的掺杂物分布和浓度。
因此，本领域中需要改良的FinFET掺杂方法。
发明内容
在一个实施方式中，提供了一种基板处理方法。所述方法包括在基板上形成的三维结构上沉积保形的含硼碳氮膜。三维结构可以是FinFET器件并且可使三维结构和膜退火以将硼扩散至三维结构中，以便掺杂FinFET器件。
在另一实施方式中，提供了一种基板处理方法。基板处理方法包括形成基板的含硅三维结构并且将三维结构暴露于含一种或多种掺杂物的前驱物和一种或多种载气。可以将保形膜沉积在三维结构上并且保形膜可以包括掺杂物和选自由碳和氮组成的群组的至少一种非掺杂物材料。可以使三维结构和保形膜退火以将掺杂物从保形膜扩散至三维结构中。
在又一实施方式中，提供了一种基板处理方法。所述方法包括将形成有三维结构在其上的基板定位在膜沉积腔室的处理区域中并且将三维结构暴露于一种或多种含掺杂物的前驱物和一种或多种载气。可以将保形膜沉积在三维结构上并且保形膜可以包括掺杂物和选自由碳和氮组成的群组的至少一种非掺杂物材料。可以将基板传送至热处理腔室，并且可以使三维结构和保形膜退火以将掺杂物从保形膜扩散至三维结构中。
附图说明
因此，为了能够详细理解本公开内容的上述特征所用方式，可以参考各个实施方式得出上文简要概述的本公开内容的更具体的描述，一些实施方式在附图中示出。然而，应当注意，附图仅示出了本公开内容的典型实施方式并且由此不被认为限制本公开内容的范围，由于本公开内容可允许其他等效实施方式。
图1示出了根据本文中所述的一个实施方式的形成有三维(3D)结构在其上的基板的示意性截面图。
图2示出了根据本文中所述的实施方式的用于进行保形膜沉积和掺杂工艺的方法的操作。
为了便于理解，在可能情况下，已经使用相同词语来指示各图中共有的相同元件。可以构想的是，一个实施方式中公开的元件可有利地用于其他实施方式，而不特别陈述。
具体实施方式
本文中所述的实施方式总体涉及对基板上的三维(3D)结构的掺杂。在一个实施方式中，保形的含掺杂物膜可沉积在3D结构上方。可结合在膜中的合适的掺杂物可以包括硼、磷、和其他合适的掺杂物。随后可使膜退火以将掺杂物扩散至3D结构中。
图1示出了根据本文中所述的一个实施方式的形成有三维(3D)结构104在其上的基板100的示意性截面图。基板100包括从基部材料层102延伸的3D结构104。在一个实施方式中，基部材料层102可以是含硅材料，诸如纯硅或掺杂硅。在另一实施方式中，基部材料层102可以是绝缘体材料，诸如氧化物、氮化物等等。例如，基板100可以是绝缘体上硅基板。本文中所述的实施方式一般参考300mm圆形基板，然而，构想的是，各种其他基板尺寸可得益于本文中所述的实施方式。
3D结构104可以通过各种图案化和蚀刻工艺形成在基部材料层102上。一般来说，形成具有适合于实现方式(如互补金属氧化物半导体(CMOS)晶体管中的鳍式场效晶体管(FinFET))的尺寸的3D结构，然而，其他晶体管类型也可得益于本文中所述的实施方式。构想的是，3D结构可适合于等同于在当前技术节点和先进技术节点(诸如子10nm节点)中利用的尺寸并且可以具有这种尺寸。
3D结构104可以是与基部材料层102相同的材料或与基部材料层102不同的材料。在一个实施方式中，3D结构104可以由硅形成。在其他实施方式中，3D结构可以包括多种材料，诸如硅和一种或多种掺杂物。3D结构104从基部材料层102延伸并且由沟槽116间隔开来。3D结构包括顶表面108和在沟槽116的顶表面108与底表面110之间延伸的侧壁106。
保形膜112沉积在3D结构104和基部材料层102上方。无论其中保形膜112被沉积的区域如何，保形膜112一般都维持固定或实质上固定的厚度。在一个实施方式中，可以以大于约70％的保形度、大于约80％的保形度、大于约90％的保形度、大于约95％的保形度或大于约98％的保形度沉积保形膜112。例如，可以在顶表面108、侧壁106、和底表面110附近维持保形膜112的厚度114，使得厚度跨保形膜112的约70％是显著相等的。在一个实施方式中，取决于3D结构尺寸和期望掺杂特性，厚度114可以在约10nm与约100nm之间。
保形膜112可以通过各种沉积技术(诸如化学气相沉积(CVD)或基于等离子体的沉积技术)沉积。在一个实施方式中，保形膜112可以通过热CVD技术进行沉积。在此实施方式中，热前驱物蒸发设备可耦接至合适地构造的膜沉积腔室以在沉积前制备各种前驱物。取决于利用的前驱物，由热前驱物蒸发设备利用的温度可以在约70℃与约150℃之间。在另一实施方式中，保形膜112可以通过等离子体增强化学气相沉积(PECVD)沉积技术进行沉积。在此实施方式中，等离子体可以通过远程等离子体源产生或可以在处理腔室内产生。在另一实施方式中，保形膜112可以通过混合热/等离子体沉积技术进行沉积。用于沉积保形膜112的合适设备是获自加利福尼亚州圣克拉拉市应用材料公司(Applied Materials,Inc.,Santa Clara,CA)的
Figure BDA0001583972810000031
腔室。构想的是，来自其他制造商的合适地构造的腔室也可用于进行根据本文中所述的实施方式的保形膜沉积。
图2示出了根据本文中所述的实施方式的用于进行保形膜沉积和掺杂工艺的方法200的操作。在操作202，保形的含掺杂物膜可以沉积在基板上形成的3D结构上。膜可以利用经构造以提供如上文中所述的保形度的合适处理条件来沉积。在一个实施方式中，可将含掺杂物的保形膜沉积在基板上，所述基板定位在膜沉积腔室的处理区域中。在某些实施方式中，含掺杂物的保形膜可以包括掺杂物和非掺杂物材料。合适的掺杂物物质包括硼、磷、砷、锑、铝、和镓等等。非掺杂物材料包括碳、氮、硅、和氧等等。一般来说，保形膜中的掺杂物在后续处理操作期间将扩散至3D结构中，而非掺杂物材料将不扩散至3D结构中。
在一个示例中，硼碳氮膜可以沉积在3D结构上。在此实施方式中，含硼前驱物(诸如二甲胺硼烷)可暴露于膜沉积腔室中的3D结构。可选地，含硼前驱物可以在进入膜沉积腔室的处理区域中之前经加热。在此实施方式中，非掺杂物材料碳和氮也可以暴露于3D特征。合适的含碳前驱物可以是含烃材料，诸如丙烯，并且合适的含氮前驱物可以是氨等等。
为了控制保形膜的元素组成，前驱物的流动速率可变化以影响保形膜组成剖面。此外，可以将各种载气(诸如氩、氮、氢、和氦等等)连同前驱物提供至膜沉积腔室的处理容积。可以将一种或多种载气以约100sccm至约20,000sccm之间的速率来提供至膜沉积腔室。掺杂物前驱物相对于载气的分压可以在约10帕斯卡至约1000帕斯卡之间。
在保形膜沉积工艺期间，膜沉积腔室的温度可以维持在约200℃与约650℃之间。在保形膜沉积工艺期间，膜沉积腔室的压力可以维持在约100mTorr与约100Torr之间。认为的是，前驱物流动速率、腔室温度、和腔室压力可以经构造以影响含掺杂物膜的保形度，从而提供适合于对3D结构的后续掺杂的保形度。
在操作204，可以使3D结构退火以将掺杂物从含掺杂物保形膜扩散至3D结构中。可以将基板从膜沉积腔室传送至退火腔室，诸如快速热处理腔室。快速热处理可以利用用于使基板退火的各种电磁能源。例如，辐射加热、激光退火、或它们的组合可以用于将掺杂物从保形膜驱使至3D结构中。在一个实施方式中，用于进行退火工艺的合适设备包括
Figure BDA0001583972810000041
ASTRATM工具、
Figure BDA0001583972810000043
PLUS工具、
Figure BDA0001583972810000044
VULCANTM工具，全部所述工具获自加利福尼亚州圣克拉拉市应用材料公司。构想的是，来自其他制造商的合适地构造的退火设备也可用于进行本文中所述的退火工艺。
退火工艺可以在约700℃与约1100℃之间(诸如约850℃与约1050℃之间)的温度下进行。退火工艺一般经构造以重复方式快速加热设置在基板上的材料。温度循环可以在毫秒量级至秒量级上进行，并且认为，退火不仅致使掺杂物从保形膜扩散至3D结构中，也会使保形膜的非掺杂物材料挥发以防止非掺杂物材料扩散至3D结构中。
由于保形的含掺杂物膜的保形度，可以可控方式进行掺杂物至3D结构中的扩散，使得在3D结构内的掺杂物分布是显著均匀的。换句话说，掺杂物从多个方向(即，侧壁和顶表面)扩散至3D结构中并且扩散深度可由退火工艺控制。在上文中所述的硼碳氮实施方式中，在3D结构(后退火)中的硼浓度可以在约2.5×1021原子/cm3与约3.5×1021原子/cm3之间。在3D结构(后退火期间)中的碳和氮浓度可以小于约5.0×1018原子/cm3，诸如小于约5.0×1017原子/cm3。取决于因退火工艺造成的扩散深度，碳和氮的浓度可以是约0原子/cm3或不显著影响3D结构的器件功能(即，阈值电压)的另一可忽略不计的浓度。通过将掺杂物以均匀方式选择性地结合到3D结构中，在3D结构中的掺杂物分布可以提供改良的阈值电压工程并且也可提供改良的器件性能。
在已经进行退火工艺后，可以从基板和3D结构移除掺杂物耗尽的保形膜的任何剩余部分。具有被选择来优先移除保形膜的化学试剂的各种蚀刻工艺(诸如湿式蚀刻或干式等离子体蚀刻工艺)可用于移除保形膜。因此，3D结构可以用期望掺杂物物质来掺杂，并且3D结构可适合于后续器件结构制造工艺。

Claims (15)

1.一种基板处理方法，包括：
通过热化学气相沉积工艺和等离子体沉积工艺的组合在基板上形成的三维结构上沉积由硼、碳和氮组成的保形膜，其中所述三维结构是含硅FinFET器件；和
使所述三维结构和所述膜退火以将硼扩散至所述三维结构中，以便掺杂所述FinFET器件。
2.如权利要求1所述的方法，其中所述膜中的所述硼源自二甲胺硼烷前驱物。
3.如权利要求1所述的方法，其中所述退火工艺是快速热退火工艺。
4.如权利要求3所述的方法，其中所述快速热退火工艺是在700℃与1100℃之间的温度下进行的尖峰退火工艺。
5.如权利要求4所述的方法，其中所述尖峰退火工艺包括激光尖峰退火。
6.一种基板处理方法，包括：
在基板上形成含硅三维结构；
将所述含硅三维结构暴露于一种或多种含掺杂物的前驱物和一种或多种载气；
通过热化学气相沉积工艺和等离子体沉积工艺的组合将由硼、碳和氮组成的保形膜沉积在所述含硅三维结构上；以及
使所述含硅三维结构和所述保形膜退火以将所述掺杂物从所述保形膜扩散至所述含硅三维结构中。
7.如权利要求6所述的方法，其中所述含硅三维结构包括FinFET器件结构。
8.如权利要求6所述的方法，其中所述掺杂物是硼并且所述含掺杂物的前驱物是二甲胺硼烷。
9.如权利要求6所述的方法，其中所述退火是在700℃与1100℃之间的温度下进行的尖峰退火工艺。
10.一种基板处理方法，包括：
将具有三维结构的基板定位在膜沉积腔室的处理区域中，所述三维结构形成于所述基板上；
将所述三维结构暴露于一种或多种含掺杂物的前驱物和一种或多种载气；
通过热化学气相沉积工艺和等离子体沉积工艺的组合将由硼、碳和氮组成的保形膜沉积在所述三维结构上；
将所述基板传送至热处理腔室；和
使所述三维结构和所述保形膜退火以将所述掺杂物从所述保形膜扩散至所述三维结构中。
11.如权利要求10所述的方法，其中所述膜沉积腔室经构造以进行热化学气相沉积工艺来沉积所述保形膜。
12.如权利要求11所述的方法，其中沉积所述保形膜是在200℃与650℃之间的温度下在所述膜沉积腔室中进行。
13.如权利要求12所述的方法，其中在所述保形膜沉积期间将所述处理区域维持在100mTorr与100Torr之间的压力下。
14.如权利要求11所述的方法，其中所述一种或多种含掺杂物的前驱物包括二甲胺硼烷。
15.如权利要求14所述的方法，其中在所述一种或多种含掺杂物的前驱物中的所述二甲胺硼烷和所述一种或多种载气的分压在10帕斯卡与1000帕斯卡之间。
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