WO2017063226A1 - 薄膜场效应晶体管及其制作方法、液晶显示器 - Google Patents

薄膜场效应晶体管及其制作方法、液晶显示器 Download PDF

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Publication number
WO2017063226A1
WO2017063226A1 PCT/CN2015/092840 CN2015092840W WO2017063226A1 WO 2017063226 A1 WO2017063226 A1 WO 2017063226A1 CN 2015092840 W CN2015092840 W CN 2015092840W WO 2017063226 A1 WO2017063226 A1 WO 2017063226A1
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metal layer
layer
drain
drain metal
source metal
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French (fr)
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冯托
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/892,318 priority Critical patent/US10290717B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6746—Amorphous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the invention relates to a field effect transistor, in particular to a thin film field effect transistor, a manufacturing method thereof and a liquid crystal display.
  • LCDs liquid crystal displays
  • a thin film field effect transistor is widely used as a switching element of an LCD.
  • An important indicator to measure the quality of TFT switching is the severity of erroneous writing during TFT charging and discharging.
  • An important factor determining the quality of TFT switching is the parasitic capacitance C gs between the gate electrode and the source electrode. Since the TFT near the opening or closing transient, when the gate voltage V gs instantaneously falls from the high level to the low level V gon V goff, V gs of the conversion amount ⁇ V gs TFT is coupled to the parasitic capacitance C gs pixels On the electrode, the pixel voltage V p is caused to jump, and the jump variable is ⁇ V p . The larger the parasitic capacitance C gs of the TFT, the larger the jump variable ⁇ V p .
  • an object of the present invention is to provide a thin film field effect transistor comprising: a gate metal layer on a substrate; and a gate insulating covering the substrate and the gate metal layer a first source metal layer and a first drain metal layer on the gate insulating layer and spaced apart from each other; active on the first source metal layer and the first drain metal layer a layer; wherein the active layer fills an interval between the first source metal layer and the first drain metal layer, and forms a channel at a location of the interval; a second source metal layer and a second drain metal layer on each side of the layer on the layer; wherein the second source metal layer is in contact with the first source metal layer, A second drain metal layer is in contact with the first drain metal layer.
  • the interval exposes a portion of the gate insulating layer, and the remaining portion of the gate insulating layer The first source metal layer and the first drain metal layer are completely covered.
  • the active layer covers a portion of the first source metal layer, and the active layer covers a portion of the first drain metal layer; the second source metal layer covers the portion a portion of a source metal layer not covered by the active layer, the second drain metal layer covering a portion of the first drain metal layer not covered by the active layer.
  • the spacing exposes a portion of the gate insulating layer, and the remaining portion of the gate insulating layer is not completely covered by the first source metal layer and the first drain metal layer.
  • the active layer covers a portion of the first source metal layer, and the active layer covers a portion of the first drain metal layer; the second source metal layer covers the portion a portion of a source metal layer not covered by the active layer and a portion of the gate insulating layer not covered by the first source metal layer, the second drain metal layer covering the first a portion of the drain metal layer not covered by the active layer and a portion of the gate insulating layer not covered by the first drain metal layer.
  • a passivation layer is formed on the second source metal layer and the second drain metal layer, and the passivation layer fills the channel And covering the second source metal layer and the second drain metal layer; forming a via in the passivation layer, wherein the via exposes the second drain metal layer; A pixel electrode is formed on the passivation layer, wherein the pixel electrode contacts the second drain metal layer via the via.
  • the active layer covers a portion of the first source metal layer, and the active layer covers a portion of the first drain metal layer; the second source metal layer covers the remaining portion a portion of a source metal layer, the second drain metal layer covering a portion of the remaining portion of the first drain metal layer.
  • a passivation layer is formed on the second source metal layer and the second drain metal layer, and the passivation layer fills the channel
  • the passivation layer covers the second source metal layer and a portion of the first source metal layer not covered by the second source metal layer, and the passivation layer covers the second drain a portion of the epitaxial metal layer and the first drain metal layer not covered by the second drain metal layer; forming a via in the passivation layer, wherein the via exposes the first drain a metal layer; a pixel electrode is formed on the passivation layer, wherein the pixel electrode contacts the first drain metal layer via the via hole.
  • Another object of the present invention is to provide a method for fabricating a thin film field effect transistor, comprising the steps of: forming a gate metal layer on a substrate; forming a gate insulating layer covering the substrate and the gate metal layer; Forming a first source metal layer and a first drain metal layer spaced apart from each other on the gate insulating layer; forming an active layer on the first source metal layer and the first drain metal layer; Wherein the active layer fills an interval between the first source metal layer and the first drain metal layer, and forms a channel at a position of the interval; on the active layer Forming a second source metal layer and a second drain metal layer respectively on both sides of the channel; wherein the second source metal layer is in contact with the first source metal layer, the second drain The polar metal layer is in contact with the first drain metal layer.
  • Still another object of the present invention is to provide a liquid crystal display comprising the above-described thin film field effect transistor or a thin film field effect transistor fabricated by the above-described fabrication method.
  • a source metal layer and a drain metal layer are respectively disposed on upper and lower layers of an active layer, which can reduce a parasitic capacitance Cgs between a gate metal layer and a source metal layer, and can be reduced.
  • the footprint of the thin film field effect transistor is reduced.
  • FIG. 1 is a schematic structural view of a thin film field effect transistor according to a first embodiment of the present invention
  • FIG. 2 is a schematic structural view of a thin film field effect transistor according to a second embodiment of the present invention.
  • FIG 3 is a schematic structural view of a thin film field effect transistor according to a third embodiment of the present invention.
  • FIG. 1 is a schematic structural view of a thin film field effect transistor according to a first embodiment of the present invention.
  • a substrate 10 is provided.
  • the substrate 10 is a transparent glass substrate, but the present invention is not limited thereto.
  • the substrate 10 may be a transparent resin substrate.
  • the gate metal layer 20 is formed of a molybdenum (Mo)/aluminum (Al) double-layer metal structure, but the invention is not limited thereto.
  • the gate metal layer 20 may also adopt a tantalum (Ta) single-layer metal structure.
  • a molybdenum/niobium (Mo/Ta) double-layer metal structure, a molybdenum/tungsten (Mo/W) double-layer metal structure or an aluminum (Al) single-layer metal structure is formed.
  • the gate insulating layer 30 covering the substrate 10 and the gate metal layer 20 is formed.
  • the gate insulating layer 30 may be made of silicon nitride and/or silicon oxide, but the invention is not limited thereto.
  • a first source metal layer 40a and a first drain metal layer 40b are formed on the gate insulating layer 30 by using a first photolithography mask; wherein, the first source metal layer 40a and the first drain The space between the metal layers 40b exposes a portion of the gate insulating layer 30, and the remaining portion of the gate insulating layer 30 is completely covered by the first source metal layer 40a and the second first drain metal layer 40b.
  • the first source metal layer 40a and the first drain metal layer 40b may each be formed of a three-layer metal structure of molybdenum (Mo)/aluminum (Al)/molybdenum (Mo), but the invention is not limited thereto.
  • the first source metal layer 40a and/or the first drain metal layer 40b may also adopt a tantalum (Ta) single-layer metal structure, a molybdenum/niobium (Mo/Ta) double-layer metal structure, molybdenum/tungsten (Mo/W) a double-layer metal structure or an aluminum (Al) single-layer metal structure or the like.
  • Ta tantalum
  • Mo/Ta molybdenum/niobium
  • Mo/W molybdenum/tungsten
  • Al aluminum
  • an active layer 50 is formed on the first source metal layer 40a and the first drain metal layer 40b; wherein the active layer 50 fills between the first source metal layer 40a and the first drain metal layer 40b Portions of the first source metal layer 40a and portions of the first drain metal layer 40b are spaced and covered, and a channel 510 is formed at a space between the first source metal layer 40a and the first drain metal layer 40b.
  • the active layer 50 is formed of amorphous silicon (a-Si), but the present invention is not limited thereto.
  • a second source metal layer 60a on the first source metal layer 40a and a second drain on the first drain metal layer 40b are formed on the active layer 50 by using the first photolithography mask.
  • the second source metal layer 60a and the second drain metal layer 60b may each be formed of a three-layer metal structure of molybdenum (Mo)/aluminum (Al)/molybdenum (Mo), but the invention is not limited thereto.
  • the second source metal layer 60a and/or the second drain metal layer 60b may also adopt a tantalum (Ta) single-layer metal structure, a molybdenum/niobium (Mo/Ta) double-layer metal structure, molybdenum/tungsten (Mo/W) a double-layer metal structure or an aluminum (Al) single-layer metal structure or the like.
  • Ta tantalum
  • Mo/Ta molybdenum/niobium
  • Mo/W molybdenum/tungsten
  • Al aluminum
  • the gate metal layer 20 of the thin film field effect transistor is simultaneously formed with a gate line (not shown), and a gate electrode
  • the metal layer 20 is connected to the gate line;
  • the first source metal layer 40a or the second source metal layer 60a of the thin film field effect transistor is simultaneously formed with a data line (not shown), and the first source metal layer 40a and the The two source metal layers 60a are each connected to the data lines; then, a passivation layer 70 covering the second source metal layer 60a and the second drain metal layer 60b is formed, and the passivation layer 70 fills the channel 510;
  • a via 710 is formed in the passivation layer 70; wherein the via 710 exposes the second drain metal layer 60b; then, a pixel electrode 80 is formed on the passivation layer 70, and the pixel electrode 80 passes through the via 710
  • FIG. 2 is a schematic structural view of a thin film field effect transistor according to a second embodiment of the present invention.
  • the substrate 10 is a transparent glass substrate, but the present invention is not limited thereto.
  • the substrate 10 may be a transparent resin substrate.
  • the gate metal layer 20 is formed of a molybdenum (Mo)/aluminum (Al) double-layer metal structure, but the invention is not limited thereto.
  • the gate metal layer 20 may also adopt a tantalum (Ta) single-layer metal structure.
  • a molybdenum/niobium (Mo/Ta) double-layer metal structure, a molybdenum/tungsten (Mo/W) double-layer metal structure or an aluminum (Al) single-layer metal structure is formed.
  • the gate insulating layer 30 covering the substrate 10 and the gate metal layer 20 is formed.
  • the gate insulating layer 30 may be made of silicon nitride and/or silicon oxide, but the invention is not limited thereto.
  • a first source metal layer 40a and a first drain metal layer 40b are formed on the gate insulating layer 30 by using a first photolithography mask; wherein, the first source metal layer 40a and the first drain The space between the metal layers 40b exposes a portion of the gate insulating layer 30, and the remaining portion of the gate insulating layer 30 is completely covered by the first source metal layer 40a and the first drain metal layer 40b.
  • the first source metal layer 40a and the first drain metal layer 40b may each be formed of a three-layer metal structure of molybdenum (Mo)/aluminum (Al)/molybdenum (Mo), but the invention is not limited thereto.
  • the first source metal layer 40a and/or the first drain metal layer 40b may also adopt a tantalum (Ta) single-layer metal structure, a molybdenum/niobium (Mo/Ta) double-layer metal structure, molybdenum/tungsten (Mo/W) a double-layer metal structure or an aluminum (Al) single-layer metal structure or the like.
  • Ta tantalum
  • Mo/Ta molybdenum/niobium
  • Mo/W molybdenum/tungsten
  • Al aluminum
  • an active layer 50 is formed on the first source metal layer 40a and the first drain metal layer 40b; wherein the active layer 50 fills between the first source metal layer 40a and the first drain metal layer 40b A portion of the first source metal layer 40a and a portion of the first drain metal layer 40b are spaced apart and form a channel 510 at a space between the first source metal layer 40a and the first drain metal layer 40b.
  • the active layer 50 is formed of amorphous silicon (a-Si), but the present invention is not limited thereto.
  • a second source metal layer 60a on the first source metal layer 40a and a second drain metal on the first drain metal layer 40b are formed on the active layer 50 by using the second photolithography mask.
  • the second source metal layer 60a and the second drain metal layer 60b may each be formed of a three-layer metal structure of molybdenum (Mo)/aluminum (Al)/molybdenum (Mo), but the invention is not limited thereto.
  • the second source metal layer 60a and/or the second drain metal layer 60b may also adopt a tantalum (Ta) single-layer metal structure, a molybdenum/niobium (Mo/Ta) double-layer metal structure, molybdenum/tungsten (Mo/W) a double-layer metal structure or an aluminum (Al) single-layer metal structure or the like.
  • Ta tantalum
  • Mo/Ta molybdenum/niobium
  • Mo/W molybdenum/tungsten
  • Al aluminum
  • the gate metal layer 20 of the thin film field effect transistor is simultaneously formed with the gate line (not shown), and the gate metal layer 20 is connected to the gate line; the first source metal layer 40a of the thin film field effect transistor or The second source metal layer 60a is formed simultaneously with the data line (not shown), and the first source metal layer 40a and the second source metal layer 60a are both connected to the data line; then, forming the first source metal layer is covered 40a, a first drain metal layer 40b, a second source metal layer 60a, and a passivation layer 70 of the second drain metal layer 60b, and the passivation layer 70 fills the channel 510; then, in the passivation layer 70 Forming a via 710; wherein the via 710 exposes the first drain metal layer 40b; finally, forming a pixel
  • FIG 3 is a schematic structural view of a thin film field effect transistor according to a third embodiment of the present invention.
  • the substrate 10 is a transparent glass substrate, but the present invention is not limited thereto.
  • the substrate 10 may be a transparent resin substrate.
  • the gate metal layer 20 is formed of a molybdenum (Mo)/aluminum (Al) double-layer metal structure, but the invention is not limited thereto.
  • the gate metal layer 20 may also adopt a tantalum (Ta) single-layer metal structure.
  • a molybdenum/niobium (Mo/Ta) double-layer metal structure, a molybdenum/tungsten (Mo/W) double-layer metal structure or an aluminum (Al) single-layer metal structure is formed.
  • the gate insulating layer 30 covering the substrate 10 and the gate metal layer 20 is formed.
  • the gate insulating layer 30 may be made of silicon nitride and/or silicon oxide, but the invention is not limited thereto.
  • a first source metal layer 40a and a first drain metal layer 40b are formed on the gate insulating layer 30 by using a second photolithography mask; wherein, the first source metal layer 40a and the first drain The space between the metal layers 40b exposes a portion of the gate insulating layer 30, and the remaining portion of the gate insulating layer 30 is not completely covered by the first source metal layer 40a and the first drain metal layer 40b, that is, the first source The metal layer 40a and the first drain metal layer 40b cover portions of the remaining portion of the gate insulating layer 30.
  • the first source metal layer 40a and the first drain metal layer 40b may each be formed of a three-layer metal structure of molybdenum (Mo)/aluminum (Al)/molybdenum (Mo), but the invention is not limited thereto.
  • the first source metal layer 40a and/or the first drain metal layer 40b may also adopt a tantalum (Ta) single-layer metal structure, a molybdenum/niobium (Mo/Ta) double layer.
  • an active layer 50 is formed on the first source metal layer 40a and the first drain metal layer 40b; wherein the active layer 50 fills between the first source metal layer 40a and the first drain metal layer 40b Portions of the first source metal layer 40a and portions of the first drain metal layer 40b are spaced and covered, and a channel 510 is formed at a space between the first source metal layer 40a and the first drain metal layer 40b.
  • the active layer 50 is formed of amorphous silicon (a-Si), but the present invention is not limited thereto.
  • a second source metal layer 60a on the first source metal layer 40a and a second drain metal on the first drain metal layer 40b are formed on the active layer 50 by using the first photolithography mask.
  • the second drain metal layer 60b covers a portion of the first drain metal layer 40b that is not covered by the active layer 50 and a portion of the gate insulating layer 30 that is not covered by the first drain metal layer 40b.
  • the second source metal layer 60a and the second drain metal layer 60b may each be formed of a three-layer metal structure of molybdenum (Mo)/aluminum (Al)/molybdenum (Mo), but the invention is not limited thereto.
  • the second source metal layer 60a and/or the second drain metal layer 60b may also adopt a tantalum (Ta) single-layer metal structure, a molybdenum/niobium (Mo/Ta) double-layer metal structure, molybdenum/tungsten (Mo/W) a double-layer metal structure or an aluminum (Al) single-layer metal structure or the like.
  • the gate metal layer 20 of the thin film field effect transistor is simultaneously formed with a gate line (not shown), and a gate electrode
  • the metal layer 20 is connected to the gate line
  • the first source metal layer 40a or the second source metal layer 60a of the thin film field effect transistor is simultaneously formed with a data line (not shown), and the first source metal layer 40a and the The two source metal layers 60a are each connected to the data lines; then, a passivation layer 70 covering the second source metal layer 60a and the second drain metal layer 60b is formed, and the passivation layer 70 fills the channel 510;
  • a via 710 is formed in the passivation layer 70; wherein the via 710 exposes the second drain metal layer 60b; finally, a pixel electrode 80 is formed on the passivation layer 70 of the thin film field effect transistor, and the pixel electrode
  • the source metal layer and the drain metal layer are respectively disposed on the upper and lower layers of the active layer, which can reduce the parasitic capacitance C between the gate metal layer and the source metal layer. Gs , and can reduce the footprint of the thin film field effect transistor.
  • the thin film field effect transistor is applied to an LCD, since the occupied area of the thin film field effect transistor is reduced, the aperture ratio of the pixel can be improved.

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Abstract

一种薄膜场效应晶体管，其包括：在基板（10）上的栅极金属层（20）；覆盖基板（10）和栅极金属层（20）的栅极绝缘层（30）；在栅极绝缘层（30）上且相互间隔的第一源极金属层（40a）和第一漏极金属层（40b）；在第一源极金属层（40a）和第一漏极金属层（40b）上的有源层（50）；其中，有源层（50）填充第一源极金属层（40a）和第一漏极金属层（40b）之间的间隔，并在间隔处形成沟道（510）；在有源层（50）上的分别位于沟道（510）两侧的第二源极金属层（60a）和第二漏极金属层（60b）；其中，第二源极金属层（60a）和第一源极金属层（40a）接触，第二漏极金属层（60b）和第一漏极金属层（40b）接触。该结构降低了薄膜场效应晶体管中的寄生电容Cgs，并且减小了薄膜场效应晶体管的占用面积。这样，当薄膜场效应晶体管应用于LCD中时，由于薄膜场效应晶体管的占用面积减小，所以能够提高像素的开口率。

Description

薄膜场效应晶体管及其制作方法、液晶显示器 技术领域
本发明涉及一种场效应晶体管，尤其涉及一种薄膜场效应晶体管及其制作方法、液晶显示器。
背景技术
随着光电与半导体技术的演进，也带动了平板显示器(Flat Panel Display)的蓬勃发展，而在诸多平板显示器中，液晶显示器(Liquid Crystal Display，简称LCD)因具有高空间利用效率、低消耗功率、无辐射以及低电磁干扰等诸多优越特性，已成为市场的主流。
目前，作为LCD的开关元件而广泛采用的是薄膜场效应晶体管(TFT)。衡量TFT开关品质的一个重要指标是TFT充放电时误写入的严重程度，决定TFT开关品质的一个重要因素是栅电极和源电极之间的寄生电容Cgs。由于TFT的打开或关闭接近瞬态，当栅极电压Vgs从高电平Vgon瞬间下降到低电平Vgoff时，Vgs的变换量ΔVgs会被TFT的寄生电容Cgs耦合到像素电极上，导致像素电压Vp跳变，跳变量为ΔVp。TFT的寄生电容Cgs越大，跳变量ΔVp愈大。
发明内容
为了解决上述现有技术存在的问题，本发明的目的在于提供一种薄膜场效应晶体管，其包括：在基板上的栅极金属层；覆盖所述基板和所述栅极金属层的栅极绝缘层；在所述栅极绝缘层上且相互间隔的第一源极金属层和第一漏极金属层；在所述第一源极金属层和所述第一漏极金属层上的有源层；其中，所述有源层填充所述第一源极金属层和所述第一漏极金属层之间的间隔，并在所述间隔的所在位置处形成沟道；在所述有源层上的分别位于所述沟道两侧的第二源极金属层和第二漏极金属层；其中，所述第二源极金属层和所述第一源极金属层接触，所述第二漏极金属层和所述第一漏极金属层接触。
进一步地，所述间隔露出部分所述栅极绝缘层，其余部分所述栅极绝缘层 被所述第一源极金属层和所述第一漏极金属层完全覆盖。
进一步地，所述有源层覆盖所述第一源极金属层的部分，且所述有源层覆盖所述第一漏极金属层的部分；所述第二源极金属层覆盖所述第一源极金属层的未被所述有源层覆盖的部分，所述第二漏极金属层覆盖所述第一漏极金属层的未被所述有源层覆盖的部分。
进一步地，所述间隔露出部分所述栅极绝缘层，其余部分所述栅极绝缘层未被所述第一源极金属层和所述第一漏极金属层完全覆盖。
进一步地，所述有源层覆盖所述第一源极金属层的部分，且所述有源层覆盖所述第一漏极金属层的部分；所述第二源极金属层覆盖所述第一源极金属层的未被所述有源层覆盖的部分以及所述栅极绝缘层未被所述第一源极金属层覆盖的部分，所述第二漏极金属层覆盖所述第一漏极金属层的未被所述有源层覆盖的部分以及所述栅极绝缘层未被所述第一漏极金属层覆盖的部分。
进一步地，当所述薄膜场效应晶体管与像素电极连接时，在所述第二源极金属层和所述第二漏极金属层上形成钝化层，所述钝化层填充所述沟道并覆盖所述第二源极金属层和所述第二漏极金属层；在所述钝化层中形成过孔，其中，所述过孔露出所述第二漏极金属层；在所述钝化层上形成像素电极，其中，所述像素电极经由所述过孔接触所述第二漏极金属层。
进一步地，所述有源层覆盖部分所述第一源极金属层，且所述有源层覆盖部分所述第一漏极金属层；所述第二源极金属层覆盖其余部分所述第一源极金属层的部分，所述第二漏极金属层覆盖其余部分所述第一漏极金属层的部分。
进一步地，当所述薄膜场效应晶体管与像素电极连接时，在所述第二源极金属层和所述第二漏极金属层上形成钝化层，所述钝化层填充所述沟道，所述钝化层覆盖所述第二源极金属层以及所述第一源极金属层未被所述第二源极金属层覆盖的部分，且所述钝化层覆盖所述第二漏极金属层以及所述第一漏极金属层未被所述第二漏极金属层覆盖的部分；在所述钝化层中形成过孔，其中，所述过孔露出所述第一漏极金属层；在所述钝化层上形成像素电极，其中，所述像素电极经由所述过孔接触所述第一漏极金属层。
本发明的另一目的还在于提供一种薄膜场效应晶体管的制作方法，其包括步骤：在基板上形成栅极金属层；形成覆盖所述基板和所述栅极金属层的栅极绝缘层；在所述栅极绝缘层上形成相互间隔的第一源极金属层和第一漏极金属层；在所述第一源极金属层和所述第一漏极金属层上形成有源层；其中，所述有源层填充所述第一源极金属层和所述第一漏极金属层之间的间隔，并在所述间隔的所在位置处形成沟道；在所述有源层上形成分别位于所述沟道两侧的第二源极金属层和第二漏极金属层；其中，所述第二源极金属层和所述第一源极金属层接触，所述第二漏极金属层和所述第一漏极金属层接触。
本发明的又一目的又在于提供一种液晶显示器，其包括上述的薄膜场效应晶体管，或者包括利用上述的制作方法制作的薄膜场效应晶体管。
本发明的有益效果：本发明在有源层的上下两层分别设置源极金属层和漏极金属层，能够降低栅极金属层和源极金属层之间的寄生电容Cgs，并且能够减小薄膜场效应晶体管的占用面积。这样，当薄膜场效应晶体管应用于LCD中时，由于薄膜场效应晶体管的占用面积减小，所以能够提高像素的开口率。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1是根据本发明的第一实施例的薄膜场效应晶体管的结构示意图；
图2是根据本发明的第二实施例的薄膜场效应晶体管的结构示意图；
图3是根据本发明的第三实施例的薄膜场效应晶体管的结构示意图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。
在附图中，为了清楚器件，夸大了层和区域的厚度。相同的标号在整个说明书和附图中可用来表示相同的元件。
将理解的是，尽管在这里可使用术语“第一”、“第二”等来描述各种元件，但是这些元件不应受这些术语的限制。这些术语仅用于将一个元件与另一个元件区分开来。
也将理解的是，在一层或元件被称为在或形成在另一层或基板“之上”或“上”时，它可以直接在或形成在该另一层或基板上，或者也可以存在中间层或中间元件。
<第一实施例>
图1是根据本发明的第一实施例的薄膜场效应晶体管的结构示意图。
参照图1，首先，提供一基板10。在本实施例中，基板10为透明的玻璃基板，但本发明并不限制于此，例如，基板10也可为透明的树脂基板。
接着，在基板10上形成栅极金属层20。这里，栅极金属层20采用钼(Mo)/铝(Al)双层金属结构形成，但本发明并不限制于此，例如栅极金属层20也可采用钽(Ta)单层金属结构、钼/钽(Mo/Ta)双层金属结构、钼/钨(Mo/W)双层金属结构或铝(Al)单层金属结构等形成。
接着，形成覆盖基板10和栅极金属层20的栅极绝缘层30。这里，该栅极绝缘层30可利用氮化硅和/或氧化硅制成，但本发明并不局限于此。
接着，利用第一光刻掩膜板在栅极绝缘层30上形成间隔的第一源极金属层40a和第一漏极金属层40b；其中，第一源极金属层40a和第一漏极金属层40b之间的间隔露出栅极绝缘层30的部分，而栅极绝缘层30的其余部分被第一源极金属层40a和第二第一漏极金属层40b完全覆盖。在本实施例中，第一源极金属层40a和第一漏极金属层40b均可采用钼(Mo)/铝(Al)/钼(Mo)三层金属结构形成，但本发明并不限制于此，例如，第一源极金属层40a和/或第一漏极金属层40b也可采用钽(Ta)单层金属结构、钼/钽(Mo/Ta)双层金属结构、钼/钨(Mo/W)双层金属结构或铝(Al)单层金属结构等形成。
接着，在第一源极金属层40a和第一漏极金属层40b上形成有源层50；其中，有源层50填充第一源极金属层40a和第一漏极金属层40b之间的间隔且覆盖第一源极金属层40a的部分和第一漏极金属层40b的部分，并在第一源极金属层40a和第一漏极金属层40b之间的间隔处形成沟道510。在本实施例中，有源层50由非晶硅(a-Si)形成，但本发明并不限制于此。
最后，利用所述第一光刻掩膜板在有源层50上形成位于第一源极金属层40a上的第二源极金属层60a和位于第一漏极金属层40b上的第二漏极金属层60b；其中，第二源极金属层60a覆盖接触第一源极金属层40a的未被有源层50覆盖的部分，第二漏极金属层60b覆盖接触第一漏极金属层40b的未被有源层50覆盖的部分。在本实施例中，第二源极金属层60a和第二漏极金属层60b均可采用钼(Mo)/铝(Al)/钼(Mo)三层金属结构形成，但本发明并不限制于此，例如，第二源极金属层60a和/或第二漏极金属层60b也可采用钽(Ta)单层金属结构、钼/钽(Mo/Ta)双层金属结构、钼/钨(Mo/W)双层金属结构或铝(Al)单层金属结构等形成。
以上为根据本发明的第一实施例的薄膜场效应晶体管的制作过程。当根据本发明的第一实施例的薄膜场效应晶体管应用在液晶显示器LCD中作为开关器件时，薄膜场效应晶体管的栅极金属层20与栅极线(未示出)同时形成，并且栅极金属层20与栅极线连接；薄膜场效应晶体管的第一源极金属层40a或第二源极金属层60a与数据线(未示出)同时形成，并且第一源极金属层40a和第二源极金属层60a均与数据线连接；接着，形成覆盖第二源极金属层60a和第二漏极金属层60b的钝化层70，并且该钝化层70填充沟道510；接着，在钝化层70中形成过孔710；其中，该过孔710将第二漏极金属层60b露出；接着，在钝化层70上形成像素电极80，该像素电极80经由过孔710与第二漏极金属层60b电接触。在本实施例中，像素电极80可由透明的氧化铟锡(ITO)制成，但本发明并不限制于此。
<第二实施例>
图2是根据本发明的第二实施例的薄膜场效应晶体管的结构示意图。
参照图2，首先，提供一基板10。在本实施例中，基板10为透明的玻璃基板，但本发明并不限制于此，例如，基板10也可为透明的树脂基板。
接着，在基板10上形成栅极金属层20。这里，栅极金属层20采用钼(Mo)/铝(Al)双层金属结构形成，但本发明并不限制于此，例如栅极金属层20也可采用钽(Ta)单层金属结构、钼/钽(Mo/Ta)双层金属结构、钼/钨(Mo/W)双层金属结构或铝(Al)单层金属结构等形成。
接着，形成覆盖基板10和栅极金属层20的栅极绝缘层30。这里，该栅极绝缘层30可利用氮化硅和/或氧化硅制成，但本发明并不局限于此。
接着，利用第一光刻掩膜板在栅极绝缘层30上形成间隔的第一源极金属层40a和第一漏极金属层40b；其中，第一源极金属层40a和第一漏极金属层40b之间的间隔露出栅极绝缘层30的部分，而栅极绝缘层30的其余部分被第一源极金属层40a和第一漏极金属层40b完全覆盖。在本实施例中，第一源极金属层40a和第一漏极金属层40b均可采用钼(Mo)/铝(Al)/钼(Mo)三层金属结构形成，但本发明并不限制于此，例如，第一源极金属层40a和/或第一漏极金属层40b也可采用钽(Ta)单层金属结构、钼/钽(Mo/Ta)双层金属结构、钼/钨(Mo/W)双层金属结构或铝(Al)单层金属结构等形成。
接着，在第一源极金属层40a和第一漏极金属层40b上形成有源层50；其中，有源层50填充第一源极金属层40a和第一漏极金属层40b之间的间隔且覆盖部分第一源极金属层40a和部分第一漏极金属层40b，并在第一源极金属层40a和第一漏极金属层40b之间的间隔处形成沟道510。在本实施例中，有源层50由非晶硅(a-Si)形成，但本发明并不限制于此。
接着，利用第二光刻掩膜板在有源层50上形成位于第一源极金属层40a上的第二源极金属层60a和位于第一漏极金属层40b上的第二漏极金属层60b；其中，第二源极金属层60a覆盖其余部分第一源极金属层40a的部分，第二漏极金属层60b覆盖其余部分第一漏极金属层40b的部分。在本实施例中，第二源极金属层60a和第二漏极金属层60b均可采用钼(Mo)/铝(Al)/钼(Mo)三层金属结构形成，但本发明并不限制于此，例如，第二源极金属层60a和/或第二漏极金属层60b也可采用钽(Ta)单层金属结构、钼/钽(Mo/Ta)双层金属结构、钼/钨(Mo/W)双层金属结构或铝(Al)单层金属结构等形成。
以上为根据本发明的第二实施例的薄膜场效应晶体管的制作过程。当根据本发明的第二实施例的薄膜场效应晶体管应用在液晶显示器LCD中作为开关 器件时，薄膜场效应晶体管的栅极金属层20与栅极线(未示出)同时形成，并且栅极金属层20与栅极线连接；薄膜场效应晶体管的第一源极金属层40a或第二源极金属层60a与数据线(未示出)同时形成，并且第一源极金属层40a和第二源极金属层60a均与数据线连接；接着，形成覆盖第一源极金属层40a、第一漏极金属层40b、第二源极金属层60a和第二漏极金属层60b的钝化层70，并且该钝化层70填充沟道510；接着，在钝化层70中形成过孔710；其中，该过孔710将第一漏极金属层40b露出；最后，在薄膜场效应晶体管的钝化层70上形成像素电极80，该像素电极80经由过孔710与第一漏极金属层40b电接触。在本实施例中，像素电极80可由透明的氧化铟锡(ITO)制成，但本发明并不限制于此。
<第三实施例>
图3是根据本发明的第三实施例的薄膜场效应晶体管的结构示意图。
参照图3，首先，提供一基板10。在本实施例中，基板10为透明的玻璃基板，但本发明并不限制于此，例如，基板10也可为透明的树脂基板。
接着，在基板10上形成栅极金属层20。这里，栅极金属层20采用钼(Mo)/铝(Al)双层金属结构形成，但本发明并不限制于此，例如栅极金属层20也可采用钽(Ta)单层金属结构、钼/钽(Mo/Ta)双层金属结构、钼/钨(Mo/W)双层金属结构或铝(Al)单层金属结构等形成。
接着，形成覆盖基板10和栅极金属层20的栅极绝缘层30。这里，该栅极绝缘层30可利用氮化硅和/或氧化硅制成，但本发明并不局限于此。
接着，利用第二光刻掩膜板在栅极绝缘层30上形成间隔的第一源极金属层40a和第一漏极金属层40b；其中，第一源极金属层40a和第一漏极金属层40b之间的间隔露出栅极绝缘层30的部分，并且栅极绝缘层30的其余部分未被第一源极金属层40a和第一漏极金属层40b完全覆盖，即第一源极金属层40a和第一漏极金属层40b覆盖其余部分栅极绝缘层30的部分。在本实施例中，第一源极金属层40a和第一漏极金属层40b均可采用钼(Mo)/铝(Al)/钼(Mo)三层金属结构形成，但本发明并不限制于此，例如，第一源极金属层40a和/或第一漏极金属层40b也可采用钽(Ta)单层金属结构、钼/钽(Mo/Ta)双层 金属结构、钼/钨(Mo/W)双层金属结构或铝(Al)单层金属结构等形成。
接着，在第一源极金属层40a和第一漏极金属层40b上形成有源层50；其中，有源层50填充第一源极金属层40a和第一漏极金属层40b之间的间隔且覆盖第一源极金属层40a的部分和第一漏极金属层40b的部分，并在第一源极金属层40a和第一漏极金属层40b之间的间隔处形成沟道510。在本实施例中，有源层50由非晶硅(a-Si)形成，但本发明并不限制于此。
接着，利用第一光刻掩膜板在有源层50上形成位于第一源极金属层40a上的第二源极金属层60a和位于第一漏极金属层40b上的第二漏极金属层60b；其中，第二源极金属层60a覆盖第一源极金属层40a的未被有源层50覆盖的部分以及栅极绝缘层30的未被第一源极金属层40a覆盖的部分，第二漏极金属层60b覆盖第一漏极金属层40b的未被有源层50覆盖的部分以及栅极绝缘层30的未被第一漏极金属层40b覆盖的部分。在本实施例中，第二源极金属层60a和第二漏极金属层60b均可采用钼(Mo)/铝(Al)/钼(Mo)三层金属结构形成，但本发明并不限制于此，例如，第二源极金属层60a和/或第二漏极金属层60b也可采用钽(Ta)单层金属结构、钼/钽(Mo/Ta)双层金属结构、钼/钨(Mo/W)双层金属结构或铝(Al)单层金属结构等形成。
以上为根据本发明的第三实施例的薄膜场效应晶体管的制作过程。当根据本发明的第三实施例的薄膜场效应晶体管应用在液晶显示器LCD中作为开关器件时，薄膜场效应晶体管的栅极金属层20与栅极线(未示出)同时形成，并且栅极金属层20与栅极线连接；薄膜场效应晶体管的第一源极金属层40a或第二源极金属层60a与数据线(未示出)同时形成，并且第一源极金属层40a和第二源极金属层60a均与数据线连接；接着，形成覆盖第二源极金属层60a和第二漏极金属层60b的钝化层70，并且该钝化层70填充沟道510；接着，在钝化层70中形成过孔710；其中，该过孔710将第二漏极金属层60b露出；最后，在薄膜场效应晶体管的钝化层70上形成像素电极80，该像素电极80经由过孔710与第二漏极金属层60b电接触。在本实施例中，像素电极80可由透明的氧化铟锡(ITO)制成，但本发明并不限制于此。
综上所述，根据本发明的各实施例，在有源层的上下两层分别设置源极金属层和漏极金属层，能够降低栅极金属层和源极金属层之间的寄生电容Cgs， 并且能够减小薄膜场效应晶体管的占用面积。这样，当薄膜场效应晶体管应用于LCD中时，由于薄膜场效应晶体管的占用面积减小，所以能够提高像素的开口率。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (11)

  1. 一种薄膜场效应晶体管，其中，包括：
    在基板上的栅极金属层；
    覆盖所述基板和所述栅极金属层的栅极绝缘层；
    在所述栅极绝缘层上且相互间隔的第一源极金属层和第一漏极金属层；
    在所述第一源极金属层和所述第一漏极金属层上的有源层；其中，所述有源层填充所述第一源极金属层和所述第一漏极金属层之间的间隔，并在所述间隔的所在位置处形成沟道；
    在所述有源层上的分别位于所述沟道两侧的第二源极金属层和第二漏极金属层；其中，所述第二源极金属层和所述第一源极金属层接触，所述第二漏极金属层和所述第一漏极金属层接触。
  2. 根据权利要求1所述的薄膜场效应晶体管，其中，所述间隔露出部分所述栅极绝缘层，其余部分所述栅极绝缘层被所述第一源极金属层和所述第一漏极金属层完全覆盖。
  3. 根据权利要求2所述的薄膜场效应晶体管，其中，所述有源层覆盖所述第一源极金属层的部分，且所述有源层覆盖所述第一漏极金属层的部分；所述第二源极金属层覆盖所述第一源极金属层的未被所述有源层覆盖的部分，所述第二漏极金属层覆盖所述第一漏极金属层的未被所述有源层覆盖的部分。
  4. 根据权利要求1所述的薄膜场效应晶体管，其中，所述间隔露出部分所述栅极绝缘层，其余部分所述栅极绝缘层未被所述第一源极金属层和所述第一漏极金属层完全覆盖。
  5. 根据权利要求4所述的薄膜场效应晶体管，其中，所述有源层覆盖所述第一源极金属层的部分，且所述有源层覆盖所述第一漏极金属层的部分；所述第二源极金属层覆盖所述第一源极金属层的未被所述有源层覆盖的部分以 及所述栅极绝缘层未被所述第一源极金属层覆盖的部分，所述第二漏极金属层覆盖所述第一漏极金属层的未被所述有源层覆盖的部分以及所述栅极绝缘层未被所述第一漏极金属层覆盖的部分。
  6. 根据权利要求3所述的薄膜场效应晶体管，其中，当所述薄膜场效应晶体管与像素电极连接时，在所述第二源极金属层和所述第二漏极金属层上形成钝化层，所述钝化层填充所述沟道并覆盖所述第二源极金属层和所述第二漏极金属层；在所述钝化层中形成过孔，其中，所述过孔露出所述第二漏极金属层；在所述钝化层上形成像素电极，其中，所述像素电极经由所述过孔接触所述第二漏极金属层。
  7. 根据权利要求5所述的薄膜场效应晶体管，其中，当所述薄膜场效应晶体管与像素电极连接时，在所述第二源极金属层和所述第二漏极金属层上形成钝化层，所述钝化层填充所述沟道并覆盖所述第二源极金属层和所述第二漏极金属层；在所述钝化层中形成过孔，其中，所述过孔露出所述第二漏极金属层；在所述钝化层上形成像素电极，其中，所述像素电极经由所述过孔接触所述第二漏极金属层。
  8. 根据权利要求2所述的薄膜场效应晶体管，其中，所述有源层覆盖部分所述第一源极金属层，且所述有源层覆盖部分所述第一漏极金属层；所述第二源极金属层覆盖其余部分所述第一源极金属层的部分，所述第二漏极金属层覆盖其余部分所述第一漏极金属层的部分。
  9. 根据权利要求8所述的薄膜场效应晶体管，其中，当所述薄膜场效应晶体管与像素电极连接时，在所述第二源极金属层和所述第二漏极金属层上形成钝化层，所述钝化层填充所述沟道，所述钝化层覆盖所述第二源极金属层以及所述第一源极金属层未被所述第二源极金属层覆盖的部分，且所述钝化层覆盖所述第二漏极金属层以及所述第一漏极金属层未被所述第二漏极金属层覆盖的部分；在所述钝化层中形成过孔，其中，所述过孔露出所述第一漏极金属层；在所述钝化层上形成像素电极，其中，所述像素电极经由所述过孔接触所述第一漏极金属层。
  10. 一种薄膜场效应晶体管的制作方法，其中，包括步骤：
    在基板上形成栅极金属层；
    形成覆盖所述基板和所述栅极金属层的栅极绝缘层；
    在所述栅极绝缘层上形成相互间隔的第一源极金属层和第一漏极金属层；
    在所述第一源极金属层和所述第一漏极金属层上形成有源层；其中，所述有源层填充所述第一源极金属层和所述第一漏极金属层之间的间隔，并在所述间隔的所在位置处形成沟道；
    在所述有源层上形成分别位于所述沟道两侧的第二源极金属层和第二漏极金属层；其中，所述第二源极金属层和所述第一源极金属层接触，所述第二漏极金属层和所述第一漏极金属层接触。
  11. 一种液晶显示器，包括薄膜场效应晶体管，其中，所述薄膜场效应晶体管包括：
    在基板上的栅极金属层；
    覆盖所述基板和所述栅极金属层的栅极绝缘层；
    在所述栅极绝缘层上且相互间隔的第一源极金属层和第一漏极金属层；
    在所述第一源极金属层和所述第一漏极金属层上的有源层；其中，所述有源层填充所述第一源极金属层和所述第一漏极金属层之间的间隔，并在所述间隔的所在位置处形成沟道；
    在所述有源层上的分别位于所述沟道两侧的第二源极金属层和第二漏极金属层；其中，所述第二源极金属层和所述第一源极金属层接触，所述第二漏极金属层和所述第一漏极金属层接触。
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