WO2017049989A1 - 一种高速低功耗动态比较器 - Google Patents

一种高速低功耗动态比较器 Download PDF

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WO2017049989A1
WO2017049989A1 PCT/CN2016/089044 CN2016089044W WO2017049989A1 WO 2017049989 A1 WO2017049989 A1 WO 2017049989A1 CN 2016089044 W CN2016089044 W CN 2016089044W WO 2017049989 A1 WO2017049989 A1 WO 2017049989A1
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nmos transistor
gate
transistor
drain
pmos transistor
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PCT/CN2016/089044
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English (en)
French (fr)
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徐代果
胡刚毅
李儒章
王健安
陈光炳
王育新
付东兵
刘涛
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中国电子科技集团公司第二十四研究所
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Priority to US16/475,123 priority Critical patent/US10666243B2/en
Publication of WO2017049989A1 publication Critical patent/WO2017049989A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral

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  • the invention belongs to the technical field of analog or digital-analog hybrid integrated circuits, and in particular relates to a high-speed low-power dynamic comparator.
  • the present invention provides a high-speed, low-power dynamic comparator that maintains a very low static power consumption while implementing a high-speed operation of the comparator, and at the same time, as the power supply voltage decreases, the present invention provides a comparison.
  • the structure of the device still maintains a relatively fast comparison speed with respect to the above-described conventional structure.
  • a high speed low power dynamic comparator including a first NMOS transistor, a second NMOS transistor, a sixth NMOS transistor, a delay unit, a first inverter, and a second reverse a director, an AND gate, an AND gate, and a latch, the latch including a first control terminal, a second control terminal, a third control terminal, a first output terminal, a second output terminal, and a power supply terminal;
  • the gate of the first NMOS transistor is connected to the first input signal
  • the gate of the second NMOS transistor is connected to the second input signal
  • the source of the first NMOS transistor and the source of the second NMOS transistor are respectively connected to the sixth NMOS transistor.
  • a drain connection a source of the sixth NMOS transistor is grounded; a drain of the first NMOS transistor is respectively connected to an input end of the second inverter, a second output end of the latch; and the second NMOS transistor a drain is respectively connected to an input end of the first inverter, a first output end of the latch; an output end of the first inverter is connected to one of the inputs of the same OR gate, the second reverse The output of the device is connected to the other input of the same OR gate, and the output of the same gate is Connected to one of the input terminals of the gate, the input of the delay unit is connected to the other input of the AND gate, and the output of the AND gate is connected to the gate of the sixth NMOS transistor; the output of the delay unit and the third control The input ends of the delay unit are respectively connected to the first control end and the second control end, and the power supply terminal is connected to Vdd.
  • the latch includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor, wherein the first NMOS transistor
  • the drain is respectively connected to the drain of the fourth NMOS transistor, the drain of the first PMOS transistor, the drain of the second PMOS transistor, the gate of the fifth NMOS transistor, and the gate of the third PMOS transistor
  • the second NMOS a drain of the tube is connected to a drain of the fifth NMOS transistor, a drain of the third PMOS transistor, a drain of the fourth PMOS transistor, a gate of the fourth NMOS transistor, and a gate of the second PMOS transistor, respectively a source of a PMOS transistor, a source of the second PMOS transistor, a source of the third PMOS transistor, and a source of the fourth PMOS transistor are respectively connected to Vdd; a gate of the first PMOS transistor and a fourth PMOS transistor gate
  • the present invention has the following beneficial technical effects:
  • the comparator output signals Dp and Dn are outputted through the same OR gate XNOR.
  • the output signal and the control signal clk1 pass through the AND gate to generate a control signal of the NMOS transistor P10, thereby solving the static power consumption problem in the conventional structure.
  • the invention has simple structure, and has no obvious increase in area compared with the conventional structure, but at the same time achieves the purpose of high speed and low power consumption.
  • Figure 1 is a schematic diagram of the structure of a high speed low offset dynamic comparator
  • Figure 2 is a schematic diagram of the structure of a high speed low noise dynamic comparator
  • Figure 3 is a schematic diagram of the structure of a low power dynamic comparator
  • Figure 4 is a schematic diagram of the structure of a high speed low power dynamic comparator
  • Figure 5 is a comparison chart of comparator comparison time with input signal
  • Figure 6 is a comparison diagram of comparator power consumption with common mode voltage variation
  • Figure 7 is a comparison of comparator comparison time with power supply voltage.
  • Figure 1 shows a schematic diagram of a high-speed low-offset dynamic comparator structure (referred to as structure [1]).
  • structure [1] When the control signal clk1 is low, clk2 acts as a low-level delay signal for clk1, and the NMOS transistor M7/M8 /M15 is in the off state, the PMOS transistor M11/M14 is turned on, the inverter output signals Dp and Dn are low through the inverter I1/I2, the comparator is in the reset state; when clk1/clk2 becomes the high level After that, the NMOS transistor M7/M8/M15 is turned on, and the latch composed of the NMOS transistor M9/M10 and the PMOS transistor M12/M13 rapidly amplifies the voltage difference between the Tip and the Tin and enters the latched state.
  • the advantage of the structure [1] is that the inverter input structure is adopted, and the offset and noise are small compared with the conventional NMOS input structure.
  • the disadvantage is that the output terminals Tip and Tin of the input stage inverter are connected to the source of the latch structure M9/M10, so only M9 and M10 are working at the beginning of the positive feedback of the latch structure, M12 and M13 Without work, this latching principle does not maximize the advantages of the latch structure, making the comparator slower.
  • the input stage uses the inverter input structure, the structure is input in the latched state. The stage still has quiescent current, so there is static power.
  • FIG. 2 shows a schematic diagram of a high-speed low-noise dynamic comparator structure (referred to as structure [2]).
  • structure [2] When the control signal clk1 is low, the NMOS transistor M3 is turned off, the NMOS transistor M10 is turned on, and the PMOS transistor M6/M9 Turned on, through the inverter I1/I2, the comparator output signals Dp and Dn are low, the comparator is in the reset state; when clk1 becomes high, M10 is turned off, M3 is turned on, by the NMOS transistor M4
  • the latches of /M5 and PMOS transistors M7/M8 quickly amplify the voltage difference between Bip and Bin and enter the latched state.
  • FIG. 3 shows a schematic diagram of a low-power dynamic comparator structure (referred to as structure [3]).
  • structure [3] When the control signal clk1 is low, clk2 acts as a low-level delay signal for clk1, and the NMOS transistor M3/M4 /M11 is turned off, the PMOS transistor M7/M10 is turned on, and the comparator output signals Dp and Dn are low through the inverter I1/I2, and the comparator is in the reset state.
  • clk1 goes high, clk2 will remain low for a period of time. At this time, M11 is turned on, M3/M4 remains off, Aip and Ain appear voltage difference, and input tube M1/M2 is saturated, which helps.
  • FIG. 4 The schematic diagram of the structure of the high-speed low-power dynamic comparator proposed by the present invention is shown in FIG. 4 .
  • the high speed low power dynamic comparator comprises a first NMOS transistor P1, a second NMOS transistor P2, a sixth NMOS transistor P10, a delay unit B1, a first inverter I1, a second inverter I2, and an OR gate XNOR And an AND gate, the latch includes a first control terminal, a second control terminal, a third control terminal, a first output terminal (outputting a first output signal), and a second output terminal (outputting a second An output signal) and a power supply terminal; a gate of the first NMOS transistor P1 is connected to a first input signal (Vinp), and a gate of the second NMOS transistor P2 is connected to a second input signal (Vinn), the first NMOS transistor The source of P1, the source of the second NMOS transistor P2 are respectively connected to the drain of the sixth NMOS transistor P10, the source of the sixth NMOS transistor P10 is grounded, and the drain of the first NMOS transistor P1 is respectively opposite to the second The input end of
  • the latch includes a third NMOS transistor P3, a fourth NMOS transistor P4, a fifth NMOS transistor P5, a first PMOS transistor P6, a second PMOS transistor P7, a third PMOS transistor P8, and a fourth PMOS transistor P9.
  • the gate of P8 is connected, the drain of the second NMOS transistor P2 is respectively connected to the drain of the fifth NMOS transistor P5, the drain of the third PMOS transistor P8, the drain of the fourth PMOS transistor P9, and the fourth NMOS transistor P4.
  • the gates of the first PMOS transistor P6 and the gate of the fourth PMOS transistor P9 are respectively connected to the input terminal of the delay unit B1, and the output terminal of the delay unit B1 is connected to the gate of the third NMOS transistor P3.
  • the drains of the third NMOS transistor P3 are respectively connected to the source of the fourth NMOS transistor P4 and the source of the fifth NMOS transistor P5, and the source of the third NMOS transistor P3 is grounded.
  • the first PMOS transistor and the fourth PMOS transistor are pull-up PMOS transistors
  • the third NMOS transistor and the sixth NMOS transistor are pull-down NMOS transistors.
  • the first output signal of the latch generates an output signal Dp via the first inverter I1
  • the second output signal of the latch generates an output signal and Dn, Dp and Dn via the second inverter I2.
  • An output signal is generated by the OR gate XNOR.
  • This output signal and control signal clk1 are used as the input signal of the AND gate AND, the output signal of the AND gate AND controls the gate of P10, and clk1 generates its delay signal clk2 through the delay unit B1.
  • the comparator shown in Figure 4 has two operating states, one is the reset state and the other is the latched state.
  • the control signals clk1 and clk2 are at a low level
  • the NMOS transistors P3 and P10 are both turned off
  • the PMOS transistors P6 and P9 are turned on
  • the signal Dip generated by the first NMOS transistor P1 and the second NMOS transistor are turned on.
  • the signal Din generated by P2 is pulled up to the power supply voltage Vdd, and the comparator output signals Dp and Dn are low level through the inverters I1 and I2; when the comparator enters the latch state, the control signal clk1 becomes the high level.
  • Clk2 acts as the delayed signal of clk1 and temporarily remains low. At this time, P10 is turned on, P3 is still off, Dip and Din start to appear voltage difference, P1 and P2 are in saturation state, which helps to suppress the equivalent input noise of the comparator. After a certain delay, the control signal clk2 also becomes a high level, and the voltage difference between Din and Din causes the latch structure composed of P6, P7, P8, and P9 to quickly enter the latch state, and the comparison is completed, thereby achieving high-speed operation. the goal of.
  • the comparator output signals Dp and Dn are one high level, the other Low level, they turn off P10 through the same OR gate XNOR, so that the comparator has no static power consumption in the reset and latched state, thus achieving the purpose of low power consumption.
  • the structure achieves high speed at the same time. And the purpose of low power consumption.
  • the comparator structure proposed by the present invention has a higher speed advantage than the above-described conventional structure.
  • the reason is that the structure of the present invention saves the source-drain voltage difference VDS of the NMOS transistor in a latch structure with respect to the structure shown in FIG. 2 and FIG. 3, so that the structure proposed by the present invention is more speedy in low power supply voltage applications.
  • the above various structures are carefully designed in a 65 nm CMOS process.
  • the same input/output tube size is used, and the latch structure is also the same size, load.
  • Capacitors are taken at 15fF.
  • the clock frequency is 1.8 GHz
  • the power supply voltage is 1.2V
  • the common mode voltage is 0.6V.
  • the comparator is considered to be compared.
  • the comparison curve of the comparison time of the above four structure comparators as a function of the input differential signal ⁇ Vin is as shown in FIG. 5.
  • the clock frequency is 1.8 GHz and the power supply voltage is 1.2 V.
  • 0.6 V, the comparator is considered to be compared.
  • the comparison curve of the power consumption of the above four structure comparators as a function of the common mode voltage Vcm is shown in FIG. 6.
  • the clock frequency is 0.4 GHz, and the input differential voltage ⁇ Vin is 50 mV.
  • 0.5 Vdd, the comparator is considered to complete the comparison.
  • the comparison curve of the comparison time of the above four structure comparators as a function of the power supply voltage Vdd is as shown in FIG.
  • the high-speed low-power comparator structure proposed by the present invention has a speed increase of at least 30% and a power consumption of at least 15% compared with the conventional structures.

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Abstract

一种高速低功耗动态比较器，包括锁存器、与门、延迟单元、同或门，锁存器具有第一至第三控制端锁存器的输出分别经过反相器I1、I2产生第一比较器输出信号和第二比较器输出信号，第一比较器输出信号和第二比较器输出信号通过同或门产生输出信号，这个输出信号和控制信号clk1作为与门的输入信号，与门的输出信号控制六NMOS管P10的栅极，clk1通过延迟单元产生其延迟信号clk2，clk2输入到锁存器的第三控制端。将比较器输出信号Dp和Dn通过同或门XNOR产生输出信号，这个输出信号和控制信号clk1经过与门，产生NMOS管P10的控制信号，解决了传统结构中的静态功耗问题。

Description

一种高速低功耗动态比较器 技术领域
本发明属于模拟或数模混合集成电路技术领域，具体涉及一种高速低功耗动态比较器。
背景技术
近年来，随着集成电路制造技术的不断发展，CMOS器件的特征尺寸不断减小，集成电路的工作电压也不断降低，在深亚微米工艺下，模数转换器的工作速度得到了极大的提高，同时，功耗进一步降低。但是，作为模数转换器的核心组成部分，比较器的性能成了高速低功耗设计的瓶颈。传统的几种比较器结构，很难同时满足速度、功耗和低电源电压等要求。
发明内容
鉴于此，本发明提供一种高速低功耗动态比较器，在实现比较器能够高速工作的情况下，仍然保持很低的静态功耗，同时，随着电源电压的降低，本发明提出的比较器结构相对于上述传统结构，仍然保持较快的比较速度。
为达到上述目的，本发明提供如下技术方案：一种高速低功耗动态比较器，包括第一NMOS管、第二NMOS管、第六NMOS管、延迟单元、第一反向器、第二反向器、同或门、与门和锁存器，所述锁存器包括第一控制端、第二控制端、第三控制端、第一输出端、第二输出端和电源端；所述第一NMOS管的栅极接第一输入信号，第二NMOS管的栅极接第二输入信号，所述第一NMOS管的源极、第二NMOS管的源极分别与第六NMOS管的漏极连接，第六NMOS管的源极接地；所述第一NMOS管的漏极分别与第二反向器的输入端、锁存器的第二输出端连接；所述第二NMOS管的漏极分别与第一反向器的输入端、锁存器的第一输出端连接；所述第一反向器的输出端与同或门的其中一个输入端连接，所述第二反向器的输出端与同或门的另一个输入端连接，所述同或门的输出端与 与门的其中一个输入端连接，延迟单元的输入端与与门的另一个输入端连接，与门的输出端与第六NMOS管的栅极连接；所述延迟单元的输出端与第三控制端连接，所述延迟单元的输入端分别与第一控制端、第二控制端连接，所述电源端接Vdd。
进一步，所述锁存器包括第三NMOS管、第四NMOS管、第五NMOS管、第一PMOS管、第二PMOS管、第三PMOS管和第四PMOS管，所述第一NMOS管的漏极分别与第四NMOS管的漏极、第一PMOS管的漏极、第二PMOS管的漏极、第五NMOS管的栅极、第三PMOS管的栅极连接，所述第二NMOS管的漏极分别与第五NMOS管的漏极、第三PMOS管的漏极、第四PMOS管的漏极、第四NMOS管的栅极、第二PMOS管的栅极连接，所述第一PMOS管的源极、第二PMOS管的源极、第三PMOS管的源极、第四PMOS管的源极分别与Vdd连接；所述第一PMOS管的栅极、第四PMOS管栅极分别与延迟单元的输入端连接，延迟单元的输出端与第三NMOS管的栅极连接，第三NMOS管的漏极分别与第四NMOS管的源极、第五NMOS管的源极连接，第三NMOS管的源极接地。
由于采用了以上技术方案，本发明具有以下有益技术效果：
1、将输入管的输出端Dip/Din分别连接在NMOS管P4、P5的漏极，同时接PMOS管P7、P8的漏极，充分发挥这种锁存器结构的高速优势。
2、将比较器输出信号Dp和Dn通过同或门XNOR产生输出信号，这个输出信号和控制信号clk1经过与门，产生NMOS管P10的控制信号，解决了传统结构中的静态功耗问题。
3、实现本发明结构简单，和传统结构相比，没有明显增加面积，但同时达到了高速和低功耗的目的。
附图说明
为了使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明作进一步的详细描述，其中：
图1为高速低失调动态比较器结构原理图；
图2为高速低噪声动态比较器结构原理图；
图3为低功耗动态比较器结构原理图；
图4为高速低功耗动态比较器结构原理图；
图5为比较器比较时间随输入信号变化对比图；
图6为比较器功耗随共模电压变化对比图；
图7为比较器比较时间随电源电压变化对比图。
具体实施方式
以下将结合附图，对本发明的优选实施例进行详细的描述；应当理解，优选实施例仅为了说明本发明，而不是为了限制本发明的保护范围。
为了更详细的理解本发明的技术方案，先来分析几种传统结构比较器的工作原理和优缺点。
图1示出了一种高速低失调动态比较器结构原理图(简称结构[1])，当控制信号clk1为低电平时，clk2作为clk1的延迟信号也为低电平，NMOS管M7/M8/M15处于关断状态，PMOS管M11/M14导通，通过反相器I1/I2，比较器输出信号Dp和Dn为低电平，比较器处于复位状态；当clk1/clk2变为高电平后，NMOS管M7/M8/M15导通，由NMOS管M9/M10和PMOS管M12/M13构成的锁存器迅速将Tip和Tin的电压差放大，并进入锁存状态。结构[1]的优点是采用了反相器输入结构，和普通的NMOS输入结构相比，失调和噪声较小。但是，缺点在于，输入级反相器的输出端Tip和Tin连接在锁存结构M9/M10的源极，所以，在锁存结构建立正反馈的初期，只有M9和M10在工作，M12和M13没有工作，这种锁存原理并不能最大程度发挥锁存结构的优点，使得比较器速度较慢；同时，由于输入级采用了反相器输入结构，使得这种结构在锁存状态下，输入级仍然有静态电流，所以存在静态功耗。
图2示出了一种高速低噪声动态比较器结构原理图(简称结构[2])，当控制信号clk1为低电平时，NMOS管M3关断，NMOS管M10导通，PMOS管M6/M9导通，通过反相器I1/I2，比较器输出信号Dp和Dn为低电平，比较器处于复位状态；当clk1变为高电平后，M10关断，M3导通，由NMOS管M4/M5和PMOS管M7/M8构成的锁存器迅速将Bip和Bin的电压差放大，并进入锁存状态。需要注意的是，图2中输入级的输出端Bip和Bin分别与M4和M5的漏极相连， 所以，在锁存结构建立正反馈的初期，M4/M5和M7/M8会同时工作，这种锁存原理最大程度发挥了锁存结构的优点，使得比较器能够快速的进入锁存状态。但是，图2所示比较器的缺点也是明显的，由于在复位状态M10、M6和M9同时导通，导致这种结构存在一个很大的静态功耗。
图3示出了一种低功耗动态比较器结构原理图(简称结构[3])，当控制信号clk1为低电平时，clk2作为clk1的延迟信号也为低电平，NMOS管M3/M4/M11都关断，PMOS管M7/M10导通，通过反相器I1/I2，比较器输出信号Dp和Dn为低电平，比较器处于复位状态。当clk1变为高电平后，clk2会保持一段时间的低电平，此时M11导通，M3/M4保持关断，Aip和Ain出现电压差，输入管M1/M2处于饱和状态，有助于噪声的抑制；随后，clk2也变为高电平，由NMOS管M5/M6和PMOS管M8/M9构成的锁存器迅速将Aip和Ain的电压差放大，并进入锁存状态。图3所示结构的优点是等效输入噪声较小，在复位和锁存状态都没有静态功耗，但缺点和图1所示结构相似，比较器速度较低。
本发明提出的高速低功耗动态比较器结构原理图如图4所示，
该高速低功耗动态比较器，包括第一NMOS管P1、第二NMOS管P2、第六NMOS管P10、延迟单元B1、第一反向器I1、第二反向器I2、同或门XNOR、与门AND和锁存器，所述锁存器包括第一控制端、第二控制端、第三控制端、第一输出端(输出第一输出信号)、第二输出端(输出第二输出信号)和电源端；所述第一NMOS管P1的栅极接第一输入信号(Vinp)，第二NMOS管P 2的栅极接第二输入信号(Vinn)，所述第一NMOS管P1的源极、第二NMOS管P2的源极分别与第六NMOS管P10的漏极连接，第六NMOS管P10的源极接地；所述第一NMOS管P1的漏极分别与第二反向器I2的输入端、锁存器的第二输出端连接；所述第二NMOS管P2的漏极分别与第一反向器I1的输入端、锁存器的第一输出端连接；所述第一反向器I1的输出端与同或门XNOR的其中一个输入端连接，所述第二反向器I2的输出端与同或门的另一个输入端连接，所述同或门的输出端与与门的其中一个输入端连接，延迟单元B1的输入端与与门的另一个输入端连接，与门的输出端与第六NMOS管P10的栅极连接；所述延迟单元B1的输出端与第三控制端连接，所述延迟单元的输入端分别与第一控制端、第二控制端连接，所述电源端接Vdd。
所述锁存器包括第三NMOS管P3、第四NMOS管P4、第五NMOS管P5、第一PMOS管P6、第二PMOS管P7、第三PMOS管P8和第四PMOS管P9，所述第一NMOS管P1的漏极分别与第四NMOS管的漏极P4、第一PMOS管的漏极P6、第二PMOS管的漏极P7、第五NMOS管P5的栅极、第三PMOS管P8的栅极连接，所述第二NMOS管P2的漏极分别与第五NMOS管P5的漏极、第三PMOS管P8的漏极、第四PMOS管P9的漏极、第四NMOS管P4的栅极、第二PMOS管P7的栅极连接，所述第一PMOS管P6的源极、第二PMOS管P7的源极、第三PMOS管P8的源极、第四PMOS管P9的源极分别与Vdd连接；所述第一PMOS管P6的栅极、第四PMOS管P9栅极分别与延迟单元B1的输入端连接，延迟单元B1的输出端与第三NMOS管P3的栅极连接，第三NMOS管P3的漏极分别与第四NMOS管P4的源极、第五NMOS管P5的源极连接，第三NMOS管P3的源极接地。
在本实施例中，第一PMOS管和第四PMOS管为上拉PMOS管，第三NMOS管和第六NMOS管为下拉NMOS管
在本实施例中，锁存器的第一输出信号经过第一反相器I1产生输出信号Dp，锁存器的第二输出信号经过第二反向器I2产生输出信号和Dn，Dp和Dn通过同或门XNOR产生输出信号，这个输出信号和控制信号clk1作为与门AND的输入信号，与门AND的输出信号控制P10的栅极，clk1通过延迟单元B1产生其延迟信号clk2。
图4所示比较器有两个工作状态，一个是复位状态，一个是锁存状态。当比较器处于复位状态时，控制信号clk1和clk2为低电平，NMOS管P3和P10都关断，PMOS管P6、P9导通，将第一NMOS管P1产生的信号Dip和第二NMOS管P2产生的信号Din上拉到电源电压Vdd，通过反相器I1、I2，比较器输出信号Dp和Dn为低电平；当比较器进入锁存状态时，控制信号clk1变为高电平，clk2作为clk1的延迟信号，暂时保持为低电平，此时，P10导通，P3仍然关闭，Dip和Din开始出现电压差，P1、P2处于饱和状态，有助于抑制比较器等效输入噪声，经过一定延迟后，控制信号clk2也变为高电平，Dip之间Din的电压差使得P6、P7和P8、P9构成的锁存器结构迅速进入锁存状态，完成比较，从而达到高速工作的目的。此时，比较器输出信号Dp和Dn一个为高电平，另一个 为低电平，它们通过同或门XNOR关闭P10，使得比较器在复位和锁存状态下，都没有静态功耗，从而达到低功耗的目的，通过上述分析，这种结构同时达到了高速并且低功耗的目的。
另一方面，随着电源电压的降低，本发明提出的比较器结构，相对于上述传统结构而言，其高速的优势更加明显。原因在于，本发明结构相对于图2和图3所示结构，节省了一个锁存器结构中NMOS管的源漏电压差VDS，使得在低电源电压应用场合，本发明提出的结构更具速度优势。
为了进一步验证本发明的上述优点，在65nmCMOS工艺下，对上述各种结构进行了仔细的设计，对于上述四种结构采用相同的输入/输出管尺寸，锁存器结构也采用相同的尺寸，负载电容都取15fF。
时钟频率为1.8GHz，电源电压为1.2V，共模电压取0.6V，当|Dp-Dn|＝0.6V时，认为比较器完成比较。上述四种结构比较器的比较时间随输入差分信号ΔVin变化而变化的对比曲线如图5所示。
时钟频率为1.8GHz，电源电压为1.2V，当|Dp-Dn|＝0.6V时，认为比较器完成比较。上述四种结构比较器的功耗随共模电压Vcm变化而变化的对比曲线如图6所示。
时钟频率为0.4GHz，输入差分电压ΔVin为50mV，当|Dp-Dn|＝0.5Vdd时，认为比较器完成比较。上述四种结构比较器的比较时间随电源电压Vdd变化而变化的对比曲线如图7所示。
比较器其他几种指标的仿真结果对比如下表所示，从表中可以看出，本发明和传统的几种结构相比，其他几种指标处于中等水平。
Figure PCTCN2016089044-appb-000001
表中【1】【2】【3】分别代表图1、图2、图3，proposed为本发明。
从上述仿真结果可以看出，本发明所提出的高速低功耗比较器结构和传统的几种结构相比，速度至少提高30％，功耗至少降低15％。
以上所述仅为本发明的优选实施例，并不用于限制本发明，显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (2)

  1. 一种高速低功耗动态比较器，其特征在于：包括第一NMOS管(P1)、第二NMOS管(P2)、第六NMOS管(P10)、延迟单元(B1)、第一反向器(I1)、第二反向器(I2)、同或门(XNOR)、与门(AND)和锁存器，所述锁存器包括第一控制端、第二控制端、第三控制端、第一输出端、第二输出端和电源端；所述第一NMOS管(P1)的栅极接第一输入信号，第二NMOS管(P2)的栅极接第二输入信号，所述第一NMOS管(P1)的源极、第二NMOS管(P2)的源极分别与第六NMOS管(P10)的漏极连接，第六NMOS管(P10)的源极接地；所述第一NMOS管(P1)的漏极分别与第二反向器(I2)的输入端、锁存器的第二输出端连接；所述第二NMOS管(P2)的漏极分别与第一反向器(I1)的输入端、锁存器的第一输出端连接；所述第一反向器(I1)的输出端与同或门(XNOR)的其中一个输入端连接，所述第二反向器(I2)的输出端与同或门的另一个输入端连接，所述同或门的输出端与与门的其中一个输入端连接，延迟单元(B1)的输入端与与门的另一个输入端连接，与门的输出端与第六NMOS管(P10)的栅极连接；所述延迟单元(B1)的输出端与第三控制端连接，所述延迟单元的输入端分别与第一控制端、第二控制端连接，所述电源端接Vdd。
  2. 根据权利要求1所述的高速低功耗动态比较器，其特征在于：所述锁存器包括第三NMOS管(P3)、第四NMOS管(P4)、第五NMOS管(P5)、第一PMOS管(P6)、第二PMOS管(P7)、第三PMOS管(P8)和第四PMOS管(P9)，所述第一NMOS管(P1)的漏极分别与第四NMOS管的漏极(P4)、第一PMOS管的漏极(P6)、第二PMOS管的漏极(P7)、第五NMOS管(P5)的栅极、第三PMOS管(P8)的栅极连接，所述第二NMOS管(P2)的漏极分别与第五NMOS管(P5)的漏极、第三PMOS管(P8)的漏极、第四PMOS管(P9)的漏极、第四NMOS管(P4)的栅极、第二PMOS管(P7)的栅极连接，所述第一PMOS管(P6)的源极、第二PMOS管(P7)的源极、第三PMOS管(P8)的源极、第四PMOS管(P9)的源极分别与Vdd连接；所述第一PMOS管(P6)的栅极、第四PMOS管(P9)栅极分别与延迟单元(B1)的输入端连接，延迟单元(B1)的输出端与第三NMOS管(P3)的栅极连接，第三NMOS管(P3)的漏极分别与第四NMOS管(P4)的源极、第五NMOS管(P5)的源极连接， 第三NMOS管(P3)的源极接地。
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