WO2017045421A1 - 一种芯片封装方法 - Google Patents

一种芯片封装方法 Download PDF

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Publication number
WO2017045421A1
WO2017045421A1 PCT/CN2016/082778 CN2016082778W WO2017045421A1 WO 2017045421 A1 WO2017045421 A1 WO 2017045421A1 CN 2016082778 W CN2016082778 W CN 2016082778W WO 2017045421 A1 WO2017045421 A1 WO 2017045421A1
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Prior art keywords
layer
chip
plastic sealing
metal
sealing layer
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PCT/CN2016/082778
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English (en)
French (fr)
Inventor
林正忠
汤红
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中芯长电半导体（江阴）有限公司
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Publication of WO2017045421A1 publication Critical patent/WO2017045421A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Definitions

  • the invention belongs to the field of semiconductor packaging and relates to a chip packaging method.
  • Fan-out wafer level packaging is an embedded package for wafer level processing. It is also one of the main advanced packages with a large number of I/Os and good integration flexibility. Fan-out wafer-level packaging technology uses wafer-level thin-film technology to eliminate traditional package substrates by redistributing Layers (RDL) to connect the chip to external terminals.
  • RDL redistributing Layers
  • fan-out wafer-level packages the chip is surrounded by a suitable material that extends the footprint of the package beyond the chip.
  • Test-qualified chips are embedded in artificial plastic wafers (reconstituted wafers) using wafer-level molding techniques.
  • the interconnect is then fanned out to the surrounding area by wafer level lithography and patterning using a front isolation and metallization process. Solder balls are again applied to the wafer and tested in parallel.
  • the reconstituted wafer is then cut into individual units, packaged and shipped.
  • the fan-out WLP supports an adaptive fan-out area with no restrictions on solder ball pitch.
  • the general process of a fan-out wafer level package consists of the following steps: first cutting a single microchip from the wafer and attaching the chip face down to the adhesive layer of the carrier using standard pick and place equipment; then forming a plastic layer The chip is embedded in the plastic sealing layer; after the plastic sealing layer is cured, the carrier and the adhesive layer are removed, and then the redistribution wiring layer process and the ball reflow process are performed, and finally the cutting and testing are performed.
  • the traditional fan-out wafer level packaging technology is complicated in process.
  • the adhesive layer is peeled off to expose the front side of the chip, and a passivation layer is formed on the front side of the chip, and then a redistribution wiring layer is formed based on the passivation layer. .
  • the passivation layer increases the thickness of the device.
  • the function of the plastic sealing layer is only to fix the chip.
  • the molding material tends to be deformed during the subsequent redistribution of the wiring layer process and the ball reflow process. Problems such as bending, which greatly affect the performance of the packaged product.
  • an object of the present invention is to provide a chip packaging method for solving the problems of complicated chip packaging process, low production efficiency, and thick device thickness in the prior art.
  • the present invention provides a chip packaging method including the following steps:
  • Pasting at least one chip on the adhesive layer, wherein the chip faces upward;
  • the redistributing lead layer includes a through-the plastic sealing layer and electrically connected to the chip
  • the corresponding conductive pillars are extracted, and the metal wires distributed on the surface of the plastic sealing layer and connected to the conductive pillars.
  • the plastic sealing layer is printed first, and then the redistribution wiring layer is printed; wherein the plastic sealing layer has a through hole for accommodating the conductive pillar after printing.
  • the redistribution lead layer is printed using a laser engineered net forming technique.
  • the conductive pillars are printed separately from the metal lines, and the method includes the following steps:
  • the metal powder is sprayed on the surface of the plastic sealing layer by a nozzle according to a preset route, and the metal powder is simultaneously melted by the laser light emitted from the laser emitting head; the molten metal powder is formed to form the metal wiring.
  • the conductive pillar is printed synchronously with the metal line, and the method includes the following steps:
  • the conductive pillars are formed, and the metal powder melted on the surface of the plastic seal layer is formed to form the metal wiring.
  • the plastic encapsulation layer and the redistribution wiring layer are simultaneously printed.
  • the composite layer composed of the plastic sealing layer and the redistribution wiring layer is decomposed into at least two layers and printed layer by layer from bottom to top; wherein, for the decomposition layer containing only the plastic sealing layer material, the first nozzle is used
  • the plasticized layer material is sprayed according to a preset route; and the decomposed layer containing the plastic sealing layer material and the metal material is obtained by alternately using the first nozzle spray molding layer material and the second nozzle spraying metal material according to a predetermined route.
  • a surface of the plastic sealing layer is formed with a groove corresponding to the metal line, and the metal circuit is embedded in the groove.
  • the carrier and the adhesive layer are further removed.
  • the material of the plastic sealing layer comprises epoxy resin, rubber or polyimide.
  • the carrier comprises a metal, wafer, glass or organic material.
  • the chip packaging method of the present invention has the following advantageous effects: 1)
  • the present invention prints a cover on the surface of the carrier by using a 3D printing method by attaching the chip face up on the adhesive layer of the carrier. a plastic encapsulation layer of the chip and a redistribution wiring layer electrically connected to the chip. Since the redistribution wiring layer is formed when the carrier is not peeled off, the deformation probability of the plastic packaging material caused by the redistribution wiring layer process and the ball implantation process is effectively reduced.
  • the redistribution wiring layer is directly printed in the plastic sealing layer, thereby eliminating the deposition step of the passivation layer and the polishing and thinning steps of the plastic sealing layer, which not only reduces the flat front surface of the chip. The risk of damage during the process also reduces production costs.
  • the chip packaging method of the present invention replaces the photolithography and etching steps of the via holes by using the 3D printing method, and replaces the photolithography, etching, and electroplating deposition process steps of the metal lines, thereby greatly reducing the process complexity.
  • the chip packaging method of the present invention after removing the carrier and the plastic sealing layer, there is no excess plastic sealing layer on the back surface of the chip, so that the final package body is thinner and lighter, and the requirements for miniaturization of the device are better met.
  • the metal line of the redistribution lead layer produced by the invention can protrude from the surface of the plastic sealing layer or can be embedded in the groove of the surface of the plastic sealing layer, and the reliability is higher.
  • FIG. 1 shows a process flow diagram of a chip packaging method of the present invention.
  • FIGS 2 to 13 are schematic diagrams showing the steps of the steps of the chip packaging method of the present invention.
  • the present invention provides a chip packaging method. Referring to FIG. 1, a process flow diagram of the method is shown, including the following steps:
  • S3 printing a plastic sealing layer covering the chip and a redistribution wiring layer electrically connected to the chip on the surface of the carrier by using a 3D printing method; the redistributing wiring layer includes the plastic sealing layer and the The chip electrically leads to a corresponding conductive post, and a metal line distributed on the surface of the plastic seal layer and connected to the conductive post.
  • step S1 is performed: a carrier 1 is provided, and an adhesive layer 2 is formed on the surface of the carrier 1.
  • the carrier 1 functions to provide a rigid structure or matrix for the adhesive layer 2 and the subsequent plastic seal layer 4.
  • the carrier 1 may be selected from, but not limited to, metal, wafer, glass or organic materials and the like.
  • the carrier 1 is made of glass.
  • the carrier 1 can be in the form of a wafer or other shape.
  • the function of the adhesive layer 2 is to fix the chip to ensure that the chip does not move in a subsequent process, and the adhesive layer 2 also has a strong bonding force with the carrier 1.
  • the adhesive force of the adhesive layer 2 to the carrier 1 needs to be greater than the bonding force with the chip, and the adhesive layer 2 is used in a subsequent process for the separation layer between the chip and the carrier 1.
  • the adhesive layer 3 is selected from the surface of the carrier 1 by a spin coating process using a UV adhesive. In other embodiments, the adhesive layer 3 may also be selected from other suitable bonding materials, and the scope of the present invention should not be unduly limited.
  • step S2 is performed: at least one chip is pasted on the adhesive layer, wherein the chip faces toward on.
  • the front side of the chip refers to the side on which the chip 3 is formed with the device and the electrode is led out.
  • the chips 3 are arranged vertically and at a distance to provide a fan-out space and a cutting space for the subsequent redistribution of the lead layer.
  • step S3 is performed: a plastic sealing layer 4 covering the chip 3 and a redistribution wiring layer 5 electrically connected to the chip 3 are printed on the surface of the carrier 1 by using a 3D printing method;
  • the distribution lead layer 5 includes a conductive post 51 penetrating the plastic seal layer 4 and electrically corresponding to the chip 3, and a metal trace 52 distributed on the surface of the mold seal layer 4 and connected to the conductive post 51.
  • 3D printing is a kind of rapid prototyping technology. It is a technique for constructing objects by layer-by-layer printing based on digital model files and using adhesive materials such as powdered metal or plastic. 3D printing works in the same way as ordinary printing.
  • the printer is equipped with "printing materials” such as liquid or powder. After connecting with the computer, the "printing materials” are superimposed by computer control, and finally the blueprint on the computer is turned into a real object. .
  • the plastic encapsulation layer 4 is first printed out, and then the redistribution wiring layer 5 is printed. As shown in FIG. 5, after the plastic sealing layer 4 is printed, it has a through hole 6 for accommodating the conductive post 51.
  • the material of the plastic sealing layer 4 includes, but is not limited to, an epoxy resin, a rubber or a polyimide.
  • the plastic sealing material 4 is made of a rubber material.
  • the molten sealing layer material is sprayed out by a nozzle according to a predetermined route to form the plastic sealing layer 4.
  • the plastic sealing layer material may also be sprayed out in a powder state, and the powdered plastic sealing layer material is bonded by glue (for example, acrylic UV shadowless glue), wherein the glue is also sprayed by the nozzle.
  • glue for example, acrylic UV shadowless glue
  • the redistribution lead layer 5 is printed using a laser-engineered net forming technique.
  • Laser Engineered Net Shaping is a new rapid prototyping technology that combines selective laser sintering (SLS) technology with laser cladding (Laser Cladding) technology to quickly achieve density and Metal parts with high strength.
  • the laser-engineered net forming system generally consists of four parts: a computer, a high-power laser, a metal powder nozzle, and an X-Y table.
  • the computer is used to establish a CAD solid model of the metal circuit in the preliminary stage of forming the metal line, and convert the CAD solid model into an STL file, and slice the STL file of the part to generate a series of thin layers and a certain thickness.
  • the computer is also used to perform the same command on the various components of the system (including laser shutters, correction optical switches, protective gas valves, nozzle motors, X-Y table motors, etc.) during the forming process. Ordered control underneath, complete the processing of metal lines.
  • the laser In a laser-engineered net forming system, the laser directly melts the metal powder to achieve cladding, thus requiring the use of a high-power laser.
  • the laser may employ a Nd:YAG high power solid pulse laser or a carbon dioxide laser.
  • the metal powder nozzle is used to spray metal powder by metal powder line by point, component metal line.
  • the X-Y workbench is used to realize the plane scanning motion. The specific method is to fix the laser head on the cantilever of the X-Y table, so that the laser head can move along with the table to realize the point-by-point laser cladding until the point is obtained.
  • a cladding section is to fix the laser head on the cantilever of the X-Y table
  • the material of the redistribution lead layer 5 includes, but is not limited to, Au, Ag, Cu or a Cu alloy.
  • the conductive post 51 and the metal line 52 are printed separately, including the following steps:
  • the nozzle is used to spray metal powder in the through hole 6, and synchronously through the laser emitted by the laser emitting head to melt the metal powder; the molten metal powder is formed to form the conductive column 51;
  • the metal powder is sprayed on the surface of the plastic sealing layer by a nozzle according to a preset route, and the metal powder is simultaneously melted by the laser light emitted from the laser emitting head; the molten metal powder is formed to form the metal wiring 52. .
  • step 1) and step 2) is interchangeable.
  • the plastic sealing layer 4 is printed first, and then the redistribution wiring layer 5 is printed.
  • Printing the redistribution lead layer 5 is also divided into two steps, that is, the conductive pillar 51 and the metal wiring 52 are printed separately.
  • the redistribution wiring layer is directly printed in the plastic sealing layer, thereby eliminating the deposition step of the passivation layer and the grinding and thinning steps of the plastic sealing layer, thereby not only reducing the front surface of the chip during the planarization process.
  • the risk of damage also reduces production costs.
  • the chip packaging method of the invention replaces the photolithography and etching steps of the via holes by using the 3D printing method, and replaces the photolithography, etching and electroplating deposition process steps of the metal lines, thereby greatly reducing the process complexity.
  • This embodiment uses substantially the same technical solution as the first embodiment, except that in the first embodiment, the conductive pillar 51 and the metal trace 52 of the redistribution lead layer 5 are printed separately, but in this embodiment, The conductive post 51 and the metal line 52 are printed simultaneously.
  • synchronously printing the conductive post 51 and the metal line 52 includes the following steps:
  • Metal powder is sprayed on the surface of the plastic sealing layer 4 and the through hole 6 according to a preset route, and the metal powder is simultaneously melted by laser light emitted from the laser emitting head; wherein the metal melted in the through hole 6 After the powder is formed, the conductive post 51 is formed, and the metal powder melted on the surface of the plastic seal layer is formed to form the metal line 52.
  • the first embodiment or the second embodiment uses substantially the same technical solution, except that in the first embodiment, the plastic sealing layer 4 and the redistribution wiring layer 5 are separately printed, but in this embodiment, The plastic seal layer 4 and the redistribution lead layer 5 are printed simultaneously.
  • the composite layer composed of the plastic sealing layer 4 and the redistribution wiring layer 5 is decomposed into at least two layers and printed layer by layer from bottom to top; wherein, for the decomposition layer containing only the plastic sealing layer material, the first layer is adopted.
  • the nozzle is obtained by spraying the plastic sealing layer material according to a preset route; and for the decomposition layer including the plastic sealing layer material and the metal material, the first nozzle spraying plastic sealing layer material and the second nozzle spraying metal material are alternately adopted according to a preset route.
  • the composite layer composed of the plastic sealing layer 4 and the redistribution wiring layer 5 is decomposed into three layers, and the decomposition layer I, the decomposition layer II and the decomposition layer III are respectively from bottom to top.
  • the decomposition layer I only contains the plastic sealing layer material
  • the decomposition layer II contains the plastic sealing layer material and the metal material
  • the decomposition layer III only contains the metal material.
  • the printing of each layer is completed by controlling parameters such as the movement path of the head and the laser head, and the amount of ejection, and a composite layer composed of the plastic sealing layer 4 and the redistribution wiring layer 5 is obtained.
  • each decomposition layer is further decomposed into a plurality of thinner thin layers, which are obtained by repeatedly printing a thin layer.
  • This embodiment is basically the same technical solution as the first, second or third embodiment, except that in the first, second and third embodiments, the metal line of the redistribution lead layer protrudes from the surface of the plastic sealing layer, and in this embodiment, The metal circuit of the redistributed lead layer is embedded in the groove on the surface of the plastic sealing layer, and the reliability is higher.
  • the surface of the plastic seal layer 4 is formed with a groove corresponding to the metal line 52, and the metal line 52 is embedded in the groove.
  • plastic sealing layer 4 and the redistribution wiring layer 5 can be separately printed.
  • specific steps refer to the first embodiment or the second embodiment, and details are not described herein again.
  • the plastic sealing layer 4 and the redistribution wiring layer 5 can also be printed synchronously, and the composite layer composed of the plastic sealing layer 4 and the redistribution wiring layer 5 can be decomposed into the same as shown in FIG.
  • the three layers, from bottom to top, are the decomposition layer I, the decomposition layer II and the decomposition layer III, wherein the decomposition layer I only contains the plastic sealing layer material, and the decomposition layer II and the decomposition layer III both contain the plastic sealing layer material and the metal material.
  • the printing of each layer is completed by controlling parameters such as the movement path of the head and the laser head, and the amount of ejection, and a composite layer composed of the plastic sealing layer 4 and the redistribution wiring layer 5 is obtained.
  • a lower under bump metal layer 7 is further formed on the surface of the redistribution wiring layer 5, and a metal layer is formed under the bump. 7 The surface forms a solder ball bump 9.
  • a dielectric layer (not shown) may be formed on the surface of the redistribution wiring layer 5 in advance, and the under bump metal layer 7 is obtained by optical masking, etching, or the like in the dielectric layer; bumps The lower metal layer 7 is embedded in the dielectric layer and connected to the rewiring lead layer 5; the top surface of the under bump metal layer may be flush with the top surface of the dielectric layer or may protrude from the surface of the dielectric layer.
  • the solder bumps 8 can be fabricated by a ball reflow process.
  • the present invention can effectively reduce the deformation probability of the plastic packaging material caused by the redistribution wiring layer process and the ball implantation process, and improve the chip packaging performance.
  • the carrier 1 and the adhesive layer 2 can be further removed.
  • the adhesive layer 2 (UV adhesive) is reduced in viscosity by an exposure method to achieve separation from the plastic seal layer 4 and the chip 3 to finally remove the carrier 1 and the adhesive layer 2 .
  • the adhesive layer 2 is made of other materials, the carrier and the adhesive layer 2 may be peeled off by other corresponding methods, and the scope of the present invention should not be unduly limited.
  • the chip packaging method of the present invention has the following beneficial effects: 1)
  • the present invention prints a cover on the surface of the carrier by using a 3D printing method by attaching the chip face up on the adhesive layer of the carrier. a plastic encapsulation layer of the chip and a redistribution wiring layer electrically connected to the chip. Since the redistribution wiring layer is formed when the carrier is not peeled off, the deformation probability of the plastic packaging material caused by the redistribution wiring layer process and the ball implantation process is effectively reduced.
  • the redistribution wiring layer is directly printed in the plastic sealing layer, thereby eliminating the deposition step of the passivation layer and the polishing and thinning steps of the plastic sealing layer, which not only reduces the flat front surface of the chip. The risk of damage during the process also reduces production costs.
  • the chip packaging method of the present invention replaces the photolithography and etching steps of the via holes by using the 3D printing method, and replaces the photolithography, etching, and electroplating deposition process steps of the metal lines, thereby greatly reducing the process complexity.
  • the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

Abstract

提供一种芯片封装方法，包括以下步骤：提供一载体（1），在所述载体（1）表面形成粘胶层（2）；在所述粘胶层（2）上粘贴至少一个芯片（3），其中，芯片（3）正面朝上；采用3D打印法在所述载体（1）表面打印出覆盖所述芯片的塑封层（4）及与所述芯片（3）电性连接的再分布引线层（5）；所述再分布引线层（5）包括贯穿所述塑封层（4）并与所述芯片（3）电性引出相对应的导电柱（51），以及分布于所述塑封层（4）表面并与所述导电柱（51）相连接的金属线路（52）。

Description

一种芯片封装方法 技术领域
本发明属于半导体封装领域，涉及一种芯片封装方法。
背景技术
扇出型晶圆级封装(Fan-out wafer level packaging，FOWLP)是一种晶圆级加工的嵌入式封装，也是I/O数较多、集成灵活性好的主要先进封装之一。扇出型晶圆级封装技术采用晶圆级薄膜技术，通过再分布引线层(Redistribution Layers，RDL)连接芯片和外部端子，消除了传统封装基板。
扇出型晶圆级封装中，芯片被合适的材料围绕，这些材料将封装所占面积扩展到芯片以外。测试合格芯片用晶圆级模塑技术嵌入人造塑料晶圆(重组晶圆)内。然后用前道绝缘和金属化工艺，以晶圆级光刻和制图方法将互连扇出到周围区域。再次在晶圆上应用焊球并进行并行测试。然后把重组晶圆切割为独立单元，包装和发运。用扇入方法时，互连数和它们的节距必须与芯片尺寸适应。相反，扇出WLP支持适应性强的扇出面积，对焊球节距没有什么限制。
扇出型晶圆级封装的一般过程包括如下几个步骤：首先从晶圆切下单个微芯片，并采用标准拾放设备将芯片正面朝下粘贴到载体的粘胶层上；然后形成塑封层，将芯片嵌入塑封层内；在塑封层固化后，去除载体及粘胶层，然后进行再分布引线层工艺及植球回流工艺，最后进行切割和测试。
传统的扇出型晶圆级封装技术工艺复杂，其在再分布引线层工艺之前，剥离粘胶层以露出芯片正面，并在芯片正面形成钝化层，然后基于钝化层制作再分布引线层。钝化层增加了器件厚度，同时，塑封层的作用仅仅是用来固定芯片，当载体被去除后，在之后的再分布引线层工艺以及植球回流工艺的过程中，塑封材料往往会出现变形弯曲等问题，从而大大影响封装产品的性能。
现有的一种解决方案是，将半导体芯片正面朝上地装配于塑封材料中，由于所述塑封材料由刚性载体作为支撑，这种方法可以大大降低后续的再分布引线层工艺以及植球工艺所造成的塑封材料的变形概率。然而，这种方法需要增加如研磨、减薄塑封层等工艺步骤以露出芯片正面，从而会造成产品成本的提高，且不够环保，并且这种方法同样需要沉积钝化层并基于钝化层制作再分布引线层。
因此，如何提供一种芯片封装方法，以降低工艺复杂性、提高生产效率并减小器件厚度， 成为本领域技术人员亟待解决的一个重要技术问题。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种芯片封装方法，用于解决现有技术中芯片封装工艺复杂、生产效率不高、器件厚度较厚的问题。
为实现上述目的及其他相关目的，本发明提供一种芯片封装方法，包括以下步骤：
提供一载体，在所述载体表面形成粘胶层；
在所述粘胶层上粘贴至少一个芯片，其中，芯片正面朝上；
采用3D打印法在所述载体表面打印出覆盖所述芯片的塑封层及与所述芯片电性连接的再分布引线层；所述再分布引线层包括贯穿所述塑封层并与所述芯片电性引出相对应的导电柱，以及分布于所述塑封层表面并与所述导电柱相连接的金属线路。
可选地，首先打印出所述塑封层，然后打印出所述再分布引线层；其中，所述塑封层打印完毕后，其中具有容纳所述导电柱的通孔。
可选地，采用激光工程化净成形技术打印所述再分布引线层。
可选地，所述导电柱与所述金属线路分别打印，包括如下步骤：
采用喷头在所述通孔内喷射金属粉末，并同步通过激光器发射头发射出的激光将金属粉末熔化；熔化的金属粉末成形后构成所述导电柱；
采用喷头按照预设路线在所述塑封层表面喷射金属粉末，并同步通过激光器发射头发射出的激光将金属粉末熔化；熔化的金属粉末成形后构成所述金属线路。
可选地，所述导电柱与所述金属线路同步打印，包括如下步骤：
采用喷头按照预设路线在所述塑封层表面及所述通孔内喷射金属粉末，并同步通过激光器发射头发射出的激光将金属粉末熔化；其中，位于所述通孔内熔化的金属粉末成形后构成所述导电柱，位于所述塑封层表面熔化的金属粉末成形后构成所述金属线路。
可选地，同步打印出所述塑封层及所述再分布引线层。
可选地，将由所述塑封层及所述再分布引线层组成的复合层分解为至少两层并自下而上逐层打印；其中，对于仅包含塑封层材料的分解层，采用第一喷头按照预设路线喷射塑封层材料得到；对于同时包含塑封层材料及金属材料的分解层，按照预设路线交替采用第一喷头喷射塑封层材料及第二喷头喷射金属材料得到。
可选地，所述塑封层表面形成有与所述金属线路相对应的凹槽，所述金属线路嵌于所述凹槽内。
可选地，进一步在所述再分布引线层表面形成凸点下金属层，并在所述凸点下金属层表 面形成焊球凸点。
可选地，进一步去除所述载体及所述粘胶层。
可选地，所述塑封层的材料包括环氧树脂、橡胶或聚酰亚胺。
可选地，所述载体包括金属、晶圆、玻璃或有机材料。
如上所述，本发明的芯片封装方法，具有以下有益效果：1)本发明通过将芯片正面朝上粘贴于载体的粘胶层上，并采用3D打印法在所述载体表面打印出覆盖所述芯片的塑封层及与所述芯片电性连接的再分布引线层。由于再分布引线层是在载体未剥离时形成，有效降低了再分布引线层工艺以及植球工艺所造成的塑封材料的变形概率。2)本发明的芯片封装方法中，再分布引线层是直接打印在塑封层中，从而省掉了钝化层的沉积步骤以及塑封层的研磨、减薄步骤，不仅降低了芯片正面在平坦化过程中损坏的风险，还降低了生产成本。3)本发明的芯片封装方法采用3D打印法代替了通孔的光刻、刻蚀步骤，并代替了金属线路的光刻、刻蚀以及电镀沉积等工艺步骤，大大降低了工艺复杂性。4)本发明芯片封装方法在去除载体及塑封层后，芯片背面没有多余的塑封层，使得最终的封装体更为轻薄，更好的满足器件小型化的要求。5)本发明制作的再分布引线层的金属线路既可以突出于塑封层表面，也可以嵌于塑封层表面的凹槽内，可靠性更高。
附图说明
图1显示为本发明的芯片封装方法的工艺流程图。
图2～图13显示为本发明的芯片封装方法各步骤所呈现的结构示意图。
元件标号说明
S1～S3                   步骤
1                        载体
2                        粘胶层
3                        芯片
4                        塑封层
5                        再分布引线层
51                       导电柱
52                       金属线路
6                        通孔
7                        凸点下金属层
8                        焊球凸点
I，II，III               分解层
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1至图13。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
实施例一
本发明提供一种芯片封装方法，请参阅图1，显示为该方法的工艺流程图，包括以下步骤：
S1：提供一载体，在所述载体圆片表面形成粘胶层；
S2：在所述粘胶层上粘贴至少一个芯片，其中，芯片正面朝上；
S3：采用3D打印法在所述载体表面打印出覆盖所述芯片的塑封层及与所述芯片电性连接的再分布引线层；所述再分布引线层包括贯穿所述塑封层并与所述芯片电性引出相对应的导电柱，以及分布于所述塑封层表面并与所述导电柱相连接的金属线路。
首先请参阅图2，执行步骤S1：提供一载体1，在所述载体1表面形成粘胶层2。
具体的，所述载体1的作用是为所述粘胶层2及后续的塑封层4提供刚性的结构或基体。所述载体1可选用但不限于金属、晶圆、玻璃或有机材料等。作为示例，所述载体1选用玻璃。所述载体1可以为圆片或其它形状。
所述粘胶层2的作用是固定芯片，以保证芯片在后续工艺中不会产生移动等情况，且所述粘胶层2与所述载体1也具有较强的结合力。一般来说，所述粘胶层2与载体1的结合力需要大于与芯片的结合力，所述粘胶层2在后续的工艺中用于芯片与载体1之间的分离层。作为示例，所述粘胶层3选用UV粘合胶，通过旋涂工艺形成于所述载体1表面。在其它实施例中，所述粘胶层3也可选用其它合适的粘合材料，此处不应过分限制本发明的保护范围。
然后请参阅图3，执行步骤S2：在所述粘胶层上粘贴至少一个芯片，其中，芯片正面朝 上。
此处芯片正面是指芯片3形成有器件以及电极引出的一面。各芯片3之间分立排列且间隔一定距离，以为后续再分布引线层的制作提供扇出空间及切割空间。
再请参阅图4，执行步骤S3：采用3D打印法在所述载体1表面打印出覆盖所述芯片3的塑封层4及与所述芯片3电性连接的再分布引线层5；所述再分布引线层5包括贯穿所述塑封层4并与所述芯片3电性引出相对应的导电柱51，以及分布于所述塑封层4表面并与所述导电柱51相连接的金属线路52。
3D打印法是快速成型技术的一种，它是一种以数字模型文件为基础，运用粉末状金属或塑料等可粘合材料，通过逐层打印的方式来构造物体的技术。3D打印与普通打印工作原理基本相同，打印机内装有液体或粉末等“打印材料”，与电脑连接后，通过电脑控制把“打印材料”一层层叠加起来，最终把计算机上的蓝图变成实物。
作为示例，首先打印出所述塑封层4，然后再打印出所述再分布引线层5。如图5所示，所述塑封层4打印完毕后，其中具有容纳所述导电柱51的通孔6。
具体的，所述塑封层4的材料包括但不限于环氧树脂、橡胶或聚酰亚胺等。作为示例，所述塑封层4的选用橡胶材料。采用喷头按照预设路线将熔融态的塑封层材料喷射出来形成所述塑封层4。在另一实施例中，也可以采用粉末态将塑封层材料喷出，并采用胶水(例如亚克力UV无影胶水)将粉末态的塑封层材料粘合，其中，胶水也采用喷头喷出。
具体的，采用激光工程化净成形技术打印所述再分布引线层5。激光工程化净成形技术(Laser Engineered Net Shaping，LENS)是一种新的快速成形技术，它将选择性激光烧结(SLS)技术和激光熔覆(Laser Cladding)技术相结合，快速获得致密度和强度均较高的金属零件。激光工程化净成形系统一般由四部分组成：计算机、高功率激光器、金属粉末喷头和X—Y工作台。其中，计算机用于在金属线路成形预备阶段建立金属线路的CAD实体模型，并将该CAD实体模型转换成STL文件，对零件的STL文件进行切片处理，生成一系列具有一定厚度的薄层及每一薄层的扫描轨迹；计算机还用于在成形加工阶段对系统中各部件(包括激光器光闸、校正光开关、保护气气阀、喷头电机以及X—Y工作台电机等等)进行同一指令下的有序控制，完成金属线路的加工过程。在激光工程化净成形系统中，激光直接熔化金属粉末，实现熔覆作用，因此要求采用高功率激光器。作为示例，所述激光器可采用Nd：YAG高功率固体脉冲激光器或二氧化碳激光器。金属粉末喷头用于将金属粉末逐点逐线喷射金属粉末，构件金属线路。X—Y工作台用于实现平面扫描运动，具体做法是将激光头固定在X—Y工作台的悬臂上，使激光头随工作台一起做平面运动，实现逐点逐线激光熔覆直至获得一个熔覆截面。
所述再分布引线层5的材料包括但不限于Au、Ag、Cu或者Cu合金。
作为示例，所述导电柱51与所述金属线路52分别打印，包括如下步骤：
1)如图6所示，采用喷头在所述通孔6内喷射金属粉末，并同步通过激光器发射头发射出的激光将金属粉末熔化；熔化的金属粉末成形后构成所述导电柱51；
2)如图7所示，采用喷头按照预设路线在所述塑封层表面喷射金属粉末，并同步通过激光器发射头发射出的激光将金属粉末熔化；熔化的金属粉末成形后构成所述金属线路52。
需要指出的是，所述步骤1)与步骤2)的顺序可互换。
本实施例中，首先采用打印出所述塑封层4，然后再打印出所述再分布引线层5。而打印所述再分布引线层5也分为两步，即所述导电柱51与所述金属线路52分别打印。
本发明的芯片封装方法中，再分布引线层是直接打印在塑封层中，从而省掉了钝化层的沉积步骤以及塑封层的研磨、减薄步骤，不仅降低了芯片正面在平坦化过程中损坏的风险，还降低了生产成本。本发明的芯片封装方法采用3D打印法代替了通孔的光刻、刻蚀步骤，并代替了金属线路的光刻、刻蚀以及电镀沉积等工艺步骤，大大降低了工艺复杂性。
实施例二
本实施例与实施例一采用基本相同的技术方案，不同之处在于，实施例一中，所述再分布引线层5的导电柱51与金属线路52是分别打印的，而本实施例中，所述导电柱51与所述金属线路52是同步打印的。
作为示例，同步打印所述导电柱51与所述金属线路52包括如下步骤：
采用喷头按照预设路线在所述塑封层4表面及所述通孔6内喷射金属粉末，并同步通过激光器发射头发射出的激光将金属粉末熔化；其中，位于所述通孔6内熔化的金属粉末成形后构成所述导电柱51，位于所述塑封层表面熔化的金属粉末成形后构成所述金属线路52。
实施例三
本实施例与实施例一或二采用基本相同的技术方案，不同之处在于，实施例一中，所述塑封层4与所述再分布引线层5是分别打印的，而本实施例中，所述塑封层4及所述再分布引线层5同步打印。
具体的，将由所述塑封层4及所述再分布引线层5组成的复合层分解为至少两层并自下而上逐层打印；其中，对于仅包含塑封层材料的分解层，采用第一喷头按照预设路线喷射塑封层材料得到；对于同时包含塑封层材料及金属材料的分解层，按照预设路线交替采用第一喷头喷射塑封层材料及第二喷头喷射金属材料得到。
作为示例，如图8所示，将由所述塑封层4及所述再分布引线层5组成的复合层分解为三层，自下而上分别为分解层I、分解层II及分解层III，其中，分解层I仅包含塑封层材料，分解层II同时包含塑封层材料及金属材料，分解层III仅包含金属材料。通过控制喷头及激光头的运动路径以及喷射量等参数，完成各层的打印，得到由所述塑封层4及所述再分布引线层5组成的复合层。当然，每一分解层也进一步分解为多个厚度更薄的薄层，通过多次重复打印薄层得到。
实施例四
本实施例与实施例一、二或三采用基本相同的技术方案，不同之处在于，实施例一、二及三中，再分布引线层的金属线路突出于塑封层表面，而本实施例中，再分布引线层的金属线路嵌于塑封层表面的凹槽内，可靠性更高。
如图9所示，所述塑封层4表面形成有与所述金属线路52相对应的凹槽，所述金属线路52嵌于所述凹槽内。
本实施例中，所述塑封层4与所述再分布引线层5可以分别打印，具体步骤可参见实施例一或实施例二，此处不再赘述。
本实施例中，所述塑封层4与所述再分布引线层5也可以同步打印，可以将由所述塑封层4及所述再分布引线层5组成的复合层分解为如图10所示的三层，自下而上分别为分解层I、分解层II及分解层III，其中，分解层I仅包含塑封层材料，分解层II及分解层III均同时包含塑封层材料及金属材料。通过控制喷头及激光头的运动路径以及喷射量等参数，完成各层的打印，得到由所述塑封层4及所述再分布引线层5组成的复合层。
实施例五
如图11所示，本实施例在实施例一、二、三或四的基础上，进一步在所述再分布引线层5表面形成凸点下金属层7，并在所述凸点下金属层7表面形成焊球凸点9。
具体的，可预先在所述再分布引线层5表面形成一介电层(未图示)，并在介电层中用光学掩膜、刻蚀等方法得到凸点下金属层7；凸点下金属层7嵌入介电层中，与再布线引线层5连接；凸点下金属层的顶面可以与介电层的顶面平齐，也可以突出于介电层的表面。所述焊球凸点8可采用植球回流工艺制得。
由于再分布引线层是在载体未剥离时形成，因此，本发明可以有效降低再分布引线层工艺以及植球工艺所造成的塑封材料的变形概率，提高芯片封装性能。
如图12及图13所示，本发明中，可进一步去除所述载体1及所述粘胶层2。
具体的，采用曝光方法使所述粘胶层2(UV粘合胶)降低黏性，以实现其与所述塑封层4及芯片3的分离，以最终去除所述载体1及粘胶层2。当然，当所述粘胶层2采用其它材料时，可采用其它相应的方法剥离所述载体及粘胶层2，此处不应过分限制本发明的保护范围。
本发明在去除载体及塑封层后，芯片背面没有多余的塑封层，使得最终的封装体更为轻薄，更好的满足器件小型化的要求。
综上所述，本发明的芯片封装方法，具有以下有益效果：1)本发明通过将芯片正面朝上粘贴于载体的粘胶层上，并采用3D打印法在所述载体表面打印出覆盖所述芯片的塑封层及与所述芯片电性连接的再分布引线层。由于再分布引线层是在载体未剥离时形成，有效降低了再分布引线层工艺以及植球工艺所造成的塑封材料的变形概率。2)本发明的芯片封装方法中，再分布引线层是直接打印在塑封层中，从而省掉了钝化层的沉积步骤以及塑封层的研磨、减薄步骤，不仅降低了芯片正面在平坦化过程中损坏的风险，还降低了生产成本。3)本发明的芯片封装方法采用3D打印法代替了通孔的光刻、刻蚀步骤，并代替了金属线路的光刻、刻蚀以及电镀沉积等工艺步骤，大大降低了工艺复杂性。4)本发明芯片封装方法在去除载体及塑封层后，芯片背面没有多余的塑封层，使得最终的封装体更为轻薄，更好的满足器件小型化的要求。5)本发明制作的再分布引线层的金属线路既可以突出于塑封层表面，也可以嵌于塑封层表面的凹槽内，可靠性更高。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (12)

  1. 一种芯片封装方法，其特征在于，包括以下步骤：
    提供一载体，在所述载体表面形成粘胶层；
    在所述粘胶层上粘贴至少一个芯片，其中，芯片正面朝上；
    采用3D打印法在所述载体表面打印出覆盖所述芯片的塑封层及与所述芯片电性连接的再分布引线层；所述再分布引线层包括贯穿所述塑封层并与所述芯片电性引出相对应的导电柱，以及分布于所述塑封层表面并与所述导电柱相连接的金属线路。
  2. 根据权利要求1所述的芯片封装方法，其特征在于：首先打印出所述塑封层，然后打印出所述再分布引线层；其中，所述塑封层打印完毕后，其中具有容纳所述导电柱的通孔。
  3. 根据权利要求2所述的芯片封装方法，其特征在于：采用激光工程化净成形技术打印所述再分布引线层。
  4. 根据权利要求3所述的芯片封装方法，其特征在于：所述导电柱与所述金属线路分别打印，包括如下步骤：
    采用喷头在所述通孔内喷射金属粉末，并同步通过激光器发射头发射出的激光将金属粉末熔化；熔化的金属粉末成形后构成所述导电柱；
    采用喷头按照预设路线在所述塑封层表面喷射金属粉末，并同步通过激光器发射头发射出的激光将金属粉末熔化；熔化的金属粉末成形后构成所述金属线路。
  5. 根据权利要求3所述的芯片封装方法，其特征在于：所述导电柱与所述金属线路同步打印，包括如下步骤：
    采用喷头按照预设路线在所述塑封层表面及所述通孔内喷射金属粉末，并同步通过激光器发射头发射出的激光将金属粉末熔化；其中，位于所述通孔内熔化的金属粉末成形后构成所述导电柱，位于所述塑封层表面熔化的金属粉末成形后构成所述金属线路。
  6. 根据权利要求1所述的芯片封装方法，其特征在于：同步打印出所述塑封层及所述再分布引线层。
  7. 根据权利要求6所述的芯片封装方法，其特征在于：将由所述塑封层及所述再分布引线层 组成的复合层分解为至少两层并自下而上逐层打印；其中，对于仅包含塑封层材料的分解层，采用第一喷头按照预设路线喷射塑封层材料得到；对于同时包含塑封层材料及金属材料的分解层，按照预设路线交替采用第一喷头喷射塑封层材料及第二喷头喷射金属材料得到。
  8. 根据权利要求1所述的芯片封装方法，其特征在于：所述塑封层表面形成有与所述金属线路相对应的凹槽，所述金属线路嵌于所述凹槽内。
  9. 根据权利要求1所述的芯片封装方法，其特征在于：进一步在所述再分布引线层表面形成凸点下金属层，并在所述凸点下金属层表面形成焊球凸点。
  10. 根据权利要求9所述的芯片封装方法，其特征在于：进一步去除所述载体及所述粘胶层。
  11. 根据权利要求1所述的芯片封装方法，其特征在于：所述塑封层的材料包括环氧树脂、橡胶或聚酰亚胺。
  12. 根据权利要求1所述的芯片封装方法，其特征在于：所述载体包括金属、晶圆、玻璃或有机材料。
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