WO2017043675A1 - Carte de circuit imprimé et procédé de fabrication - Google Patents

Carte de circuit imprimé et procédé de fabrication Download PDF

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Publication number
WO2017043675A1
WO2017043675A1 PCT/KR2015/009508 KR2015009508W WO2017043675A1 WO 2017043675 A1 WO2017043675 A1 WO 2017043675A1 KR 2015009508 W KR2015009508 W KR 2015009508W WO 2017043675 A1 WO2017043675 A1 WO 2017043675A1
Authority
WO
WIPO (PCT)
Prior art keywords
bump
copper foil
bol
insulating layer
base
Prior art date
Application number
PCT/KR2015/009508
Other languages
English (en)
Korean (ko)
Inventor
오정윤
김상진
Original Assignee
대덕전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 대덕전자 주식회사 filed Critical 대덕전자 주식회사
Priority to PCT/KR2015/009508 priority Critical patent/WO2017043675A1/fr
Priority to KR1020167016711A priority patent/KR20170041161A/ko
Publication of WO2017043675A1 publication Critical patent/WO2017043675A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Definitions

  • the present invention relates to a circuit board, in particular a "bump on lead (BOL)" manufacturing technology according to the embedded trace substrate (ETS) method. More particularly, the present invention relates to a technology for manufacturing a package substrate having a fine pitch BOL.
  • BOL buffer on lead
  • ETS embedded trace substrate
  • BOL technology is a method of attaching a copper bump to an interconnection pad array of a semiconductor chip and soldering directly to the lead of the package substrate.
  • the spacing between the bumps and the leads must be uniform and the spacing should be minimized.
  • the gaps between bumps of semiconductor die have been miniaturized to several micrometers
  • the gaps between bumps to be manufactured on package substrates have to be miniaturized to several micrometers.
  • the ETS method is used.
  • the ETS method is a method of manufacturing the bumps in the insulating layer. It is advantageous for miniaturization.
  • FIG. 1A to 1I are views illustrating a process of manufacturing a bump according to the ETS method according to the prior art.
  • a material 100 having a copper foil 100c coated with an adhesive 100b on one or both surfaces of a thick carrier 100a serving as a support is used as a starting material.
  • the accompanying drawings show examples in which copper foil is coated on both surfaces.
  • the dry film 110 is coated, and a series of image operations such as photographs, development, and etching are performed to transfer a predetermined BOL circuit pattern to the dry film 110.
  • a copper plating bump 120 is formed on the copper foil 100c having the surface exposed (see FIG. 1D). Then, when the insulation layer 130 and the copper foil 140 are laminated, heated and laminated, the copper plating bumps 120 are embedded in the insulation layer 130 to form an embedded tray structure (see FIG. 1E).
  • a plating mask is formed by coating the dry film 150 on the laminated copper foil 140 and transferring a pattern by performing a series of image processes such as photo, development, and etching. Subsequently, referring to FIG. 1G, copper plating 160 is formed using the pattern transferred dry film 150 as a plating mask. Referring to FIG. 1H, the dry film 150 is peeled off.
  • the carrier 100a that has been bonded through the adhesive layer 100b is separated from the structure. Then, when the copper foil (100c) is etched away through a flash etch (flash etch), as shown in Figure 2, a copper plated bump is embedded in the insulating layer 130, a pattern is formed.
  • flash etch flash etch
  • the copper plating 120 may not be etched together in the flash etching step of FIG. 2, so that the copper plating bumps 120 may be recessed to slightly enter the surface of the insulating layer 130. do. That is, a recess depth occurs.
  • FIG. 2 is a view showing a shape in which the pad is recessed inward with respect to the surface of the insulating layer when the pad is manufactured by applying the ETS method according to the prior art.
  • the inventors of the present invention have shown that the recessed depth is considerable and the bumps are deeply recessed into the insulating layer 130 so that the semiconductor die and the BOL junction can be formed. In the process, a non-wet issue often occurs.
  • the second object of the present invention is to provide a BOL pad manufacturing method and a BOL structure in which the BOL pad is not recessed into the insulating layer in the manufacture of the BOL pad of the ETS method in addition to the first object. have.
  • a first bump is formed on a base copper foil, and an insulating layer is laminated and heated under pressure lamination so that the first bump is embedded into the insulating layer, and then the base copper foil corresponding to the portion where the first bump is formed is formed.
  • a second bump is formed on the first bump.
  • the BOL bumps of the present invention formed from the combination of the first bump and the second bump thereon essentially prevent the bumps from being recessed into the insulating layer.
  • bumps are formed by the base copper foil without going through an additional copper plating process.
  • the present invention prevents the BOL pads of the package substrate from being recessed into the surface of the insulating layer, thereby preventing the occurrence of bonding failure in the step of solder bonding the bumps of the semiconductor die and the BOL pads of the package substrate.
  • the present invention may be such that the height of the metal bumps formed separately using only the etching process on the ETS substrate has the same or higher cross-sectional structure as that of the general circuit.
  • the present invention provides a bump forming technique that solves the non-wet issue using only a selective etching process using a base copper foil without going through an additional copper plating process.
  • the substrate according to the prior art has a bump pad of 10 ⁇ m or more higher than the base material (CCL) to hinder the underfill or EMC fluidity, but the present invention minimizes the protrusion width, which may help underfill or EMC fluidity.
  • CCL base material
  • the ETS structure according to the prior art has a disadvantage that the foreign material can be easily introduced to lower the height of the PAD than the base material, the present invention can solve this problem.
  • the prior art may cause a wetting problem when the height of the chip bumps is low or the recess depth is large, but the present invention may solve this problem.
  • FIGS. 1A to 1I are views illustrating a process of manufacturing a BOL bump according to the ETS method according to the prior art.
  • FIG. 2 is a view showing a BOL bump made according to the prior art is deeply recessed into the insulating layer.
  • 3A to 3I are views illustrating a process of manufacturing a BOL bump according to the ETS method according to the present invention.
  • the present invention provides a method of manufacturing a circuit board, comprising the steps of: (a) fabricating a first bump on which a predetermined BOL pattern is transferred onto a base copper foil of a detachable core; (b) depositing the first bump into which the upper surface and the side surface are exposed into the second insulating layer by laminating and laminating a second insulating layer and a second copper foil on the first bump; (c) forming a third copper foil on which the predetermined pattern is transferred on the second copper foil; (d) separating the detachable core from the base copper foil to expose one surface of the base copper foil; (e) forming an etching mask having a size smaller than or corresponding to a size of the first bump in a region corresponding to the first bump on the exposed base surface; And (f) performing flash etching while the etching mask is coated to etch away the exposed base copper on one surface of the substrate and the exposed second copper foil on the opposite side of the substrate, thereby forming a second bump on
  • the present invention provides a circuit board having a BOL bump for a BOL junction, wherein the BOL bump comprises: a first bump embedded in an insulating layer with an embedded trace structure; It is composed of a second bump protruding on the first bump, the second bump provides a circuit board, characterized in that produced by selectively etching the base copper foil.
  • a detachable core may be used as a starting material as a preferred embodiment of the present invention, but the present invention is not necessarily limited thereto.
  • Copper foil 100 also called a "base copper foil” is formed on the surface of the detachable core, and the detachable core 50 and the copper foil 100 are bonded by an adhesive, if necessary. Applying a slight physical force can peel off the copper foil 100 from the detachable core 50 to separate.
  • Carrier copper foil can often be used as the detachable core, and a material having a copper foil coated with an adhesive on a film having a predetermined thickness may be used.
  • the thickness of the copper foil 100 can be about 5 ⁇ m.
  • the copper foil of reference numeral 100 will be referred to as a base copper foil.
  • a dry film (D / F; not shown) is coated on the base copper foil 100, and a series of image processes such as photographing, exposure, development, and etching are performed to apply a predetermined BOL pattern to the dry film. Transfer to prepare a plating mask.
  • the second insulating layer 130 and the second copper foil 140 are laminated and heated and laminated. Subsequently, a dry film (not shown) is coated on the second copper foil 140, a predetermined circuit pattern is transferred to form a plating mask, and then electroplating is performed to thereby transfer the third copper foil 160 on which the circuit pattern is transferred. Form (see FIG. 3D).
  • the detachable core is peeled off and separated to obtain two structures.
  • 3E illustrates a lower structure of the two upper and lower structures for convenience, hereinafter, the present invention will be described based on this.
  • the dry film 170 is closely attached to the surface of the base copper foil 100 exposed by the detachable core separation, and the surface of the base copper foil 100 is not exposed so that the area corresponding to the first bump 120 is not exposed.
  • the pattern is transferred so that the dry film 160 is covered.
  • a pattern may be formed in the dry film 160 to form a mask of the same size as the first bump, a slightly smaller size, or a slightly larger size.
  • 3F shows a mask of a size slightly smaller than the size of the first bump in one embodiment.
  • the second bump 100 having the same size, a slightly smaller size, or about a larger size is formed on the first bump 120 embedded in the insulating layer 130.
  • the first bump 120 is embedded in the insulating layer 130, the mask is coated on the surface of the base copper foil during the flash etching of the second copper foil 140 of the lower surface,
  • the base copper foil on the bump 120 is not etched, and the base copper foil left unetched becomes the second bump, and the BOL bump according to the present invention is the first bump 100 and the second bump 100 thereon. It is composed of.
  • the dry film 170 used as the etching mask is peeled off.
  • the process is completed by applying and finishing the solder resist 180.
  • inventive concepts and embodiments disclosed herein may be used by those skilled in the art as a basis for modifying or designing other structures for carrying out the same purposes of the present invention.
  • modifications or altered equivalent structures by those skilled in the art may be variously evolved, substituted and changed without departing from the spirit or scope of the invention described in the claims.
  • the present invention prevents the BOL pads of the package substrate from being recessed into the surface of the insulating layer, thereby preventing the occurrence of bonding failure in the step of solder bonding the bumps of the semiconductor die and the BOL pads of the package substrate.
  • the present invention may be such that the height of the metal bumps formed separately using only the etching process on the ETS substrate has the same or higher cross-sectional structure as that of the general circuit.
  • the present invention provides a bump forming technique that solves the non-wet issue using only a selective etching process using a base copper foil without going through an additional copper plating process.
  • the substrate according to the prior art hinders fluidity because the bump pad protrudes more than a few tens of micrometers more than the base material (CCL), but the present invention minimizes the protrusion width and thus may help underfill or EMC fluidity.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

La présente invention forme une bosse BOL sur un revêtement en cuivre de base, empile une couche isolante sur celle-ci, et met sous pression à la chaleur et stratifie la couche isolante de manière à permettre à la bosse BOL d'être enfoncée dans la couche isolante, puis étale un masque de gravure ayant la même forme qu'un motif de bosse BOL sur une surface exposée du revêtement en cuivre de base, et effectue une gravure flash correspondante, de manière à permettre au revêtement en cuivre de base d'être laissé sur la bosse BOL, ce qui permet d'empêcher la bosse d'être en retrait dans la couche isolante.
PCT/KR2015/009508 2015-09-10 2015-09-10 Carte de circuit imprimé et procédé de fabrication WO2017043675A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/KR2015/009508 WO2017043675A1 (fr) 2015-09-10 2015-09-10 Carte de circuit imprimé et procédé de fabrication
KR1020167016711A KR20170041161A (ko) 2015-09-10 2015-09-10 회로기판 및 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/KR2015/009508 WO2017043675A1 (fr) 2015-09-10 2015-09-10 Carte de circuit imprimé et procédé de fabrication

Publications (1)

Publication Number Publication Date
WO2017043675A1 true WO2017043675A1 (fr) 2017-03-16

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KR (1) KR20170041161A (fr)
WO (1) WO2017043675A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114521057A (zh) * 2020-11-18 2022-05-20 深南电路股份有限公司 一种印制线路板及其制备方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101981135B1 (ko) 2017-06-14 2019-05-23 대덕전자 주식회사 회로배선판 제조방법

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011151348A (ja) * 2009-07-06 2011-08-04 Fujikura Ltd 積層配線基板及びその製造方法
KR101151347B1 (ko) * 2010-10-07 2012-06-08 대덕전자 주식회사 칩 내장형 인쇄회로기판 제조방법
KR101158213B1 (ko) * 2010-09-14 2012-06-19 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 이의 제조 방법
KR101287742B1 (ko) * 2011-11-23 2013-07-18 삼성전기주식회사 인쇄 회로 기판 및 그 제조 방법
KR101375998B1 (ko) * 2009-12-28 2014-03-19 니혼도꾸슈도교 가부시키가이샤 다층 배선기판의 제조방법 및 다층 배선기판

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011151348A (ja) * 2009-07-06 2011-08-04 Fujikura Ltd 積層配線基板及びその製造方法
KR101375998B1 (ko) * 2009-12-28 2014-03-19 니혼도꾸슈도교 가부시키가이샤 다층 배선기판의 제조방법 및 다층 배선기판
KR101158213B1 (ko) * 2010-09-14 2012-06-19 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 이의 제조 방법
KR101151347B1 (ko) * 2010-10-07 2012-06-08 대덕전자 주식회사 칩 내장형 인쇄회로기판 제조방법
KR101287742B1 (ko) * 2011-11-23 2013-07-18 삼성전기주식회사 인쇄 회로 기판 및 그 제조 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114521057A (zh) * 2020-11-18 2022-05-20 深南电路股份有限公司 一种印制线路板及其制备方法

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