WO2017035907A1 - Cmos goa电路 - Google Patents

Cmos goa电路 Download PDF

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Publication number
WO2017035907A1
WO2017035907A1 PCT/CN2015/091715 CN2015091715W WO2017035907A1 WO 2017035907 A1 WO2017035907 A1 WO 2017035907A1 CN 2015091715 W CN2015091715 W CN 2015091715W WO 2017035907 A1 WO2017035907 A1 WO 2017035907A1
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Prior art keywords
signal
type tft
gate
electrically connected
twenty
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PCT/CN2015/091715
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English (en)
French (fr)
Inventor
赵莽
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Wuhan China Star Optoelectronics Technology Co Ltd
TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US14/786,537 priority Critical patent/US9761194B2/en
Publication of WO2017035907A1 publication Critical patent/WO2017035907A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0871—Several active elements per pixel in active matrix panels with level shifting
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a CMOS GOA circuit.
  • GOA Gate Driver on Array
  • TFT Thin Film Transistor
  • the driving method has the advantages of reducing production cost and realizing the narrow frame design of the panel, and is used for various displays.
  • the GOA circuit has two basic functions: the first is to output the scan drive signal, drive the gate line in the panel, open the TFT in the display area to charge the pixel; the second is the shift register function, when the Nth scan After the drive signal output is completed, the output of the (N+1)th scan drive signal is performed by clock control, and is sequentially transmitted.
  • LTPS TFT liquid crystal displays are also receiving more and more attention. Since the silicon crystal arrangement of LTPS is more ordered than amorphous silicon, LTPS semiconductor has ultra-high carrier mobility, and the liquid crystal display using LTPS TFT has the advantages of high resolution, fast response speed, high brightness, and high aperture ratio. The peripheral integrated circuit of the LTPS TFT liquid crystal display has also become the focus of display technology.
  • Figure 1 shows an existing CMOS GOA circuit including a plurality of cascaded GOA units.
  • the existing CMOS GOA circuit has various levels. The scan drive signal is all raised to a high level at the same time.
  • N be a positive integer
  • the Nth stage GOA unit includes an input control module 100, a latch module 300, a signal processing module 400, and an output buffer module 500.
  • the input control module 100 accesses the level transmission signal Q(N-1) of the upper level GOA unit, the first clock signal CK1, the first inverted clock signal XCK1, the constant voltage high potential signal VGH, and the constant voltage low potential.
  • the signal VGL, the signal P(N) opposite to the potential of the level signal Q(N-1) of the GOA unit of the previous stage is input to the latch module 300;
  • the latch module 300 includes an inverter F, which inverts the signal P(N) to obtain the level-transmitted signal Q(N) of the N-th stage GOA unit, and the latch module 300 locks the level-transmitted signal Q(N). Save
  • the signal processing module 400 accesses the level transmission signal Q(N), the second clock signal CK2, the constant voltage high potential signal VGH, the constant voltage low potential signal VGL, and the global signal Gas; the signal processing module The block 400 is configured to perform NAND processing on the second clock signal CK2 and the level transmission signal Q(N) to generate the scan driving signal G(N) of the Nth stage GOA unit; and to transmit the second clock signal CK2 and the level
  • the signal Q(N) is ORed or non-logically processed with the result of the logic processing and the global signal Gas, and the global signal Gas is controlled to all of the scan drive signals of all stages simultaneously rising to a high potential. Further, when the global signal Gas is at a high potential, all of the scanning drive signals are controlled to rise to a high potential at the same time;
  • the output buffer module 500 is electrically connected to the signal processing module 400 for increasing the driving capability of the scan driving signal G(N) and reducing the RC loading during signal transmission.
  • each level of the GOA unit of the existing CMOS GOA circuit further includes a reset module 200.
  • the reset module 200 includes a P-type TFT, the gate of the P-type TFT is connected to the reset signal Reset, and the source is connected to the constant-voltage high-potential signal VGH. The drain is connected to the input terminal of the inverter F in the latch module 300.
  • the reset module 200 is separately provided to improve the performance of the circuit, the additional components, traces, and signals increase the area of the GOA circuit, which increases the signal complexity and is not conducive to the design of the narrow bezel.
  • the area of the GOA circuit improves the stability of the GOA circuit and avoids the risk of failure of the GOA circuit when it starts to work normally.
  • the present invention provides a CMOS GOA circuit comprising a plurality of cascaded GOA units
  • N be a positive integer
  • the Nth stage GOA unit includes: an input control module, a latch module electrically connected to the input control module, a signal processing module electrically connected to the latch module, and an output buffer module of the electrical connection signal processing module, And electrically connecting the latch module and the signal processing module storage capacitance;
  • the input control module accesses a level transmission signal, a first clock signal, a global signal, a constant voltage high potential signal, and a constant voltage low potential signal of the upper N-1th GOA unit;
  • the input control module includes the first a NOR gate and a second NOR gate;
  • the first input end of the first NOR gate is connected to the level transmission signal of the upper N-1th GOA unit, the second input end is connected to the global signal, and the output end is Outputting a result of a gradation signal of the upper N-1th GOA unit and a NAND processing result of the global signal;
  • the first input of the second NOR gate is connected to the first clock signal, and the second input is connected a global signal, the output terminal outputs a first clock signal and a global signal NAND processing result as a first inverted clock signal;
  • the input control module is configured to transmit a level signal of the upper N-1th GOA unit Inverting the phase signal with the global signal or the non-logic processing result, and inputting the in
  • the latch module includes a first inverter, an input of the first inverter inputs an inverted phase transmission signal, and an output terminal outputs a phase transmission signal; the latch module is configured to lock the level transmission signal Save
  • the signal processing module accesses the level transmission signal, the second clock signal, the constant voltage high potential signal, the constant voltage low potential signal, and the global signal, and is used for performing NAND processing on the second clock signal and the level transmission signal, Generating a scan driving signal of the Nth stage GOA unit; performing a logical processing result on the second clock signal and the level transmission signal and performing a non-logic processing on the global signal, so as to realize global signal control, and all the scan driving signals are simultaneously raised to high Potential
  • the output buffer module includes a plurality of second inverters sequentially connected in series for outputting a scan driving signal and increasing a driving capability of the scan driving signal;
  • One end of the storage capacitor is electrically connected to the level transmission signal, and the other end is grounded to store the potential of the level transmission signal;
  • the global signal includes a single pulse, and when it is at a high potential, all of the scan drive signals are controlled to rise to a high potential at the same time, and the first NOR gate and the second NOR gate are controlled to output a low potential, thereby controlling the reverse
  • the phase-level signal is high, and the potential of the signals transmitted by the stages is pulled down by the first inverter in the latch module, and the signals transmitted at all levels are reset.
  • the input control module further includes a first P-type TFT, a second P-type TFT, a third N-type TFT, and a fourth N-type TFT connected in series; the gate of the first P-type TFT is connected to the first anti- a phase clock signal, a source connected to the constant voltage high potential signal; a gate of the second P-type TFT and the third N-type TFT are connected to an output end of the first NOR gate; the second P-type TFT Connected to the drain of the third N-type TFT, outputting an inverted phase-transmitting signal; the gate of the fourth N-type TFT is connected to the first clock signal, and the source is connected to the constant-voltage low-potential signal;
  • the latch module further includes a fifth P-type TFT, a sixth P-type TFT, a seventh N-type TFT, and an eighth N-type TFT connected in series; the gate of the fifth P-type TFT is connected to the first clock Signal, The source is connected to the constant voltage high potential signal; the gates of the sixth P-type TFT and the seventh N-type TFT are both connected to the level transmission signal; and the drains of the sixth P-type TFT and the seventh N-type TFT are mutually Connecting and electrically connecting the drains of the second P-type TFT and the third N-type TFT; the gate of the eighth N-type TFT is connected to the first inverted clock signal, and the source is connected to the constant voltage low potential signal;
  • the signal processing module includes: a ninth P-type TFT, a gate of the ninth P-type TFT is connected to a global signal, a source is connected to a constant voltage high potential signal; a tenth P-type TFT, the tenth P-type The gate of the TFT is connected to the pass signal, the source is electrically connected to the drain of the ninth P-type TFT, the drain is electrically connected to the node, and the eleventh P-type TFT is connected to the gate of the eleventh P-type TFT.
  • the pole is connected to the second clock signal
  • the source is electrically connected to the drain of the ninth P-type TFT
  • the drain is electrically connected to the node
  • the twelfth N-type TFT is connected to the gate of the twelfth N-type TFT a stepping signal, a drain electrically connected to the node
  • a thirteenth N-type TFT a gate of the thirteenth N-type TFT is connected to the second clock signal, and a drain is electrically connected to the twelfth N
  • the source of the TFT the source is connected to the constant voltage low potential signal
  • the fourteenth N-type TFT the gate of the fourteenth N-type TFT is connected to the global signal
  • the source is connected to the constant voltage low potential signal
  • the drain Very electrically connected to the node.
  • the output buffer module includes three second inverters connected in series in series, and an input end of the second inverter closest to the signal processing module is electrically connected to the node, and is farthest from the second inverter of the signal processing module.
  • the output outputs a scan drive signal.
  • the first inverter is composed of a fifteenth P-type TFT connected in series with a sixteenth N-type TFT, and the fifteenth P-type TFT and the gate of the sixteenth N-type TFT are electrically connected to each other to constitute the first
  • An input end of an inverter is input with an inverted phase signal, a source of the fifteenth P-type TFT is connected to a constant voltage high potential signal, and a source of the sixteenth N-type TFT is connected to a constant voltage
  • the potential signal, the fifteenth P-type TFT and the drain of the sixteenth N-type TFT are electrically connected to each other to form an output end of the first inverter and output a level transmission signal.
  • the second inverter is composed of a seventeenth P-type TFT connected in series with an eighteenth N-type TFT, and the seventeenth P-type TFT and the eighteenth-type TFT are electrically connected to each other to form the first inverter.
  • a source of the seventeenth P-type TFT is connected to a constant voltage high potential signal
  • a source of the eighteenth N-type TFT is connected to a constant voltage low potential signal
  • the drains of the seven P-type TFTs and the drains of the eighteenth-type TFTs are electrically connected to each other to form an output end of the second inverter; the output ends of the previous second inverters are electrically connected to the second inverters Input.
  • the first NOR gate includes a nineteenth P-type TFT, a twentieth P-type TFT, a twenty-first N-type TFT, and a twenty-second N-type TFT; the twentieth P-type TFT and the second The gates of the eleven N-type TFTs are electrically connected to each other to form a first input end of the first NOR gate and to access a level-transmitting signal of the upper-stage N-1th GOA unit; the nineteenth P-type TFT Electrically connecting with the gate of the twenty-two N-type TFT to form a second input end of the first NOR gate and accessing a global signal;
  • the source of the nineteen P-type TFT is connected to a constant voltage high potential signal, and the drain is electrically connected to the source of the twentieth P-type TFT; the source of the twenty-first N-type TFT and the twenty-second N-type TFT
  • the poles are connected to the constant voltage low potential signal; the drains of the twentieth P-type TFT 21st N-type TFT
  • the second NOR gate includes a twenty-three P-type TFT, a twenty-fourth P-type TFT, a twenty-fifth N-type TFT, and a twenty-sixth N-type TFT; the twenty-fourth P-type TFT and The gates of the twenty-fifth N-type TFT are electrically connected to each other to form a first input end of the second NOR gate and to access a first clock signal; the Twenty-third P-type TFT and the second sixteen N-type The gates of the TFTs are electrically connected to each other to form a second input end of the second NOR gate and are connected to the global signal; the source of the 23rd P-type TFT is connected to a constant voltage high potential signal, and the drain is electrically Connecting a source of the twenty-fourth P-type TFT; a source of the twenty-fifth N-type TFT and the second sixteen-N-type TFT are connected to a constant voltage low potential signal; and the twenty-fourth P-type TFT
  • the first input of the first NOR gate is connected to the circuit enable signal.
  • the present invention also provides a CMOS GOA circuit comprising a plurality of cascaded GOA units;
  • N be a positive integer
  • the Nth stage GOA unit includes: an input control module, a latch module electrically connected to the input control module, a signal processing module electrically connected to the latch module, and an output buffer module of the electrical connection signal processing module, And electrically connecting the storage capacitor of the latch module and the signal processing module;
  • the input control module accesses a level transmission signal, a first clock signal, a global signal, a constant voltage high potential signal, and a constant voltage low potential signal of the upper N-1th GOA unit;
  • the input control module includes the first a NOR gate and a second NOR gate;
  • the first input end of the first NOR gate is connected to the level transmission signal of the upper N-1th GOA unit, the second input end is connected to the global signal, and the output end is Outputting a result of a gradation signal of the upper N-1th GOA unit and a NAND processing result of the global signal;
  • the first input of the second NOR gate is connected to the first clock signal, and the second input is connected a global signal, the output terminal outputs a first clock signal and a global signal NAND processing result as a first inverted clock signal;
  • the input control module is configured to transmit a level signal of the upper N-1th GOA unit Inverting the phase signal with the global signal or the non-logic processing result, and inputting the in
  • the latch module includes a first inverter, an input of the first inverter inputs an inverted phase transmission signal, and an output terminal outputs a phase transmission signal; the latch module is configured to lock the level transmission signal Save
  • the signal processing module accesses a level transmission signal, a second clock signal, a constant voltage high potential signal, a constant voltage low potential signal and a global signal are used for NAND processing of the second clock signal and the level transmission signal to generate a scan driving signal of the Nth stage GOA unit; and for the second clock signal and the level transmission signal Performing or non-logical processing with the result of the logic processing and the global signal, realizing the global signal control all the scan drive signals of all stages simultaneously rise to a high potential;
  • the output buffer module includes a plurality of second inverters sequentially connected in series for outputting a scan driving signal and increasing a driving capability of the scan driving signal;
  • One end of the storage capacitor is electrically connected to the level transmission signal, and the other end is grounded to store the potential of the level transmission signal;
  • the global signal includes a single pulse, and when it is at a high potential, all of the scan drive signals are controlled to rise to a high potential at the same time, and the first NOR gate and the second NOR gate are controlled to output a low potential, thereby controlling the reverse
  • the phase-level signal is high, and then the potential of the signals transmitted by the stages is pulled down by the first inverter in the latch module, and the signals transmitted at all levels are reset and reset;
  • the input control module further includes a first P-type TFT, a second P-type TFT, a third N-type TFT, and a fourth N-type TFT connected in series in sequence; a gate of the first P-type TFT is connected to the gate An inverted clock signal, the source is connected to the constant voltage high potential signal; the gates of the second P-type TFT and the third N-type TFT are both connected to the output end of the first NOR gate; the second P The TFT of the type and the drain of the third N-type TFT are connected to each other to output an inverted phase-transmitting signal; the gate of the fourth N-type TFT is connected to the first clock signal, and the source is connected to the constant-voltage low-potential signal;
  • the latch module further includes a fifth P-type TFT, a sixth P-type TFT, a seventh N-type TFT, and an eighth N-type TFT connected in series; the gate of the fifth P-type TFT is connected to the first clock The signal and the source are connected to the constant voltage high potential signal; the gates of the sixth P-type TFT and the seventh N-type TFT are both connected to the level transmission signal; and the leakage of the sixth P-type TFT and the seventh N-type TFT The poles are connected to each other and electrically connected to the drains of the second P-type TFT and the third N-type TFT; the gate of the eighth N-type TFT is connected to the first inverted clock signal, and the source is connected to the constant voltage Low potential signal
  • the signal processing module includes: a ninth P-type TFT, a gate of the ninth P-type TFT is connected to a global signal, a source is connected to a constant voltage high potential signal; a tenth P-type TFT, the tenth P-type The gate of the TFT is connected to the pass signal, the source is electrically connected to the drain of the ninth P-type TFT, the drain is electrically connected to the node, and the eleventh P-type TFT is connected to the gate of the eleventh P-type TFT.
  • the pole is connected to the second clock signal, the source is electrically connected to the drain of the ninth P-type TFT, the drain is electrically connected to the node, and the twelfth N-type TFT is connected to the gate of the twelfth N-type TFT a stepping signal, a drain electrically connected to the node; a thirteenth N-type TFT, a gate of the thirteenth N-type TFT is connected to the second clock signal, and a drain is electrically connected to the twelfth N
  • the source of the TFT the source is connected to the constant voltage low potential signal;
  • the fourteenth N-type TFT, the gate of the fourteenth N-type TFT is connected to the global signal, the source is connected to the constant voltage low potential signal, and the drain Extremely electrically connected to the node;
  • the first NOR gate includes a nineteenth P-type TFT, a twentieth P-type TFT, a twenty-first N-type TFT, and a twenty-second N-type TFT; and the twentieth P-type TFT and The gates of the twenty-first N-type TFTs are electrically connected to each other to constitute a first input end of the first NOR gate and are connected to a level-transmitting signal of the upper-stage N-1th GOA unit; the nineteenth P The TFTs of the TFTs and the gates of the 22nd N-type TFTs are electrically connected to each other to form a second input end of the first NOR gate and are connected to a global signal; the source of the 19th P-type TFT is connected to a constant voltage a high potential signal, the drain is electrically connected to the source of the twentieth P-type TFT; the source of the 21st N-type TFT and the 22nd N-type TFT are both connected to a constant voltage low potential signal; The drains of the twentieth P-type TFT,
  • the second NOR gate includes a twenty-three P-type TFT, a twenty-fourth P-type TFT, a twenty-fifth N-type TFT, and a twenty-sixth N-type TFT; the twenty-fourth P-type The TFT and the gate of the twenty-fifth N-type TFT are electrically connected to each other to form a first input end of the second NOR gate and access a first clock signal; the Twenty-third P-type TFT and the second sixteen The gates of the N-type TFTs are electrically connected to each other to form a second input end of the second NOR gate and are connected to the global signal; the source of the 23rd P-type TFT is connected to the constant voltage high potential signal, and the drain Electrically connecting the source of the twenty-fourth P-type TFT; the sources of the twenty-fifth N-type TFT and the twenty-sixth N-type TFT are both connected to a constant voltage low potential signal; the twenty-fourth P The drains of the TFT
  • the present invention provides a CMOS GOA circuit in which a first NOR gate and a second NOR gate are disposed in an input control module, and the two input terminals of the first NOR gate are respectively connected to the upper level.
  • the level signal and the global signal of the GOA unit respectively connect the two input terminals of the second NOR gate to the first clock signal and the global signal, and when the global signal is high, all the scanning drive signals of each level are simultaneously raised to high.
  • the reset module is not separately provided, and the additional components, the traces, and the reset signal are omitted, and the GOA circuit is reduced.
  • FIG. 1 is a circuit diagram of a conventional CMOS GOA circuit
  • FIG. 2 is a circuit diagram of a CMOS GOA circuit of the present invention
  • FIG. 3 is a circuit diagram of a first stage GOA unit of a CMOS GOA circuit of the present invention
  • FIG. 5 is a schematic structural diagram of a specific circuit of a first NOR gate in an input control module of a CMOS GOA circuit of the present invention
  • FIG. 6 is a schematic diagram showing a specific circuit structure of a second NOR gate in an input control module of a CMOS GOA circuit of the present invention
  • FIG. 7 is a schematic diagram showing a specific circuit structure of a first inverter in a latch module of a CMOS GOA circuit according to the present invention.
  • FIG. 8 is a schematic structural diagram of a specific circuit of three second inverters connected in series in an output buffer module of a CMOS GOA circuit of the present invention.
  • the present invention provides a CMOS GOA circuit including a plurality of cascaded GOA units, each of which uses a plurality of N-type TFTs and a plurality of P-type TFTs, and each TFT is It is a low temperature polysilicon semiconductor thin film transistor.
  • N be a positive integer.
  • the Nth stage GOA unit includes: an input control module 1, a latch module 3 electrically connected to the input control module 1, a signal processing module 4 electrically connected to the latch module 3, and an electrical connection signal processing module.
  • the output buffer module 5 of the 4 and the storage capacitor 7 of the signal processing module 4 are electrically connected to the latch module 3.
  • the input control module 1 accesses the level transmission signal Q(N-1) of the first-stage N-1th GOA unit, the first clock signal CK1, the global signal Gas, the constant voltage high potential signal VGH, and the constant voltage low Potential signal VGL.
  • the input control module 1 includes a first NOR gate Y1 and a second NOR gate Y2; the first input terminal A of the first NOR gate Y1 is connected to the level transmission signal of the upper N-1th GOA unit.
  • Q(N-1) the second input terminal B is connected to the global signal Gas, and the output terminal D is outputted to the previous one.
  • the input control module 1 is configured to invert the gradation signal Q(N-1) of the upper N-1th GOA unit and the NAND processing result of the global signal Gas to obtain an inverted phase transmission signal XQ(N And input the inverted phase signal XQ(N) to the latch module 3.
  • the input control module 1 further includes a first P-type TFT T1, a second P-type TFT T2, a third N-type TFT T3, and a fourth N-type TFT T4 connected in series in series: the first P-type TFT
  • the gate of T1 is connected to the first inverted clock signal XCK1, and the source is connected to the constant voltage high potential signal VGH;
  • the gates of the second P-type TFT T2 and the third N-type TFT T3 are connected to the first or The output terminal D of the non-gate Y1;
  • the second P-type TFT T2 and the drain of the third N-type TFT T3 are connected to each other, and output an inverted-stage signal XQ(N);
  • the gate of the fourth N-type TFT T4 The pole is connected to the first clock signal CK1, and the source is connected to the constant voltage low potential signal VGL.
  • the specific circuit structure of the first NOR gate Y1 is as shown in FIG. 5, and includes a nineteenth P-type TFT T19, a twentieth P-type TFT T20, a twenty-first N-type TFT T21, and a second a twelve N-type TFT T22; the twentieth P-type TFT T20 and the gate of the twenty-first N-type TFT T21 are electrically connected to each other to form a first input terminal A of the first NOR gate Y1 and connected thereto a graded signal Q(N-1) of the first-stage N-1th GOA unit; the nineteenth P-type TFT T19 and the gate of the twenty-second type N TFT T22 are electrically connected to each other to constitute the first or
  • the second input terminal B of the non-gate Y1 is connected to the global signal Gas; the source of the nineteenth P-type TFT T19 is connected to the constant voltage high potential signal VGH, and the drain is electrically connected to the twentieth P-type TFT T20.
  • a source of the twenty-first N-type TFT T21 and the twenty-second N-type TFT T22 are connected to the constant voltage low potential signal VGL; the twentieth P-type TFT T20, the twenty-first N
  • the drains of the TFTs T21 and T22 are electrically connected to each other to form the output D of the first NOR gate Y1 and output the level signal Q of the upper N-1th GOA unit ( N-1) and global signal Gas or non-logic processing result
  • the specific circuit structure of the second NOR gate Y2 is as shown in FIG. 6, and includes twenty-three P-type TFTs T23, twenty-fourth P-type TFTs T24, twenty-fifth N-type TFTs T25, and twenty-sixth.
  • the N-type TFT T26; the twenty-fourth P-type TFT T24 and the gate of the twenty-fifth N-type TFT T25 are electrically connected to each other to form the first input terminal A' of the second NOR gate Y2 and are connected to the first a clock signal CK1; the gates of the twenty-third P-type TFT T23 and the second sixteen-type TFT T26 are electrically connected to each other to form a second input terminal B' of the second NOR gate Y2 and are connected to the global a signal Gas; a source of the twenty-third P-type TFT T23 is connected to the constant voltage high potential signal VGH, and a drain is electrically connected to a source of the twenty-fourth P-type TFT T24; the twenty-fifth N-type The source of the TFT T25 and the twenty-sixth N-type TFT T26 are both connected to the constant voltage low potential signal VGL; the twenty-fourth P-type TFT T24, The drains of the twenty-f
  • the output signal is low after the circumstance or non-logic processing.
  • the global signal Gas connected to the second input terminal B of the first NOR gate Y1 is low, the N-th access to the first input terminal A of the first NOR gate Y1 is When the level-transmitted signal Q(N-1) of the level 1 GOA unit is at a high potential, the output terminal D of the first NOR gate Y1 outputs a low potential, and is connected to the first input terminal A of the first NOR gate Y1.
  • the output terminal D of the first NOR gate Y1 outputs a high potential; if the first NOR gate Y1 The global signal Gas accessed by the second input terminal B is high, and the level signal Q (N- of the upper-stage N-1th GOA unit accessed by the first input terminal A of the first NOR gate Y1 is not present. 1) At what potential, the output terminal D of the first NOR gate Y1 outputs a low potential. If the global signal Gas connected to the second input terminal B' of the second NOR gate Y2 is low, the first clock signal CK1 accessed at the first input terminal A' of the second NOR gate Y2 is high.
  • the first inverted clock signal XCK1 outputted from the output terminal D' of the second NOR gate Y2 is low, the first clock signal CK1 is accessed at the first input terminal A' of the second NOR gate Y2.
  • the first inverted clock signal XCK1 outputted from the output terminal D' of the second NOR gate Y2 is high; if the second input terminal B' of the second NOR gate Y2 is connected to the global signal Gas is high, the first inverted clock outputted by the output terminal D' of the second NOR gate Y2 regardless of the potential of the first clock signal CK1 accessed by the first input terminal A' of the second NOR gate Y2 Signal XCK1 is low.
  • the third N-type TFT T3 is turned on and the fourth N-type TFT T4 is turned on, and is outputted from the drain of the third N-type TFT T3.
  • the low-level inverted-phase transmission signal XQ(N) in the case where the first NOR gate Y1 outputs a low potential and the first inverted clock signal XCK1 is at a low potential, the first P-type TFT T1 and the second P-type TFT T2 is turned on, and a high-potential inverted phase signal XQ(N) is outputted from the drain of the second P-type TFT T2.
  • the latch module 3 includes a first inverter F1, the input terminal K of the first inverter F1 inputs an inverted phase transmission signal XQ(N), and the output terminal L outputs a level transmission signal (Q(N) ).
  • the latch module 3 further includes a fifth P-type TFT T5, a sixth P-type TFT T6, a seventh N-type TFT T7, and an eighth N-type TFT T8 connected in series; the gate of the fifth P-type TFT T5 The pole is connected to the first clock signal CK1, the source is connected to the constant voltage high potential signal VGH; the gates of the sixth P-type TFT T6 and the seventh N-type TFT T7 are connected to the level-transmitting signal Q(N);
  • the sixth P-type TFT T6 and the drain of the seventh N-type TFT T7 are connected to each other, and are electrically connected to the drains of the second P-type TFT T2 and the third N-type TFT T3; the eighth N-type TFT The gate
  • a fifteenth P-type TFT T15 is connected in series with a sixteenth N-type TFT T16, and the fifteenth P-type TFT T15 and the sixteenth N-type TFT T16 are electrically connected to each other.
  • the source of the fifteenth P-type TFT T15 is connected to the constant voltage high potential signal VGH, the tenth The source of the six N-type TFT T16 is connected to the constant voltage low potential signal VGL, and the fifteenth P-type TFT T15 and the drain of the sixteenth N-type TFT T16 are electrically connected to each other to constitute the first inverter F1.
  • the output terminal L outputs a level transmission signal Q(N). For the inverter, the output signal is low when its input signal is high, and the output signal is high when its input signal is low.
  • the seventh N-type TFT T7 is turned on and the eighth N-type TFT T8 controlled by the first inverted clock signal XCK1.
  • the low-potential output of the drain of the seventh N-type TFT T7 that is, the inverted-stage signal XQ(N) is kept low, and the level-transmitted signal Q(N) output by the first inverter F1 is still high.
  • the potential realizes latching of the level transfer signal Q(N); if the level transfer signal Q(N) is low, the sixth P type TFT T6 and the fifth P type TFT T5 controlled by the first clock signal CK1 Turning on, the high-potential output of the drain of the sixth P-type TFT T6, that is, keeping the inverted-stage signal XQ(N) at a high potential, the level-transmitted signal Q(N) output by the first inverter F1 is still For low potential, latching of the level-transmitted signal Q(N) is achieved.
  • the signal processing module 4 accesses the level transmission signal Q(N), the second clock signal CK2, the constant voltage high potential signal VGH, the constant voltage low potential signal VGL, and the global signal Gas for the second clock signal CK2 and
  • the gradation signal Q(N) is subjected to NAND processing to generate the scan driving signal G(N) of the Nth stage GOA unit; the result of logical processing of the second clock signal CK2 and the level transmission signal Q(N) And global signal Gas or non-logic processing, the global signal Gas control level scan drive signal G (N) all simultaneously rise to a high potential.
  • the signal processing module 4 includes: a ninth P-type TFT T9, a gate of the ninth P-type TFT T9 is connected to the global signal Gas, a source is connected to the constant voltage high potential signal VGH; and a tenth P-type TFT T10, the gate of the tenth P-type TFT T10 is connected to the pass signal Q(N), the source is electrically connected to the drain of the ninth P-type TFT T9, and the drain is electrically connected to the node A(N).
  • the eleventh P-type TFT T11, the gate of the eleventh P-type TFT T11 is connected to the second clock signal CK2, the source is electrically connected to the drain of the ninth P-type TFT T9, and the drain is electrically connected
  • the node A(N); the twelfth N-type TFT T12, the gate of the twelfth N-type TFT T12 is connected to the pass signal Q(N), and the drain is electrically connected to the node A(N);
  • a thirteenth N-type TFT T13, the gate of the thirteenth N-type TFT T13 is connected to the second clock signal CK2, and the drain is electrically connected to the source of the twelfth N-type TFT T12, and the source is connected.
  • the constant voltage low potential signal VGL; the fourteenth N-type TFT T14, the gate of the fourteenth N-type TFT T14 is connected to the global signal Gas, the source is connected to the constant voltage low potential signal VGL, and the drain is electrically connected to the drain Node A (N).
  • the twelfth N-type TFT T12 is turned on with the thirteenth N-type TFT T13, and the potential of the node A(N) is low; in the second clock signal CK2 and When the level transfer signal Q(N) is at a low potential, the ninth P-type TFT T9, the tenth P-type TFT T10, and the eleventh P-type TFT T11 are turned on, and the potential of the node A(N) is high.
  • the fourteenth N-type TFT T14 is turned on regardless of the potential of the second clock signal CK2 and the level-transmitted signal Q(N), and the potential of the node A(N) is low.
  • the output buffer module 5 includes a plurality of second inverters F2 connected in series for sequentially outputting the scan driving signal G(N) and increasing the driving capability of the scan driving signal G(N).
  • the output buffer module 5 includes three second inverters F2 connected in series in series. As shown in FIG. 8, the second inverter F2 is connected in series by a seventeenth P-type TFT T17.
  • the N-type TFT T18 is configured to electrically connect the gates of the seventeenth P-type TFT T17 and the eighteenth-type TFT T18 to form an input terminal K' of the second inverter F2, the seventeenth P The source of the TFT T17 is connected to the constant voltage high potential signal VGH, the source of the eighteenth N-type TFT T18 is connected to the constant voltage low potential signal VGL, and the seventeenth P-type TFT T17 and the eighteenth N
  • the drains of the TFTs T18 are electrically connected to each other to form an output terminal L' of the second inverter F2; the input terminal K' of the second inverter F2 closest to the signal processing module 4 is electrically connected to the node A ( N), the output L' of the second inverter F2 farthest from the signal processing module 4 outputs the scan driving signal G(N), and the output L' of the previous second inverter F2 is electrically connected to the second Input K' of inverter F2.
  • the scan driving signal G(N) When the potential of the node A(N) is low, the scan driving signal G(N) is high through the reverse action of the three second inverters F2 connected in series in the output buffer module 5; when the node A ( When the potential of N) is high, the scan drive signal G(N) is at a low potential by the reverse action of the three second inverters F2 connected in series in the output buffer module 5.
  • One end of the storage capacitor 7 is electrically connected to the level transmission signal Q(N), and the other end is grounded for storing the potential of the level transmission signal Q(N).
  • the global signal Gas includes a single pulse, and the single pulse is triggered before the GOA circuit operates normally.
  • the global signal Gas is at a high potential, the fourteenth N-type TFT T14 in each level of the GOA unit circuit is turned on, and the potential of the node A(N) in each level of the GOA unit circuit is low, and the GOA is in various stages.
  • the reverse action of the three second inverters F2 connected in series, the scan drive signals G(N) of all stages are simultaneously raised to a high potential; and the high-level global signal Gas is simultaneously Controlling the first NOR gate Y1 and the second NOR gate Y2 to output a low potential, the first P-type TFT T1 and the second P-type TFT T2 are turned on, and the drain of the second P-type TFT T2 outputs a high potential
  • the inverting stage transmits a signal XQ(N), and then pulls down the potential of each level of the signal Q(N) through the first inverter F1 in the latch module 3, and transmits a signal Q(N) to each level.
  • the storage capacitor 7 pairs the signal Q(N) The low potential is stored.
  • the global signal Gas transitions to a low potential, and since the storage capacitor 7 stores a low potential, the ninth P-type TFT T9 and the tenth P The TFT T10 is turned on, and the potential of the node A(N) is converted to a high potential, and the reverse action of the three second inverters F2 connected in series through the output buffer module 5 in each level of the GOA unit circuit, scanning at each level The drive signals G(N) all simultaneously transition to a low potential, avoiding the problem of sustaining the scan drive signal. After that, the CMOS GOA circuit works normally.
  • the above CMOS GOA circuit does not need to separately set the reset module, which eliminates additional components, routing, and reset signals, reduces the area of the GOA circuit, simplifies the complexity of the signal, and is advantageous for narrowing.
  • the design of the bezel panel by providing the storage capacitor 7, the low potential of the level transfer signal Q(N) is stored when all of the scan drive signals G(N) are simultaneously raised to a high potential, and then the low potential pairs stored by the storage capacitor 7 are used.
  • the stage scan driving signal G(N) is reset, so that the scanning drive signals G(N) of each stage are kept low, the stability of the GOA circuit is improved, and the risk of failure of the GOA circuit starting normal operation is avoided.
  • the first clock signal CK1 and the second clock signal CK2 may be in a high impedance state. After the global signal Gas transitions from a high potential to a low potential, the first clock signal CK1 is one pulse width ahead of the second clock signal CK2.
  • the first input terminal A of the first NOR gate Y1 is connected to the circuit enable signal STV.
  • the global signal Gas is low
  • the circuit start signal STV is low
  • the first clock signal CK1 is high
  • the first NOR gate Y1 outputs a high potential.
  • the second NOR gate Y2 outputs a low potential
  • the third N-type TFT T3 is turned on by the fourth N-type TFT T4, and the low-voltage inverted-phase signal XQ(1) is outputted from the drain of the third N-type TFT T3;
  • the level transfer signal Q(1) output by the first inverter F1 of the latch module 3 is at a high potential, and after the first clock signal CK1 transitions to a low potential, the stage transfer signal Q(1) is still latched.
  • the second stage GOA unit receives the level transfer signal Q(1) of the first stage GOA unit for scan driving, and so on, until the last stage GOA unit completes the scan drive.
  • the CMOS GOA circuit of the present invention has a first NOR gate and a second NOR gate in the input control module, and the two input terminals of the first NOR gate are respectively connected to the level of the upper level GOA unit. Transmitting the signal and the global signal, respectively connecting the two input ends of the second NOR gate to the first clock signal and the global signal, and when the global signal is high, controlling all the scan driving signals at the same time Is high, while controlling the first NOR gate and the second NOR gate to output a low potential, thereby controlling the inverting stage signal to be high, and then pulling down each of the first inverters in the latch module The potential of the level-level signal is used to clear and reset the signals transmitted at different levels.
  • the reset module Compared with the prior art, there is no need to separately set the reset module, eliminating the need for additional components, routing, and reset signals, and reducing the GOA.
  • the area of the circuit in addition, by setting the storage capacitor, the low-level potential of the level-transmitted signal is stored when all the scan drive signals are simultaneously raised to a high potential, and then the scan drive signals of the respective stages are reset by the low potential stored by the storage capacitor.
  • the scanning drive signal of each stage is kept low, the stability of the GOA circuit is improved, and the risk of failure of the GOA circuit starting normal operation is avoided.

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Abstract

一种CMOS GOA电路，在输入控制模块(1)中设置第一或非门(Y1)与第二或非门(Y2)，将第一或非门(Y1)的两输入端分别接入上一级GOA单元的级传信号(Q(N-1))与全局信号(Gas)，将第二或非门(Y2)的两输入端分别接入第一时钟信号(CK1)与全局信号(Gas)，当全局信号(Gas)为高电位时，控制各级扫描驱动信号(G(N))全部同时上升为高电位，同时控制第一或非门(Y1)与第二或非门(Y2)均输出低电位，从而控制反相级传信号(XQ(N))为高电位，再通过锁存模块(3)内的第一反相器(F1)拉低各级级传信号(Q(N))的电位，进行清零复位，无需单独设置复位模块，减小了GOA电路的面积；此外，通过设置存储电容(7)来提高电路的稳定性。

Description

CMOS GOA电路 技术领域
本发明涉及显示技术领域，尤其涉及一种CMOS GOA电路。
背景技术
GOA(Gate Driver on Array)技术即阵列基板行驱动技术，是利用薄膜晶体管(Thin Film Transistor，TFT)液晶显示器阵列制程将栅极扫描驱动电路制作在薄膜晶体管阵列基板上，以实现逐行扫描的驱动方式，具有降低生产成本和实现面板窄边框设计的优点，为多种显示器所使用。GOA电路具有两项基本功能：第一是输出扫描驱动信号，驱动面板内的栅极线，打开显示区内的TFT，以对像素进行充电；第二是移位寄存功能，当第N个扫描驱动信号输出完成后，通过时钟控制进行第N+1个扫描驱动信号的输出，并依次传递下去。
随着低温多晶硅(Low Temperature Poly-Silicon，LTPS)半导体薄膜晶体管的发展，LTPS TFT液晶显示器也越来越受关注。由于LTPS的硅结晶排列较非晶硅有次序，LTPS半导体具有超高的载流子迁移率，采用LTPS TFT的液晶显示器具有高分辨率、反应速度快、高亮度、高开口率等优点，相应的，LTPS TFT液晶显示器的面板周边集成电路也成为显示技术关注的焦点。
图1所示为一种现有的CMOS GOA电路，包括级联的多个GOA单元，该现有的CMOS GOA电路除了具备基本的扫描驱动功能与移位寄存功能以外，还带有使各级扫描驱动信号全部同时上升为高电位的功能。
设N为正整数，第N级GOA单元包括：输入控制模块100、锁存模块300、信号处理模块400、与输出缓冲模块500。
其中，输入控制模块100接入上一级GOA单元的级传信号Q(N-1)、第一时钟信号CK1、第一反相时钟信号XCK1、恒压高电位信号VGH、及恒压低电位信号VGL，将与上一级GOA单元的级传信号Q(N-1)电位相反的信号P(N)输入锁存模块300；
锁存模块300包括一反相器F，将信号P(N)反相后得到该第N级GOA单元的级传信号Q(N)，锁存模块300对级传信号Q(N)进行锁存；
信号处理模块400接入级传信号Q(N)、第二时钟信号CK2、恒压高电位信号VGH、恒压低电位信号VGL、及全局信号Gas；所述信号处理模 块400用于对第二时钟信号CK2与级传信号Q(N)做与非逻辑处理，以产生该第N级GOA单元的扫描驱动信号G(N)；对第二时钟信号CK2与级传信号Q(N)做与逻辑处理的结果和全局信号Gas进行或非逻辑处理，实现全局信号Gas控制各级扫描驱动信号全部同时上升为高电位。进一步地，全局信号Gas为高电位时控制各级扫描驱动信号全部同时上升为高电位；
所述输出缓冲模块500电性连接信号处理模块400，用于增加扫描驱动信号G(N)的驱动能力，减小信号传输过程中的阻容负载(RC Loading)。
上述现有的CMOS GOA电路，在实现All Gate On功能时，由于扫描驱动信号持续(Holding)的问题，必须在GOA电路正常工作之前，对级传信号和扫描驱动信号进行电位的复位清零处理，因此该现有的CMOS GOA电路的每一级GOA单元还包括一复位模块200。如图1所示，以第N级GOA单元为例，所述复位模块200包括一P型TFT，该P型TFT的栅极接入复位信号Reset，源极接入恒压高电位信号VGH，漏极连接锁存模块300内反相器F的输入端，当复位信号Reset输入一低电位时，所述P型TFT导通，所述反相器F对恒压高电位信号VGH进行反相，从而拉低级传信号Q(N)的电位，对级传信号Q(N)进行清零。单独设置复位模块200虽然会提高电路的性能，但由此附加的元件、走线、与信号却增大了GOA电路的面积，提高了信号复杂度，不利于窄边框面板的设计。
另外，在All Gate On期间，除了全局信号Gas、恒压高电位信号VGH、与恒压低电位信号VGL以外，其余的所有信号都处于高阻态(Floating)，以降低整个电路的待机功耗，此时，电路中各个节点的电位也都是不确定的，在GOA电路复机开始正常工作的时候，很可能会造成电路的失效。
发明内容
本发明的目的在于提供一种CMOS GOA电路，其不仅具有使各级扫描驱动信号全部同时上升为高电位的功能，还能够在不采用复位模块的情况下避免扫描驱动信号持续的问题，减小GOA电路的面积，提高GOA电路的稳定性，避免GOA电路开始正常工作时的失效风险。
为实现上述目的，本发明提供了一种CMOS GOA电路，包括级联的多个GOA单元；
设N为正整数，第N级GOA单元包括：输入控制模块、电性连接输入控制模块的锁存模块、电性连接锁存模块的信号处理模块、电性连接信号处理模块的输出缓冲模块、及电性连接锁存模块与信号处理模块的存储 电容；
所述输入控制模块接入上一级第N-1级GOA单元的级传信号、第一时钟信号、全局信号、恒压高电位信号、及恒压低电位信号；该输入控制模块包括第一或非门与第二或非门；所述第一或非门的第一输入端接入上一级第N-1级GOA单元的级传信号、第二输入端接入全局信号，输出端输出上一级第N-1级GOA单元的级传信号与全局信号的或非逻辑处理结果；所述第二或非门的第一输入端接入第一时钟信号、第二输入端接入全局信号，输出端将第一时钟信号与全局信号的或非逻辑处理结果作为第一反相时钟信号输出；所述输入控制模块用于将上一级第N-1级GOA单元的级传信号与全局信号的或非逻辑处理结果反相得到反相级传信号，并将反相级传信号输入锁存模块；
所述锁存模块包括一第一反相器，所述第一反相器的输入端输入反相级传信号，输出端输出级传信号；所述锁存模块用于对级传信号进行锁存；
所述信号处理模块接入级传信号、第二时钟信号、恒压高电位信号、恒压低电位信号、及全局信号，用于对第二时钟信号与级传信号做与非逻辑处理，以产生该第N级GOA单元的扫描驱动信号；对第二时钟信号与级传信号做与逻辑处理的结果和全局信号进行或非逻辑处理，实现全局信号控制各级扫描驱动信号全部同时上升为高电位；
所述输出缓冲模块包括依次串联的多个第二反相器，用于输出扫描驱动信号并增加扫描驱动信号的驱动能力；
所述存储电容的一端电性连接级传信号，另一端接地，用于存储级传信号的电位；
所述全局信号包含单个脉冲，其为高电位时，控制各级扫描驱动信号全部同时上升为高电位，同时控制所述第一或非门与第二或非门均输出低电位，从而控制反相级传信号为高电位，再通过所述锁存模块内的第一反相器拉低各级级传信号的电位，对各级级传信号进行清零复位。
所述输入控制模块还包括依次串联的第一P型TFT、第二P型TFT、第三N型TFT、与第四N型TFT；所述第一P型TFT的栅极接入第一反相时钟信号、源极接入恒压高电位信号；所述第二P型TFT与第三N型TFT的栅极均连接所述第一或非门的输出端；所述第二P型TFT与第三N型TFT的漏极相互连接，输出反相级传信号；所述第四N型TFT的栅极接入第一时钟信号、源极接入恒压低电位信号；
所述锁存模块还包括依次串联的第五P型TFT、第六P型TFT、第七N型TFT、与第八N型TFT；所述第五P型TFT的栅极接入第一时钟信号、 源极接入恒压高电位信号；所述第六P型TFT与第七N型TFT的栅极均接入级传信号；所述第六P型TFT与第七N型TFT的漏极相互连接，并电性连接所述第二P型TFT与第三N型TFT的漏极；所述第八N型TFT的栅极接入第一反相时钟信号、源极接入恒压低电位信号；
所述信号处理模块包括：第九P型TFT，所述第九P型TFT的栅极接入全局信号，源极接入恒压高电位信号；第十P型TFT，所述第十P型TFT的栅极接入级传信号，源极电性连接于第九P型TFT的漏极，漏极电性连接于节点；第十一P型TFT，所述第十一P型TFT的栅极接入第二时钟信号，源极电性连接于第九P型TFT的漏极，漏极电性连接于节点；第十二N型TFT，所述第十二N型TFT的栅极接入级传信号，漏极电性连接于节点；第十三N型TFT，所述第十三N型TFT的栅极接入第二时钟信号，漏极电性连接于所述第十二N型TFT的源极，源极接入恒压低电位信号；第十四N型TFT，所述第十四N型TFT的栅极接入全局信号，源极接入恒压低电位信号，漏极电性连接于节点。
所述输出缓冲模块包括依次串联的三个第二反相器，最靠近信号处理模块的第二反相器的输入端电性连接所述节点，最远离信号处理模块的第二反相器的输出端输出扫描驱动信号。
所述第一反相器由一第十五P型TFT串联一第十六N型TFT构成，所述第十五P型TFT与第十六N型TFT的栅极相互电性连接构成该第一反相器的输入端并输入反相级传信号，所述第十五P型TFT的源极接入恒压高电位信号，所述第十六N型TFT的源极接入恒压低电位信号，所述第十五P型TFT与第十六N型TFT的漏极相互电性连接构成该第一反相器的输出端并输出级传信号。
所述第二反相器由一第十七P型TFT串联一第十八N型TFT构成，所述第十七P型TFT与第十八N型TFT的栅极相互电性连接构成该第二反相器的输入端，所述第十七P型TFT的源极接入恒压高电位信号，所述第十八N型TFT的源极接入恒压低电位信号，所述第十七P型TFT与第十八N型TFT的漏极相互电性连接构成该第二反相器的输出端；前一个第二反相器的输出端电性连接后一个第二反相器的输入端。
所述第一或非门包括第十九P型TFT、第二十P型TFT、第二十一N型TFT、及第二十二N型TFT；所述第二十P型TFT与第二十一N型TFT的栅极相互电性连接构成该第一或非门的第一输入端并接入上一级第N-1级GOA单元的级传信号；所述第十九P型TFT与第二十二N型TFT的栅极相互电性连接构成该第一或非门的第二输入端并接入全局信号；所述第 十九P型TFT的源极接入恒压高电位信号，漏极电性连接第二十P型TFT的源极；所述第二十一N型TFT与第二十二N型TFT的源极均接入恒压低电位信号；所述第二十P型TFT第二十一N型TFT、及第二十二N型TFT的漏极相互电性连接构成该第一或非门的输出端并输出上一级第N-1级GOA单元的级传信号与全局信号的或非逻辑处理结果。
所述第二或非门包括二十三P型TFT、第二十四P型TFT、第二十五N型TFT、及第二十六N型TFT；所述第二十四P型TFT与第二十五N型TFT的栅极相互电性连接构成该第二或非门的第一输入端并接入第一时钟信号；所述第二十三P型TFT与第二十六N型TFT的栅极相互电性连接构成该第二或非门的第二输入端并接入全局信号；所述第二十三P型TFT的源极接入恒压高电位信号，漏极电性连接第二十四P型TFT的源极；所述第二十五N型TFT与第二十六N型TFT的源极均接入恒压低电位信号；所述第二十四P型TFT、第二十五N型TFT、及第二十六N型TFT的漏极相互电性连接构成该第二或非门的输出端并输出第一反相时钟信号。
在第一级GOA单元中，所述第一或非门的第一输入端接入电路启动信号。
本发明还提供一种CMOS GOA电路，包括级联的多个GOA单元；
设N为正整数，第N级GOA单元包括：输入控制模块、电性连接输入控制模块的锁存模块、电性连接锁存模块的信号处理模块、电性连接信号处理模块的输出缓冲模块、及电性连接锁存模块与信号处理模块的存储电容；
所述输入控制模块接入上一级第N-1级GOA单元的级传信号、第一时钟信号、全局信号、恒压高电位信号、及恒压低电位信号；该输入控制模块包括第一或非门与第二或非门；所述第一或非门的第一输入端接入上一级第N-1级GOA单元的级传信号、第二输入端接入全局信号，输出端输出上一级第N-1级GOA单元的级传信号与全局信号的或非逻辑处理结果；所述第二或非门的第一输入端接入第一时钟信号、第二输入端接入全局信号，输出端将第一时钟信号与全局信号的或非逻辑处理结果作为第一反相时钟信号输出；所述输入控制模块用于将上一级第N-1级GOA单元的级传信号与全局信号的或非逻辑处理结果反相得到反相级传信号，并将反相级传信号输入锁存模块；
所述锁存模块包括一第一反相器，所述第一反相器的输入端输入反相级传信号，输出端输出级传信号；所述锁存模块用于对级传信号进行锁存；
所述信号处理模块接入级传信号、第二时钟信号、恒压高电位信号、 恒压低电位信号、及全局信号，用于对第二时钟信号与级传信号做与非逻辑处理，以产生该第N级GOA单元的扫描驱动信号；对第二时钟信号与级传信号做与逻辑处理的结果和全局信号进行或非逻辑处理，实现全局信号控制各级扫描驱动信号全部同时上升为高电位；
所述输出缓冲模块包括依次串联的多个第二反相器，用于输出扫描驱动信号并增加扫描驱动信号的驱动能力；
所述存储电容的一端电性连接级传信号，另一端接地，用于存储级传信号的电位；
所述全局信号包含单个脉冲，其为高电位时，控制各级扫描驱动信号全部同时上升为高电位，同时控制所述第一或非门与第二或非门均输出低电位，从而控制反相级传信号为高电位，再通过所述锁存模块内的第一反相器拉低各级级传信号的电位，对各级级传信号进行清零复位；
其中，所述输入控制模块还包括依次串联的第一P型TFT、第二P型TFT、第三N型TFT、与第四N型TFT；所述第一P型TFT的栅极接入第一反相时钟信号、源极接入恒压高电位信号；所述第二P型TFT与第三N型TFT的栅极均连接所述第一或非门的输出端；所述第二P型TFT与第三N型TFT的漏极相互连接，输出反相级传信号；所述第四N型TFT的栅极接入第一时钟信号、源极接入恒压低电位信号；
所述锁存模块还包括依次串联的第五P型TFT、第六P型TFT、第七N型TFT、与第八N型TFT；所述第五P型TFT的栅极接入第一时钟信号、源极接入恒压高电位信号；所述第六P型TFT与第七N型TFT的栅极均接入级传信号；所述第六P型TFT与第七N型TFT的漏极相互连接，并电性连接所述第二P型TFT与第三N型TFT的漏极；所述第八N型TFT的栅极接入第一反相时钟信号、源极接入恒压低电位信号；
所述信号处理模块包括：第九P型TFT，所述第九P型TFT的栅极接入全局信号，源极接入恒压高电位信号；第十P型TFT，所述第十P型TFT的栅极接入级传信号，源极电性连接于第九P型TFT的漏极，漏极电性连接于节点；第十一P型TFT，所述第十一P型TFT的栅极接入第二时钟信号，源极电性连接于第九P型TFT的漏极，漏极电性连接于节点；第十二N型TFT，所述第十二N型TFT的栅极接入级传信号，漏极电性连接于节点；第十三N型TFT，所述第十三N型TFT的栅极接入第二时钟信号，漏极电性连接于所述第十二N型TFT的源极，源极接入恒压低电位信号；第十四N型TFT，所述第十四N型TFT的栅极接入全局信号，源极接入恒压低电位信号，漏极电性连接于节点；
其中，所述第一或非门包括第十九P型TFT、第二十P型TFT、第二十一N型TFT、及第二十二N型TFT；所述第二十P型TFT与第二十一N型TFT的栅极相互电性连接构成该第一或非门的第一输入端并接入上一级第N-1级GOA单元的级传信号；所述第十九P型TFT与第二十二N型TFT的栅极相互电性连接构成该第一或非门的第二输入端并接入全局信号；所述第十九P型TFT的源极接入恒压高电位信号，漏极电性连接第二十P型TFT的源极；所述第二十一N型TFT与第二十二N型TFT的源极均接入恒压低电位信号；所述第二十P型TFT、第二十一N型TFT、及第二十二N型TFT的漏极相互电性连接构成该第一或非门的输出端并输出上一级第N-1级GOA单元的级传信号与全局信号的或非逻辑处理结果；
其中，所述第二或非门包括二十三P型TFT、第二十四P型TFT、第二十五N型TFT、及第二十六N型TFT；所述第二十四P型TFT与第二十五N型TFT的栅极相互电性连接构成该第二或非门的第一输入端并接入第一时钟信号；所述第二十三P型TFT与第二十六N型TFT的栅极相互电性连接构成该第二或非门的第二输入端并接入全局信号；所述第二十三P型TFT的源极接入恒压高电位信号，漏极电性连接第二十四P型TFT的源极；所述第二十五N型TFT与第二十六N型TFT的源极均接入恒压低电位信号；所述第二十四P型TFT、第二十五N型TFT、及第二十六N型TFT的漏极相互电性连接构成该第二或非门的输出端并输出第一反相时钟信号。
本发明的有益效果：本发明提供的一种CMOS GOA电路，在输入控制模块中设置第一或非门与第二或非门，将第一或非门的两输入端分别接入上一级GOA单元的级传信号与全局信号，将第二或非门的两输入端分别接入第一时钟信号与全局信号，当全局信号为高电位时，控制各级扫描驱动信号全部同时上升为高电位，同时控制所述第一或非门与第二或非门均输出低电位，从而控制反相级传信号为高电位，再通过锁存模块内的第一反相器拉低各级级传信号的电位，对各级级传信号进行清零复位，与现有技术相比，不需要单独设置复位模块，省去了附加的元件、走线、与复位信号，减小了GOA电路的面积；此外，通过设置存储电容在各级扫描驱动信号全部同时上升为高电位时对级传信号的低电位进行存储，然后利用存储电容所存储的低电位对各级扫描驱动信号进行复位，使得各级扫描驱动信号保持低电位，提高了GOA电路的稳定性，避免GOA电路开始正常工作时的失效风险。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本 发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为一种现有的CMOS GOA电路的电路图；
图2为本发明的CMOS GOA电路的电路图；
图3为本发明的CMOS GOA电路的第一级GOA单元的电路图；
图4为本发明的CMOS GOA电路的工作时序图；
图5为本发明的CMOS GOA电路的输入控制模块中第一或非门的具体电路结构示意图；
图6为本发明的CMOS GOA电路的输入控制模块中第二或非门的具体电路结构示意图；
图7为本发明的CMOS GOA电路的锁存模块中第一反相器的具体电路结构示意图；
图8为本发明的CMOS GOA电路的输出缓冲模块中依次串联的三个第二反相器的具体电路结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请同时参阅图2与图4，本发明提供一种CMOS GOA电路，包括级联的多个GOA单元，每一级GOA单元均采用多个N型TFT与多个P型TFT，且各个TFT均为低温多晶硅半导体薄膜晶体管。设N为正整数，第N级GOA单元包括：输入控制模块1、电性连接输入控制模块1的锁存模块3、电性连接锁存模块3的信号处理模块4、电性连接信号处理模块4的输出缓冲模块5、及电性连接锁存模块3与信号处理模块4的存储电容7。
所述输入控制模块1接入上一级第N-1级GOA单元的级传信号Q(N-1)、第一时钟信号CK1、全局信号Gas、恒压高电位信号VGH、及恒压低电位信号VGL。该输入控制模块1包括第一或非门Y1与第二或非门Y2；所述第一或非门Y1的第一输入端A接入上一级第N-1级GOA单元的级传信号Q(N-1)、第二输入端B接入全局信号Gas，输出端D输出上一 级第N-1级GOA单元的级传信号Q(N-1)与全局信号Gas的或非逻辑处理结果；所述第二或非门Y2的第一输入端A’接入第一时钟信号CK1、第二输入端B’接入全局信号Gas，输出端D’将第一时钟信号CK1与全局信号Gas的或非逻辑处理结果作为第一反相时钟信号XCK1输出。所述输入控制模块1用于将上一级第N-1级GOA单元的级传信号Q(N-1)与全局信号Gas的或非逻辑处理结果反相得到反相级传信号XQ(N)，并将反相级传信号XQ(N)输入锁存模块3。具体地，所述输入控制模块1还包括依次串联的第一P型TFT T1、第二P型TFT T2、第三N型TFT T3、与第四N型TFT T4：所述第一P型TFT T1的栅极接入第一反相时钟信号XCK1、源极接入恒压高电位信号VGH；所述第二P型TFT T2与第三N型TFT T3的栅极均连接所述第一或非门Y1的输出端D；所述第二P型TFT T2与第三N型TFT T3的漏极相互连接，输出反相级传信号XQ(N)；所述第四N型TFT T4的栅极接入第一时钟信号CK1、源极接入恒压低电位信号VGL。
进一步地，所述第一或非门Y1的具体电路结构如图5所示，包括第十九P型TFT T19、第二十P型TFT T20、第二十一N型TFT T21、及第二十二N型TFT T22；所述第二十P型TFT T20与第二十一N型TFT T21的栅极相互电性连接构成该第一或非门Y1的第一输入端A并接入上一级第N-1级GOA单元的级传信号Q(N-1)；所述第十九P型TFT T19与第二十二N型TFT T22的栅极相互电性连接构成该第一或非门Y1的第二输入端B并接入全局信号Gas；所述第十九P型TFT T19的源极接入恒压高电位信号VGH，漏极电性连接第二十P型TFT T20的源极；所述第二十一N型TFT T21与第二十二N型TFT T22的源极均接入恒压低电位信号VGL；所述第二十P型TFT T20、第二十一N型TFT T21、及第二十二N型TFT T22的漏极相互电性连接构成该第一或非门Y1的输出端D并输出上一级第N-1级GOA单元的级传信号Q(N-1)与全局信号Gas的或非逻辑处理结果。
所述第二或非门Y2的具体电路结构如图6所示，包括二十三P型TFT T23、第二十四P型TFT T24、第二十五N型TFT T25、及第二十六N型TFT T26；所述第二十四P型TFT T24与第二十五N型TFT T25的栅极相互电性连接构成该第二或非门Y2的第一输入端A’并接入第一时钟信号CK1；所述第二十三P型TFT T23与第二十六N型TFT T26的栅极相互电性连接构成该第二或非门Y2的第二输入端B’并接入全局信号Gas；所述第二十三P型TFT T23的源极接入恒压高电位信号VGH，漏极电性连接第二十四P型TFT T24的源极；所述第二十五N型TFT T25与第二十六N型TFT T26的源极均接入恒压低电位信号VGL；所述第二十四P型TFT T24、 第二十五N型TFT T25、及第二十六N型TFT T26的漏极相互电性连接构成该第二或非门Y2的输出端D’并输出第一反相时钟信号XCK1。
对于或非门来说，只要两个输入信号中至少一个输入信号为高电位时，经过或非逻辑处理，输出信号即为低电位。举例说明如下：若第一或非门Y1的第二输入端B接入的全局信号Gas为低电位，则在第一或非门Y1的第一输入端A接入的上一级第N-1级GOA单元的级传信号Q(N-1)为高电位的情况下，第一或非门Y1的输出端D输出低电位，在第一或非门Y1的第一输入端A接入的上一级第N-1级GOA单元的级传信号Q(N-1)为低电位的情况下，第一或非门Y1的输出端D输出高电位；若第一或非门Y1的第二输入端B接入的全局信号Gas为高电位，则无论第一或非门Y1的第一输入端A接入的上一级第N-1级GOA单元的级传信号Q(N-1)处于什么电位，第一或非门Y1的输出端D均输出低电位。若第二或非门Y2的第二输入端B’接入的全局信号Gas为低电位，则在第二或非门Y2的第一输入端A’接入的第一时钟信号CK1为高电位的情况下，第二或非门Y2的输出端D’输出的第一反相时钟信号XCK1为低电位，在第二或非门Y2的第一输入端A’接入的第一时钟信号CK1为低电位的情况下，第二或非门Y2的输出端D’输出的第一反相时钟信号XCK1为高电位；若第二或非门Y2的第二输入端B’接入的全局信号Gas为高电位，则无论第二或非门Y2的第一输入端A’接入的第一时钟信号CK1处于什么电位，第二或非门Y2的输出端D’输出的第一反相时钟信号XCK1均为低电位。在第一或非门Y1输出高电位、第一时钟信号CK1为高电位的情况下，第三N型TFT T3与第四N型TFT T4导通，由第三N型TFT T3的漏极输出低电位的反相级传信号XQ(N)；在第一或非门Y1输出低电位、第一反相时钟信号XCK1为低电位的情况下，第一P型TFT T1与第二P型TFT T2导通，由第二P型TFT T2的漏极输出高电位的反相级传信号XQ(N)。
所述锁存模块3包括一第一反相器F1，所述第一反相器F1的输入端K输入反相级传信号XQ(N)，输出端L输出级传信号(Q(N))。所述锁存模块3还包括依次串联的第五P型TFT T5、第六P型TFT T6、第七N型TFT T7、与第八N型TFT T8；所述第五P型TFT T5的栅极接入第一时钟信号CK1、源极接入恒压高电位信号VGH；所述第六P型TFT T6与第七N型TFT T7的栅极均接入级传信号Q(N)；所述第六P型TFT T6与第七N型TFT T7的漏极相互连接，并电性连接所述第二P型TFT T2与第三N型TFT T3的漏极；所述第八N型TFT T8的栅极接入第一反相时钟信号XCK1、源极接入恒压低电位信号VGL。所述第一反相器F1的具体电路结 构如图7所示，由一第十五P型TFT T15串联一第十六N型TFT T16构成，所述第十五P型TFT T15与第十六N型TFT T16的栅极相互电性连接构成该第一反相器F1的输入端K并输入反相级传信号XQ(N)，所述第十五P型TFT T15的源极接入恒压高电位信号VGH，所述第十六N型TFT T16的源极接入恒压低电位信号VGL，所述第十五P型TFT T15与第十六N型TFT T16的漏极相互电性连接构成该第一反相器F1的输出端L并输出级传信号Q(N)。对于反相器来说，在其输入信号为高电位时，输出信号为低电位，而在其输入信号为低电位时，输出信号为高电位。在第一时钟信号CK1转变为低电位时，若级传信号Q(N)为高电位，则第七N型TFT T7与受第一反相时钟信号XCK1控制的第八N型TFT T8导通，由第七N型TFT T7的漏极输出低电位，即保持反相级传信号XQ(N)为低电位，所述第一反相器F1输出的级传信号Q(N)仍为高电位，实现了对级传信号Q(N)的锁存；若级传信号Q(N)为低电位，则第六P型TFT T6与受第一时钟信号CK1控制的第五P型TFT T5导通，由第六P型TFT T6的漏极输出高电位，即保持反相级传信号XQ(N)为高电位，所述第一反相器F1输出的级传信号Q(N)仍为低电位，实现了对级传信号Q(N)的锁存。
所述信号处理模块4接入级传信号Q(N)、第二时钟信号CK2、恒压高电位信号VGH、恒压低电位信号VGL、及全局信号Gas，用于对第二时钟信号CK2与级传信号Q(N)做与非逻辑处理，以产生该第N级GOA单元的扫描驱动信号G(N)；对第二时钟信号CK2与级传信号Q(N)做与逻辑处理的结果和全局信号Gas进行或非逻辑处理，实现全局信号Gas控制各级扫描驱动信号G(N)全部同时上升为高电位。具体地，所述信号处理模块4包括：第九P型TFT T9，所述第九P型TFTT9的栅极接入全局信号Gas，源极接入恒压高电位信号VGH；第十P型TFT T10，所述第十P型TFT T10的栅极接入级传信号Q(N)，源极电性连接于第九P型TFT T9的漏极，漏极电性连接于节点A(N)；第十一P型TFT T11，所述第十一P型TFT T11的栅极接入第二时钟信号CK2，源极电性连接于第九P型TFT T9的漏极，漏极电性连接于节点A(N)；第十二N型TFT T12，所述第十二N型TFT T12的栅极接入级传信号Q(N)，漏极电性连接于节点A(N)；第十三N型TFT T13，所述第十三N型TFT T13的栅极接入第二时钟信号CK2，漏极电性连接于所述第十二N型TFT T12的源极，源极接入恒压低电位信号VGL；第十四N型TFT T14，所述第十四N型TFT T14的栅极接入全局信号Gas，源极接入恒压低电位信号VGL，漏极电性连接于节点A(N)。进一步地，当全局信号Gas为低电位时：在第二时钟信号CK2与级 传信号Q(N)均为高电位的情况下，第十二N型TFT T12与第十三N型TFT T13导通，节点A(N)的电位为低电位；在第二时钟信号CK2与级传信号Q(N)均为低电位的情况下，第九P型TFTT9、第十P型TFT T10、与第十一P型TFTT11导通，节点A(N)的电位为高电位。而当全局信号Gas为高电位时，不管第二时钟信号CK2与级传信号Q(N)处于什么电位，第十四N型TFT T14导通，节点A(N)的电位为低电位。
所述输出缓冲模块5包括依次串联的多个第二反相器F2，用于输出扫描驱动信号G(N)并增加扫描驱动信号G(N)的驱动能力。优选的，所述输出缓冲模块5包括依次串联的三个第二反相器F2，如图8所示，所述第二反相器F2由一第十七P型TFT T17串联一第十八N型TFT T18构成，所述第十七P型TFT T17与第十八N型TFT T18的栅极相互电性连接构成该第二反相器F2的输入端K’，所述第十七P型TFT T17的源极接入恒压高电位信号VGH，所述第十八N型TFT T18的源极接入恒压低电位信号VGL，所述第十七P型TFT T17与第十八N型TFT T18的漏极相互电性连接构成该第二反相器F2的输出端L’；最靠近信号处理模块4的第二反相器F2的输入端K’电性连接所述节点A(N)，最远离信号处理模块4的第二反相器F2的输出端L’输出扫描驱动信号G(N)，前一个第二反相器F2的输出端L’电性连接后一个第二反相器F2的输入端K’。当节点A(N)的电位为低电位时，经输出缓冲模块5内依次串联的三个第二反相器F2的反向作用，扫描驱动信号G(N)为高电位；当节点A(N)的电位为高电位时，经输出缓冲模块5内依次串联的三个第二反相器F2的反向作用，扫描驱动信号G(N)为低电位。
所述存储电容7的一端电性连接级传信号Q(N)，另一端接地，用于存储级传信号Q(N)的电位。
特别需要说明的是，所述全局信号Gas包含单个脉冲，且该单个脉冲在GOA电路正常工作之前触发。当所述全局信号Gas为高电位时，各级GOA单元电路中的第十四N型TFT T14导通，各级GOA单元电路中的节点A(N)的电位为低电位，经各级GOA单元电路中的输出缓冲模块5内依次串联的三个第二反相器F2的反向作用，各级扫描驱动信号G(N)全部同时上升为高电位；同时所述高电位的全局信号Gas控制所述第一或非门Y1与第二或非门Y2均输出低电位，第一P型TFT T1与第二P型TFT T2导通，由第二P型TFT T2的漏极输出高电位的反相级传信号XQ(N)，再通过所述锁存模块3内的第一反相器F1拉低各级级传信号Q(N)的电位，对各级级传信号Q(N)进行清零复位，此时，存储电容7对级传信号Q(N) 的低电位进行存储。在使各级扫描驱动信号G(N)全部同时上升为高电位的功能作用完毕之后，全局信号Gas转变为低电位，由于存储电容7存储了低电位，第九P型TFT T9与第十P型TFT T10导通，节点A(N)的电位转变为高电位，经各级GOA单元电路中的输出缓冲模块5内依次串联的三个第二反相器F2的反向作用，各级扫描驱动信号G(N)全部同时转变为低电位，避免了扫描驱动信号持续的问题。之后，CMOS GOA电路正常工作。
与现有技术相比，上述CMOS GOA电路，不需要单独设置复位模块，省去了附加的元件、走线、与复位信号，减小了GOA电路的面积，简化了信号的复杂度，利于窄边框面板的设计。另外，通过设置存储电容7在各级扫描驱动信号G(N)全部同时上升为高电位时对级传信号Q(N)的低电位进行存储，然后利用存储电容7所存储的低电位对各级扫描驱动信号G(N)进行复位，使得各级扫描驱动信号G(N)保持低电位，提高了GOA电路的稳定性，避免GOA电路开始正常工作时的失效风险。
值得一提的是，当所述全局信号Gas为高电位时，所述第一时钟信号CK1与第二时钟信号CK2均可处于高阻态。所述全局信号Gas由高电位转变为低电位后，所述第一时钟信号CK1比第二时钟信号CK2提前一个脉宽。
特别地，如图3所示，在第一级GOA单元中，所述第一或非门Y1的第一输入端A接入电路启动信号STV。结合图3与图4，当CMOS GOA开始电路正常工作时，全局信号Gas为低电位，电路启动信号STV为低电位，第一时钟信号CK1为高电位，第一或非门Y1输出高电位，第二或非门Y2输出低电位，第三N型TFT T3与第四N型TFT T4导通，由第三N型TFT T3的漏极输出低电位的反相级传信号XQ(1)；所述锁存模块3的第一反相器F1输出的级传信号Q(1)为高电位，且在第一时钟信号CK1转变为低电位后，仍锁存级传信号Q(1)的高电位；随着第二时钟信号CK2为高电位，第十二N型TFT T12与第十三N型TFT T13导通，节点A(1)的电位为低电位；经输出缓冲模块5内依次串联的三个第二反相器F2的反向作用，扫描驱动信号G(1)为高电位。之后，第二级GOA单元接收第一级GOA单元的级传信号Q(1)进行扫描驱动，以此类推，直至最后一级GOA单元完成扫描驱动。
综上所述，本发明的CMOS GOA电路，在输入控制模块中设置第一或非门与第二或非门，将第一或非门的两输入端分别接入上一级GOA单元的级传信号与全局信号，将第二或非门的两输入端分别接入第一时钟信号与全局信号，当全局信号为高电位时，控制各级扫描驱动信号全部同时上升 为高电位，同时控制所述第一或非门与第二或非门均输出低电位，从而控制反相级传信号为高电位，再通过锁存模块内的第一反相器拉低各级级传信号的电位，对各级级传信号进行清零复位，与现有技术相比，不需要单独设置复位模块，省去了附加的元件、走线、与复位信号，减小了GOA电路的面积；此外，通过设置存储电容在各级扫描驱动信号全部同时上升为高电位时对级传信号的低电位进行存储，然后利用存储电容所存储的低电位对各级扫描驱动信号进行复位，使得各级扫描驱动信号保持低电位，提高了GOA电路的稳定性，避免GOA电路开始正常工作时的失效风险。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (13)

  1. 一种CMOS GOA电路，包括级联的多个GOA单元；
    设N为正整数，第N级GOA单元包括：输入控制模块、电性连接输入控制模块的锁存模块、电性连接锁存模块的信号处理模块、电性连接信号处理模块的输出缓冲模块、及电性连接锁存模块与信号处理模块的存储电容；
    所述输入控制模块接入上一级第N-1级GOA单元的级传信号、第一时钟信号、全局信号、恒压高电位信号、及恒压低电位信号；该输入控制模块包括第一或非门与第二或非门；所述第一或非门的第一输入端接入上一级第N-1级GOA单元的级传信号、第二输入端接入全局信号，输出端输出上一级第N-1级GOA单元的级传信号与全局信号的或非逻辑处理结果；所述第二或非门的第一输入端接入第一时钟信号、第二输入端接入全局信号，输出端将第一时钟信号与全局信号的或非逻辑处理结果作为第一反相时钟信号输出；所述输入控制模块用于将上一级第N-1级GOA单元的级传信号与全局信号的或非逻辑处理结果反相得到反相级传信号，并将反相级传信号输入锁存模块；
    所述锁存模块包括一第一反相器，所述第一反相器的输入端输入反相级传信号，输出端输出级传信号；所述锁存模块用于对级传信号进行锁存；
    所述信号处理模块接入级传信号、第二时钟信号、恒压高电位信号、恒压低电位信号、及全局信号，用于对第二时钟信号与级传信号做与非逻辑处理，以产生该第N级GOA单元的扫描驱动信号；对第二时钟信号与级传信号做与逻辑处理的结果和全局信号进行或非逻辑处理，实现全局信号控制各级扫描驱动信号全部同时上升为高电位；
    所述输出缓冲模块包括依次串联的多个第二反相器，用于输出扫描驱动信号并增加扫描驱动信号的驱动能力；
    所述存储电容的一端电性连接级传信号，另一端接地，用于存储级传信号的电位；
    所述全局信号包含单个脉冲，其为高电位时，控制各级扫描驱动信号全部同时上升为高电位，同时控制所述第一或非门与第二或非门均输出低电位，从而控制反相级传信号为高电位，再通过所述锁存模块内的第一反相器拉低各级级传信号的电位，对各级级传信号进行清零复位。
  2. 如权利要求1所述的CMOS GOA电路，其中，所述输入控制模块 还包括依次串联的第一P型TFT、第二P型TFT、第三N型TFT、与第四N型TFT；所述第一P型TFT的栅极接入第一反相时钟信号、源极接入恒压高电位信号；所述第二P型TFT与第三N型TFT的栅极均连接所述第一或非门的输出端；所述第二P型TFT与第三N型TFT的漏极相互连接，输出反相级传信号；所述第四N型TFT的栅极接入第一时钟信号、源极接入恒压低电位信号；
    所述锁存模块还包括依次串联的第五P型TFT、第六P型TFT、第七N型TFT、与第八N型TFT；所述第五P型TFT的栅极接入第一时钟信号、源极接入恒压高电位信号；所述第六P型TFT与第七N型TFT的栅极均接入级传信号；所述第六P型TFT与第七N型TFT的漏极相互连接，并电性连接所述第二P型TFT与第三N型TFT的漏极；所述第八N型TFT的栅极接入第一反相时钟信号、源极接入恒压低电位信号；
    所述信号处理模块包括：第九P型TFT，所述第九P型TFT的栅极接入全局信号，源极接入恒压高电位信号；第十P型TFT，所述第十P型TFT的栅极接入级传信号，源极电性连接于第九P型TFT的漏极，漏极电性连接于节点；第十一P型TFT，所述第十一P型TFT的栅极接入第二时钟信号，源极电性连接于第九P型TFT的漏极，漏极电性连接于节点；第十二N型TFT，所述第十二N型TFT的栅极接入级传信号，漏极电性连接于节点；第十三N型TFT，所述第十三N型TFT的栅极接入第二时钟信号，漏极电性连接于所述第十二N型TFT的源极，源极接入恒压低电位信号；第十四N型TFT，所述第十四N型TFT的栅极接入全局信号，源极接入恒压低电位信号，漏极电性连接于节点。
  3. 如权利要求2所述的CMOS GOA电路，其中，所述输出缓冲模块包括依次串联的三个第二反相器，最靠近信号处理模块的第二反相器的输入端电性连接所述节点，最远离信号处理模块的第二反相器的输出端输出扫描驱动信号。
  4. 如权利要求1所述的CMOS GOA电路，其中，所述第一反相器由一第十五P型TFT串联一第十六N型TFT构成，所述第十五P型TFT与第十六N型TFT的栅极相互电性连接构成该第一反相器的输入端并输入反相级传信号，所述第十五P型TFT的源极接入恒压高电位信号，所述第十六N型TFT的源极接入恒压低电位信号，所述第十五P型TFT与第十六N型TFT的漏极相互电性连接构成该第一反相器的输出端并输出级传信号。
  5. 如权利要求3所述的CMOS GOA电路，其中，所述第二反相器由一第十七P型TFT串联一第十八N型TFT构成，所述第十七P型TFT与 第十八N型TFT的栅极相互电性连接构成该第二反相器的输入端，所述第十七P型TFT的源极接入恒压高电位信号，所述第十八N型TFT的源极接入恒压低电位信号，所述第十七P型TFT与第十八N型TFT的漏极相互电性连接构成该第二反相器的输出端；前一个第二反相器的输出端电性连接后一个第二反相器的输入端。
  6. 如权利要求1所述的CMOS GOA电路，其中，所述第一或非门包括第十九P型TFT、第二十P型TFT、第二十一N型TFT、及第二十二N型TFT；所述第二十P型TFT与第二十一N型TFT的栅极相互电性连接构成该第一或非门的第一输入端并接入上一级第N-1级GOA单元的级传信号；所述第十九P型TFT与第二十二N型TFT的栅极相互电性连接构成该第一或非门的第二输入端并接入全局信号；所述第十九P型TFT的源极接入恒压高电位信号，漏极电性连接第二十P型TFT的源极；所述第二十一N型TFT与第二十二N型TFT的源极均接入恒压低电位信号；所述第二十P型TFT、第二十一N型TFT、及第二十二N型TFT的漏极相互电性连接构成该第一或非门的输出端并输出上一级第N-1级GOA单元的级传信号与全局信号的或非逻辑处理结果。
  7. 如权利要求1所述的CMOS GOA电路，其中，所述第二或非门包括二十三P型TFT、第二十四P型TFT、第二十五N型TFT、及第二十六N型TFT；所述第二十四P型TFT与第二十五N型TFT的栅极相互电性连接构成该第二或非门的第一输入端并接入第一时钟信号；所述第二十三P型TFT与第二十六N型TFT的栅极相互电性连接构成该第二或非门的第二输入端并接入全局信号；所述第二十三P型TFT的源极接入恒压高电位信号，漏极电性连接第二十四P型TFT的源极；所述第二十五N型TFT与第二十六N型TFT的源极均接入恒压低电位信号；所述第二十四P型TFT、第二十五N型TFT、及第二十六N型TFT的漏极相互电性连接构成该第二或非门的输出端并输出第一反相时钟信号。
  8. 如权利要求2所述的CMOS GOA电路，其中，在第一级GOA单元中，所述第一或非门的第一输入端接入电路启动信号。
  9. 一种CMOS GOA电路，包括级联的多个GOA单元；
    设N为正整数，第N级GOA单元包括：输入控制模块、电性连接输入控制模块的锁存模块、电性连接锁存模块的信号处理模块、电性连接信号处理模块的输出缓冲模块、及电性连接锁存模块与信号处理模块的存储电容；
    所述输入控制模块接入上一级第N-1级GOA单元的级传信号、第一时 钟信号、全局信号、恒压高电位信号、及恒压低电位信号；该输入控制模块包括第一或非门与第二或非门；所述第一或非门的第一输入端接入上一级第N-1级GOA单元的级传信号、第二输入端接入全局信号，输出端输出上一级第N-1级GOA单元的级传信号与全局信号的或非逻辑处理结果；所述第二或非门的第一输入端接入第一时钟信号、第二输入端接入全局信号，输出端将第一时钟信号与全局信号的或非逻辑处理结果作为第一反相时钟信号输出；所述输入控制模块用于将上一级第N-1级GOA单元的级传信号与全局信号的或非逻辑处理结果反相得到反相级传信号，并将反相级传信号输入锁存模块；
    所述锁存模块包括一第一反相器，所述第一反相器的输入端输入反相级传信号，输出端输出级传信号；所述锁存模块用于对级传信号进行锁存；
    所述信号处理模块接入级传信号、第二时钟信号、恒压高电位信号、恒压低电位信号、及全局信号，用于对第二时钟信号与级传信号做与非逻辑处理，以产生该第N级GOA单元的扫描驱动信号；对第二时钟信号与级传信号做与逻辑处理的结果和全局信号进行或非逻辑处理，实现全局信号控制各级扫描驱动信号全部同时上升为高电位；
    所述输出缓冲模块包括依次串联的多个第二反相器，用于输出扫描驱动信号并增加扫描驱动信号的驱动能力；
    所述存储电容的一端电性连接级传信号，另一端接地，用于存储级传信号的电位；
    所述全局信号包含单个脉冲，其为高电位时，控制各级扫描驱动信号全部同时上升为高电位，同时控制所述第一或非门与第二或非门均输出低电位，从而控制反相级传信号为高电位，再通过所述锁存模块内的第一反相器拉低各级级传信号的电位，对各级级传信号进行清零复位；
    其中，所述输入控制模块还包括依次串联的第一P型TFT、第二P型TFT、第三N型TFT、与第四N型TFT；所述第一P型TFT的栅极接入第一反相时钟信号、源极接入恒压高电位信号；所述第二P型TFT与第三N型TFT的栅极均连接所述第一或非门的输出端；所述第二P型TFT与第三N型TFT的漏极相互连接，输出反相级传信号；所述第四N型TFT的栅极接入第一时钟信号、源极接入恒压低电位信号；
    所述锁存模块还包括依次串联的第五P型TFT、第六P型TFT、第七N型TFT、与第八N型TFT；所述第五P型TFT的栅极接入第一时钟信号、源极接入恒压高电位信号；所述第六P型TFT与第七N型TFT的栅极均接入级传信号；所述第六P型TFT与第七N型TFT的漏极相互连接，并电性 连接所述第二P型TFT与第三N型TFT的漏极；所述第八N型TFT的栅极接入第一反相时钟信号、源极接入恒压低电位信号；
    所述信号处理模块包括：第九P型TFT，所述第九P型TFT的栅极接入全局信号，源极接入恒压高电位信号；第十P型TFT，所述第十P型TFT的栅极接入级传信号，源极电性连接于第九P型TFT的漏极，漏极电性连接于节点；第十一P型TFT，所述第十一P型TFT的栅极接入第二时钟信号，源极电性连接于第九P型TFT的漏极，漏极电性连接于节点；第十二N型TFT，所述第十二N型TFT的栅极接入级传信号，漏极电性连接于节点；第十三N型TFT，所述第十三N型TFT的栅极接入第二时钟信号，漏极电性连接于所述第十二N型TFT的源极，源极接入恒压低电位信号；第十四N型TFT，所述第十四N型TFT的栅极接入全局信号，源极接入恒压低电位信号，漏极电性连接于节点；
    其中，所述第一或非门包括第十九P型TFT、第二十P型TFT、第二十一N型TFT、及第二十二N型TFT；所述第二十P型TFT与第二十一N型TFT的栅极相互电性连接构成该第一或非门的第一输入端并接入上一级第N-1级GOA单元的级传信号；所述第十九P型TFT与第二十二N型TFT的栅极相互电性连接构成该第一或非门的第二输入端并接入全局信号；所述第十九P型TFT的源极接入恒压高电位信号，漏极电性连接第二十P型TFT的源极；所述第二十一N型TFT与第二十二N型TFT的源极均接入恒压低电位信号；所述第二十P型TFT、第二十一N型TFT、及第二十二N型TFT的漏极相互电性连接构成该第一或非门的输出端并输出上一级第N-1级GOA单元的级传信号与全局信号的或非逻辑处理结果；
    其中，所述第二或非门包括二十三P型TFT、第二十四P型TFT、第二十五N型TFT、及第二十六N型TFT；所述第二十四P型TFT与第二十五N型TFT的栅极相互电性连接构成该第二或非门的第一输入端并接入第一时钟信号；所述第二十三P型TFT与第二十六N型TFT的栅极相互电性连接构成该第二或非门的第二输入端并接入全局信号；所述第二十三P型TFT的源极接入恒压高电位信号，漏极电性连接第二十四P型TFT的源极；所述第二十五N型TFT与第二十六N型TFT的源极均接入恒压低电位信号；所述第二十四P型TFT、第二十五N型TFT、及第二十六N型TFT的漏极相互电性连接构成该第二或非门的输出端并输出第一反相时钟信号。
  10. 如权利要求9所述的CMOS GOA电路，其中，所述输出缓冲模块包括依次串联的三个第二反相器，最靠近信号处理模块的第二反相器的输 入端电性连接所述节点，最远离信号处理模块的第二反相器的输出端输出扫描驱动信号。
  11. 如权利要求9所述的CMOS GOA电路，其中，所述第一反相器由一第十五P型TFT串联一第十六N型TFT构成，所述第十五P型TFT与第十六N型TFT的栅极相互电性连接构成该第一反相器的输入端并输入反相级传信号，所述第十五P型TFT的源极接入恒压高电位信号，所述第十六N型TFT的源极接入恒压低电位信号，所述第十五P型TFT与第十六N型TFT的漏极相互电性连接构成该第一反相器的输出端并输出级传信号。
  12. 如权利要求10所述的CMOS GOA电路，其中，所述第二反相器由一第十七P型TFT串联一第十八N型TFT构成，所述第十七P型TFT与第十八N型TFT的栅极相互电性连接构成该第二反相器的输入端，所述第十七P型TFT的源极接入恒压高电位信号，所述第十八N型TFT的源极接入恒压低电位信号，所述第十七P型TFT与第十八N型TFT的漏极相互电性连接构成该第二反相器的输出端；前一个第二反相器的输出端电性连接后一个第二反相器的输入端。
  13. 如权利要求9所述的CMOS GOA电路，其中，在第一级GOA单元中，所述第一或非门的第一输入端接入电路启动信号。
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CN108010496B (zh) * 2017-11-22 2020-04-14 武汉华星光电技术有限公司 一种goa电路
CN107958649B (zh) * 2018-01-02 2021-01-26 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN110689839B (zh) * 2019-12-10 2020-04-17 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN113870755B (zh) * 2020-06-30 2024-01-19 京东方科技集团股份有限公司 栅极驱动单元、栅极驱动电路、驱动方法及显示装置
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