WO2017008488A1 - 移位寄存单元、移位寄存器、栅极驱动电路和显示装置 - Google Patents

移位寄存单元、移位寄存器、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2017008488A1
WO2017008488A1 PCT/CN2016/071545 CN2016071545W WO2017008488A1 WO 2017008488 A1 WO2017008488 A1 WO 2017008488A1 CN 2016071545 W CN2016071545 W CN 2016071545W WO 2017008488 A1 WO2017008488 A1 WO 2017008488A1
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Prior art keywords
transistor
signal
pole
inverter
conversion module
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PCT/CN2016/071545
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English (en)
French (fr)
Inventor
彭于航
金鑫
杨文斌
廖鹏宇
谭超
王俊喜
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US15/103,983 priority Critical patent/US9704451B1/en
Publication of WO2017008488A1 publication Critical patent/WO2017008488A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0871—Several active elements per pixel in active matrix panels with level shifting
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to the field of display devices, and in particular to a shift register unit, a shift register including the shift register unit, a gate drive circuit including the shift register, and a gate including the same A display device for a drive circuit.
  • the gate drive circuit includes a shift register, and the shift register is cascaded by a multi-stage shift register unit.
  • the shift register unit is driven by two or more phase clock signals, thereby increasing the complexity of the shift register unit, which is disadvantageous for achieving narrow frame of the display device.
  • An object of the present invention is to provide a shift register unit, a shift register including the shift register unit, a gate drive circuit including the shift register, and a display device including the gate drive circuit .
  • the structure of the shift register unit is relatively simple.
  • a shift register unit including a start signal input terminal, a clock signal terminal, a high level input terminal, a low level input terminal, and a signal output.
  • the shift register unit further includes a first signal conversion module and a second signal conversion module, wherein an input end of the first signal conversion module is connected to the start signal input end, and the first signal conversion module The output end is connected to the input end of the second signal conversion module, the output end of the second signal conversion module is connected to the signal output end, and the first signal conversion module is further connected to the clock signal end,
  • the high level input end is connected to the low level input end
  • the second signal conversion module is further connected to the clock signal end and the high level input end respectively Connected to the low-level input terminal, one of a high-level signal input through the high-level input terminal and a low-level signal input through the low-level input terminal is a valid signal, and the other Is an invalid signal, and inputting a clock signal through
  • the first signal conversion module outputs an invalid signal to the second signal conversion module when the clock signal is at a first level and the start signal is an invalid signal
  • the second signal conversion module is configured according to The invalid signal output by the first signal conversion module and the clock signal output an invalid signal
  • the first signal conversion module outputs an invalid signal to the second signal conversion module, where the clock signal is at a second level, and the start signal is a valid signal.
  • the conversion module outputs an invalid signal according to the invalid signal output by the first signal conversion module and the clock signal;
  • the first signal conversion module outputs a valid signal to the second signal conversion module, the second signal, when the clock signal is at a first level and the start signal is a valid signal.
  • the conversion module outputs an invalid signal according to the valid signal output by the first signal conversion module and the clock signal;
  • the first signal conversion module outputs a valid signal to the second signal conversion module, where the clock signal is at a second level, and the start signal is an invalid signal, the second signal conversion module Outputting a valid signal according to the valid signal output by the first signal conversion module and the clock signal;
  • the first signal conversion module outputs a valid signal to the second signal conversion module, where the clock signal is at a first level, and the start signal is an invalid signal, the second signal conversion module And outputting a valid signal according to the valid signal output by the first signal conversion module and the clock signal.
  • the first signal conversion module and the second signal conversion module are respectively one of a positive latch and a negative latch, and when the clock signal is at a first level, the first signal The conversion module is in a transparent mode, the second signal conversion module is in a maintenance mode; when the clock signal is at a second level, the first signal conversion module is in a maintenance mode, and the second signal conversion module is in a transparent mode.
  • the first signal conversion module includes a first inverter and a second inverter connected in series with each other, the first inverter being capable of inputting a clock through the clock signal terminal The start signal is inverted when the signal is the first level signal, and the second inverter is capable of outputting the first inverter when the clock signal is the first level signal Signal inversion;
  • the second signal conversion module includes a third inverter and a fourth inverter connected in series with each other, and the third inverter is connected in series with the second inverter when a clock input through the clock signal terminal
  • the third inverter is capable of inverting a signal output by the second inverter
  • the fourth inverter is capable of outputting the third inverter The signal is inverted.
  • the first inverter includes a first transistor, a second transistor, and a third transistor, and a gate of the first transistor and a gate of the third transistor are both connected to the start signal input end, a gate of the second transistor is connected to the clock signal end, the first transistor is a P-type transistor, the third transistor is an N-type transistor, a first pole of the first transistor is opposite to the high voltage The flat input is connected, the second pole of the first transistor is connected to the first pole of the second transistor, and the second pole of the second transistor is connected to the first pole of the third transistor, the a second pole of the three transistor is connected to the low level input terminal;
  • the second transistor is an N-type transistor, and an output of the first inverter is a first pole of the second transistor.
  • the second inverter includes a fourth transistor, a fifth transistor, and a sixth transistor, the fourth transistor is a P-type transistor, and the fifth transistor and the sixth transistor are N-type transistors;
  • a first pole of the fourth transistor is connected to the high level input terminal, a second pole of the fourth transistor is connected to a first pole of the fifth transistor, and a second pole of the fifth transistor is a first pole of the sixth transistor is connected, and a second pole of the sixth transistor is connected to the low level input end;
  • a gate of the fifth transistor is connected to the clock signal end, and a gate of the fourth transistor and a gate of the sixth transistor are connected to an output end of the first inverter;
  • the second of the fourth transistor is the output of the second inverter.
  • the third inverter comprises a seventh transistor, an eighth transistor and a ninth transistor, the seventh transistor is a P-type transistor, and the ninth transistor is an N-type crystal Body tube
  • a gate of the seventh transistor and a gate of the ninth transistor are both connected to an output end of the second inverter, and a gate of the eighth transistor is connected to the clock signal end;
  • a first pole of the seventh transistor is connected to the high level input terminal, a second pole of the seventh transistor is connected to a first pole of the eighth transistor, and a second pole of the eighth transistor is a first pole of the ninth transistor is connected, and a second pole of the ninth transistor is connected to the low level input end;
  • the second transistor is the output terminal of the third inverter
  • the eighth transistor is a P-type transistor
  • the gate of the eighth transistor is connected to the clock signal terminal.
  • the fourth inverter comprises a tenth transistor, an eleventh transistor and a twelfth transistor, the tenth transistor and the eleventh transistor are P-type transistors, and the twelfth transistor is an N-type transistor ;
  • a gate of the tenth transistor and the twelfth transistor is connected to an output end of the third inverter, and a gate of the eleventh transistor is connected to the clock signal end;
  • a first pole of the tenth transistor is connected to the high level input terminal, a second pole of the tenth transistor is connected to a first pole of the eleventh transistor, and a second one of the eleventh transistor a pole connected to the first pole of the twelfth transistor, and a second pole of the twelfth transistor connected to the low level input terminal;
  • the signal output is coupled to the second pole of the tenth transistor.
  • the first signal conversion module includes a first inverter and a second inverter
  • the first inverter includes a first transistor, a second transistor, and a third transistor, and a gate of the first transistor and a gate of the third transistor are both connected to the start signal input end, where a gate of the second transistor is connected to the clock signal terminal, the first transistor is a P-type transistor, the third transistor is an N-type transistor, a first pole of the first transistor and the high-level input terminal Connected, a second pole of the first transistor is coupled to a first pole of the second transistor, and a second pole of the second transistor is coupled to a first pole of the third transistor, the third transistor a second pole is connected to the low level input terminal;
  • the second transistor is a P-type transistor, and an output end of the first inverter is a second pole of the second transistor;
  • the second inverter includes a fourth transistor, a fifth transistor, and a sixth transistor, the fourth transistor is a P-type transistor, and the fifth transistor and the sixth transistor are N-type transistors;
  • a first pole of the fourth transistor is connected to the high level input terminal, a second pole of the fourth transistor is connected to a first pole of the fifth transistor, and a second pole of the fifth transistor is a first pole of the sixth transistor is connected, and a second pole of the sixth transistor is connected to the low level input end;
  • a gate of the fifth transistor is connected to an output end of the first inverter, and a gate of the fourth transistor and a gate of the sixth transistor are connected to the clock signal end;
  • the second transistor is the output terminal of the second inverter, and the fifth transistor has a width to length ratio greater than a width to length ratio of the third transistor.
  • the second signal conversion module includes a third inverter and a fourth inverter,
  • the third inverter includes an eighth transistor, a seventh transistor, and a ninth transistor, the seventh transistor is a P-type transistor, and the ninth transistor and the eighth transistor are N-type transistors;
  • a gate of the seventh transistor and a gate of the ninth transistor are connected to an output end of the first signal conversion module, and a gate of the eighth transistor is connected to the clock signal end;
  • a first pole of the seventh transistor is connected to the high level input terminal, a second pole of the seventh transistor is connected to a first pole of the control transistor, and a second pole of the eighth transistor is a first pole of the ninth transistor is connected, and a second pole of the ninth transistor is connected to the low level input terminal;
  • the fourth inverter includes a tenth transistor and a twelfth transistor, the tenth transistor is a P-type transistor, and the twelfth transistor is an N-type transistor;
  • a gate of the tenth transistor and a gate of the twelfth transistor are both connected to an output of the third inverter, and a first pole of the tenth transistor is connected to the high level input a second pole of the tenth transistor is coupled to a first pole of the twelfth transistor, and a second pole of the thirteenth transistor is coupled to the low level input, the signal The output is coupled to the second pole of the tenth transistor.
  • the aspect ratio of the sixth transistor is greater than the aspect ratio of any one of the third transistor, the eighth transistor, and the ninth transistor.
  • the fifth transistor and the sixth transistor have a width to length ratio of 40:1
  • the third transistor, the eighth transistor, and the ninth transistor have a width to length ratio of 10:1.
  • a shift register including a cascaded multi-stage shift register unit, wherein the shift register unit is the above-described shift register unit provided by the present invention .
  • a gate driving circuit including a shift register, a high level signal line, an odd clock signal line, an even clock signal line, and a low level signal line.
  • the shift register is the above shift register provided by the invention, the high level signal line is connected to the high level input end, and the low level signal line and the low level input end are Connected, the odd clock signal line is connected to the clock signal terminal of the odd-numbered shift register unit, and the even clock signal line is connected to the clock signal terminal of the even-numbered shift register unit.
  • a display device including a gate driving circuit, wherein the gate driving circuit is the above-described gate driving circuit provided by the present invention.
  • the shift register unit provided by the present invention only a single-phase clock signal is required for control, thereby simplifying the structure of the shift register unit and reducing the power consumption of the shift register unit.
  • the display device using the shift register unit provided by the present invention can achieve a narrow bezel and low power consumption.
  • FIG. 1 is a block diagram of a shift register unit provided by the present invention.
  • FIG. 2 is a circuit diagram of an embodiment of a shift register unit provided by the present invention.
  • FIG. 3 is a timing chart showing the operation of the shift register unit shown in Figure 2;
  • FIG. 4 is a circuit diagram of another embodiment of a shift register unit provided by the present invention.
  • Fig. 5 is a timing chart showing the operation of the shift register unit shown in Fig. 4.
  • first signal conversion module 200 second signal conversion module
  • T1 first transistor
  • T2 second transistor
  • T3 third transistor T4: fourth transistor
  • T5 fifth transistor
  • T6 sixth transistor
  • T7 seventh transistor
  • T8 eighth transistor
  • T9 ninth transistor T10: tenth transistor
  • T11 eleventh transistor
  • T12 twelfth transistor
  • a shift register unit includes a start signal input terminal Vin, a clock signal terminal CK, a high level input terminal VDD, and a low level input.
  • the terminal VSS and the signal output terminal Vout and further includes a first signal conversion module 100 and a second signal conversion module 200.
  • the input end of the first signal conversion module 100 is connected to the start signal input terminal Vin
  • the output end of the first signal conversion module 100 is connected to the input end of the second signal conversion module 200
  • the output end and signal output of the second signal conversion module 200 are output.
  • the end Vout is connected.
  • the first signal conversion module 100 is also connected to the clock signal terminal CK, the high level input terminal VDD, and the low level input terminal VSS, respectively.
  • the second signal conversion module 200 is also connected to the clock signal terminal CK, the high level input terminal VDD, and the low level input terminal VSS, respectively, and is input through the high level input terminal VDD.
  • One of the incoming high level signal and the low level signal input through the low level input terminal VSS is a valid signal, and the other is an invalid signal, and the clock signal is input through the clock signal terminal CLK.
  • the start signal output 200 as invalid preprocessing stage (stage 3 and t 0 in FIG. 5) signal, a first signal converting module 100 to convert the signal to a second module in the clock signal
  • the second signal conversion module 200 is capable of outputting an invalid signal according to the invalid signal output by the first signal conversion module 100 and the clock signal.
  • the clock signal is at a second level
  • the start signal is the first signal writing phase (t phase 1 and FIG. 3 in FIG. 5) of the useful signal
  • a first signal converting module 100 can convert the second signal
  • the module 200 outputs an invalid signal
  • the second signal conversion module 200 can output an invalid signal according to the invalid signal output by the first signal conversion module 100 and the clock signal.
  • the first signal conversion module 100 is capable of converting to the second signal when the clock signal is at a first level and the start signal is a valid signal at a second signal writing phase (t 2 stages in FIGS. 3 and 5)
  • the module 200 outputs an effective signal, and the second signal conversion module 200 can output an invalid signal according to the valid signal output by the first signal conversion module 100 and the clock signal.
  • the first signal conversion module 100 can switch to the second signal conversion module 200 at a first output stage (the t 3 stage in FIGS. 3 and 5) in which the clock signal is at a second level and the start signal is an invalid signal.
  • the valid signal is output, and the second signal conversion module 200 can output a valid signal according to the valid signal output by the first signal conversion module 100 and the clock signal.
  • the first signal conversion module 100 can be configured to the second signal conversion module 200 at a second output stage in which the clock signal is at a first level and the start signal is an invalid signal (t 4 stages in FIGS. 3 and 5) The invalid signal is output, and the second signal conversion module 200 can output an effective signal according to the invalid signal output by the first signal conversion module 100 and the clock signal.
  • the first level is different from the second level.
  • the second level is low; when the first level is low, the second level is High level.
  • the level of the "valid signal” and the "invalid signal” is determined according to the type of the thin film transistor in the display area of the display device employing the shift register unit, wherein the so-called “effective signal” means that the display device can be made
  • the signal of the thin film transistor in the display area is turned on, and the so-called “invalid signal” refers to a signal capable of turning off the thin film transistor in the display area of the display device.
  • the shift of the input signal is completed.
  • the shift register unit provided by the present invention only the single-phase clock signal is required for control, thereby simplifying the structure of the shift register unit and reducing the power consumption of the shift register unit.
  • the display device using the shift register unit provided by the present invention can achieve a narrow bezel and low power consumption.
  • the first signal conversion module 100 and the second signal conversion module 200 may be one of the positive latch and the negative latch, respectively.
  • the first signal conversion module 100 is a positive latch and the second signal conversion module 200 is a negative latch.
  • the first level is a high level
  • the second level is a low level
  • the latch module when the latch module is in the transparent mode, the output signal of the latch module is the same as its input signal, and when the latch module is in the sustain mode, the latch module maintains the output signal of the previous stage unchanged.
  • the output signal of the first signal conversion module 100 is the same as the input signal input to the first signal conversion module 100; when the first signal conversion module 100 is in the maintenance mode, the output signal is Same as the signal from the previous stage.
  • the second signal conversion module 200 is in the transparent mode, the output signal of the second signal conversion module 200 is the same as the input signal input to the second signal conversion module 200, when the second signal conversion module 200 is in the maintenance mode, The output signal maintains the output signal of the previous stage unchanged.
  • the pulse width of the input signal is greater than the pulse width of the clock signal, and the high level duration of the input signal is related to the time of one cycle of the clock signal. with.
  • the first signal conversion module 100 When the input signal is a valid signal and the clock signal is at the second level, the first signal conversion module 100 is in a maintenance state, and therefore, the signal output by the first signal conversion module 100 is an invalid signal. Since the clock signal is the second level signal, the second signal conversion module 200 is in a transparent state. Therefore, the second signal conversion module 200 can output the same signal as the invalid signal output by the first signal conversion module 100.
  • the first signal conversion module 100 When the input signal is a valid signal and the clock signal is at the first level, the first signal conversion module 100 is in a transparent state. Therefore, the signal output by the first signal conversion module 100 is the same as the input signal, and is a valid signal. Since the clock signal is at the first level, the second signal conversion module 200 is in the maintenance state, and the output signal output by the second signal conversion module 200 is still the invalid signal of the previous stage.
  • the first signal conversion module 100 When the input signal is an invalid signal and the clock signal is at the second level, the first signal conversion module 100 is in the maintenance state, and the valid signal of the previous stage can still be maintained. Since the clock signal is at the second level, the second signal conversion module 200 is in a transparent state, which can output the same signal as the signal input to the second signal conversion module 200, and thus can output a valid signal.
  • the first signal conversion module 100 and the second signal conversion module 200 in the shift register unit provided by the present invention constitute a master-slave edge flip-flop, thereby eliminating the duty ratio of the clock signal.
  • the effect of size on the output signal results in a stable and effective output signal.
  • the effective signal duration of the output signal is only related to the period of the clock signal, effectively avoiding the adverse effects caused by the overlap of the multi-phase clock signals in the prior art.
  • the effective signal is a low level signal; when a thin film transistor in a display region of the display device using the shift register unit is used When it is an N-type transistor, the valid signal is a high level signal.
  • the valid signal is a high level signal and the invalid signal is a low level signal.
  • the level of the first level and the second level are not specifically defined, and the level of the first level and the second level are determined by the first signal conversion module and the second signal. The type of transistor used in the number conversion module is determined.
  • the specific structure of the first signal conversion module 100 and the second signal conversion module 200 is not particularly limited as long as the first signal conversion module 100 and the second signal conversion module 200 are connected in series to form a master-slave edge trigger. Further, the function of the shift register unit can be realized.
  • the first signal conversion module 100 includes a first inverter 110 and a second inverter 120 connected in series, and the clock signal input through the clock signal terminal CK is At the first level, the first inverter 110 can invert the input start signal, and the second inverter 120 can invert the signal output from the first inverter 110.
  • the first level is a high level and the second level is a low level.
  • the second signal conversion module 200 includes a third inverter 210 and a fourth inverter 220 connected in series, and when the clock signal input through the clock signal terminal CK is at the second level, the third inverter 210 can The signal output from the second inverter 120 is inverted, and the fourth inverter 220 is capable of inverting the signal output from the third inverter 210.
  • the first inverter 110 When the clock signal is at the first level, the first inverter 110 performs a first inversion operation on the signal input through the start signal input terminal Vin, and supplies the signal after the first inversion operation to the second inverter 120. And the second inverter 120 performs the second inversion operation on the signal after the first inversion operation, that is, the signal level after the second inversion operation is the same as the original input signal, thereby achieving the first The transparent mode of the signal conversion module 100.
  • the first inverter 110 does not perform an inversion operation (ie, the first inverter 110 maintains the output of the previous stage), and the second inverter 120 does not perform the inversion.
  • the operation ie, the second inverter 120 maintains the output of the previous stage) allows the first signal conversion module 100 to be in a maintained state.
  • the third inverter 210 and the fourth inverter 220 do not perform an inversion operation, so that the second signal conversion module 200 can be brought into a sustain state.
  • the third inverter 220 can perform the first inversion operation on the signal output from the second inverter, and output the signal after the first inversion operation to the fourth inverter 230.
  • the fourth inverter 230 is capable of performing a second inversion operation on the signal after the first inversion operation, that is, the signal level after the second inversion operation and the original input signal. The same, thereby implementing the transparent mode of the second signal conversion module 200.
  • each of the above-described inverters (including the first inverter, the second inverter, the third inverter, and the fourth inverter) is not specifically defined.
  • the first inverter 110 includes a first transistor T1, a second transistor T2, and a third transistor T3, wherein the first transistor T1 is a P-type transistor, and the second The transistor T2 and the third transistor T3 are N-type transistors.
  • the gate of the first transistor T1 and the gate of the third transistor T3 are both connected to the start signal input terminal Vin, and the gate of the second transistor T2 is connected to the clock signal terminal CK.
  • the first pole of the first transistor T1 is connected to the high level input terminal VDD
  • the second pole of the first transistor T1 is connected to the first pole of the second transistor T2, and the second pole of the second transistor T2 is connected to the third pole.
  • the first pole of the transistor T3 is connected, and the second pole of the third transistor T3 is connected to the low level input terminal VSS.
  • the first transistor of the second transistor T2 is the output terminal of the first inverter 110.
  • the first level signal should be a high level signal
  • the second level signal should be a low level signal.
  • both the P-type transistor and the N-type transistor are included, and therefore, the first inverter can be formed by a CMOS process, thereby making the first inverter have high speed and integration. High and strong anti-interference ability.
  • the second transistor T2 When the clock signal input through the clock signal terminal CK is a high level signal, the second transistor T2 is turned on. Since the first transistor T1 is a P-type transistor and the third transistor T3 is an N-type transistor, one of the first transistor T1 and the third transistor T3 is turned on regardless of whether the input signal is a high level or a low level. And the other is the deadline.
  • the start signal is a high level signal
  • the first transistor T1 is turned off, and the third transistor T3 is turned on, thereby turning on the first pole of the second transistor T2 and the low level input terminal VSS, thereby outputting a low level signal, Equivalent to inverting the start signal.
  • the third transistor T3 When the start signal is low, the third transistor T3 is turned off, and the first transistor T1 is turned on, thereby turning on the first pole of the second transistor T2 and the high level input terminal VDD, thereby outputting a high level signal, which is equivalent Invert the start signal.
  • the second transistor T2 When the clock signal is a low level signal, the second transistor T2 is turned off. In this case, when the input signal is a high level signal, although the eighth transistor T3 can be turned on, The second transistor T2 is turned off. Therefore, the first pole of the second transistor T2 maintains the output of the previous stage; when the input signal is the low level signal, the first transistor T1 is turned on, and the first inverter 110 outputs high. Level signal.
  • the second inverter 120 includes a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, wherein the fourth transistor T4 is a P-type transistor, and the fifth transistor T5 and the sixth transistor T6 are N-type transistors.
  • the first pole of the fourth transistor T4 is connected to the high level input terminal VDD
  • the second pole of the fourth transistor T4 is connected to the first pole of the fifth transistor T5
  • the second pole of the fifth transistor T5 is connected to the sixth transistor T6.
  • the first pole is connected
  • the second pole of the sixth transistor T6 is connected to the low level input terminal VSS.
  • the gate of the fifth transistor T5 is connected to the clock signal terminal CK
  • the gate of the fourth transistor T4 and the gate of the sixth transistor T6 are connected to the output terminal of the first inverter 110
  • the second electrode of the fourth transistor T4 is connected.
  • the output of the second inverter 120 is connected to the clock signal terminal CK
  • the fifth transistor T5 when the clock signal input through the clock signal terminal CK is a high level signal, the fifth transistor T5 is turned on.
  • the fourth transistor T4 if the first inverter 110 outputs a high level signal, the fourth transistor T4 is turned off, and the sixth transistor T6 is turned on, thereby guiding the first and low level input terminals of the fifth transistor T5. Passing, thereby outputting a low level signal; if the first inverter 110 outputs a low level signal, the sixth transistor T6 is turned off, and the fourth transistor T4 is turned on, thereby turning the first pole and the high level of the fifth transistor T5 The input terminal VDD is turned on to output a high level signal.
  • the fifth transistor T5 when the clock signal input through the clock signal terminal CK is at a low level, the fifth transistor T5 is turned off. In this case, if the first inverter 110 outputs a high level, the fourth transistor T4 is turned off, and the sixth transistor T6 is turned on, since the fifth transistor T5 is turned off, the second inverter 120 maintains the previous stage.
  • the level low level in this embodiment; when the first inverter 110 outputs a low level, the fourth transistor T4 is turned on, and therefore, the second inverter 120 can output a high level signal.
  • the third inverter 210 includes a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9, wherein the seventh transistor T7 and the eighth transistor T8 are P-type transistors, and the ninth transistor T9 is N-type transistor.
  • the gate of the seventh transistor T7 and the gate of the ninth transistor T9 are both connected to the output of the second inverter 120, and the gate of the eighth transistor T8 is connected to the clock signal terminal CK.
  • the first pole of the seventh transistor T7 is connected to the high level input terminal VDD
  • the second pole of the seventh transistor T7 is connected to the first pole of the eighth transistor T8, and the second pole of the eighth transistor T8 is connected to the second pole of the eighth transistor T9.
  • the first pole is connected
  • the second pole of the ninth transistor T9 is connected to the low level input terminal VSS.
  • the second transistor of the seventh transistor T7 is an output terminal of the third inverter 210.
  • the eighth transistor T8 when the clock signal input through the clock signal terminal CK is a low level signal, the eighth transistor T8 is turned on.
  • the seventh transistor T7 When the signal output by the first signal conversion module 100 is a high level signal, the seventh transistor T7 is turned off, and the ninth transistor T9 is turned on, thereby connecting the first pole of the eighth transistor T8 to the low level through the ninth transistor T9.
  • the input terminal VSS causes the third inverter 210 to output a low level signal.
  • the seventh transistor T7 When the signal output by the first signal conversion module 100 is a low level signal, the seventh transistor T7 is turned on, the ninth transistor T9 is turned off, and the first electrode of the eighth transistor T8 is connected to the high level input VDD through the seventh transistor T7. Therefore, the third inverter outputs a high level signal.
  • the eighth transistor T8 When the clock signal input through the clock signal terminal CK is a high level signal, the eighth transistor T8 is turned off. In this case, when the signal output from the first signal conversion module 100 is a high level signal, the ninth transistor T9 is turned on, and the seventh transistor T7 is turned off. Since the eighth transistor T8 is turned off, the first pole of the eighth transistor T8 maintains the level signal of the previous stage. When the clock signal input through the clock signal terminal CK is a low level signal, the eighth transistor T8 is turned on. When the signal outputted from the output terminal Vin' of the first signal conversion module 100 is a high level signal, the ninth transistor T9 is turned on, and the seventh transistor T7 is turned off, thereby passing the first end of the eighth transistor T8 through the ninth transistor T9.
  • the seventh transistor T7 is turned on, and the ninth transistor T9 is turned off. Therefore, the first pole and the high level input of the eighth transistor T8 are The terminal VDD is turned on and outputs a high level signal.
  • the fourth inverter 220 includes a tenth transistor T10, an eleventh transistor T11, and a tenth
  • the two transistors T12, the tenth transistor T10 and the eleventh transistor T11 are P-type transistors, and the twelfth transistor T12 is an N-type transistor.
  • the gates of the tenth transistor T10 and the twelfth transistor T12 are connected to the output terminal of the third inverter 210, and the gate of the eleventh transistor T11 is connected to the clock signal terminal CK.
  • the first pole of the tenth transistor T10 is connected to the high level input terminal VDD
  • the second pole of the tenth transistor T10 is connected to the first pole of the eleventh transistor T11
  • the second pole of the eleventh transistor T11 is the twelfth
  • the first pole of the transistor T12 is connected
  • the second pole of the twelfth transistor T12 is connected to the low level input terminal VSS.
  • the signal output terminal Vout is connected to the second pole of the tenth transistor T10.
  • the eleventh transistor T11 When the clock signal input through the clock signal terminal CK is a high level signal, the eleventh transistor T11 is turned off. In this case, when the signal output by the third inverter 210 is a high level signal, the tenth transistor T10 is turned off, the twelfth transistor T12 is turned on, and the first pole of the eleventh transistor T11 is maintained in the previous stage. When the signal outputted by the third inverter is a low level signal, the tenth transistor T10 is turned on, and the twelfth transistor T12 is turned off, thereby turning on the signal output terminal Vout and the high level input terminal VDD, so that The shift register unit outputs a high level signal (corresponding to inverting the signal output from the third inverter 210).
  • the eleventh transistor T11 When the clock signal input through the clock signal terminal CK is a low level signal, the eleventh transistor T11 is turned on.
  • the signal output by the third inverter 210 When the signal output by the third inverter 210 is a high level signal, the twelfth transistor T12 is turned on, thereby turning on the first pole of the eleventh transistor T11 and the low level input terminal VSS, and outputting a low level. signal.
  • the signal output by the third inverter 210 When the signal output by the third inverter 210 is a low level signal, the tenth transistor T10 is turned on, and the first pole of the eleventh transistor T11 is turned on with the high level input terminal VDD, thereby outputting a high level signal. .
  • the first level signal is a high level signal and the second level signal is a low level signal.
  • the second transistor T2 of the first inverter 110 is an N-type transistor, and the output of the first inverter 110 is the first pole of the second transistor T2.
  • the gate of the fifth transistor T5 of the second inverter 120 is connected to the clock signal terminal CK, the gate of the fourth transistor T4 of the second inverter 120 and the gate of the sixth transistor T6 are both connected to the first inverter.
  • the outputs of 110 are connected.
  • the fourth inverter 220 includes an eleventh transistor T11, a tenth transistor T10, and a twelfth transistor T12.
  • the first inverter 110 and the second inverter 120 are connected in series to form a first signal conversion module 100, and the third inverter 210 and the fourth inverter 220 are connected in series to form a second signal conversion module 200.
  • the first level signal is a high level signal
  • the second level signal is a low level signal
  • the active signal is a high level signal.
  • the high level duration of the start signal input through the start signal input terminal Vin is the same as the duration of one cycle of the clock signal.
  • phase t0 the clock signal of a high level signal
  • the second transistor T2 is turned on
  • the fifth transistor T5 is turned on
  • the eighth transistor T8 is turned off
  • the eleventh transistor T11 is turned off. Since the start signal is a low level signal, the first transistor T1 is turned on, and the third transistor T3 is turned off, so that the first inverter 110 outputs a high level signal.
  • the high level signal output by the first inverter 110 causes the sixth transistor T6 of the second inverter to be turned on, and the fourth transistor T4 is turned off, and therefore, the second inverter 120 outputs a low level signal.
  • the first signal conversion module 100 is in a transparent state at this time, that is, the input signal and the output signal of the first signal conversion module 100 are both low level signals. Since the signal outputted from the output terminal Vin' of the first signal conversion module 100 is a low level signal, the seventh transistor T7 of the third inverter 210 is turned on, and the ninth transistor T9 is turned off. Therefore, the third inverter is turned on.
  • the signal outputted by 210 is a high level signal, so that the tenth transistor T10 of the fourth inverter 220 is turned off and the twelfth transistor T12 is turned on, so that the signal output terminal Vout can maintain the output signal of the previous stage, that is, The maintenance state of the second signal conversion module 200 is achieved.
  • phase t 1 the clock signal is a low level signal
  • the first inverter 110 of the second transistor T2 is turned off
  • a second inverter 120 the fifth transistor T5 is turned off.
  • the start signal is a high level signal
  • the first transistor T1 is turned off
  • the third transistor T3 is turned on
  • the first electrode of the second transistor T2 maintains a high level signal of the t 0 phase, so that the sixth transistor T6 is turned on.
  • the fourth transistor T4 is turned off, and therefore, t is 0 phase signal, i.e., a first signal converting module in the standby mode, the fifth transistor T5 and the output stage of the sustain signal.
  • the signal output by the output node Vin' of the first signal conversion module 100 is a low level signal.
  • the eighth transistor T8 of the third inverter 210 Since the phase of the clock signal t 1 at a low level, and therefore, the eighth transistor T8 of the third inverter 210 is turned on by a first signal converting module output node Vin '100 is input to a third inverter 210 The signal is inverted to a high level signal. At this time, the eleventh transistor T11 of the fourth inverter 210 is turned on. Therefore, the fourth inverter 210 inverts the signal input to the fourth inverter to a low level signal, so that the signal output terminal Vout is output. A low level signal, thereby implementing a transparent mode of the second signal conversion module 200.
  • the second transistor T2 of the first inverter 110 is turned on, and the fifth transistor T5 of the second inverter 120 is turned on, and therefore, the first inverter 110 Both the inverter and the second inverter 120 can perform an inversion operation. Since the start signal is a high level signal, the signal output by the first inverter 110 is a low level signal, and the signal output by the second inverter 120 is a high level signal, thereby implementing the first signal conversion module 100. Transparent mode.
  • the eighth transistor T8 of the third inverter 210 and the eleventh transistor T11 of the fourth inverter 220 are both turned off, in this case, due to the first signal conversion module 100
  • the output signal of the output terminal Vin' is a high level signal. Therefore, the ninth transistor T9 of the third inverter 210 is turned on, and the seventh transistor T7 of the third inverter 210 is turned off, and the third inverter 210 is turned off.
  • the output terminal maintains the high level signal of the previous stage, so that the tenth transistor T10 of the fourth inverter is turned off, and the twelfth transistor T12 of the fourth inverter is turned on, therefore, the fourth inverter output is in the previous stage.
  • the low level signal thereby implementing the sustain mode of the second signal conversion module 200.
  • the clock signal is a low level signal
  • the first inverter 110 of the second transistor T2 and a second inverter 120 the fifth transistor T5 is turned off; signal is low since the start signal,
  • the first transistor T1 is turned on
  • the first inverter 110 outputs a high level signal, so that the sixth transistor T6 is turned on, and the fourth transistor T4 is turned off. Therefore, the second inverter 120 maintains the high level signal of the previous stage. .
  • the first signal conversion module 100 is in the maintenance mode. Since the clock signal is a low level signal, the eighth transistor T8 of the third inverter 210 and the eleventh transistor T11 of the fourth inverter 220 are turned on.
  • the output signal of the third inverter 210 is a low level signal
  • the output signal of the fourth inverter is a high level signal, thereby realizing the first The transparent mode of the two signal conversion module 200.
  • the clock signal is high, the first inverter 110 of the second transistor T2 is turned on, the second inverter 120 fifth transistor T5 is turned on; as the start signal is low, Therefore, the first transistor T1 is turned on, the third transistor T3 is turned off, the first inverter 110 outputs a high level signal, the sixth transistor T6 of the second inverter is turned on, and the fourth transistor T4 is turned off, therefore, the second The inverter 120 outputs a low level signal such that the first signal conversion module 100 is in a transparent state. Since the clock signal is a high level signal, the eighth transistor T8 and the eleventh transistor T11 are turned off.
  • the seventh transistor T7 is turned on, and the ninth transistor T9 is turned off, so the third inverter 210 outputs a high level signal, and the tenth of the fourth inverter
  • the second transistor T12 is turned on to turn off the tenth transistor T10. Therefore, the fourth inverter 220 can output a high level signal of the previous stage, so that the second signal conversion module 200 is in a maintained state.
  • the first signal conversion module 100 can also have the embodiment shown in FIG.
  • the first signal conversion module 100 includes a first inverter 110 and a second inverter 120.
  • the first inverter 110 includes a first transistor T1, a second transistor T2, and a third transistor T3, wherein the first transistor T1 is a P-type transistor, and the second transistor T2 and the third transistor T3 are N-type transistors.
  • the gate of the first transistor T1 and the gate of the third transistor T3 are both connected to the start signal input terminal Vin, and the gate of the second transistor T2 is connected to the clock signal terminal, and the first pole of the first transistor T1 is The high level input terminal VDD is connected, the second pole of the first transistor T1 is connected to the first pole of the second transistor T2, the second pole of the second transistor T2 is connected to the first pole of the third transistor T3, and the third A second electrode of the transistor T3 is connected to the low level input terminal VSS.
  • the second of the second transistor T2 is the output of the first inverter.
  • the second inverter includes a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, wherein the fourth transistor T4 is a P-type transistor, and the fifth transistor T5 and the sixth transistor T6 are N-type transistors.
  • the first pole of the fourth transistor T4 is connected to the high level input terminal VDD
  • the second pole of the fourth transistor T4 is connected to the first pole of the fifth transistor T5, and the fifth transistor T5
  • the second pole is connected to the first pole of the sixth transistor T6, and the second pole of the sixth transistor T6 is connected to the low level input terminal VSS.
  • a gate of the fifth transistor T5 is connected to an output terminal of the first inverter, and a gate of the fourth transistor T4 and a gate of the sixth transistor T6 are connected to the clock signal terminal.
  • the second transistor T4 is second to the output of the second inverter, and the fifth transistor T5 has a width to length ratio greater than that of the third transistor T3.
  • the aspect ratio of the fifth transistor T5 and the sixth transistor T6 is greater than the aspect ratio of the third transistor T3, the eighth transistor T8, and the ninth transistor T9, so that the discharge speed of the first electrode of the fifth transistor T5 is greater than the third transistor.
  • the discharge speed of the first pole of T3 is greater than the discharge speed of the first pole of the eighth transistor T8.
  • the advantage of this setup is that the output signal can be stabilized without glitch.
  • the aspect ratio of the fifth transistor T5 and the sixth transistor T6 may both be 40:1, and the aspect ratio of the third transistor T3, the eighth transistor T8, and the ninth transistor T9 may both be 10:1, but the present invention Not limited to this.
  • the second signal conversion module 200 includes a third inverter 210 and a fourth inverter 220.
  • the third inverter 210 includes an eighth transistor T8, a seventh transistor T7, and a ninth transistor T9.
  • the seventh transistor T7 is a P-type transistor
  • the ninth transistor T9 and the eighth transistor T8 are N-type transistors.
  • the gate of the seventh transistor T7 and the gate of the ninth transistor T9 are connected to the output of the first signal conversion module 100, and the gate of the eighth transistor T8 is connected to the clock signal terminal CLK.
  • the first pole of the seventh transistor T7 is connected to the high level input terminal VDD
  • the second pole of the seventh transistor T7 is connected to the first pole of the eighth transistor T8, and the second pole and the ninth transistor of the eighth transistor T8 are connected.
  • the first pole of T9 is connected, and the second pole of the ninth transistor T9 is connected to the low level input terminal VSS.
  • the fourth inverter includes a tenth transistor T10 and a twelfth transistor T12, wherein the tenth transistor T10 is a P-type transistor, and the twelfth transistor T12 is an N-type transistor;
  • the gate of the tenth transistor T10 and the gate of the twelfth transistor T12 are both connected to the output of the third inverter 210, and the first pole of the tenth transistor T10 is connected to the high level input terminal VDD.
  • the second pole of the tenth transistor T10 and the twelfth transistor T12 The first pole of the twelveth transistor T12 is connected to the low level input terminal VSS, and the signal output terminal is connected to the second pole of the tenth transistor T10.
  • the specific operation principle of the shift register unit of the second embodiment of the present invention will be described below with reference to FIGS. 4 and 5.
  • the shift register unit of the second embodiment shown in FIG. 4 requires only 11 transistors, which further simplifies the structure of the shift register unit.
  • the first level signal is a low level signal and the second level signal is a high level signal.
  • the start signal is a low level signal
  • the clock signal is low-level signal phase t 0
  • the second transistor T2 is turned on
  • the first transistor T1 is turned on
  • the third transistor T3 is turned off, so that the output of the first inverter 110 high Level signal.
  • the high level signal output by the first inverter 110 causes the fifth transistor T5 of the second inverter 120 to be turned on, and at this time, the fourth transistor T4 of the second inverter 120 is turned on, and the sixth transistor T6 is turned off. Therefore, the second inverter 120 outputs a high level signal.
  • the seventh transistor T7 of the third inverter 210 is turned off, and the ninth transistor T9 is turned on, because the eighth transistor T8 is turned off, therefore,
  • the first pole of the eighth transistor T8 maintains the high level signal of the previous stage, so that the tenth transistor T10 of the fourth inverter 220 is turned off and the twelfth transistor T12 is turned on, so that the signal output terminal Vout outputs low power.
  • Flat signal Since the signal outputted from the output end of the first signal conversion module 100 is a high level signal, the seventh transistor T7 of the third inverter 210 is turned off, and the ninth transistor T9 is turned on, because the eighth transistor T8 is turned off, therefore,
  • the first pole of the eighth transistor T8 maintains the high level signal of the previous stage, so that the tenth transistor T10 of the fourth inverter 220 is turned off and the twelfth transistor T12 is turned on, so that the signal output terminal Vout outputs low power.
  • Flat signal Since the signal outputted from the
  • Signal is high at the beginning of a clock signal of a high level signal is phase t 1, a first inverter 110 of the second transistor T2 is turned off, the third inverter 210, the eighth transistor T8 is turned on. Since the start signal is a high level signal, the third transistor T3 of the first inverter 110 is turned on, and the first transistor T1 is turned off. Therefore, the first inverter 110 outputs a low level signal.
  • the aspect ratio of the fifth transistor T5 and the sixth transistor T6 is greater than the aspect ratio of the third transistor T3
  • the discharge speeds of the fifth transistor T5 and the sixth transistor T6 are greater than the third transistor T3 and the eighth transistor T8,
  • the discharge speed of the nine-transistor T9 therefore, the gate of the seventh transistor T7 is discharged to the low-level signal earlier, the seventh transistor T7 is turned on, the ninth transistor T9 is turned off, and the second transistor T7 is turned off.
  • the pole is connected to the high level input terminal VDD through the first pole of the seventh transistor T7, thereby outputting a high level signal to the fourth inverter 220, and turning on the twelfth transistor T12 of the fourth inverter 220 to
  • the signal output terminal Vout is connected to the low-level input terminal VSS through the twelfth transistor T12, thereby outputting a low-level signal.
  • the second transistor T2 is turned on, and the third transistor T3 is turned on, and the first inverter 110 is turned on.
  • a low level signal is output to turn off the fifth transistor T5 of the second inverter 120.
  • the fourth transistor T4 is turned on.
  • the second inverter 120 outputs a high level signal, turns on the ninth transistor T9 and turns off the seventh transistor T7, and the eighth transistor T8 is turned off, so the eighth transistor T8 a first electrode maintains a high level signal phase t 1, so that the tenth transistor T10 is turned off, the twelfth transistor T12 is turned on, so that the signal output terminal Vout is connected to the input of the low level VSS via the twelfth transistor T12, Thereby outputting a low level signal.
  • the start signal is a low level signal
  • the clock signal is a high-level signal phase t 3
  • the first transistor T1 is turned on
  • the second transistor T2 is turned off
  • the third transistor T3 is turned off, therefore, the output of the first inverter Output the low level signal of the previous stage.
  • the fifth transistor T5 is turned off
  • the fourth transistor T4 is turned off
  • the sixth transistor T6 is turned on
  • the first electrode of the fifth transistor T5 maintains a high level signal of the previous stage, thereby turning on the ninth transistor T9.
  • the third inverter outputs a low level signal, turns on the tenth transistor T10, and the twelfth transistor T12 turns off, thereby turning the signal output terminal Vout
  • the high level signal is output by the tenth transistor T10 being connected to the high level input terminal VDD.
  • the first transistor T1 and the second transistor T2 are both turned on, and the third transistor T3 is turned off. Therefore, the first inverter 110 outputs High level signal.
  • the fifth transistor T5 is turned on, the fourth transistor T4 is turned on, the sixth transistor T6 is turned off, and the second inverter 120 outputs a high level signal.
  • the ninth transistor T9 is turned on, the seventh transistor T7 is turned off, and the eighth transistor T8 is turned off.
  • the first pole of the eighth transistor T8 maintains the low level signal of the previous stage, thereby turning on the tenth transistor T10, the tenth The second transistor T12 is turned off, thereby connecting the signal output terminal Vout to the high-level input terminal VDD through the tenth transistor T10, thereby outputting a high-level signal.
  • a shift register including a cascaded multi-stage shift register unit, wherein the shift register unit is the above-described shift register unit provided by the present invention .
  • the shift register unit has a relatively simple structure
  • the shift register provided by the present invention also has a relatively simple structure.
  • a gate driving circuit including a shift register, a high level signal line, an odd clock signal line, an even clock signal line, and a low level signal line.
  • the shift register is the above shift register provided by the invention, the high level signal line is connected to the high level input end, and the low level signal line and the low level input end are Connected, the odd clock signal line is connected to the clock signal terminal of the odd-numbered shift register unit, and the even clock signal line is connected to the clock signal terminal of the even-numbered shift register unit.
  • a display device including a gate driving circuit, wherein the gate driving circuit is the above-described gate driving circuit provided by the present invention.

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Abstract

一种移位寄存单元，以及包括该移位寄存单元的一种移位寄存器、一种栅极驱动电路和一种显示装置，该移位寄存单元包括第一信号转换模块（100）和第二信号转换模块（200），第一信号转换模块（100）分别与开始信号输入端（Vin）、时钟信号端（CK）、高电平输入端（VDD）、低电平输入端（VSS）和第二信号转换模块（200）的输入端相连，第二信号转换模块（200）分别与第一信号转换模块（100）的输出端、时钟信号端（CK）、信号输出端（Vout）、高电平输入端（VDD）和低电平输入端（VSS）相连。该移位寄存单元仅需要单相时钟信号进行控制，从而简化了移位寄存单元的结构。

Description

移位寄存单元、移位寄存器、栅极驱动电路和显示装置 技术领域
本发明涉及显示装置领域，具体地，涉及一种移位寄存单元、一种包括该移位寄存单元的移位寄存器、一种包括该移位寄存器的栅极驱动电路和一种包括该栅极驱动电路的显示装置。
背景技术
在现有的显示装置中，通常需要利用栅极驱动电路为栅线提供扫描信号。栅极驱动电路包括移位寄存器，而移位寄存器则是由多级移位寄存单元级联而成。通常，移位寄存单元要采取两相或者更多相时钟信号进行驱动，从而增加了移位寄存单元的复杂程度，不利于实现显示装置的窄边框化。
因此，如何简化移位寄存单元成为本领域亟待解决的技术问题。
发明内容
本发明的目的在于提供一种移位寄存单元、一种包括该移位寄存单元的移位寄存器、一种包括该移位寄存器的栅极驱动电路和一种包括该栅极驱动电路的显示装置。所述移位寄存单元结构较为简单。
为了实现上述目的，作为本发明的一个方面，提供一种移位寄存单元，所述移位寄存单元包括开始信号输入端、时钟信号端、高电平输入端、低电平输入端和信号输出端，其中，所述移位寄存单元还包括第一信号转换模块和第二信号转换模块，所述第一信号转换模块的输入端与所述开始信号输入端相连，所述第一信号转换模块的输出端与所述第二信号转换模块的输入端相连，所述第二信号转换模块的输出端与所述信号输出端相连，所述第一信号转换模块还分别与所述时钟信号端、所述高电平输入端相连和所述低电平输入端相连，所述第二信号转换模块还分别与所述时钟信号端、所述高电平输入端相连 和所述低电平输入端相连，通过所述高电平输入端输入的高电平信号与通过所述低电平输入端输入的低电平信号中的一者为有效信号，另一者为无效信号，并且通过所述时钟信号端输入时钟信号；
在所述时钟信号为第一电平、所述开始信号为无效信号的预处理阶段，所述第一信号转换模块向所述第二信号转换模块输出无效信号，所述第二信号转换模块根据所述第一信号转换模块输出的无效信号以及所述时钟信号输出无效信号；
在所述时钟信号为第二电平、所述开始信号为有效信号的第一信号写入阶段，所述第一信号转换模块向所述第二信号转换模块输出无效信号，所述第二信号转换模块根据所述第一信号转换模块输出的无效信号以及所述时钟信号输出无效信号；
在所述时钟信号为第一电平、所述开始信号为有效信号的第二信号写入阶段，所述第一信号转换模块向所述第二信号转换模块输出有效信号，所述第二信号转换模块根据所述第一信号转换模块输出的有效信号以及所述时钟信号输出无效信号；
在所述时钟信号为第二电平、所述开始信号为无效信号的第一输出阶段，所述第一信号转换模块向所述第二信号转换模块输出有效信号，所述第二信号转换模块根据所述第一信号转换模块输出的有效信号以及所述时钟信号输出有效信号；
在所述时钟信号为第一电平、所述开始信号为无效信号的第二输出阶段，所述第一信号转换模块向所述第二信号转换模块输出有效信号，所述第二信号转换模块根据所述第一信号转换模块输出的有效信号以及所述时钟信号输出有效信号。
优选地，所述第一信号转换模块和所述第二信号转换模块分别为正锁存器和负锁存器中的一种，当所述时钟信号为第一电平时，所述第一信号转换模块处于透明模式，所述第二信号转换模块处于维持模式；当所述时钟信号为第二电平时，所述第一信号转换模块处于维持模式，所述第二信号转换模块处于透明模式。
优选地，所述第一信号转换模块包括互相串联的第一反相器和第二反相器，所述第一反相器能够在通过所述时钟信号端输入的时钟 信号为所述第一电平信号时将输入的所述开始信号反相，所述第二反相器能够在所述时钟信号为所述第一电平信号时将第一反相器输出的信号反相；
所述第二信号转换模块包括互相串联的第三反相器和第四反相器，所述第三反相器与所述第二反相器串联，当通过所述时钟信号端输入的时钟信号为第二电平信号时，所述第三反相器能够将所述第二反相器输出的信号反相，并且所述第四反相器能够将所述第三反相器输出的信号反相。
优选地，所述第一反相器包括第一晶体管、第二晶体管和第三晶体管，所述第一晶体管的栅极和所述第三晶体管的栅极均与所述开始信号输入端相连，所述第二晶体管的栅极与所述时钟信号端相连，所述第一晶体管为P型晶体管，所述第三晶体管为N型晶体管，所述第一晶体管的第一极与所述高电平输入端相连，所述第一晶体管的第二极与所述第二晶体管的第一极相连，所述第二晶体管的第二极与所述第三晶体管的第一极相连，所述第三晶体管的第二极与所述低电平输入端相连；
所述第二晶体管为N型晶体管，所述第一反相器的输出端为所述第二晶体管的第一极。
优选地，所述第二反相器包括第四晶体管、第五晶体管和第六晶体管，所述第四晶体管为P型晶体管，所述第五晶体管和所述第六晶体管为N型晶体管；
所述第四晶体管的第一极与所述高电平输入端相连，所述第四晶体管的第二极与所述第五晶体管的第一极相连，所述第五晶体管的第二极与所述第六晶体管的第一极相连，所述第六晶体管的第二极与所述低电平输入端相连；
所述第五晶体管的栅极与所述时钟信号端相连，所述第四晶体管的栅极和所述第六晶体管的栅极与所述第一反相器的输出端相连；
所述第四晶体管的第二极为所述第二反相器的输出端。
优选地，所述第三反相器包括第七晶体管、第八晶体管和第九晶体管，所述第七晶体管为P型晶体管，所述第九晶体管为N型晶 体管；
所述第七晶体管的栅极和所述第九晶体管的栅极均与所述第二反相器的输出端相连，所述第八晶体管的栅极与所述时钟信号端相连；
所述第七晶体管的第一极与所述高电平输入端相连，所述第七晶体管的第二极与所述第八晶体管的第一极相连，所述第八晶体管的第二极与所述第九晶体管的第一极相连，所述第九晶体管的第二极与所述低电平输入端相连；
所述第七晶体管的第二极为所述第三反相器的输出端，所述第八晶体管为P型晶体管，所述第八晶体管的栅极与所述时钟信号端相连。
优选地，所述第四反相器包括第十晶体管、第十一晶体管和第十二晶体管，所述第十晶体管和第十一晶体管为P型晶体管，所述第十二晶体管为N型晶体管；
所述第十晶体管和所述第十二晶体管的栅极与所述第三反相器的输出端相连，所述第十一晶体管的栅极与所述时钟信号端相连；
所述第十晶体管的第一极与所述高电平输入端相连，所述第十晶体管的第二极与所述第十一晶体管的第一极相连，所述第十一晶体管的第二极与所述第十二晶体管的第一极相连，所述第十二晶体管的第二极与低电平输入端相连；
所述信号输出端与所述第十晶体管的第二极相连。
优选地，所述第一信号转换模块包括第一反相器和第二反相器，
所述第一反相器包括第一晶体管、第二晶体管和第三晶体管，所述第一晶体管的栅极和所述第三晶体管的栅极均与所述开始信号输入端相连，所述第二晶体管的栅极与所述时钟信号端相连，所述第一晶体管为P型晶体管，所述第三晶体管为N型晶体管，所述第一晶体管的第一极与所述高电平输入端相连，所述第一晶体管的第二极与所述第二晶体管的第一极相连，所述第二晶体管的第二极与所述第三晶体管的第一极相连，所述第三晶体管的第二极与所述低电平输入端相连；
所述第二晶体管为P型晶体管，所述第一反相器的输出端为所述第二晶体管的第二极；
所述第二反相器包括第四晶体管、第五晶体管和第六晶体管，所述第四晶体管为P型晶体管，所述第五晶体管和所述第六晶体管为N型晶体管；
所述第四晶体管的第一极与所述高电平输入端相连，所述第四晶体管的第二极与所述第五晶体管的第一极相连，所述第五晶体管的第二极与所述第六晶体管的第一极相连，所述第六晶体管的第二极与所述低电平输入端相连；
所述第五晶体管的栅极与所述第一反相器的输出端相连，所述第四晶体管的栅极和所述第六晶体管的栅极与所述时钟信号端相连；
所述第四晶体管的第二极为所述第二反相器的输出端，所述第五晶体管的宽长比大于所述第三晶体管的宽长比。
优选地，所述第二信号转换模块包括第三反相器和第四反相器，
所述第三反相器包括第八晶体管、第七晶体管和第九晶体管，所述第七晶体管为P型晶体管，所述第九晶体管和所述第八晶体管为N型晶体管；
所述第七晶体管的栅极和所述第九晶体管的栅极与所述第一信号转换模块的输出端相连，所述第八晶体管的栅极与所述时钟信号端相连；
所述第七晶体管的第一极与所述高电平输入端相连，所述第七晶体管的第二极与所述控制晶体管的第一极相连，所述第八晶体管的第二极与所述第九晶体管的第一极相连，所述第九晶体管的第二极与所述低电平输入端相连；
所述第四反相器包括第十晶体管和第十二晶体管，所述第十晶体管为P型晶体管，所述第十二晶体管为N型晶体管；
所述第十晶体管的栅极和所述第十二晶体管的栅极均与所述第三反相器的输出端相连，所述第十晶体管的第一极与所述高电平输入端相连，所述第十晶体管的第二极与所述第十二晶体管的第一极相连，所述第十二晶体管的第二极与所述低电平输入端相连，所述信号 输出端与所述第十晶体管的第二极相连。
优选地，所述第六晶体管的宽长比大于所述第三晶体管、所述第八晶体管和所述第九晶体管中的任意一者的宽长比。
优选地，所述第五晶体管和所述第六晶体管的宽长比均为40∶1，所述第三晶体管、所述第八晶体管、所述第九晶体管的宽长比均为10∶1。
作为本发明的另一方面，提供一种移位寄存器，所述移位寄存器包括级联的多级移位寄存单元，其中，所述移位寄存单元为本发明所提供的上述移位寄存单元。
作为本发明的再一个方面，提供一种栅极驱动电路，所述栅极驱动电路包括移位寄存器、高电平信号线、奇数时钟信号线、偶数时钟信号线、和低电平信号线，其中，所述移位寄存器为本发明所提供的上述移位寄存器，所述高电平信号线与所述高电平输入端相连，所述低电平信号线与所述低电平输入端相连，所述奇数时钟信号线与奇数级的移位寄存单元的时钟信号端相连，所述偶数时钟信号线与偶数级的移位寄存单元的时钟信号端相连。
作为本发明的还一个方面，提供一种显示装置，所述显示装置包括栅极驱动电路，其中，所述栅极驱动电路为本发明所提供的上述栅极驱动电路。
在本发明所提供的移位寄存单元中，仅需要单相时钟信号进行控制，从而简化了移位寄存单元的结构，并且降低了移位寄存单元的功耗。采用本发明所提供的移位寄存单元的显示装置可以实现窄边框和低能耗。
附图说明
附图是用来提供对本发明的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本发明，但并不构成对本发明的限制。在附图中：
图1是本发明所提供的移位寄存单元的框图；
图2是本发明所提供的移位寄存单元的一种实施方式的电路图；
图3是图2中所示的移位寄存单元的工作时序图；
图4是本发明所提供的移位寄存单元的另一种实施方式的电路图；
图5是图4中所示的移位寄存单元的工作时序图。
附图标记说明
100：第一信号转换模块  200：第二信号转换模块
110：第一反相器        120：第二反相器
210：第三反相器        220：第四反相器
T1：第一晶体管         T2：第二晶体管
T3：第三晶体管         T4：第四晶体管
T5：第五晶体管         T6：第六晶体管
T7：第七晶体管         T8：第八晶体管
T9：第九晶体管         T10：第十晶体管
T11：第十一晶体管      T12：第十二晶体管
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本发明，并不用于限制本发明。
如图1所示，作为本发明的一个方面，提供一种移位寄存单元，所述移位寄存单元包括开始信号输入端Vin、时钟信号端CK、高电平输入端VDD、低电平输入端VSS和信号输出端Vout，并且还包括第一信号转换模块100和第二信号转换模块200。第一信号转换模块100的输入端与开始信号输入端Vin相连，第一信号转换模块100的输出端与第二信号转换模块200的输入端相连，第二信号转换模块200的输出端与信号输出端Vout相连。第一信号转换模块100还分别与时钟信号端CK、高电平输入端VDD相连和低电平输入端VSS相连。第二信号转换模块200还分别与时钟信号端CK、高电平输入端VDD相连和低电平输入端VSS相连，通过高电平输入端VDD输 入的高电平信号与通过低电平输入端VSS输入的低电平信号中的一者为有效信号，另一者为无效信号，通过所述时钟信号端CLK输入时钟信号。
在所述时钟信号为第一电平、所述开始信号为无效信号的预处理阶段(图3和图5中的t0阶段)，第一信号转换模块100能够向第二信号转换模块200输出无效信号，第二信号转换模块200能够根据第一信号转换模块100输出的无效信号以及时钟信号输出无效信号。
在所述时钟信号为第二电平、所述开始信号为有效信号的第一信号写入阶段(图3和图5中的t1阶段)，第一信号转换模块100能够向第二信号转换模块200输出无效信号，第二信号转换模块200能够根据第一信号转换模块100输出的无效信号以及所述时钟信号输出无效信号。
在所述时钟信号为第一电平、所述开始信号为有效信号的第二信号写入阶段(图3和图5中的t2阶段)，第一信号转换模块100能够向第二信号转换模块200输出有效信号，第二信号转换模块200能够根据第一信号转换模块100输出的有效信号以及所述时钟信号输出无效信号。
在所述时钟信号为第二电平、所述开始信号为无效信号的第一输出阶段(图3和图5中的t3阶段)，第一信号转换模块100能够向第二信号转换模块200输出有效信号，第二信号转换模块200能够根据第一信号转换模块100输出的有效信号以及所述时钟信号输出有效信号。
在所述时钟信号为第一电平、所述开始信号为无效信号的第二输出阶段(图3和图5中的t4阶段)，第一信号转换模块100能够向第二信号转换模块200输出无效信号，第二信号转换模块200能够根据第一信号转换模块100输出的无效信号以及所述时钟信号输出有效信号。
容易理解的是，第一电平不同于第二电平。当第一电平为高电平时，第二电平则为低电平；当第一电平为低电平时，第二电平则为 高电平。“有效信号”和“无效信号”的电平高低是根据采用所述移位寄存单元的显示装置的显示区中的薄膜晶体管的类型确定的，其中所谓的“有效信号”是指能够使得显示装置的显示区中的薄膜晶体管导通的信号，而所谓的“无效信号”则是指能够使得显示装置的显示区中的薄膜晶体管截止的信号。
上述五个阶段结束后，完成了一次输入信号的移位。通过以上描述可知，在本发明所提供的移位寄存单元中，仅需要单相时钟信号进行控制，从而简化了移位寄存单元的结构，并且降低了移位寄存单元的功耗。采用本发明所提供的移位寄存单元的显示装置可以实现窄边框和低能耗。
作为本发明的一种实施方式，第一信号转换模块100和第二信号转换模块200可以分别是正锁存器和负锁存器中的一种和另一种。例如，第一信号转换模块100为正锁存器，第二信号转换模块200为负锁存器。这种情况下，所述第一电平为高电平，所述第二电平为低电平，当所述时钟信号端CK输入的信号为第一电平时，第一信号转换模块100处于透明模式，第二信号转换模块200处于维持模式；当所述时钟信号为第二电平时，第一信号转换模块100处于维持模式，第二信号转换模块200处于透明模式。
本领域技术人员应当理解的是，当锁存模块处于透明模式时，锁存模块的输出信号与其输入信号相同，当锁存模块处于维持模式时，锁存模块维持上一阶段的输出信号不变。
当第一信号转换模块100处于透明模式时，该第一信号转换模块100的输出信号与输入至第一信号转换模块100的输入信号相同；当第一信号转换模块100处于维持模式时，输出信号与上一阶段的信号相同。同样地，当第二信号转换模块200处于透明模式时，该第二信号转换模块200的输出信号与输入第二信号转换模块200的输入信号相同，当第二信号转换模块200处于维持模式时，输出信号维持上一阶段的输出信号不变。
在本发明中，输入信号的脉冲宽度大于时钟信号的脉冲宽度，并且，输入信号的高电平持续时间与时钟信号的一个周期的时间相 同。
当输入信号为有效信号时、时钟信号为第二电平时，第一信号转换模块100处于维持状态，因此，第一信号转换模块100输出的信号为无效信号。由于时钟信号为第二电平信号，第二信号转换模块200处于透明状态，因此，第二信号转换模块200可以输出与第一信号转换模块100所输出的无效信号相同的信号。
当输入信号为有效信号、时钟信号为第一电平时，第一信号转换模块100处于透明状态，因此，第一信号转换模块100输出的信号与输入信号相同，均为有效信号。由于时钟信号为第一电平，因此，第二信号转换模块200处于维持状态，第二信号转换模块200输出的输出信号仍然是上一阶段的无效信号。
当输入信号为无效信号、时钟信号为第二电平时，第一信号转换模块100处于维持状态，仍然可以维持输出上一个阶段的有效信号。由于时钟信号为第二电平，因此第二信号转换模块200处于透明状态，其可以输出与输入至第二信号转换模块200的信号相同的信号，因此可以输出有效的信号。
通过上述描述还可以知道，本发明所提供的移位寄存单元中的第一信号转换模块100和第二信号转换模块200构成了主从边沿触发器，因此，消除了时钟信号的占空比的大小对输出信号的影响，可以获得稳定的有效输出信号。并且，输出信号的有效信号持续时间仅与时钟信号的周期有关，有效避免了现有技术中多相时钟信号重叠所带来的不良影响。
当使用所述移位寄存单元的显示装置的显示区中的薄膜晶体管为P型晶体管时，有效信号为低电平信号；当使用所述移位寄存单元的显示装置的显示区中的薄膜晶体管为N型晶体管时，有效信号为高电平信号。
在本发明所提供的实施方式中，有效信号为高电平信号，无效信号为低电平信号。
并且，在本发明中，第一电平和第二电平的高低也没有具体的规定，第一电平和第二电平的高低则是由第一信号转换模块和第二信 号转换模块中采用的晶体管的类型所决定的。
在本发明中，对第一信号转换模块100以及第二信号转换模块200的具体结构并没有特殊的限制，只要第一信号转换模块100和第二信号转换模块200串联能够形成主从边沿触发器，进而实现移位寄存单元的功能即可。
作为本发明的一种实施方式，如图2中所示，第一信号转换模块100包括串联的第一反相器110和第二反相器120，当通过时钟信号端CK输入的时钟信号为第一电平时，第一反相器110能够将输入的所述开始信号反相，第二反相器120能够将第一反相器110输出的信号反相。在图2所示的实施例中，第一电平为高电平，第二电平为低电平。
相应地，第二信号转换模块200包括串联的第三反相器210和第四反相器220，当通过时钟信号端CK输入的时钟信号为第二电平时，第三反相器210能够将第二反相器120输出的信号反相，并且第四反相器220能够将第三反相器210输出的信号反相。
当时钟信号为第一电平时，第一反相器110将通过开始信号输入端Vin输入的信号进行第一反相操作，并将第一反相操作后的信号输送至第二反相器120，而第二反相器120将第一反相操作后的信号进行第二反相操作，也就是说，第二反相操作后的信号电平与原始的输入信号相同，从而实现了第一信号转换模块100的透明模式。当时钟信号为第二电平信号时，第一反相器110不进行反相操作(即，第一反相器110维持上一个阶段的输出)，第二反相器120也不进行反相操作(即，第二反相器120维持上一个阶段的输出)，从而可以使得第一信号转换模块100处于维持状态。
当时钟信号为第一电平时，第三反相器210和第四反相器220不进行反相操作，从而可以使得第二信号转换模块200处于维持状态。当时钟信号为第二电平时，第三反相器220能够将第二反相器输出的信号进行第一反相操作，并将第一反相操作后的信号输出至第四反相器230，第四反相器230能够对第一反相操作后的信号进行第二反相操作，也就是说，第二反相操作后的信号电平与原始的输入信号 相同，从而实现了第二信号转换模块200的透明模式。
在本发明中，对上述各个反相器(包括第一反相器、第二反相器、第三反相器和第四反相器)的具体结构并没有特殊的规定。
作为本发明的一种实施方式，如图2中所示，第一反相器110包括第一晶体管T1、第二晶体管T2和第三晶体管T3，其中第一晶体管T1为P型晶体管，第二晶体管T2和第三晶体管T3为N型晶体管，第一晶体管T1的栅极和第三晶体管T3的栅极均与开始信号输入端Vin相连，第二晶体管T2的栅极与时钟信号端CK相连，，第一晶体管T1的第一极与高电平输入端VDD相连，第一晶体管T1的第二极与第二晶体管T2的第一极相连，第二晶体管T2的第二极与所述第三晶体管T3的第一极相连，第三晶体管T3的第二极与所述低电平输入端VSS相连。第二晶体管T2的第一极为第一反相器110的输出端。
当第一反相器110具有上述结构时，第一电平信号应当为高电平信号，而第二电平信号应当为低电平信号。在具有上述结构的第一反相器中，既包括P型晶体管，又包括N型晶体管，因此，可以利用CMOS工艺形成第一反相器，从而使得第一反相器具有速度快、集成度高、抗干扰能力强等优点。
当通过时钟信号端CK输入的时钟信号为高电平信号时，第二晶体管T2导通。由于第一晶体管T1为P型晶体管，而第三晶体管T3为N型晶体管，因此，无论输入信号是高电平还是低电平，第一晶体管T1和第三晶体管T3中必有一个是导通的、而另一个是截止的。当开始信号为高电平信号时，第一晶体管T1截止，第三晶体管T3导通，从而将第二晶体管T2的第一极与低电平输入端VSS导通，从而输出低电平信号，相当于将开始信号反相。当开始信号为低电平时，第三晶体管T3截止，第一晶体管T1导通，从而将第二晶体管T2的第一极与高电平输入端VDD导通，从而输出高电平信号，亦相当于将开始信号反相。
当时钟信号为低电平信号时，第二晶体管T2截止。这种情况下，当输入信号为高电平信号，虽然第八晶体管T3能够导通，但是由于 第二晶体管T2是截止的，因此，第二晶体管T2的第一极维持上一个阶段的输出；当输入信号为低电平信号时，第一晶体管T1导通，第一反相器110输出高电平信号。
同样地，图2中还示出了第二反相器的一种具体实施方式。具体地，第二反相器120包括第四晶体管T4、第五晶体管T5和第六晶体管T6，其中，第四晶体管T4为P型晶体管，第五晶体管T5和第六晶体管T6为N型晶体管。
第四晶体管T4的第一极与高电平输入端VDD相连，第四晶体管T4的第二极与第五晶体管T5的第一极相连，第五晶体管T5的第二极与第六晶体管T6的第一极相连，第六晶体管T6的第二极与低电平输入端VSS相连。
第五晶体管T5的栅极与时钟信号端CK相连，第四晶体管T4的栅极和第六晶体管T6的栅极与第一反相器110的输出端相连，并且第四晶体管T4的第二极为第二反相器120的输出端。
在图2中所示的实施方式中，当通过时钟信号端CK输入的时钟信号为高电平信号时，第五晶体管T5导通。这种情况下，如果第一反相器110输出高电平信号，那么第四晶体管T4截止，而第六晶体管T6导通，从而将第五晶体管T5的第一极与低电平输入端导通，从而输出低电平信号；如果第一反相器110输出低电平信号，那么第六晶体管T6截止，第四晶体管T4导通，从而将第五晶体管T5的第一极与高电平输入端VDD导通，从而输出高电平信号。
在图2中所示的实施方式中，当通过时钟信号端CK输入的时钟信号为低电平时，第五晶体管T5截止。这种情况下，如果第一反相器110输出高电平，第四晶体管T4截止，第六晶体管T6导通，由于第五晶体管T5截止，因此，第二反相器120维持上一阶段的电平(在本实施例中为低电平)；当第一反相器110输出低电平，第四晶体管T4导通，因此，第二反相器120可以输出高电平信号。
同样地，图2中还示出了第三反相器210的实施方式。第三反相器210包括第七晶体管T7、第八晶体管T8和第九晶体管T9，其中第七晶体管T7和第八晶体管T8为P型晶体管，第九晶体管T9为 N型晶体管。
第七晶体管T7的栅极和第九晶体管T9的栅极均与第二反相器120的输出端相连，第八晶体管T8的栅极与时钟信号端CK相连。第七晶体管T7的第一极与高电平输入端VDD相连，第七晶体管T7的第二极与第八晶体管T8的第一极相连，第八晶体管T8的第二极与第九晶体管T9的第一极相连，第九晶体管T9的第二极与低电平输入端VSS相连。第七晶体管T7的第二极为第三反相器210的输出端。
在图2中所示的实施方式中，当通过时钟信号端CK输入的时钟信号为低电平信号时，第八晶体管T8导通。当第一信号转换模块100输出的信号为高电平信号时，第七晶体管T7截止，第九晶体管T9导通，从而将第八晶体管T8的第一极通过第九晶体管T9连接至低电平输入端VSS，使得第三反相器210输出低电平信号。当第一信号转换模块100输出的信号为低电平信号时，第七晶体管T7导通，第九晶体管T9截止，第八晶体管T8的第一极通过第七晶体管T7连接至高电平输入VDD，因此，第三反相器输出高电平信号。
当通过时钟信号端CK输入的时钟信号为高电平信号时，第八晶体管T8截止。这种情况下，当第一信号转换模块100输出的信号为高电平信号时，第九晶体管T9导通，第七晶体管T7截止。由于第八晶体管T8截止，因此，第八晶体管T8的第一极维持上一个阶段的电平信号。当通过时钟信号端CK输入的时钟信号为低电平信号时，第八晶体管T8导通。当第一信号转换模块100的输出端Vin’输出的信号为高电平信号时，第九晶体管T9导通，第七晶体管T7截止，从而将第八晶体管T8的第一端通过第九晶体管T9连接至低电平输入端VSS，输出低电平信号。当第一信号转换模块100的输出端Vin’输出的信号为低电平信号时，第七晶体管T7导通，第九晶体管T9截止，因此，第八晶体管T8的第一极与高电平输入端VDD导通，输出高电平信号。
在图2中还示出了第四反相器220的一种具体实施方式。具体地，第四反相器220包括第十晶体管T10、第十一晶体管T11和第十 二晶体管T12，第十晶体管T10和第十一晶体管T11为P型晶体管，第十二晶体管T12为N型晶体管。第十晶体管T10和第十二晶体管T12的栅极与第三反相器210的输出端相连，第十一晶体管T11的栅极与时钟信号端CK相连。第十晶体管T10的第一极与高电平输入端VDD相连，第十晶体管T10的第二极与第十一晶体管T11的第一极相连，第十一晶体管T11的第二极与第十二晶体管T12的第一极相连，第十二晶体管T12的第二极与低电平输入端VSS相连。信号输出端Vout与第十晶体管T10的第二极相连。
当通过时钟信号端CK输入的时钟信号为高电平信号时，第十一晶体管T11截止。这种情况下，当第三反相器210输出的信号为高电平信号时，第十晶体管T10截止，第十二晶体管T12导通，第十一晶体管T11的第一极维持上一个阶段的电位；当第三反相器输出的信号为低电平信号时，第十晶体管T10导通，第十二晶体管T12截止，从而将信号输出端Vout与高电平输入端VDD导通，使得所述移位寄存单元输出高电平信号(相当于将第三反相器210输出的信号反相)。
当通过时钟信号端CK输入的时钟信号为低电平信号时，第十一晶体管T11导通。当第三反相器210输出的信号为高电平信号时，第十二晶体管T12导通，从而将第十一晶体管T11的第一极与低电平输入端VSS导通，输出低电平信号。当第三反相器210输出的信号为低电平信号时，第十晶体管T10导通，将第十一晶体管T11的第一极与高电平输入端VDD导通，从而输出高电平信号。
下面结合图2和图3描述图2中所示的具体实施方式的工作原理。在这种实施方式中，第一电平信号为高电平信号，第二电平信号为低电平信号。
在图2所示的实施方式中，第一反相器110的第二晶体管T2为N型晶体管，第一反相器110的输出端为第二晶体管T2的第一极。第二反相器120的第五晶体管T5的栅极与时钟信号端CK相连，第二反相器120的第四晶体管T4的栅极以及第六晶体管T6的栅极均与第一反相器110的输出端相连。第四反相器220包括第十一晶体管 T11、第十晶体管T10和第十二晶体管T12。第一反相器110和第二反相器120串联形成了第一信号转换模块100，第三反相器210和第四反相器220串联形成了第二信号转换模块200。在这种实施方式中，第一电平信号为高电平信号，第二电平信号为低电平信号，并且，有效信号为高电平信号。
如图3中所示，通过开始信号输入端Vin输入的开始信号的高电平持续时间与时钟信号的一个周期持续的时间相同。
在t0阶段，由于时钟信号为高电平信号，因此第二晶体管T2导通、第五晶体管T5导通、第八晶体管T8截止，第十一晶体管T11截止。由于开始信号为低电平信号，因此，第一晶体管T1导通，第三晶体管T3截止，使得第一反相器110输出高电平信号。第一反相器110输出的高电平信号使得第二反相器的第六晶体管T6导通，第四晶体管T4截止，因此，第二反相器120输出低电平信号。此时，第一信号转换模块100此时处于透明状态，也就是说，第一信号转换模块100的输入信号和输出信号都为低电平信号。由于第一信号转换模块100的输出端Vin’输出的信号为低电平信号，因此，第三反相器210的第七晶体管T7导通，第九晶体管T9截止，因此，第三反相器210输出的信号为高电平信号，从而使得第四反相器220的第十晶体管T10截止、第十二晶体管T12导通，从而可以使得信号输出端Vout维持上一个阶段的输出信号，也就是实现了第二信号转换模块200的维持状态。
在t1阶段，由于时钟信号为低电平信号，因此第一反相器110的第二晶体管T2截止，第二反相器120的第五晶体管T5截止。由于开始信号为高电平信号，因此，第一晶体管T1截止，第三晶体管T3导通，第二晶体管T2的第一极维持t0阶段的高电平信号，使得第六晶体管T6导通，第四晶体管T4截止，因此，第五晶体管T5输出的也是t0阶段的信号，也就是说，第一信号转换模块处于维持模式并维持上一个阶段的信号。第一信号转换模块100的输出节点Vin’输出的信号为低电平信号。由于在t1阶段中时钟信号为低电平，因此，第三反相器210的第八晶体管T8导通，通过第一信号转换模块 100的输出节点Vin’输入到第三反相器210的信号被反相为高电平信号。此时，第四反相器210的第十一晶体管T11导通，因此，第四反相器210将输入该第四反相器的信号反相为低电平信号，使得信号输出端Vout输出低电平信号，从而实现第二信号转换模块200的透明模式。
在t2阶段，由于时钟信号为高电平，因此第一反相器110的第二晶体管T2导通、第二反相器120的第五晶体管T5导通，因此，第一反相器110和第二反相器120均可进行反相操作。由于开始信号为高电平信号，因此，第一反相器110输出的信号为低电平信号，第二反相器120输出的信号为高电平信号，从而实现了第一信号转换模块100的透明模式。由于时钟信号为高电平信号，因此，第三反相器210的第八晶体管T8和第四反相器220的第十一晶体管T11均截止，这种情况下，由于第一信号转换模块100的输出端Vin’输出的信号为高电平信号，因此，第三反相器210的第九晶体管T9导通，第三反相器210的第七晶体管T7截止，第三反相器210的输出端维持上一阶段的高电平信号，使得第四反相器的第十晶体管T10截止，第四反相器的第十二晶体管T12导通，因此，第四反相器输出上一阶段的低电平信号，从而实现第二信号转换模块200的维持模式。
在t3阶段，由于时钟信号为低电平信号，因此第一反相器110的第二晶体管T2和第二反向器120的第五晶体管T5截止；由于开始信号为低电平信号，因此第一晶体管T1导通，第一反相器110输出高电平信号，使得第六晶体管T6导通，第四晶体管T4截止，因此，第二反相器120维持上一阶段的高电平信号。此时，第一信号转换模块100处于维持模式。由于时钟信号为低电平信号，因此，第三反相器210的第八晶体管T8、第四反相器220的第十一晶体管T11导通。由于第三反相器210的输入信号为高电平信号，因此，第三反相器210的输出信号为低电平信号，第四反相器的输出信号为高电平信号，从而实现第二信号转换模块200的透明模式。
在t4阶段，由于时钟信号为高电平，因此第一反相器110的第二晶体管T2导通，第二反相器120的第五晶体管T5导通；由于开 始信号为低电平，因此，第一晶体管T1导通，第三晶体管T3截止，第一反相器110输出高电平信号，第二反相器的第六晶体管T6导通，第四晶体管T4截止，因此，第二反相器120输出低电平信号，使得第一信号转换模块100处于透明状态。由于时钟信号为高电平信号，因此，第八晶体管T8和第十一晶体管T11截止。由于第一信号转换模块100输出低电平信号，因此，第七晶体管T7导通，第九晶体管T9截止，所以第三反相器210输出高电平信号，将第四反相器的第十二晶体管T12导通，将第十晶体管T10截止，因此，第四反相器220可以输出上一个阶段的高电平信号，使得第二信号转换模块200处于维持状态。
至此，完成一次移位操作，通过信号输入端Vin输入的开始信号经过移位后成为通过信号输出端Vout输出的输出信号。
除了图2中所示的实施方式之外，第一信号转换模块100还可以具有图4中所示的实施方式。
具体地，如图4中所示，第一信号转换模块100包括第一反相器110和第二反相器120。
第一反相器110包括第一晶体管T1、第二晶体管T2和第三晶体管T3，其中第一晶体管T1为P型晶体管，第二晶体管T2和第三晶体管T3为N型晶体管。第一晶体管T1的栅极和第三晶体管T3的栅极均与所述开始信号输入端Vin相连，第二晶体管T2的栅极与所述时钟信号端相连，第一晶体管T1的第一极与所述高电平输入端VDD相连，第一晶体管T1的第二极与第二晶体管T2的第一极相连，第二晶体管T2的第二极与第三晶体管T3的第一极相连，第三晶体管T3的第二极与所述低电平输入端VSS相连。第二晶体管T2的第二极为所述第一反相器的输出端。
所述第二反相器包括第四晶体管T4、第五晶体管T5和第六晶体管T6，其中第四晶体管T4为P型晶体管，第五晶体管T5和第六晶体管T6为N型晶体管。
第四晶体管T4的第一极与所述高电平输入端VDD相连，第四晶体管T4的第二极与第五晶体管T5的第一极相连，第五晶体管T5 的第二极与第六晶体管T6的第一极相连，第六晶体管T6的第二极与所述低电平输入端VSS相连。
第五晶体管T5的栅极与所述第一反相器的输出端相连，第四晶体管T4的栅极和第六晶体管T6的栅极与所述时钟信号端相连。
第四晶体管T4的第二极为所述第二反相器的输出端，第五晶体管T5的宽长比大于第三晶体管T3的宽长比。
第五晶体管T5、第六晶体管T6的宽长比大于第三晶体管T3、第八晶体管T8、第九晶体管T9的宽长比，可以使得第五晶体管T5的第一极的放电速度大于第三晶体管T3的第一极的放电速度并且大于第八晶体管T8第一极的放电速度。如此设置的优点是可使输出信号稳定，没有毛刺。例如，第五晶体管T5和第六晶体管T6的宽长比可以均为40∶1，第三晶体管T3、第八晶体管T8、第九晶体管T9的宽长比可以均为10∶1，但是本发明不限于此。
优选地，第二信号转换模块200包括第三反相器210和第四反相器220。
第三反相器210包括第八晶体管T8、第七晶体管T7和第九晶体管T9。其中，第七晶体管T7为P型晶体管，第九晶体管T9和第八晶体管T8为N型晶体管。
第七晶体管T7的栅极和第九晶体管T9的栅极与所述第一信号转换模块100的输出端相连，第八晶体管T8的栅极与所述时钟信号端CLK相连。
第七晶体管T7的第一极与所述高电平输入端VDD相连，第七晶体管T7的第二极与第八晶体管T8的第一极相连，第八晶体管T8的第二极与第九晶体管T9的第一极相连，第九晶体管T9的第二极与所述低电平输入端VSS相连。
所述第四反相器包括第十晶体管T10和第十二晶体管T12，其中第十晶体管T10为P型晶体管，第十二晶体管T12为N型晶体管；
第十晶体管T10的栅极和第十二晶体管T12的栅极均与所述第三反相器210的输出端相连，第十晶体管T10的第一极与所述高电平输入端VDD相连，第十晶体管T10的第二极与第十二晶体管T12 的第一极相连，第十二晶体管T12的第二极与所述低电平输入端VSS相连，所述信号输出端与第十晶体管T10的第二极相连。
下面结合图4和图5描述本发明的第二种实施方式的移位寄存单元的具体工作原理。如图4所示的第二种实施方式的移位寄存单元只需要11个晶体管，进一步简化了移位寄存单元的结构。
在图4中所示的实施方式中，第一电平信号为低电平信号，第二电平信号为高电平信号。
在开始信号为低电平信号、时钟信号为低电平信号的t0阶段，第二晶体管T2导通，第一晶体管T1导通，第三晶体管T3截止，使得第一反相器110输出高电平信号。第一反相器110输出的高电平信号使得第二反相器120的第五晶体管T5导通，并且此时第二反相器120的第四晶体管T4导通，第六晶体管T6截止，因此，第二反相器120输出高电平信号。由于第一信号转换模块100的输出端输出的信号为高电平信号，因此，第三反相器210的第七晶体管T7截止，第九晶体管T9导通，由于第八晶体管T8截止，因此，第八晶体管T8的第一极维持上一个阶段的高电平信号，从而使得第四反相器220的第十晶体管T10截止以及第十二晶体管T12导通，从而使得信号输出端Vout输出低电平信号。
在开始信号为高电平信号、时钟信号为高电平信号的t1阶段，第一反相器110的第二晶体管T2截止，第三反相器210的第八晶体管T8导通。由于开始信号为高电平信号，因此，第一反相器110的第三晶体管T3导通、第一晶体管T1截止，因此，第一反相器110输出低电平信号。由于第五晶体管T5、第六晶体管T6的宽长比大于第三晶体管T3的宽长比，因此，第五晶体管T5、第六晶体管T6的放电速度大于第三晶体管T3、第八晶体管T8、第九晶体管T9的放电速度，因此，第七晶体管T7的栅极更早地放电到低电平信号，将第七晶体管T7导通，第九晶体管T9截止，并使得该第七晶体管T7的第二极通过第七晶体管T7的第一极连接至高电平输入端VDD，从而向第四反相器220输出高电平信号，将第四反相器220的第十二晶 体管T12导通，以将信号输出端Vout通过第十二晶体管T12连接至低电平输入端VSS，从而输出低电平信号。
在开始信号为高电平信号、时钟信号为低电平信号的t2阶段，在第一反相器110中，第二晶体管T2导通，第三晶体管T3导通，第一反相器110输出低电平信号，将第二反相器120的第五晶体管T5截止。第四晶体管T4是导通的，因此，第二反相器120输出高电平信号，将第九晶体管T9导通并将第七晶体管T7截止，第八晶体管T8截止，因此第八晶体管T8的第一极维持t1阶段的高电平信号，从而将第十晶体管T10截止、第十二晶体管T12导通，以使得信号输出端Vout通过第十二晶体管T12连接至低电平输入端VSS，从而输出低电平信号。
在开始信号为低电平信号、时钟信号为高电平信号的t3阶段，第一晶体管T1导通，第二晶体管T2截止，第三晶体管T3截止，因此，第一反相器的输出端输出上一阶段的低电平信号。第五晶体管T5截止，第四晶体管T4截止，第六晶体管T6导通，第五晶体管T5的第一极维持上一个阶段的高电平信号，从而将第九晶体管T9导通。由于第八晶体管T8也是导通的且第七晶体管T7截止，因此，第三反向器输出低电平信号，将第十晶体管T10导通，第十二晶体管T12截止，从而将信号输出端Vout通过第十晶体管T10连接至高电平输入端VDD，从而输出高电平信号。
在开始信号为低电平信号、时钟信号也为低电平信号的t4阶段，第一晶体管T1和第二晶体管T2均导通，第三晶体管T3截止，因此，第一反相器110输出高电平信号。第五晶体管T5导通，第四晶体管T4导通，第六晶体管T6截止，第二反相器120输出高电平信号。第九晶体管T9导通，第七晶体管T7截止，第八晶体管T8截止，因此，第八晶体管T8的第一极维持上一个阶段的低电平信号，从而将第十晶体管T10导通，第十二晶体管T12截止，从而将信号输出端Vout通过第十晶体管T10连接至高电平输入端VDD，从而输出高电平信号。
至此，完成一次移位操作，通过信号输入端Vin输入的开始信 号经过移位后成为通过信号输出端Vout输出的输出信号。
作为本发明的另一个方面，提供一种移位寄存器，所述移位寄存器包括级联的多级移位寄存单元，其中，所述移位寄存单元为本发明所提供的上述移位寄存单元。
由于所述移位寄存单元具有较为简单的结构，因此，本发明所提供的移位寄存器也具有较为简单的结构。
作为本发明的再一个方面，提供一种栅极驱动电路，所述栅极驱动电路包括移位寄存器、高电平信号线、奇数时钟信号线、偶数时钟信号线、和低电平信号线，其中，所述移位寄存器为本发明所提供的上述移位寄存器，所述高电平信号线与所述高电平输入端相连，所述低电平信号线与所述低电平输入端相连，所述奇数时钟信号线与奇数级的移位寄存单元的时钟信号端相连，所述偶数时钟信号线与偶数级的移位寄存单元的时钟信号端相连。
作为本发明的还一个方面，提供一种显示装置，所述显示装置包括栅极驱动电路，其中，所述栅极驱动电路为本发明所提供的上述栅极驱动电路。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (14)

  1. 一种移位寄存单元，所述移位寄存单元包括开始信号输入端、时钟信号端、高电平输入端、低电平输入端和信号输出端以及第一信号转换模块和第二信号转换模块，其中
    所述第一信号转换模块的输入端与所述开始信号输入端相连，所述第一信号转换模块的输出端与所述第二信号转换模块的输入端相连，所述第二信号转换模块的输出端与所述信号输出端相连，所述第一信号转换模块还分别与所述时钟信号端、所述高电平输入端相连和所述低电平输入端相连，所述第二信号转换模块还分别与所述时钟信号端、所述高电平输入端相连和所述低电平输入端相连，通过所述高电平输入端输入的高电平信号与通过所述低电平输入端输入的低电平信号中的一者为有效信号，另一者为无效信号，并且通过所述时钟信号端输入时钟信号；
    在所述时钟信号为第一电平、所述开始信号为无效信号的预处理阶段，所述第一信号转换模块向所述第二信号转换模块输出无效信号，所述第二信号转换模块根据所述第一信号转换模块输出的无效信号以及所述时钟信号输出无效信号；
    在所述时钟信号为第二电平、所述开始信号为有效信号的第一信号写入阶段，所述第一信号转换模块向所述第二信号转换模块输出无效信号，所述第二信号转换模块根据所述第一信号转换模块输出的无效信号以及所述时钟信号输出无效信号；
    在所述时钟信号为第一电平、所述开始信号为有效信号的第二信号写入阶段，所述第一信号转换模块向所述第二信号转换模块输出有效信号，所述第二信号转换模块根据所述第一信号转换模块输出的有效信号以及所述时钟信号输出无效信号；
    在所述时钟信号为第二电平、所述开始信号为无效信号的第一输出阶段，所述第一信号转换模块向所述第二信号转换模块输出有效信号，所述第二信号转换模块根据所述第一信号转换模块输出的有效信号以及所述时钟信号输出有效信号；
    在所述时钟信号为第一电平、所述开始信号为无效信号的第二输出阶段，所述第一信号转换模块向所述第二信号转换模块输出有效信号，所述第二信号转换模块根据所述第一信号转换模块输出的有效信号以及所述时钟信号输出有效信号。
  2. 根据权利要求1所述的移位寄存单元，其中，所述第一信号转换模块和所述第二信号转换模块分别为正锁存器和负锁存器中的一种，并且其中
    当所述时钟信号为第一电平时，所述第一信号转换模块处于透明模式，所述第二信号转换模块处于维持模式；
    当所述时钟信号为第二电平时，所述第一信号转换模块处于维持模式，所述第二信号转换模块处于透明模式。
  3. 根据权利要求2所述的移位寄存单元，其中，所述第一信号转换模块包括串联的第一反相器和第二反相器，当所述时钟信号为所述第一电平时，所述第一反相器将输入的所述开始信号反相并输出至所述第二反相器，所述第二反相器将第一反相器输出的信号反相；
    所述第二信号转换模块包括串联的第三反相器和第四反相器，当所述时钟信号为第二电平信号时，所述第三反相器将所述第二反相器输出的信号反相并输出至所述第四反相器，并且所述第四反相器将所述第三反相器输出的信号反相。
  4. 根据权利要求3所述的移位寄存单元，其中，所述第一反相器包括第一晶体管、第二晶体管和第三晶体管，并且所述第一晶体管为P型晶体管，所述第二晶体管和所述第三晶体管为N型晶体管；
    所述第一晶体管的栅极和所述第三晶体管的栅极均与所述开始信号输入端相连，所述第二晶体管的栅极与所述时钟信号端相连，所述第一晶体管的第一极与所述高电平输入端相连，所述第一晶体管的第二极与所述第二晶体管的第一极相连，所述第二晶体管的第二极与所述第三晶体管的第一极相连，所述第三晶体管的第二极与所述低电 平输入端相连，并且所述第二晶体管的第一极为所述第一反相器的输出端；
    其中，所述第一电平为高电平，所述第二电平为低电平。
  5. 根据权利要求3所述的移位寄存单元，其中，所述第二反相器包括第四晶体管、第五晶体管和第六晶体管，所述第四晶体管为P型晶体管，所述第五晶体管和所述第六晶体管为N型晶体管；
    所述第四晶体管的第一极与所述高电平输入端相连，所述第四晶体管的第二极与所述第五晶体管的第一极相连，所述第五晶体管的第二极与所述第六晶体管的第一极相连，所述第六晶体管的第二极与所述低电平输入端相连；所述第五晶体管的栅极与所述时钟信号端相连，所述第四晶体管的栅极和所述第六晶体管的栅极均与所述第一反相器的输出端相连；并且所述第四晶体管的第二极为所述第二反相器的输出端；
    其中，所述第一电平为高电平，所述第二电平为低电平。
  6. 根据权利要求3所述的移位寄存单元，其中，所述第三反相器包括第七晶体管、第八晶体管和第九晶体管，所述第七晶体管和第八晶体管为P型晶体管，所述第九晶体管为N型晶体管；
    所述第七晶体管的栅极和所述第九晶体管的栅极均与所述第二反相器的输出端相连，所述第八晶体管的栅极与所述时钟信号端相连；所述第七晶体管的第一极与所述高电平输入端相连，所述第七晶体管的第二极与所述第八晶体管的第一极相连，所述第八晶体管的第二极与所述第九晶体管的第一极相连，所述第九晶体管的第二极与所述低电平输入端相连；并且所述第七晶体管的第二极为所述第三反相器的输出端；
    其中，所述第一电平为高电平，所述第二电平为低电平。
  7. 根据权利要求3所述的移位寄存单元，其中，所述第四反相器包括第十晶体管、第十一晶体管和第十二晶体管，所述第十晶体管 和第十一晶体管为P型晶体管，所述第十二晶体管为N型晶体管；
    所述第十晶体管和所述第十二晶体管的栅极与所述第三反相器的输出端相连，所述第十一晶体管的栅极与所述时钟信号端相连；所述第十晶体管的第一极与所述高电平输入端相连，所述第十晶体管的第二极与所述第十一晶体管的第一极相连，所述第十一晶体管的第二极与所述第十二晶体管的第一极相连，所述第十二晶体管的第二极与低电平输入端相连；并且所述信号输出端与所述第十晶体管的第二极相连，
    其中，所述第一电平为高电平，所述第二电平为低电平。
  8. 根据权利要求3所述的移位寄存单元，其中，所述第一反相器包括第一晶体管、第二晶体管和第三晶体管，其中所述第一晶体管和所述第二晶体管为P型晶体管，所述第三晶体管为N型晶体管；
    所述第一晶体管的栅极和所述第三晶体管的栅极均与所述开始信号输入端相连，所述第二晶体管的栅极与所述时钟信号端相连，所述第一晶体管的第一极与所述高电平输入端相连，所述第一晶体管的第二极与所述第二晶体管的第一极相连，所述第二晶体管的第二极与所述第三晶体管的第一极相连，所述第三晶体管的第二极与所述低电平输入端相连，并且所述第二晶体管的第二极为所述第一反相器的输出端；
    所述第二反相器包括第四晶体管、第五晶体管和第六晶体管，其中所述第四晶体管为P型晶体管，所述第五晶体管和所述第六晶体管为N型晶体管；
    所述第四晶体管的第一极与所述高电平输入端相连，所述第四晶体管的第二极与所述第五晶体管的第一极相连，所述第五晶体管的第二极与所述第六晶体管的第一极相连，所述第六晶体管的第二极与所述低电平输入端相连；所述第五晶体管的栅极与所述时钟信号端相连，所述第四晶体管的栅极和所述第六晶体管的栅极与所述第一反相器的输出端相连，并且所述第四晶体管的第二极为所述第二反相器的输出端；
    其中，所述第五晶体管的宽长比大于所述第三晶体管的宽长比；
    其中，所述第一电平为低电平，所述第二电平为高电平。
  9. 根据权利要求3所述的移位寄存单元，其中，所述第三反相器包括第八晶体管、第七晶体管和第九晶体管，所述第七晶体管为P型晶体管，所述第八晶体管和所述第九晶体管为N型晶体管；
    所述第七晶体管的栅极和所述第九晶体管的栅极与所述第一信号转换模块的输出端相连，所述第八晶体管的栅极与所述时钟信号端相连；所述第七晶体管的第一极与所述高电平输入端相连，所述第七晶体管的第二极与所述控制晶体管的第一极相连，所述第八晶体管的第二极与所述第九晶体管的第一极相连，所述第九晶体管的第二极与所述低电平输入端相连；并且所述第七晶体管的第二极为所述第三反相器的输出端；
    所述第四反相器包括第十晶体管和第十二晶体管，所述第十晶体管为P型晶体管，所述第十二晶体管为N型晶体管；
    所述第十晶体管的栅极和所述第十二晶体管的栅极均与所述第三反相器的输出端相连，所述第十晶体管的第一极与所述高电平输入端相连，所述第十晶体管的第二极与所述第十二晶体管的第一极相连，所述第十二晶体管的第二极与所述低电平输入端相连，所述信号输出端与所述第十晶体管的第二极相连。
  10. 根据权利要求8或9所述的移位寄存单元，其中，所述第六晶体管的宽长比大于所述第三晶体管、所述第八晶体管和所述第九晶体管中的任意一者的宽长比。
  11. 根据权利要求10所述的移位寄存单元，其中，所述第五晶体管和所述第六晶体管的宽长比均为40∶1，所述第三晶体管、所述第八晶体管、所述第九晶体管的宽长比均为10∶1。
  12. 一种移位寄存器，所述移位寄存器包括级联的多级移位寄 存单元，其中，所述移位寄存单元为权利要求1至11中任意一项所述的移位寄存单元。
  13. 一种栅极驱动电路，所述栅极驱动电路包括移位寄存器、高电平信号线、奇数时钟信号线、偶数时钟信号线、和低电平信号线，其中，所述移位寄存器为权利要求12所述的移位寄存器，所述高电平信号线与所述高电平输入端相连，所述低电平信号线与所述低电平输入端相连，所述奇数时钟信号线与奇数级的移位寄存单元的时钟信号端相连，所述偶数时钟信号线与偶数级的移位寄存单元的时钟信号端相连。
  14. 一种显示装置，所述显示装置包括如权利要求13所述的栅极驱动电路。
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