WO2017012166A1 - 面板及面板制备方法 - Google Patents

面板及面板制备方法 Download PDF

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Publication number
WO2017012166A1
WO2017012166A1 PCT/CN2015/087820 CN2015087820W WO2017012166A1 WO 2017012166 A1 WO2017012166 A1 WO 2017012166A1 CN 2015087820 W CN2015087820 W CN 2015087820W WO 2017012166 A1 WO2017012166 A1 WO 2017012166A1
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WIPO (PCT)
Prior art keywords
layer
hole
disposed
insulating layer
shielding
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Ceased
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PCT/CN2015/087820
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English (en)
French (fr)
Inventor
谢剑星
夏军
黄俊宏
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means

Definitions

  • the present invention relates to the field of display, and in particular to a panel and a method for preparing a panel.
  • touch display integration referred to as touch integration
  • cell technology is regarded as a high-end technology in the field and is widely sought after.
  • the so-called in cell technology refers to embedding the touch panel function into the liquid crystal pixels.
  • the common electrode is usually cut to form a plurality of sensing electrodes distributed in a matrix, and a slit is formed between adjacent sensing units.
  • a shielding device is usually formed above the cutting slit, and the shielding device is electrically connected to the driving chip through a lead wire, and the shielding device is controlled by the driving chip.
  • the driver chip needs to add a drive signal to control the shielding device.
  • the newly added shielding device is equivalent to a capacitor with a large capacitance value connected in parallel to each sensing unit, which increases the load of the driving chip.
  • the newly added shielding device affects the capacitance of the sensing unit around the shielding device, and the algorithm needs to eliminate the influence of the shielding device on the peripheral sensing unit, thereby increasing the design difficulty of the driving chip.
  • the invention provides a panel, the panel comprising:
  • a substrate comprising opposite first and second surfaces
  • the thin film transistor array disposed on the first surface, the thin film transistor array including a plurality of thin film transistors distributed in a matrix;
  • a common electrode layer is disposed on the first insulating layer, and the common electrode layer includes a plurality of sensing units distributed in a matrix, and a gap is disposed between adjacent sensing units;
  • a second insulating layer disposed on the common electrode layer and filling the gap
  • a shielding layer disposed on the second insulating layer and disposed corresponding to the gap; the shielding layer being electrically connected to the common electrode layer.
  • the panel further comprises:
  • a third insulating layer disposed on the shielding layer and the second insulating layer; a first through hole is disposed on the second insulating layer, and the first through hole is disposed corresponding to the common electrode layer, a second through hole and a third through hole are disposed on the third insulating layer, wherein the second through hole is in communication with the first through hole, and the third through hole is disposed corresponding to the shielding layer;
  • a connecting member disposed on the third insulating layer, and one end is electrically connected to the common electrode layer through the first through hole and the second through hole, and the other end passes through the third through hole and the The shield is electrically connected.
  • the panel further comprises:
  • a pixel electrode is disposed on the third insulating layer, and the pixel electrode is electrically connected to a drain of the thin film transistor.
  • the connecting member and the pixel electrode are formed in the same reticle; or/and the first through hole, the second through hole and the third through hole are formed in the same reticle.
  • the shielding layer includes a plurality of shielding units disposed along a first direction, the shielding unit is disposed corresponding to a gap between two adjacent sensing units, and the shielding unit and the corresponding two sensing units thereof One of the electrical connections.
  • the invention also provides a method for preparing a panel, the method for preparing the panel comprises:
  • the substrate comprising opposite first and second surfaces
  • the thin film transistor array Forming a thin film transistor array on the first surface, the thin film transistor array including a plurality of thin film transistors distributed in a matrix;
  • the second insulating layer is disposed on the sensing unit and filling the gap;
  • the shielding layer is electrically connected to the common electrode layer.
  • the preparation method of the panel further includes:
  • the step of "electrically connecting the shielding layer to the common electrode layer” includes:
  • first through hole Forming a first through hole on the second insulating layer, the first through hole is disposed corresponding to the common electrode layer, and forming a second through hole and a third through hole on the third insulating layer, a second through hole communicating with the first through hole, wherein the third through hole is disposed corresponding to the shielding layer;
  • the panel preparation method further comprises:
  • a pixel electrode is formed on the third insulating layer, and the pixel electrode is electrically connected to a drain of the thin film transistor.
  • the connecting member and the pixel electrode are formed in the same reticle; or/and the first through hole, the second through hole and the third through hole are formed in the same reticle.
  • the step of “forming a shielding layer on the second insulating layer, and the shielding layer corresponding to the gap setting” includes:
  • the shielding layer includes a plurality of shielding units disposed along a first direction, and the shielding unit corresponds to two adjacent ones a gap setting between the sensing units;
  • the step of "electrically connecting the shielding layer to the common electrode layer” includes:
  • the shielding unit is electrically connected to one of its corresponding two sensing units, and each sensing unit is electrically connected to one shielding unit.
  • the panel and the panel manufacturing method of the present invention have the thin film transistor array disposed on the first surface of the substrate, and the first insulating layer is disposed between the common electrode layer and the thin film transistor array through the common electrode
  • the layer is disposed as a plurality of sensing units distributed in a matrix, and a gap is disposed between the adjacent sensing units, thereby sensing the common electrode layer of the liquid crystal display panel and the touch detection function in the touch technology. Units are merged.
  • a second insulating layer is disposed on the common electrode layer, and the gap is filled, the shielding layer is disposed on the second insulating layer, and the shielding layer is electrically connected to the common electrode layer corresponding to the gap.
  • the driving chip distributes the driving signal
  • the common signal is loaded on the common electrode layer, and the touch signal and the detection signal are transmitted back to the driving chip for operation processing in the touch phase.
  • the common electrode layer is electrically connected to the shielding layer
  • the common signal is also loaded on the shielding layer, and it is not necessary to separately load a separate driving signal for the shielding layer.
  • the present invention integrates the common electrode layer and the shielding layer into one body. Therefore, the shielding layer does not become a load of the common electrode layer, which reduces the difficulty of the operation processing of the driving chip.
  • FIG. 1 is a schematic top plan view of a panel according to a preferred embodiment of the present invention.
  • Figure 2 is a schematic cross-sectional view taken along line II-II of Figure 1.
  • FIG. 3 is a flow chart of a method of fabricating a panel according to a preferred embodiment of the present invention.
  • FIG. 1 is a schematic top plan view of a panel according to a preferred embodiment of the present invention
  • FIG. 2 is a cross-sectional structural view taken along line II-II of FIG.
  • the panel 10 includes a substrate 110 , a thin film transistor array 120 , a first insulating layer 130 , a common electrode layer 140 , a second insulating layer 150 , and a shielding layer 160 .
  • the substrate 110 includes a first surface 111 and a second surface 112 that are disposed opposite each other.
  • the thin film transistor array 120 is disposed on the first surface 111, and the thin film transistor array 120 includes a plurality of thin film transistors distributed in a matrix.
  • the first insulating layer 130 is disposed on the thin film transistor array 120, the common electrode layer 140 is disposed on the first insulating layer 130, and the common electrode layer 140 includes a plurality of senses distributed in a matrix.
  • a sensor 141 is disposed between the adjacent sensing units 141 with a gap 142.
  • the second insulating layer 150 is disposed on the common electrode layer 140 and fills the gap 142.
  • the shielding layer 160 is disposed on the second insulating layer 150 and disposed corresponding to the gap 142. The shielding layer 160 is electrically connected to the common electrode layer.
  • the substrate 110 may be a transparent substrate such as a glass substrate or a plastic substrate.
  • the material of the substrate 110 is not limited.
  • the thin film transistor 120 is disposed on the first surface 111 of the substrate 110. In other embodiments, the thin film transistor 120 may also be disposed in the embodiment. On the second surface 112.
  • the thin film transistor array 120 includes a plurality of thin film transistors distributed in a matrix for controlling pixel points in the panel 10.
  • the thin film transistor includes a gate, a source, and a drain, the gate is configured to receive a gate voltage, and control the source under the control of the gate voltage And turning on or off the drain.
  • the thin film transistor is turned on when the source and the drain are turned on under the control of the gate voltage; and the source and the drain are turned off under the control of the gate voltage At the time, the thin film transistor is turned off.
  • the material of the first insulating layer 130 may be, but not limited to, one of silicon nitride (SiNx), silicon dioxide (SiO 2 ), silicon oxynitride, and combinations thereof.
  • the common electrode layer 140 is transparent, and the material of the common electrode layer 140 may be, but not limited to, a material such as indium oxide.
  • Each of the sensing units 141 is electrically connected to the driving chip b through a touch panel trace (a).
  • the material of the second insulating layer 150 may be, but not limited to, one of silicon nitride, silicon dioxide, silicon oxynitride, and a combination thereof, and the material of the second insulating layer 150 may be insulated from the first Floor
  • the material of the second insulating layer 150 may be different from the material of the first insulating layer 130, which is not limited in the present invention.
  • the shielding layer 160 includes a plurality of shielding units 161 disposed along a first direction, the shielding unit 161 is disposed corresponding to a gap 142 between two adjacent sensing units 141, and the shielding The unit 161 is electrically connected to one of its corresponding two sensing units 141, and each of the sensing units 141 is electrically connected to one of the shielding units 161.
  • the width of the shielding unit 161 is greater than or equal to the width of the gap 142 between the adjacent two sensing units 141. .
  • the width of the shielding unit 161 is named da, the unit of da is micrometer, and the shielding unit 161 corresponds to the width of the gap 142 between the adjacent two sensing units 141.
  • the unit of db is micron. Then, the shielding experiment proves that the width of the shielding unit 161 ranges from db-2 ⁇ da ⁇ db+2. At this time, the shielding unit 161 still has a good performance. Shielding effect.
  • the panel 10 further includes a third insulating layer 170 and a connector 180.
  • the third insulating layer 170 is disposed on the shielding layer 160 and the second insulating layer 150.
  • a first through hole 151 is disposed on the second insulating layer 150, and the first through hole 151 is disposed corresponding to the common electrode layer 140.
  • a second through hole 171 and a third through hole 172 are disposed in the third insulating layer 170.
  • the second through hole 171 is in communication with the first through hole 151, and the third through hole 172 corresponds to the shielding layer. 160 settings.
  • the connecting member 180 is disposed on the third insulating layer 170, and one end of the connecting member 180 is electrically connected to the common electrode layer 140 through the first through hole 151 and the second through hole 171. The other end of the connecting member 180 is electrically connected to the shielding layer 160 through the third through hole 172.
  • the connector 180 electrically connects the shield layer 160 to the common electrode layer 140.
  • the shielding layer 160 includes a plurality of shielding units 161 disposed along the first direction, and one end of the connecting member 180 passes through the first through holes 151 and the second through holes 171 and the common electrode layer 140
  • the sensing unit 141 is electrically connected, and the other end of the connecting member 180 is electrically connected to the shielding layer 160 through the third through hole 172.
  • the panel 10 further includes a pixel electrode 190 disposed on the third insulating layer 170, and the pixel electrode 190 is electrically connected to a drain of the thin film transistor of the thin film transistor array 120.
  • the pixel electrode 190 is transparent, and the material of the pixel electrode 190 may be, but not limited to, a material such as indium oxide.
  • the connecting member 180 and the pixel electrode 190 are formed in the same mask to A process of preparing the connector 180 and the pixel electrode 190.
  • the first through hole 151, the second through hole 171 and the third through hole 172 are formed in the same reticle to save the first through hole 151 and the second through hole 171. And a preparation process of the third through hole 172.
  • the panel 10 of the present invention is disposed on the first surface 111 of the substrate 110, and the first insulating layer 130 is disposed between the common electrode layer 140 and the thin film transistor array 120.
  • the common electrode layer 140 is disposed as a plurality of sensing units 141 distributed in a matrix, and a gap 142 is disposed between the adjacent sensing units 141, thereby having the common electrode layer of the liquid crystal display panel and the touch technology.
  • the sensing unit of the touch detection function is integrated.
  • the second insulating layer 150 is disposed on the common electrode layer 140, and the gap 142 is filled, and the shielding layer 160 is disposed on the second insulating layer 150, and is disposed corresponding to the gap 142, and the shielding layer 160 is disposed.
  • the common electrode layer 140 is electrically connected. Therefore, the driving chip is configured to distribute the driving signal, and a common signal is loaded on the common electrode layer 140 during the display phase, and the touch signal and the detection signal are transmitted back to the driving chip for operation processing in the touch phase. Since the common electrode layer 140 is electrically connected to the shielding layer 160, the common signal is also loaded on the shielding layer 160, and it is not necessary to separately load the shielding layer 160 with a separate driving signal. At the same time, the common electrode layer 140 and the shielding layer 160 are integrally connected to each other. Therefore, the shielding layer 160 does not become the load of the common electrode layer 140, which reduces the difficulty of the operation processing of the driving chip.
  • FIG. 3 is a flowchart of a method for fabricating a panel according to a preferred embodiment of the present invention.
  • the panel preparation method includes, but is not limited to, the following steps.
  • a substrate 110 is provided, and the substrate 110 includes a first surface 111 and a second surface 112 disposed opposite to each other.
  • the substrate 110 may be a transparent substrate such as a glass substrate or a plastic substrate.
  • the material of the substrate 110 is not limited.
  • Step S102 forming a thin film transistor array 120 on the first surface 111, the thin film transistor array 120 comprising a plurality of thin film transistors distributed in a matrix.
  • the thin film transistor 120 is disposed on the first surface 111 of the substrate 110. In other embodiments, the thin film transistor 120 may also be disposed in the embodiment.
  • the thin film transistor array 120 includes a plurality of thin film transistors distributed in a matrix.
  • the thin film transistor is used to control pixel points in the panel 10.
  • the thin film transistor includes a gate, a source and a drain, the gate is configured to receive a gate voltage, and control conduction of the source and the drain under control of the gate voltage or cutoff.
  • the thin film transistor is turned on when the source and the drain are turned on under the control of the gate voltage; and the source and the drain are turned off under the control of the gate voltage At the time, the thin film transistor is turned off.
  • Step S103 forming a first insulating layer 130 on the thin film transistor array 120.
  • the material of the first insulating layer 130 may be, but not limited to, one of silicon nitride (SiNx), silicon dioxide (SiO 2 ), silicon oxynitride, and combinations thereof.
  • Step S104 forming a common electrode layer 140 on the first insulating layer 130, and patterning the common electrode layer 140 to obtain a plurality of sensing units 141 distributed in a matrix, and adjacent sensing units 141 A gap 142 is provided therebetween.
  • the common electrode layer 140 is transparent, and the material of the common electrode layer 140 may be, but not limited to, a material such as indium oxide.
  • a second insulating layer 150 is formed on the common electrode layer 140, and the second insulating layer 150 is disposed on the sensing unit 141 and fills the gap 142.
  • the material of the second insulating layer 150 may be, but not limited to, one of silicon nitride, silicon dioxide, silicon oxynitride, and a combination thereof, and the material of the second insulating layer 150 may be insulated from the first
  • the material of the second insulating layer 150 may be different from the material of the first insulating layer 130, which is not limited in the present invention.
  • Step S106 forming a shielding layer 160 on the second insulating layer 150, and the shielding layer 160 is disposed corresponding to the gap 142.
  • the step S106 includes: forming a metal layer on the second insulating layer 150, patterning the metal layer to obtain the shielding layer 160, and the shielding layer 160 includes a plurality of layers disposed along the first direction.
  • the shielding unit 161 is disposed corresponding to the gap 142 between the adjacent two sensing units 141.
  • the trace a can be formed simultaneously.
  • the shielding layer 160 is electrically connected to the common electrode layer 140.
  • the shielding layer 160 includes a plurality of shieldings disposed along the first direction.
  • the unit 161 when the shielding unit 161 is disposed corresponding to the gap 142 between the two adjacent sensing units 141, correspondingly, the step S107 includes: the shielding unit 161 and the two sensing units corresponding thereto One of the 141 is electrically connected, and each of the sensing units 141 is electrically connected to a shielding unit 161.
  • the panel preparation method further includes:
  • step I a third insulating layer 170 is formed on the shielding layer 160.
  • step S107 includes:
  • Step II a first through hole 151 is formed on the second insulating layer 150.
  • the first through hole 151 is disposed corresponding to the common electrode layer 140, and a second through hole 171 is formed on the third insulating layer 170.
  • a third through hole 172, the second through hole 171 is in communication with the first through hole 151, and the third through hole 172 is disposed corresponding to the shielding layer 160.
  • Step III providing a transparent conductive layer on the third insulating layer 170.
  • step IV the transparent conductive layer is patterned to form a connecting member 180.
  • One end of the connecting member 180 is electrically connected to the common electrode layer 140 through the first through hole 151 and the second through hole 171.
  • the other end is electrically connected to the shielding layer 160 through the third through hole 172.
  • the panel preparation method further includes: forming a pixel electrode 190 on the third insulating layer 170, and the pixel electrode 190 is electrically connected to a drain of the thin film transistor.
  • the pixel electrode 190 is transparent, and the material of the pixel electrode 190 may be, but not limited to, a material such as indium oxide.
  • the first through hole 151, the second through hole 171 and the third through hole 172 are formed in the same reticle. Specifically, when the first through hole 151, the second through hole 171, and the third through hole 172 are formed, a photoresist layer is disposed on the third insulating layer 170 through the translucent cover. (half tone mask), the first through hole 151, the second through hole 171, and the third through hole 172 are simultaneously formed in this step.
  • the connecting member 180 and the pixel electrode 190 are formed in the same reticle.
  • a transparent conductive layer is disposed on a surface of the third insulating layer 170;
  • a photoresist layer is disposed on the transparent conductive layer, and the transparent conductive layer is patterned through a photomask to form a connection.
  • a member 180 and a pixel electrode 19, and one end of the connecting member 180 is electrically connected to the common electrode layer 140 through the first through hole 151 and the second through hole 171, and the other end of the connecting member 180 passes
  • the third through hole 172 is electrically connected to the shielding layer 160.
  • the panel manufacturing method of the present invention places the thin film transistor array 120 on the first surface 111 of the substrate 110, between the common electrode layer 140 and the thin film transistor array 120.
  • the first insulating layer 130 is disposed, and the common electrode layer 140 is disposed as a plurality of sensing units 141 distributed in a matrix, and a gap 142 is disposed between the adjacent sensing units 141, thereby the common electrode of the liquid crystal display panel.
  • the layer is integrated with the sensing unit with touch detection function in the touch technology.
  • the second insulating layer 150 is disposed on the common electrode layer 140, and the gap 142 is filled, and the shielding layer 160 is disposed on the second insulating layer 150, and is disposed corresponding to the gap 142, and the shielding layer 160 is disposed.
  • the common electrode layer 140 is electrically connected. Therefore, the driving chip is configured to distribute the driving signal, and a common signal is loaded on the common electrode layer 140 during the display phase, and the touch signal and the detection signal are transmitted back to the driving chip for operation processing in the touch phase. Since the common electrode layer 140 is electrically connected to the shielding layer 160, the common signal is also loaded on the shielding layer 160, and it is not necessary to separately load the shielding layer 160 with a separate driving signal. At the same time, the common electrode layer 140 and the shielding layer 160 are integrally connected to each other. Therefore, the shielding layer 160 does not become the load of the common electrode layer 140, which reduces the difficulty of the operation processing of the driving chip.

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Abstract

一种面板（10）及面板（10）制备方法。所述面板（10）包括：基板（110），包括相对设置的第一表面（111）及第二表面（112）；薄膜晶体管阵列（120），设置在所述第一表面（111）上，所述薄膜晶体管阵列（120）包括呈矩阵状分布的多个薄膜晶体管；第一绝缘层（130），设置在所述薄膜晶体管阵列（120）上；公共电极层（140），设置于所述第一绝缘层（130）上，且所述公共电极层（140）包括呈矩阵状分布的多个感测单元（141），相邻的感测单元（141）之间设置有间隙（142）；第二绝缘层（150），设置于所述公共电极层（140）上且填充所述间隙（142）；屏蔽层（160），设置于所述第二绝缘层（150）上，且对应所述间隙（142）设置；所述屏蔽层（160）与所述公共电极层（140）电连接。

Description

面板及面板制备方法
本发明要求2015年7月20日递交的发明名称为“面板及面板制备方法”的申请号201510426338.8的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示领域，尤其涉及一种面板及面板制备方法。
背景技术
随着智能手机市场竞争的激烈化程度的日渐加深，触控显示一体化(简称，触显一体化)产品迎来了新一轮的竞逐。In cell技术被视为该领域的高端技术，广受追捧。所谓的in cell技术，是指将触控面板功能嵌入到液晶像素中。在目前的自容式触控技术方案中，通常将公共电极进行切割，从而形成矩阵状分布的多个感测单元(sensor)，且相邻的感测单元之间存在切割狭缝。当数据线(data line)在进行信号传输时产生的电场穿过感测单元之间的切割狭缝时，会对切割狭缝处对应的液晶产生影响，干扰此处的液晶的转向，造成该位置漏光，从而造成了显示的异常。现有技术中，为了解决此技术问题，通常在切割狭缝的上方制作屏蔽装置，屏蔽装置通过引线与驱动芯片电连接，并通过驱动芯片控制所述屏蔽装置。然而，屏蔽装置的引进产生了一系列问题。首先，从驱动上来讲，驱动芯片需要增加一个驱动信号来控制屏蔽装置。其次，新增的屏蔽装置相当于给各个感测单元并联上了一个电容值较大的电容，增大了驱动芯片的负载(loading)。再次，新增的屏蔽装置会影响到所述屏蔽装置周边的感测单元的电容量，需要通过算法对消除屏蔽装置对周边感测单元的影响，进而增加了驱动芯片的设计难度。
发明内容
本发明提供一种面板，所述面板包括：
基板，包括相对设置的第一表面及第二表面；
薄膜晶体管阵列，设置在所述第一表面上，所述薄膜晶体管阵列包括呈矩阵状分布的多个薄膜晶体管；
第一绝缘层，设置在所述薄膜晶体管阵列上；
公共电极层，设置于所述第一绝缘层上，且所述公共电极层包括呈矩阵状分布的多个感测单元，相邻的感测单元之间设置有间隙；
第二绝缘层，设置于所述公共电极层上且填充所述间隙；
屏蔽层，设置于所述第二绝缘层上，且对应所述间隙设置；所述屏蔽层与所述公共电极层电连接。
其中，所述面板还包括：
第三绝缘层，设置在所述屏蔽层及所述第二绝缘层上；所述第二绝缘层上设置第一贯孔，所述第一贯孔对应所述公共电极层设置，所述第三绝缘层上设置第二贯孔及第三贯孔，所述第二贯孔与所述第一贯孔连通，所述第三贯孔对应所述屏蔽层设置；
连接件，设置在所述第三绝缘层上，且一端通过所述第一贯孔及所述第二贯孔与所述公共电极层电连接，另一端通过所述第三贯孔与所述屏蔽层电连接。
其中，所述面板还包括：
像素电极，设置在所述第三绝缘层上，且所述像素电极与所述薄膜晶体管的漏极电连接。
其中，所述连接件与所述像素电极在同一道光罩中形成；或者/以及所述第一贯孔、所述第二贯孔及所述第三贯孔在同一道光罩中形成。
其中，所述屏蔽层包括沿第一方向设置的多个屏蔽单元，所述屏蔽单元对应相邻的两个感测单元之间的间隙设置，且所述屏蔽单元与其对应的两个感测单元之一电连接。
本发明还提供了一种面板的制备方法，所述面板的制备方法包括：
提供一基板，所述基板包括相对设置的第一表面及第二表面；
在所述第一表面上形成薄膜晶体管阵列，所述薄膜晶体管阵列包括呈矩阵状分布的多个薄膜晶体管；
在形成薄膜晶体管阵列上形成第一绝缘层；
在所述第一绝缘层上形成公共电极层，将所述公共电极层进行图案化以得到形成呈矩阵状分布的多个感测单元，相邻的感测单元之间设置有间隙；
在所述公共电极层上形成第二绝缘层，所述第二绝缘层设置在所述感测单元上且填充所述间隙；
在所述第二绝缘层上形成屏蔽层，且所述屏蔽层对应所述间隙设置；
将所述屏蔽层与所述公共电极层电连接。
其中，在所述步骤“在所述第二绝缘层上形成屏蔽层，且所述屏蔽层对应所述间隙设置”与所述步骤“将所述屏蔽层与所述公共电极层电连接”之间，所述面板的制备方法还包括：
在所述屏蔽层上形成第三绝缘层；
所述步骤“将所述屏蔽层与所述公共电极层电连接”包括：
在所述第二绝缘层上形成第一贯孔，所述第一贯孔对应所述公共电极层设置，在所述第三绝缘层上形成第二贯孔及第三贯孔，所述第二贯孔与所述第一贯孔连通，所述第三贯孔对应所述屏蔽层设置；
在所述第三绝缘层上设置透明导电层；
将所述透明导电层进行图案化，以形成连接件，所连接件的一端通过所述第一贯孔及所述第二贯孔与所述公共电极层电连接，另一端通过所述第三贯孔与所述屏蔽层电连接。
其中，所述面板制备方法还包括：
在所述第三绝缘层上形成像素电极，且所述像素电极与所述薄膜晶体管的漏极电连接。
其中，所述连接件与所述像素电极在同一道光罩中形成；或者/以及所述第一贯孔、所述第二贯孔及所述第三贯孔在同一道光罩中形成。
其中，所述步骤“在所述第二绝缘层上形成屏蔽层，且所述屏蔽层对应所述间隙设置”包括：
在所述第二绝缘层上形成一金属层，图案化所述金属层得到所述屏蔽层，所述屏蔽层包括沿第一方向设置的多个屏蔽单元，所述屏蔽单元对应相邻的两个感测单元之间的间隙设置；
所述步骤“将所述屏蔽层与所述公共电极层电连接”包括：
将所述屏蔽单元与其对应的两个感测单元之一电连接，且每个感测单元均与一个屏蔽单元电连接。
相较于现有技术，本发明的面板及面板制备方法将所述薄膜晶体管阵列设置所述基板的第一表面上，公共电极层与薄膜晶体管阵列之间设置第一绝缘层，通过将公共电极层设置为呈矩阵状分布的多个感测单元，且相邻的感测单元之间设置有间隙，从而将液晶显示面板的公共电极层与触控技术中的具有触控检测功能的感测单元相融合。将第二绝缘层设置于所述公共电极层，且填充所述间隙，将屏蔽层设置于第二绝缘层上，且对应所述间隙设置，所述屏蔽层与所述公共电极层电连接。从而使得驱动芯片分配驱动信号时变得简单，在显示阶段将公共电极层上加载一公共信号，在触控阶段将触控信号及检测信号传输回所述驱动芯片进行运算处理。由于所述公共电极层与所述屏蔽层电连接，因此，所述屏蔽层上也被加载所述公共信号，无需单独对所述屏蔽层加载单独的驱动信号。同时，本发明将所述公共电极层与所述屏蔽层连接成为一体，因此，所述屏蔽层不会成为所述公共电极层的负载，降低了驱动芯片运算处理的难度。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的面板的俯视结构示意图。
图2为图1中沿II-II线的剖面结构示意图。
图3为本发明一较佳实施方式的面板制备方法的流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造 性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请一并参阅图1及图2及图3，图1为本发明一较佳实施方式的面板的俯视结构示意图；图2为图1中沿II-II线的剖面结构示意图。所述面板10包括基板110、薄膜晶体管阵列120、第一绝缘层130、公共电极层140、第二绝缘层150及屏蔽层160。所述基板110包括相对设置的第一表面111和第二表面112。所述薄膜晶体管阵列120设置在所述第一表面111上，所述薄膜晶体管阵列120包括呈矩阵状分布的多个薄膜晶体管。所述第一绝缘层130设置在所述薄膜晶体管阵列120上，所述公共电极层140设置于所述第一绝缘层130上，且所述公共电极层140包括呈矩阵状分布的多个感测单元(sensor)141，相邻的感测单元141之间设置有间隙142。所述第二绝缘层150设置在所述公共电极层140上且填充所述间隙142。所述屏蔽层160设置于所述第二绝缘层150上，且对应所述间隙142设置，所述屏蔽层160与所述公共电极层电连接。
所述基板110可以为玻璃基板、塑料基板等透明的基板，在本实施中，不对所述基板110的材料做限定。可以理解地，在本实施方式中，以所述薄膜晶体管120设置在所述基板110的所述第一表面111上为例进行说明，在其他实施方式中，所述薄膜晶体管120也可以设置在所述第二表面112上。
所述薄膜晶体管阵列120包括呈矩阵状分布的多个薄膜晶体管，所述薄膜晶体管用于控制所述面板10中像素点。所述薄膜晶体管包括栅极(gate)、源极(source)及漏极(drain)，所述栅极用于接收一栅极电压，并在所述栅极电压的控制下控制所述源极及所述漏极的导通或者截止。当所述源极及所述漏极在所述栅极电压的控制下导通时，所述薄膜晶体管导通；当所述源极及所述漏极在所述栅极电压的控制下截止时，所述薄膜晶体管断开。
所述第一绝缘层130的材料可以为但不仅限于为氮化硅(SiNx)、二氧化硅(SiO2)、氮氧化硅及其组合的其中之一。
所述公共电极层140为透明的，所述公共电极层140的材料可以为但不仅限于为氧化铟等材料。每个感测单元141通过一个迹线a(touch panel trace)与驱动芯片b电连接。
所述第二绝缘层150的材料可以为但不仅限于为氮化硅、二氧化硅、氮氧化硅及其组合的其中之一，所述第二绝缘层150的材料可以与所述第一绝缘层 130的材料相同，所述第二绝缘层150的材料也可以与所述第一绝缘层130的材料不同，在本发明中不做限定。
在本实施方式中，所述屏蔽层160包括沿第一方向设置的多个屏蔽单元161，所述屏蔽单元161对应相邻的两个感测单元141之间的间隙142设置，且所述屏蔽单元161与其对应的两个感测单元141之一电连接，且每个感测单元141与一个屏蔽单元161电连接。在一实施方式中，所述屏蔽单元161对应相邻的两个感测单元141设置时，所述屏蔽单元161的宽度大于或等于相邻的两个感测单元141之间的间隙142的宽度。在另一实施方式中，为了方面描述，所述屏蔽单元161的宽度命名为da，da的单位为微米，所述屏蔽单元161对应相邻的两个感测单元141之间的间隙142的宽度为db，db的单位为微米，则，经过屏蔽实验证明，所述屏蔽单元161的宽度的范围为，db-2≤da≤db+2，此时，所述屏蔽单元161仍然具有较好的屏蔽效果。
所述面板10还包括第三绝缘层170及连接件180。所述第三绝缘层170设置在所述屏蔽层160及所述第二绝缘层150上。所述第二绝缘层150上设置第一贯孔151，所述第一贯孔151对应所述公共电极层140设置。所述第三绝缘层170上设置第二贯孔171及第三贯孔172，所述第二贯孔171与所述第一贯孔151连通，所述第三贯孔172对应所述屏蔽层160设置。所述连接件180设置在所述第三绝缘层170上，且所述连接件180的一端通过所述第一贯孔151及所述第二贯孔171与所述公共电极层140电连接，所述连接件180的另一端通过所述第三贯孔172与所述屏蔽层160电连接。由此可见，所述连接件180将所述屏蔽层160与所述公共电极层140电连接。由于所述屏蔽层160包括沿第一方向设置的多个屏蔽单元161，所述连接件180的一端通过所述第一贯孔151及所述第二贯孔171与所述公共电极层140的感测单元141电连接，所述连接件180的另一端通过所述第三贯孔172与所述屏蔽层160电连接。
所述面板10还包括像素电极190，所述像素电极190设置在所述第三绝缘层170上，且所述像素电极190与所述薄膜晶体管阵列120的薄膜晶体管的漏极电连接。所述像素电极190为透明的，所述像素电极190的材料可以为但不仅限于为氧化铟等材料。
优选地，所述连接件180与所述像素电极190在同一道光罩中形成，以节 约所述连接件180与所述像素电极190的制备工序。
优选地，所述第一贯孔151、所述第二贯孔171及所述第三贯孔172在同一道光罩中形成，以节约所述第一贯孔151、所述第二贯孔171及所述第三贯孔172的制备工序。
相较于现有技术，本发明的面板10将所述薄膜晶体管阵列120设置所述基板110的第一表面111上，公共电极层140与薄膜晶体管阵列120之间设置第一绝缘层130，通过将公共电极层140设置为呈矩阵状分布的多个感测单元141，且相邻的感测单元141之间设置有间隙142，从而将液晶显示面板的公共电极层与触控技术中的具有触控检测功能的感测单元相融合。将第二绝缘层150设置于所述公共电极层140，且填充所述间隙142，将屏蔽层160设置于第二绝缘层150上，且对应所述间隙142设置，所述屏蔽层160与所述公共电极层140电连接。从而使得驱动芯片分配驱动信号时变得简单，在显示阶段将公共电极层140上加载一公共信号，在触控阶段将触控信号及检测信号传输回所述驱动芯片进行运算处理。由于所述公共电极层140与所述屏蔽层160电连接，因此，所述屏蔽层160上也被加载所述公共信号，无需单独对所述屏蔽层160加载单独的驱动信号。同时，本发明将所述公共电极层140与所述屏蔽层160连接成为一体，因此，所述屏蔽层160不会成为所述公共电极层140的负载，降低了驱动芯片运算处理的难度。
下面对本发明的面板制备方法进行介绍，请参阅图3，图3为本发明一较佳实施方式的面板制备方法的流程图。所述面板制备方法包括但不仅限于以下步骤。
步骤S101，提供一基板110，所述基板110包括相对设置的第一表面111和第二表面112。所述基板110可以为玻璃基板、塑料基板等透明的基板，在本实施中，不对所述基板110的材料做限定。
步骤S102，在所述第一表面111上形成薄膜晶体管阵列120，所述薄膜晶体管阵列120包括呈矩阵状分布的多个薄膜晶体管。可以理解地，在本实施方式中，以所述薄膜晶体管120设置在所述基板110的所述第一表面111上为例进行说明，在其他实施方式中，所述薄膜晶体管120也可以设置在所述第二表面112上。所述薄膜晶体管阵列120包括呈矩阵状分布的多个薄膜晶体管，所 述薄膜晶体管用于控制所述面板10中像素点。所述薄膜晶体管包括栅极、源极及漏极，所述栅极用于接收一栅极电压，并在所述栅极电压的控制下控制所述源极及所述漏极的导通或者截止。当所述源极及所述漏极在所述栅极电压的控制下导通时，所述薄膜晶体管导通；当所述源极及所述漏极在所述栅极电压的控制下截止时，所述薄膜晶体管断开。
步骤S103，在所述薄膜晶体管阵列120上形成第一绝缘层130。所述第一绝缘层130的材料可以为但不仅限于为氮化硅(SiNx)、二氧化硅(SiO2)、氮氧化硅及其组合的其中之一。
步骤S104，在所述第一绝缘层130上形成公共电极层140，将所述公共电极层140进行图案化以得到呈矩阵状分布的多个感测单元141，相邻的感测单元141之间设置间隙142。所述公共电极层140为透明的，所述公共电极层140的材料可以为但不仅限于为氧化铟等材料。
步骤S105，在所述公共电极层140形成第二绝缘层150，所述第二绝缘层150设置在所述感测单元141上且填充所述间隙142。所述第二绝缘层150的材料可以为但不仅限于为氮化硅、二氧化硅、氮氧化硅及其组合的其中之一，所述第二绝缘层150的材料可以与所述第一绝缘层130的材料相同，所述第二绝缘层150的材料也可以与所述第一绝缘层130的材料不同，在本发明中不做限定。
步骤S106，在所述第二绝缘层150上形成屏蔽层160，且所述屏蔽层160对应所述间隙142设置。具体地，所述步骤S106包括：在所述第二绝缘层150上形成一金属层，图案化所述金属层得到所述屏蔽层160，所述屏蔽层160包括沿第一方向设置的多个屏蔽单元161，所述屏蔽单元161对应相邻的两个感测单元141之间的间隙142设置。优选地，在此步骤中，可以同时形成所述迹线a。
步骤S107，将所述屏蔽层160与所述公共电极层140电连接。当，所述步骤S106包括：在所述第二绝缘层150上形成一金属层，图案化所述金属层得到所述屏蔽层160，所述屏蔽层160包括沿第一方向设置的多个屏蔽单元161，所述屏蔽单元161对应相邻的两个感测单元141之间的间隙142设置时，相应地，所述步骤S107包括：将所述屏蔽单元161与其对应的两个感测单元 141之一电连接，且每个感测单元141均与一屏蔽单元161电连接。
优选地，在所述步骤S106及所述步骤S107之间，所述面板制备方法还包括：
步骤I，在所述屏蔽层160上形成第三绝缘层170。
则，所述步骤S107包括：
步骤II，在所述第二绝缘层150上形成第一贯孔151，所述第一贯孔151对应所述公共电极层140设置，在所述第三绝缘层170上形成第二贯孔171及第三贯孔172，所述第二贯孔171与所述第一贯孔151连通，所述第三贯孔172对应所述屏蔽层160设置。
步骤III，在所述第三绝缘层170上设置透明导电层。
步骤IV，将所述透明导电层进行图案化，以形成连接件180，所述连接件180的一端通过所述第一贯孔151及所述第二贯孔171与所述公共电极层140电连接，另一端通过所述第三贯孔172与所述屏蔽层160电连接。
优选地，所述面板制备方法还包括：在所述第三绝缘层170上形成像素电极190，且所述像素电极190与所述薄膜晶体管的漏极电连接。所述像素电极190为透明的，所述像素电极190的材料可以为但不仅限于为氧化铟等材料。
优选地，所述第一贯孔151、所述第二贯孔171及所述第三贯孔172在同一道光罩中形成。具体地，形成所述第一贯孔151、所述第二贯孔171及所述第三贯孔172时，在所述第三绝缘层170上设置一层光阻层，通过半透光罩(half tone mask)，在此步骤中同时形成所述第一贯孔151、所述第二贯孔171及所述第三贯孔172。
优选地，所述连接件180与所述像素电极190在同一道光罩中形成。具体地，在所述第三绝缘层170的表面设置透明导电层；在所述透明导电层上设置一层光阻层，通过一道光罩，将所述透明导电层进行图案化，以形成连接件180以及像素电极19，且所述连接件180的一端通过所述第一贯孔151及所述第二贯孔171与所述公共电极层140电连接，所述连接件180的另一端通过所述第三贯孔172与所述屏蔽层160电连接。
相较于现有技术，本发明的面板制备方法将所述薄膜晶体管阵列120设置所述基板110的第一表面111上，公共电极层140与薄膜晶体管阵列120之间 设置第一绝缘层130，通过将公共电极层140设置为呈矩阵状分布的多个感测单元141，且相邻的感测单元141之间设置有间隙142，从而将液晶显示面板的公共电极层与触控技术中的具有触控检测功能的感测单元相融合。将第二绝缘层150设置于所述公共电极层140，且填充所述间隙142，将屏蔽层160设置于第二绝缘层150上，且对应所述间隙142设置，所述屏蔽层160与所述公共电极层140电连接。从而使得驱动芯片分配驱动信号时变得简单，在显示阶段将公共电极层140上加载一公共信号，在触控阶段将触控信号及检测信号传输回所述驱动芯片进行运算处理。由于所述公共电极层140与所述屏蔽层160电连接，因此，所述屏蔽层160上也被加载所述公共信号，无需单独对所述屏蔽层160加载单独的驱动信号。同时，本发明将所述公共电极层140与所述屏蔽层160连接成为一体，因此，所述屏蔽层160不会成为所述公共电极层140的负载，降低了驱动芯片运算处理的难度。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (10)

  1. 一种面板，其中，所述面板包括：
    基板，包括相对设置的第一表面及第二表面；
    薄膜晶体管阵列，设置在所述第一表面上，所述薄膜晶体管阵列包括呈矩阵状分布的多个薄膜晶体管；
    第一绝缘层，设置在所述薄膜晶体管阵列上；
    公共电极层，设置于所述第一绝缘层上，且所述公共电极层包括呈矩阵状分布的多个感测单元，相邻的感测单元之间设置有间隙；
    第二绝缘层，设置于所述公共电极层上且填充所述间隙；
    屏蔽层，设置于所述第二绝缘层上，且对应所述间隙设置；所述屏蔽层与所述公共电极层电连接。
  2. 如权利要求1所述的面板，其中，所述面板还包括：
    第三绝缘层，设置在所述屏蔽层及所述第二绝缘层上；所述第二绝缘层上设置第一贯孔，所述第一贯孔对应所述公共电极层设置，所述第三绝缘层上设置第二贯孔及第三贯孔，所述第二贯孔与所述第一贯孔连通，所述第三贯孔对应所述屏蔽层设置；
    连接件，设置在所述第三绝缘层上，且一端通过所述第一贯孔及所述第二贯孔与所述公共电极层电连接，另一端通过所述第三贯孔与所述屏蔽层电连接。
  3. 如权利要求2所述的面板，其中，所述面板还包括：
    像素电极，设置在所述第三绝缘层上，且所述像素电极与所述薄膜晶体管的漏极电连接。
  4. 如权利要求3所述的面板，其中，所述连接件与所述像素电极在同一道光罩中形成；或者/以及所述第一贯孔、所述第二贯孔及所述第三贯孔在同一道光罩中形成。
  5. 如权利要求1所述的面板，其中，所述屏蔽层包括沿第一方向设置的多个屏蔽单元，所述屏蔽单元对应相邻的两个感测单元之间的间隙设置，且所述屏蔽单元与其对应的两个感测单元之一电连接。
  6. 一种面板的制备方法，其中，所述面板的制备方法包括：
    提供一基板，所述基板包括相对设置的第一表面及第二表面；
    在所述第一表面上形成薄膜晶体管阵列，所述薄膜晶体管阵列包括呈矩阵状分布的多个薄膜晶体管；
    在形成薄膜晶体管阵列上形成第一绝缘层；
    在所述第一绝缘层上形成公共电极层，将所述公共电极层进行图案化以得到形成呈矩阵状分布的多个感测单元，相邻的感测单元之间设置有间隙；
    在所述公共电极层上形成第二绝缘层，所述第二绝缘层设置在所述感测单元上且填充所述间隙；
    在所述第二绝缘层上形成屏蔽层，且所述屏蔽层对应所述间隙设置；
    将所述屏蔽层与所述公共电极层电连接。
  7. 如权利要求6所述的面板的制备方法，其中，在所述步骤“在所述第二绝缘层上形成屏蔽层，且所述屏蔽层对应所述间隙设置”与所述步骤“将所述屏蔽层与所述公共电极层电连接”之间，所述面板的制备方法还包括：
    在所述屏蔽层上形成第三绝缘层；
    所述步骤“将所述屏蔽层与所述公共电极层电连接”包括：
    在所述第二绝缘层上形成第一贯孔，所述第一贯孔对应所述公共电极层设置，在所述第三绝缘层上形成第二贯孔及第三贯孔，所述第二贯孔与所述第一贯孔连通，所述第三贯孔对应所述屏蔽层设置；
    在所述第三绝缘层上设置透明导电层；
    将所述透明导电层进行图案化，以形成连接件，所连接件的一端通过所述第一贯孔及所述第二贯孔与所述公共电极层电连接，另一端通过所述第三贯孔与所述屏蔽层电连接。
  8. 如权利要求7所述的面板制备方法，其中，所述面板制备方法还包括：
    在所述第三绝缘层上形成像素电极，且所述像素电极与所述薄膜晶体管的漏极电连接。
  9. 如权利要求8所述的面板制备方法，其中，所述连接件与所述像素电极在同一道光罩中形成；或者/以及所述第一贯孔、所述第二贯孔及所述第三贯孔在同一道光罩中形成。
  10. 如权利要求7所述的面板的制备方法，其中，所述步骤“在所述第二绝缘层上形成屏蔽层，且所述屏蔽层对应所述间隙设置”包括：
    在所述第二绝缘层上形成一金属层，图案化所述金属层得到所述屏蔽层，所述屏蔽层包括沿第一方向设置的多个屏蔽单元，所述屏蔽单元对应相邻的两个感测单元之间的间隙设置；
    所述步骤“将所述屏蔽层与所述公共电极层电连接”包括：
    将所述屏蔽单元与其对应的两个感测单元之一电连接，且每个感测单元均与一个屏蔽单元电连接。
PCT/CN2015/087820 2015-07-20 2015-08-21 面板及面板制备方法 Ceased WO2017012166A1 (zh)

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