WO2017000906A1 - Transistor à haute mobilité électronique à double canal à enrichissement - Google Patents

Transistor à haute mobilité électronique à double canal à enrichissement Download PDF

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WO2017000906A1
WO2017000906A1 PCT/CN2016/088062 CN2016088062W WO2017000906A1 WO 2017000906 A1 WO2017000906 A1 WO 2017000906A1 CN 2016088062 W CN2016088062 W CN 2016088062W WO 2017000906 A1 WO2017000906 A1 WO 2017000906A1
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layer
upper channel
semiconductor device
channel layer
recess
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PCT/CN2016/088062
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English (en)
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Jing Chen
Jin Wei
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The Hong Kong University Of Science And Technology
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Priority to CN201680039328.1A priority Critical patent/CN107735863A/zh
Publication of WO2017000906A1 publication Critical patent/WO2017000906A1/fr

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

Definitions

  • This disclosure relates generally to enhancement-mode high-electron-mobility transistors (HEMTs) , and more particularly to enhancement-mode (E-mode) double-channel (DC) HEMTs based on group III-nitride (III-N) compound semiconductor materials.
  • HEMTs enhancement-mode high-electron-mobility transistors
  • E-mode enhancement-mode double-channel HEMTs based on group III-nitride (III-N) compound semiconductor materials.
  • III-N compound semiconductor materials such as GaN
  • a wide-bandgap heterostructure system such as a system incorporating an aluminum gallium nitride (AlGaN) /GaN heterostructure
  • AlGaN aluminum gallium nitride
  • 2DEG two-dimensional electron gas
  • HEMTs based on III-N semiconductor heterostructures such as AlGaN/GaN are considered as promising candidates for the next generation power devices.
  • the traditional III-N HEMTs are depletion-mode devices with negative threshold voltage. The depletion-mode operation hinders quick adoption of these devices in applications.
  • FIG. 1 presents a conventional III-nitride enhancement-mode (E-mode) HEMT device with a fully recessed barrier layer under the gate.
  • E-mode III-nitride enhancement-mode
  • FIG. 2 shows the resistance components of a conventional III-nitride E-mode HEMT device with a fully recessed barrier layer under the gate.
  • FIG. 3 presents another conventional III-nitride E-mode HEMT device with a partially recessed barrier layer under the gate.
  • FIG. 4 presents an example E-mode semiconductor device in accordance with one or more embodiments described herein.
  • FIG. 5 presents a circuit diagram of the equivalent resistance of an example E-mode semiconductor device in accordance with various aspects and embodiments described herein.
  • FIG. 6 provides a graph depicting the simulated conduction bands at the access region of an example E-mode semiconductor device in accordance with aspects and embodiments described herein.
  • FIG. 7 provides another graph depicting the simulated conduction bands at the recessed gate region of an example E-mode semiconductor device in accordance with aspects and embodiments described herein.
  • FIG. 8 presents graphs demonstrating the threshold voltage robustness of an example E-mode semiconductor device having with different gate structure recess depths in accordance with one or more embodiments described herein.
  • FIGs. 9-14 present an example fabrication process of an example E-mode semiconductor device in accordance with one or more embodiments described herein.
  • FIG. 15 presents another example E-mode semiconductor device in accordance with one or more additional embodiments described herein.
  • FIGs. 16-20 present an example fabrication process of another example E-mode semiconductor device in accordance with one or more additional embodiments described herein.
  • FIG. 21 presents another example E-mode semiconductor device in accordance with one or more additional embodiments described herein.
  • FIG. 22 presents another example E-mode semiconductor device configured in a rectifier mode in accordance with one or more additional embodiments described herein.
  • FIG. 23 provides graphs demonstrating the experimental transfer I D -V GS characteristics of an example DC-MOS-HEMT in accordance with one or more embodiments described herein.
  • FIG. 24 provides a graph demonstrating the experimental transfer I D -V DS characteristics of an example DC-MOS-HEMT in accordance with one or more embodiments described herein.
  • FIG. 25 provides a graph depicting the measured field-effect mobility of an example DC-MOS-HEMT in accordance with one or more embodiments described herein.
  • FIG. 26 provides a graph of the experimental off-state breakdown characteristics of an example DC-MOS-HEMT in accordance with one or more embodiments described herein.
  • FIG. 27 provides a graph of the experimental IV characteristics of a DC-MOS-HEMT configured as a field-effect rectifier in accordance with one or more embodiments described herein.
  • FIG. 28 presents a flow diagram of an example method for fabricating an E-mode semiconductor device in accordance with one or more embodiments described herein.
  • FIG. 29 presents a flow diagram of another example method for fabricating an E-mode semiconductor device in accordance with one or more embodiments described herein.
  • FIG. 30 presents a flow diagram of another example method for fabricating an E-mode semiconductor device in accordance with one or more embodiments described herein.
  • the subject matter disclosed herein relates to enhancement-mode (E-mode) semiconductor devices, and more particularly to E-mode HEMTs including a double channel (DC) .
  • the subject semiconductor devices are HEMTs including a III-N DC heterostructure and a metal-oxide-semiconductor (MOS) structure, also referred to herein as a DC-MOS-HEMT.
  • MOS metal-oxide-semiconductor
  • Methods for fabricating such DC-MOS-HEMTs are also provided. It is contemplated and intended that the design of the various features of the subject E-mode semiconductor devices can be applied to other heterostructures.
  • various exemplary embodiments of the subject E-mode semiconductor devices are based on an AlGaN/GaN heterostructure.
  • a person of ordinary person in the art can extend the various features of the subject E-mode semiconductor devices to other heterostructure variations and forms of design.
  • the subject E-mode semiconductor devices have a well-controlled threshold voltage and a low on-resistance.
  • the subject E-mode semiconductor devices feature an upper MOS-channel and a lower heterojunction channel under the control gate. Two heterojunction channels are formed in the the source-to-gate and gate-to-drain access regions, an upper channel and a lower channel, both of which exhibit high electron mobility and relatively high electron density. Carriers in the E-mode semiconductor device can flow from the upper channel to the lower channel or from the lower channel to the upper channel with very low resistance.
  • the E-mode semiconductor device includes a group III-nitride heterostructure including a substrate, a nucleation layer, a buffer layer, a lower channel layer, an insertion layer, an upper channel layer, and one or more barrier layers. At least one of the one or more barrier layers has a bandgap larger than that of the underlying upper channel layer, and the insertion layer has a bandgap larger than the underlying lower channel layer.
  • the heterostructure features two channels, one at the interface between the barrier and the upper channel layer, and the other one at the interface between the insertion layer and lower channel layer.
  • the E-mode semiconductor device further includes a recessed gate structure provided within a recess formed within the one or more barrier layers and in some embodiments, at least a portion of the upper channel layer.
  • a gate dielectric and a gate electrode are then formed in the gate recess.
  • a source electrode and a drain electrode are formed at opposite sides of the gate electrode.
  • the semiconductor devices operate as an E-mode device. Because the recess is terminated at or within the upper channel layer, the lower channel layer maintains a heterojunction channel with high electron mobility. In addition, the electrical connections between the access regions and the gate-controlled channel are not disrupted, resulting in a low connection resistance. Consequently, a low overall on-state resistance can be realized in subject E-mod semiconductor devices.
  • the threshold voltage of the subject E-mode semiconductor devices is also insensitive to variations in recess depth of the recessed gate structure as long as recess is terminated at or within the upper channel layer.
  • a semiconductor device in one or more embodiments, includes a substrate and a heterostructure formed on the substrate.
  • the heterostructure can include a lower channel layer, an upper channel layer, an insertion layer formed between the lower channel layer and the upper channel layer, and one or more barrier layers formed on the upper channel layer.
  • the insertion layer has a first bandgap that is larger than a second bandgap of the lower channel layer.
  • at least one of the one or more barrier layers has a first bandgap that is larger than a second bandgap of the upper channel layer.
  • the semiconductor device further includes a recess formed within the one or more barrier layers and at least a first portion of the upper channel layer, a gate structure formed within the recess.
  • the gate structure has a gate dielectric layer formed on and adjacent to a wall of the recess and a gate electrode formed on and adjacent to the electrode dielectric layer.
  • the semiconductor device further includes an upper channel formed within the upper channel layer near an interface between the upper channel layer and the one or more barrier layers, and a lower channel formed within the lower channel layer near an interface between the lower channel layer and the insertion layer.
  • the upper channel and the lower channel can be electrically connected thereby facilitating merged conduction of the upper channel and the lower channel.
  • the semiconductor device can have a low on-state resistance (e.g., less than about 7.0 ⁇ mm) based on the merged conduction of the upper channel and the lower channel.
  • the semiconductor device has a buffer layer formed between the upper channel layer and the insertion layer, and wherein the recess is formed through the upper channel layer and reaches the buffer layer without passing through the buffer layer.
  • a threshold voltage of the semiconductor device does not vary based on a depth of the recess within the at least the first portion of the upper channel layer.
  • a semiconductor device in another embodiment, includes a buffer layer, a lower channel layer formed on and adjacent to the buffer layer, an upper channel layer formed on and adjacent to the lower channel layer and one or more barrier layer formed on and adjacent to the upper channel layer.
  • the upper channel layer has a first bandgap that is larger than a second bandgap of the lower channel layer.
  • at least one of the one or more barrier layers has a first bandgap that is larger than a second bandgap of the upper channel layer.
  • the semiconductor device further includes a recess formed within the one or more barrier layers and at least a first portion of the upper channel layer, and a gate structure formed within the recess.
  • the gate structure includes a gate dielectric layer formed on and adjacent to a wall of the recess and a gate electrode formed on and adjacent to the electrode dielectric layer.
  • the semiconductor device can further include an upper channel formed within the upper channel layer near an interface between the upper channel layer and the one or more barrier layers, and a lower channel formed within the lower channel layer near an interface between the lower channel layer and the upper channel layer.
  • the upper channel and the lower channel can be electrically connected thereby causing merged conduction of the upper channel and the lower channel.
  • an on-state resistance of the semiconductor device is less than about 7.0 ⁇ mm based on the merged conduction of the upper channel and the lower channel.
  • a method in yet another embodiment, includes forming a heterostructure including a buffer layer, a lower channel layer on and adjacent to the buffer layer, an insertion layer on and adjacent to the lower channel layer, an upper channel layer on the insertion layer, and a barrier layer on the upper channel layer.
  • the method further includes forming a source electrode and a drain electrode on and adjacent to the barrier layer of the heterostructure, forming a passivation layer on and adjacent to the barrier layer and between the source electrode and the drain electrode, and forming a recess through the passivation layer, the barrier layer and a first portion of the upper channel layer, wherein a second portion of the upper channel layer remains below the recess.
  • the method further includes forming a gate dielectric layer on and adjacent to a wall of the recess and the passivation layer, and forming a gate electrode within the recess and adjacent to the gate dielectric layer structure formed within the recess.
  • the method further includes forming an upper channel within the upper channel layer near an interface between the upper channel layer and the one or more barrier layers, forming a lower channel within the lower channel layer near an interface between the lower channel layer and the insertion layer, and electrically connecting the upper channel and the lower channel resulting in merged conduction of the upper channel and the lower channel.
  • the method further includes, applying the positive voltage to the gate electrode, achieving an on-state resistance of less than about 7.0 ⁇ mm based the merged conduction of the upper channel and the lower channel.
  • FIG. 1 presents a conventional III-nitride enhancement-mode (E-mode) HEMT device 100 in accordance with various aspects and embodiments described herein.
  • Device 100 has a heterostructure that includes a substrate 102, a nucleation layer 104 formed on and adjacent to the substrate 102, a buffer layer 106 formed on and adjacent to the nucleation layer 104, a channel layer 108 formed on and adjacent to the buffer layer 106, and a barrier layer 110 formed on and adjacent to the channel layer 108.
  • Device 100 also includes a passivation layer 112 formed on and adjacent to the barrier layer 110.
  • Device 100 further includes a recessed gate structure formed with a recess that passes completely through the passivation layer 112 and the barrier layer 110 and into the channel layer 108.
  • the recessed gate structure includes a gate dielectric layer 114 formed on and adjacent to a wall of the recess (e.g., lining the recess) and a gate electrode 118 formed within and above the recess on and adjacent to the gate dielectric layer 114.
  • the gate dielectric layer 114 further covers portions of the passivation layer 112.
  • a source electrode 116 and drain electrode 120 are respectively provided on the heterostructure on either sides of the gate electrode 118.
  • Device 100 further includes a channel 122 located within the channel layer 108 at or near the interface between the channel layer 108 and the barrier layer 110.
  • Device 100 includes a fully recessed barrier layer 110 under the gate electrode 118.
  • the bottom or foot region 123 of the recessed gate structure (e.g., including the gate dielectric layer 114 and the gate electrode 118) , extends through the entire thickness of the barrier layer 110.
  • the foot region 123 of the recessed gate structure extends into a portion of the channel layer 108.
  • Device 100 (and devices having a similar structure) can operate as an E-mode device as a result of recessing the gate structure into the barrier layer 110.
  • the gate dielectric layer 114 serves to suppress gate leakage current at the foot region 123.
  • device 100 does not include any portion of the barrier layer 110 below the foot region 123, the electrons or carriers at the gate foot region 123 flow at the interface between the gate dielectric layer 114 and the underlying channel layer 108.
  • the interface between the gate dielectric layer 114 and the underlying channel layer 108 is a metal-insulator-semiconductor channel (abbreviated as MIS-channel) .
  • MIS-channel metal-insulator-semiconductor channel
  • carriers flowing through a MIS-channel exhibit reduced mobility compared to carriers at the interface of a heterojunction. Reduced carrier mobility leads to undesirable effects such as high conduction loss and lower power conversion efficiency.
  • the depth d1 of the recessed gate structure substantially affects the conduction path between the channel 122 and the access regions (not shown) respectively located on either sides of the gate electrode 114 near the source electrode 116 and the drain electrode 120.
  • the depth d1 of the gate foot region 123 below the upper surface of the channel 108. For example, if there is any over-recess of depth d1 by even a few nanometers, the conduction path between the access regions (not shown) and the channel 122 will be disrupted.
  • FIG. 2 shows the resistance components of conventional III-nitride E-mode HEMT device 100 with a fully recessed barrier layer under the gate. Repetitive description of like elements employed in respective embodiments is omitted for sake of brevity.
  • Line 200 represents the flow of carriers through the device 100 when in an on-state.
  • the respective rectangles along line 200 represent regions where carrier flow is hindered.
  • device 100 exhibits a large carrier resistance at an area 204 under the recessed gate structure at the foot region 123, and at the two corner areas 202 and 206 at the two edges of the gate region.
  • a large on-resistance leads to higher conduction loss and lower power conversion efficiency.
  • device 100 provides the advantages of being an E-mode III-nitride device, device 100 has a relatively high conduction loss and low power conversion efficiency.
  • FIG. 3 presents another conventional III-nitride E-mode HEMT device 300 in accordance with various aspects and embodiments described herein.
  • Device 300 includes same or similar features as device 100 with the modification of having a partially recessed barrier layer 110. Repetitive description of like elements employed in respective embodiments is omitted for sake of brevity.
  • the foot region 123 of the recessed gate structure (e.g., including the gate dielectric layer 114 and the gate electrode 118) of device 300 extends through only a portion of the thickness of the barrier layer 110.
  • a portion 302 of the barrier layer 110 remains between the foot region 123 of the recessed gate structure and the channel layer 108.
  • Carriers at this heterojunction interface exhibits higher mobility relative to carriers in the MIS-channel of device 100 (e.g., the interface between the gate dielectric layer 114 and the upper channel layer 108) .
  • the thickness of portion 302 of the barrier layer below the foot region 123 of the recessed gate structure is difficult to control.
  • the threshold voltage of device 300 is highly sensitive to the thickness of the portion 302 of the barrier layer below the foot region 123 of the recessed gate structure. As a result, the threshold voltage of device 300 is difficult to control. Therefore, although device 300 has reduced on-state resistance relative to device 100, device 300 suffers from a hindered ability to control the uniformity and repeatability of the threshold voltage for the partially recessed gate structure, since the threshold voltage is highly sensitive to the recess depth.
  • FIG. 4 presents an example E-mode semiconductor device 400 in accordance with one or more embodiments described herein.
  • semiconductor device 400 is a DC-MOS-HEMT. Similar to devices 100 and 300, device 400 includes a recessed gate structure, resulting in operation of device 400 as an E-mode device. However, device 400 includes several notable differences relative to devices 100 and 300, as explained in detail below. These differences result in device 400 having a well-controlled threshold voltage and a low on-state resistance relative to devices 100, 300 and other similar E-mode HEMTs.
  • Device 400 has a heterostructure that includes a substrate 402, a nucleation layer 404 formed on and adjacent to the substrate 402, and a buffer layer 406 formed on and adjacent to the nucleation layer 404.
  • the substrate can include but is not limited to, silicon, sapphire, diamond, silicon carbide (SiC) , aluminum nitride (AlN) , gallium nitride (GaN) , and other suitable materials.
  • the nucleation layer 404 can include but is not limited to, AlN, GaN, indium nitride (InN) , or their alloys.
  • the buffer 406 can include but is not limited to, AlN, GaN, InN, or their alloys.
  • the heterostructure further includes a lower channel layer 408b, an insertion layer 409, an upper channel layer 408a, and a barrier layer 410.
  • the barrier layer 410 can include a stack of two or more layers (not shown) .
  • the materials of the lower channel layer 408b, the insertion layer 409, the upper channel layer 408a, and the barrier layer 410 can vary so long as the bandgap of the insertion layer 409 is larger than the bandgap of the lower channel layer 408b, and the bandgap of the barrier layer 410 (or at least one layer of the barrier layer 410 when the barrier layer 410 is composed of two or more layers) is larger than the bandgap of the upper channel layer 408a.
  • the materials of the lower channel layer 408b, the insertion layer 409, the upper channel layer 408a, and the barrier layer 410 respectively include group III-nitrides.
  • the lower channel layer 408b can include but is not limited, to GaN, AlN, InN, or their alloys.
  • the lower channel layer 408b includes GaN.
  • the insertion layer 409 can also include but is not limited to, GaN, AlN, InN, or their alloys.
  • the insertion layer 409 includes AlN.
  • the upper channel layer 408a can also include but is not limited to, GaN, AlN, InN, or their alloys.
  • the upper channel layer 408a includes GaN.
  • the barrier layer 410 can also include GaN, AlN, InN, or their alloys. In one implementation, the barrier layer 410 includes AlGaN.
  • the barrier layer 410 includes a stack of two or more layers formed with different materials selected from GaN, AlN, InN, or their alloys.
  • the barrier layer 410 includes a layer of AlN and a layer of GaN.
  • the barrier layer can include an AlN layer formed on and adjacent to the upper channel layer 408a, an AlGaN layer formed on and adjacent to the AlN layer, and a GaN layer formed on and adjacent to the AlGaN layer.
  • device 400 also includes a passivation layer 412 (or layers) formed on and adjacent to the barrier layer 410.
  • the passivation layer 412 is adopted to relieve the current collapse phenomenon in III-nitride HEMTs.
  • the passivation can include but is not limited to, one or more insulating, or semi-conducting layers, such as silicon nitride (SiN x ) , silicon dioxide (SiO 2 ) , di-aluminium trioxide (Al 2 O 3 ) , AlN, GaN, Si, or diamond.
  • Device 400 further includes a recessed gate structure formed with a recess that passes completely through the passivation layer 412 and the barrier layer 410 and into the upper channel layer 408a.
  • the recessed gate structure includes a gate dielectric layer 414 formed on and adjacent to a wall of the recess (e.g., lining the recess) and a gate electrode 418 formed within and above the recess on and adjacent to the gate dielectric layer 414.
  • the gate dielectric layer 414 further covers portions of the passivation layer 412.
  • the gate dielectric layer 414 serves to insulate the gate electrode 418 and prevent gate current leakage.
  • the gate dielectric layer 414 can include but is not limited to one or more of Al 2 O 3 , AlN, SiN x , gallium trioxide (Ga 2 O 3 ) , SiO 2 , hafnium dioxide (HfO 2 ) , or any other dielectrics commonly practiced in semiconductor technology.
  • the gate electrode 418 covers at least the recessed gate region so that the recessed gate region is modulated by the gate voltage. In the embodiment shown, the gate electrode 418 also covers portions of the heterostrucure on either sides of the recess.
  • the gate electrode 418 can include any suitable metal.
  • the gate electrode can include but is not limited to one or more of one or more of, titanium (Ti) , Al, nickel (Ni) , gold (Au) , tungsten (W) , vanadium (V) , and tantalum (Ta) .
  • a source electrode 416 and a drain electrode 420 are respectively provided on (or within, not shown) the heterostructure on either sides of the gate electrode 418.
  • the source electrode 416 and the drain electrode 420 are respectively provided on and adjacent to the barrier layer 410 on either sides of the gate electrode 418.
  • the passivation layer 412 is further provided on the barrier layer 410 between the source electrode 416 and the drain electrode 420.
  • the source electrode 416 and the drain electrode 420 can be provided on either sides of the gate electrode 418 and within portions of the passivation layer 412 and/or the barrier layer 410 (not shown) .
  • the source electrode 416 and the drain electrode 420 are Ohmic contacts formed with a metal, including but not limited to one or more of, Ti, Al, Ni, Au, W, V, and Ta.
  • a thermal annealing process is applied to device 400 during the fabrication process to cause the source electrode 416 and the drain electrode 420 to become Ohmic.
  • device 400 includes two channels, an upper channel 422a and a lower channel 422b.
  • the upper channel 422a is formed within the upper channel layer 408a at the heterojunction interface between the upper channel layer 408a and the barrier layer 410.
  • the lower channel 422b is formed within the lower channel layer 408b at the heterojunction interface between the insertion layer 409 and the lower channel layer 408b.
  • the upper channel 422a and the lower channel 422b are electrically connected thereby facilitating movement of electrons or carriers between the upper channel 422a and the lower channel 422b when a positive gate voltage is applied to gate electrode 418 to turn the device 400 on.
  • carriers move between the upper channel 422a and the lower channel 422b, they have to cross the upper channel layer 408a and/or the insertion layer 409.
  • the thickness of upper channel layer 408a thus determines the 2DEG distribution. Accordingly, the thicknesses of the insertion layer 409 and the upper channel layer 408a can be selected so as to facilitate movement of carriers between the respective channels (e.g., so as that the two channels in the access region are effectively connected to the channel under the gate) .
  • a thickness of the insertion layer 409 and the upper channel layer 408a is selected to facilitate movement of electrons from the lower channel 422b to the upper channel 422a, and vice versa.
  • the thickness of the insertion layer 409 is thin enough so that at a zero gate-to-source voltage, both the upper channel 422a and the lower channel 422b are pinched off.
  • the insertion layer 409 has a thickness from about 0.1 nanometer (nm) to about 10 nm. In another embodiment, the insertion layer 409 has a thickness from about 0.5 nm to about 5.0 nm. Still in yet another embodiment, the insertion layer 409 has a thickness of about 1.5 nm. Further, the upper channel layer 408a can have a thickness from about 1.0 nm to about 20 nm. In another embodiment, the upper channel layer 408a has a thickness form about 2.0 nm to about 15 nm. Still in another embodiment, the upper channel layer 408a has a thickness of about 4.0 nm to about 10.0 nm.
  • the upper channel layer 408a has a thickness of about 6.0 nm. In various embodiments, a combined thickness of the upper channel layer 408a and the insertion layer 409 is from about 1.0 nm to about 30.0 nm. In other embodiments, a combined thickness of the upper channel layer 408a and the insertion layer 409 is from about 10.0 nm to about 20.0 nm.
  • the recessed gate structure is formed in a recess that passes completely through the thickness of the barrier layer 410 thereby making device 400 an E-mode device. Also similar to device 100, in device 400 the recess of the recessed gate structure extends into a portion of the upper channel layer 408a. As a result, the upper channel 422a at the gate foot region 423 is located between gate dielectric layer 410 and the upper channel layer 408a, which is referred to as a metal insulator semiconductor (MIS) channel. As discussed above with respect to FIGs. 1 and 3, the electron mobility of an MIS channel (e.g., upper channel 422a) is lower than a channel located at a heterojunction interface.
  • MIS metal insulator semiconductor
  • device 422b also includes lower channel 422b which is formed at the heterojunction interface between the lower channel layer 408b and the insertion layer 409. Further, the lower channel 422b is located away from the gate foot region 423 of the recessed gate structure. As a result, high electron mobility is maintained in the lower channel 422b and the resistance originated from the gate foot region 423 is greatly reduced.
  • Device 400 When a positive gate voltage is applied to the gate electrode 418, because the upper channel 422a and the lower channel 422b are electrically connected, electrons flow between the two channels, resulting in a merged conductance of the two channels.
  • Device 400 thus exhibits a reduced on-state resistance relative to devices 100 and 300 as a result of merged conduction of the upper channel 422a and the lower channel 422b.
  • the resistance originated from the access region is determined by the 2DEG density and electron mobility in the access region, independent of the characteristics of the recessed gate structure region.
  • the thickness of upper channel layer 408a determines the 2DEG distribution. Therefore, the resistance originated from the access region maintains low.
  • the total on-state resistance (R on ) of device 400 is less than about 7.0 ⁇ mm (e.g., about 6.9 ⁇ mm) which is significantly less than that of device 100 (e.g., which is about 20.0 ⁇ mm) .
  • FIG. 5 presents a circuit diagram 500 of the equivalent resistance of example E-mode semiconductor device 400 in accordance with various aspects and embodiments described herein.
  • the total on-resistance ( Ron ) of semiconductor device 400 is a combination of the contact resistances Rc , resistance at source-side access region RS , resistance at drain-side access region RD , and the resistance at the gated region RG .
  • FIG. 6 provides a graph 600 depicting the simulated conduction bands at the access region of an example E-mode semiconductor device (e.g., device 400) in accordance with aspects and embodiments described herein.
  • FIG. 7 provides another graph depicting the simulated conduction bands at the recessed region of the example E-mode semiconductor device in accordance with aspects and embodiments described herein.
  • the graphs of FIGs. 6 and 7 are generated based on the subject E-mode semiconductor device 400 having a gate dielectric layer 414 including Al 2 O 3 , a barrier layer 410 including an upper layer of GaN, a middle layer of AlGaN and lower layer of AlN, an upper channel layer 408a including GaN, an insertion layer 409 including AlN, and a lower channel layer 408b including GaN.
  • the conduction band depicted in graph 600 is simulated for the access region of device 400 when voltages of all electrodes are zero. Owing to the polarization effect in the insertion layer, a channel is formed at the interface between the insertion layer and the upper channel layer, in addition to the original upper channel at the interface between the barrier and the upper channel layer.
  • the conduction band depicted in graph 700 is simulated for the recessed gate region for device 400, with voltage of the gate electrode increasing from 0 V to 6 V. With the polarization effect in the insertion layer, the lower channel is turned on first, and the upper channel is turned on later with a larger gate voltage.
  • device 300 suffers from a hindered ability to control the uniformity and repeatability of the threshold voltage for the partially recessed gate structure since the threshold voltage is highly sensitive to the recess depth.
  • device 400 is substantially insensitive to variations in recess depth of the recessed gate structure as long as recess is terminated at or within the upper channel layer 408a.
  • the threshold voltage of device 400 does not vary (or substantially vary) based on a depth of the recess within the at least the first portion of the upper channel layer.
  • the depth (d1) of the gate foot region 423 below the upper surface of the upper channel 408a, or the depth (d2) between the gate foot region 423 and the lower surface of the upper channel 408a is not critical in device 400 to ensure the conduction paths of channel 422a or channel 422b between the access regions (not shown) are not disrupted.
  • the threshold voltage of device 400 varies less than 10%when the depth (d1) of the gate foot region 423 below the upper surface of the upper channel 408a increases or decreases by 150%.
  • FIG. 8 presents graphs 801-806 demonstrating the threshold voltage robustness of example E-mode semiconductor device 400 with different gate structure recess depths in accordance with one or more embodiments described herein.
  • the graphs of FIG. 8 generated based on the subject E-mode semiconductor device 400 having a gate dielectric layer 414 including Al 2 O 3 , a barrier layer 410 including an upper layer of GaN, a middle layer of AlGaN and lower layer of AlN, an upper channel layer 408a including GaN, an insertion layer 409 including AlN, and a lower channel layer 408b including GaN.
  • Graphs 801, 803 and 805 respectively depict simulated conduction bands of the device 400 when d2 (e.g., the thickness of the upper channel layer 408a below the foot region 423 of the recessed gate structure) is 6.0 nm, 4.0 nm and 2.0 nm respectively.
  • Graphs 802, 804 and 806 depict the simulated threshold voltage V th when d2 is 6.0 nm, 4.0 nm and 2.0 nm respectively.
  • the threshold voltage (V th ) of device 400 is about 0.3 V when d2 is 6.0 nm, about 0.25 V when d2 is 4.0 nm, and about 0.22 V when d2 is 2 nm.
  • the threshold voltage of device 400 does not vary or significantly vary (e.g., varies less than 10%) based on the depth of the recessed gate structure so long as the depth of the recessed gate structure remains within the thickness of the upper channel layer 408a.
  • FIGs. 9-14 present an example fabrication process of an example E-mode semiconductor device 400 in accordance with one or more embodiments described herein. Repetitive description of like elements employed in respective embodiments is omitted for sake of brevity.
  • FIG. 9 presents an initial heterostructure 900 from which device 400 can be created.
  • the heterostructure 900 includes a substrate 402, a nucleation layer 404 formed on and adjacent to the substrate 402, a buffer layer 406 formed on and adjacent to the nucleation layer 404, a lower channel layer 408a formed on and adjacent to the buffer layer 406, an insertion layer 409 formed on and adjacent to the lower channel layer 408b, an upper channel layer 408a formed on and adjacent to the insertion layer 409 and a barrier layer 410 (or layers) formed on and adjacent to the upper channel layer 408a.
  • the heterostructure 900 can be prepared or grown using various semiconductor fabrication techniques, including but not limited to metal-organic chemical vapour deposition (MOCVD) , molecular beam epitaxy (MBE) , hydride vapour phase epitaxy (HVPE) , and other suitable techniques.
  • MOCVD metal-organic chemical vapour deposition
  • MBE molecular beam epitaxy
  • HVPE hydride vapour phase epitaxy
  • the heterostructure 900 is composed of various layers including III-nitrides.
  • the lower channel layer 408b includes GaN
  • the insertion layer 409 includes AlN
  • the upper channel layer 408a includes GaN
  • the barrier layer 410 includes AlGaN.
  • the insertion layer 409 has a larger bandgap relative to the bandgap of the lower channel layer 408b and the barrier layer 410 has a larger bandgap relative to the upper channel layer 408b.
  • the heterostructure 900 includes an upper channel 422a at the interface between the barrier layer 410 and the upper channel layer 408a, and a lower channel 422b at the interface between the insertion layer 409 and the lower channel layer 408b.
  • Ohmic contacts are formed on the heterostructure 900 for the source electrode 416 and the drain electrode 420.
  • the metal employed to form the source electrode 416 and the drain electrode 420 can include but is not limited to one or more of, Ti, Al, Ni, Au, W, V, or Ta.
  • a thermal annealing process is employed to cause the source electrode 416 and the drain electrode 420 to be Ohmic contacts.
  • a passivation layer 412 is formed on the heterostructure between the source electrode 416 and the drain electrode 420, as shown in FIG. 11.
  • the passivation layer 412 can include one or a combination of insulating, or semi-conducting layers, such as SiNx, SiO2, Al2O3, AlN, GaN, Si, or diamond.
  • a recess 1202 is then formed through the passivation layer 412, the barrier layer 410, and a portion of the upper channel layer 408a using a suitable etching technique, as shown in FIG. 12.
  • the etching of the passivation layer 412 can include a wet etch or dry etch depending on the material employed for the passivation layer 412.
  • the method for etching the barrier layer 410 and the portion of upper channel layer 408a is not limited.
  • suitable methods for etching the barrier layer 410 and/or the upper channel layer 408a can include but are not limited to, plasma dry etching, digital etching, or a combination of them.
  • the depth of the recess 1202 can vary so long as the recess does not pass through the upper channel layer 408a and into the insertion layer 409.
  • the depth d2 of the recess 1202 is between about 0.1 nm and about 19.0 nm.
  • the depth d2 of the recess 1202 is between about 1.0 nm and about 10.0 nm.
  • the depth d2 of the recess 1202 is between about 2.0 nm and about 6.0 nm.
  • the depth d1 of the recess 1202 can also vary based on the thickness of the upper channel layer 408a which is preferably between about 0.1 nm to about 20.0 nm.
  • the depth d1 of the recess is about 90%of the thickness of the upper channel layer 408a. In another implementation the depth d1 of the recess is about 75%of the thickness of the upper channel layer 408a. In another implementation the depth d1 of the recess is about 50%of the thickness of the upper channel layer 408a. In another implementation the depth d1 of the recess is about 25%of the thickness of the upper channel layer 408a. In yet another implementation the depth d1 of the recess is about 10%of the thickness of the upper channel layer 408a.
  • the gate dielectric layer 414 is deposited as shown in FIG. 13.
  • the gate dielectric layer 414 can include various suitable dielectric materials, including but not limited to one or more of, Al 2 O 3 , AlN, SiN x , Ga 2 O 3 , SiO 2 , or HfO 2 , the gate dielectric layer 414 can be deposited using various techniques, including but not limited to, MOCVD, plasma-enhanced chemical vapor deposition (PECVD) , atomic layer deposition (ALD) , low-pressure chemical vapor deposition (LPCVD) , thermal oxidation, sputtering, evaporation, or spin-coating.
  • the gate electrode 418 is then formed over the gate dielectric layer 414 within the recess, resulting in the formation of E-mode semiconductor device 400.
  • FIG. 15 presents another example E-mode semiconductor device 1500 in accordance with one or more additional embodiments described herein.
  • semiconductor device 1500 is a DC-MOS-HEMT.
  • Semiconductor device 1500 includes same or similar feature as semiconductor device 400 with the difference noted below. Repetitive description of like elements employed in respective embodiments is omitted herein for sake of brevity.
  • the structure of device 1500 differs from that of device 400 with respect to the depth of the recessed gate structure (e.g., including the gate electrode 418 and the gate dielectric layer 414) and the addition of a buffer layer 1502 between the insertion layer 409 and the upper channel layer 408a.
  • the structure of device 1500 also does not include a passivation layer 412.
  • the gate dielectric layer 418 can be formed directly on the barrier layer 410.
  • the recessed gate structure of device 1500 extends through the entire thickness of the upper channel layer 408a.
  • the gate foot region 423 is located at the interface between the upper channel layer 408 and the buffer layer 1502.
  • the upper buffer layer 1502 includes at least one of GaN, AlN, InN, or their alloys. In an exemplary embodiment, the upper buffer layer 1502 includes GaN. In addition, in one or more implementations, the upper buffer layer 1502 and the upper channel layer 408a respectively include the same material (e.g., GaN) .
  • the thicknesses of the upper channel layer 408a, the buffer layer 1502 and the insertion layer 409 are designed not to isolate the two channels (e.g., so as to facilitate movement of electrons between the two channels with low resistance) .
  • the upper channel layer 408a can have a thickness from about 1.0 nm to about 20 nm.
  • the upper channel layer 408a has a thickness form about 5.0 nm to about 15 nm.
  • the upper channel layer 408a has a thickness of about 10.0 nm.
  • the buffer layer 1502 can have a thickness from about 1.0 nm to about 20 nm. In another embodiment, the buffer layer 1502 has a thickness form about 5.0 nm to about 15 nm. Still in another embodiment, the buffer layer 1502 has a thickness of about 10.0 nm. Further, in one or more embodiments, the insertion layer 409 has a thickness from about 0.1 nanometer (nm) to about 10 nm. In another embodiment, the insertion layer 409 has a thickness from about 0.5 nm to about 5.0 nm. Still in yet another embodiment, the insertion layer 409 has a thickness of about 1.5 nm.
  • a combined thickness of the upper channel layer 408a, the buffer layer 1502 and the insertion layer is from about 1.0 nm to about 30.0 nm. In other embodiments, a combined thickness of the upper channel layer, 408a, the buffer layer 1502 and the insertion layer is from about 10.0 nm to about 20.0 nm.
  • Device 1500 provides the same or similar advantages as device 400.
  • the semiconductor device 1500 operate as an E-mode device. Because the recess is terminated within the upper channel layer 408a, the lower channel layer 408b maintains a heterojunction channel (e.g., lower channel 422b) with high electron mobility. Because the upper channel 422a and the lower channel 422b are electrically connected, electrons flow between the two channels, resulting in a merged conductance of the two channels. As a result, device 1500 thus exhibits a reduced on-state resistance relative to devices 100.
  • the total on-state resistance of device 1500 is less than about 7.0 ⁇ mm while that of device 100 is about 20.0 ⁇ mm.
  • device 400 is substantially insensitive to variations in recess depth of the recessed gate structure as long as recess is terminated at or within the upper channel layer 408a.
  • the threshold voltage of device 1500 does not vary (or substantially vary) based on the depth of the recess spanning the entire width of the upper channel layer 408a. Accordingly, the threshold voltage of device 1500 can be easily controlled.
  • FIGs. 16-20 present an example fabrication process of example E-mode semiconductor device 1500 in accordance with one or more additional embodiments described herein. Repetitive description of like elements employed in respective embodiments is omitted for sake of brevity.
  • FIG. 16 presents an initial heterostructure 1600 from which device 1500 can be created.
  • the heterostructure 1560 includes a substrate 402, a nucleation layer 404 formed on and adjacent to the substrate 402, a buffer layer 406 formed on and adjacent to the nucleation layer 404, a lower channel layer 408a formed on and adjacent to the buffer layer 406, an insertion layer 409 formed on and adjacent to the lower channel layer 408b, and a second buffer layer 1502 formed on and adjacent to the insertion layer 409.
  • the heterostructure 1600 can be prepared or grown using various semiconductor fabrication techniques, including but not limited to metal-organic chemical vapour deposition (MOCVD) , molecular beam epitaxy (MBE) , hydride vapour phase epitaxy (HVPE) , and other suitable techniques.
  • MOCVD metal-organic chemical vapour deposition
  • MBE molecular beam epitaxy
  • HVPE hydride vapour phase epitaxy
  • the heterostructure 1600 is composed of various layers including III-nitrides.
  • the fabrication process of device 1500 involves the formation of a regrowth mask 1702 (referred to herein as “mask” ) on a portion of the second buffer layer 1502 where the recessed gate structure will later be formed.
  • a regrowth mask 1702 (referred to herein as “mask” ) on a portion of the second buffer layer 1502 where the recessed gate structure will later be formed.
  • Various materials could be used as the mask, for example SiO 2 , Al 2 O 3 , SiN, or another suitable material.
  • the upper channel layer 408a and the barrier layer 410 are then formed or grown on the second buffer layer 1502 around the mask.
  • the upper channel 422a is further established within the upper channel layer 408a at the heterojunction interface between the upper channel layer 408a and the barrier layer 410, and a lower channel 422b is established within the lower channel layer 408b at the heterojunction interface between the lower channel layer 408b and the insertion layer 409.
  • the mask 1702 is then removed (e.g., by wet etch or dry etch) and a recess 1902 is formed within the barrier layer 410 and the upper channel layer 408, as shown in FIG. 19.
  • the gate recess 1902 is terminated within the upper channel layer 408a.
  • the gate dielectric layer 414 is deposited onto the one or more barrier layers 410 and the source electrode 416, the gate electrode 418 and the drain electrode 420 are formed, resulting in device 1500.
  • the gate dielectric layer 414 can include various suitable dielectric materials, including but not limited to one or more of, Al 2 O 3 , AlN, SiN x , Ga 2 O 3 , SiO 2 , or HfO 2 , the gate dielectric layer 414 can be deposited using various techniques, including but not limited to, MOCVD, plasma-enhanced chemical vapor deposition (PECVD) , atomic layer deposition (ALD) , low-pressure chemical vapor deposition (LPCVD) , thermal oxidation, sputtering, evaporation, or spin-coating.
  • PECVD plasma-enhanced chemical vapor deposition
  • ALD atomic layer deposition
  • LPCVD low-pressure chemical vapor deposition
  • the gate electrode 418 can cover at least the recessed gate region, so that the recessed region is modulated by the gate voltage.
  • the lower channel 422b of device 1500 is turned on first due to the polarization effect of the insertion layer 409. Because the lower channel 422b remains a heterojunction channel, the electron mobility in the lower channel is high, thus compensating for the lower electron mobility of the upper channel 422a which is a MIS-channel formed between the upper channel layer 408a and the gate dielectric layer 418.
  • FIG. 21 presents another example E-mode semiconductor device 2100 in accordance with one or more additional embodiments described herein.
  • semiconductor device 2000 is a DC-MOS-HEMT.
  • Semiconductor device 2000 includes same or similar feature as semiconductor devices with the difference noted below. Repetitive description of like elements employed in respective embodiments is omitted herein for sake of brevity.
  • the structure of device 2100 differs from that of device 400 with respect to the removal of the insertion layer 409. Although the insertion layer 409 is removed, device 2100 still includes the upper channel layer 408a and the lower channel layer 408b as well as the upper channel 422a and the lower channel 422b. According to this embodiment, the upper channel layer 408a, the lower channel layer 408b, and the barrier layer 410 have different bandgaps. In particular, the upper channel layer 408a can have a larger bandgap than the lower channel layer 408b and the barrier layer 410 can have a larger bandgap than the upper channel layer.
  • the lower channel layer 408b can include InGaN
  • the upper channel layer 408a can include GaN
  • the barrier layer 410 can include stack of three layers, including an AlN layer formed on and adjacent to the upper channel layer 408a, an AlGaN layer formed on and adjacent to the AlN layer, and a GaN layer formed on and adjacent to the AlGaN layer.
  • the upper channel 422a of device 2100 is provided at the interface between the upper channel layer 408a and the barrier layer 410.
  • the lower channel 422b is provided at the interface between the lower channel layer 408a and the upper channel layer 408b, which is a heterojunction.
  • the electrons move between the two channels in response to application of a positive voltage to the gate electrode 418, they have to cross only the upper channel layer 408a.
  • the thicknesses of the upper channel layer 408a and the conduction band off-set between the upper channel layer 408a and the lower channel layer 408b are designed so as to not to isolate the two channels (e.g.
  • the thickness of the upper channel layer 408a can is from about 1.0 nm to about 30 nm. In another embodiment, the upper channel layer 408a has a thickness form about 1.0 nm to about 20 nm. In another embodiment, the upper channel layer 408a has a thickness form about 5.0 nm to about 15 nm. Still in another embodiment, the upper channel layer 408a has a thickness of about 10.0 nm. The gate recess is terminated within the upper channel layer 408a.
  • the depth of the gate recess (e.g., d1 or d2) can vary so long as the gate recess does not extend into the lower channel layer 408b.
  • the lower channel 422b is turned on first due to the polarization effect of the upper channel layer 408a. As the lower channel remains a heterojunction channel, the electron mobility in the lower channel is high.
  • FIG. 22 presents another example E-mode semiconductor device 2200 configured in a rectifier mode in accordance with one or more additional embodiments described herein.
  • semiconductor device 2200 is a DC-MOS-HEMT, configured as a field-effect rectifier.
  • Semiconductor device 2200 includes same or similar feature as semiconductor device 400 with the difference noted below. Repetitive description of like elements employed in respective embodiments is omitted herein for sake of brevity.
  • Semiconductor device 2200 differs from semiconductor device 400 in that its gate electrode 418 is shorted to the source electrode 416.
  • the combination of the gate electrode 418 and the source electrode 416 serves as the anode 2202 of the semiconductor device 2200.
  • the drain electrode 420 serves as the cathode of the semiconductor device 2200.
  • the resulting semiconductor device 2200 thus has a two-terminal configuration and exhibits rectifying characteristics based on the two-terminal configuration (e.g., the resulting semiconductor device 2200 operates as a rectifier) .
  • the semiconductor device 2200 When operating as a rectifier and being configured with the subject DC-MOS-HEMT structure, the semiconductor device 2200 features a low channel resistance, which is beneficial in reducing the on-state voltage of the rectifier.
  • the distance between electrode 416 and electrode 418 can be shortened and is preferably as short as possible. It is noted that although semiconductor device 2200 includes substantially the same heterostructure as device 400, it is feasible to configure the semiconductor devices 1500 and 2100 into rectifiers using a similar technique (e.g., by shorting the gate electrode 418 to the source electrode 116) .
  • FIG. 23 provides graphs 2301 and 2302 demonstrating the experimental transfer I D -V GS characteristics of an example DC-MOS-HEMT (e.g., device 400) in accordance with one or more embodiments described herein.
  • the threshold voltage V th is 0.5 V for the DC-MOS-HEMT at a drain current criterion of 10.0 ⁇ A/mm.
  • two g m peaks are present, indicating the strongest gate modulation of the lower channel and upper channel, respectively.
  • the device has a source-to-gate distance L GS , gate length L G , and gate-to-drain distance L GD of 2 ⁇ m, 1.5 ⁇ m and 15 ⁇ m, respectively.
  • FIG. 24 provides a graph 2400 demonstrating the experimental transfer I D -V DS characteristics of an example DC-MOS-HEMT (e.g., device 400 in accordance with one or more embodiments described herein.
  • the gate-to-source voltage V GS is changed from 0 V to 10 V, with a step of 2 V.
  • a very low on-resistance e.g., about 6.9 ⁇ mm
  • gate-to-drain distance 15 ⁇ m.
  • FIG. 25 provides a graph 2500 depicting the measured field-effect mobility of an example DC-MOS-HEMT (e.g., device 400) in accordance with one or more embodiments described herein.
  • the maximum field-effect mobility of the lower channel in the DC-MOS-HEMT is around 1800 cm 2 / (V ⁇ s) , which is close to the maximum field effect mobility of the lower channel in the double-channel HEMT (DC-HEMT) with no gate recess. Therefore, the gate recess process causes very little degradation of the mobility in the lower channel of the DC-MOS-HEMT.
  • the subject DC-MOS-HEMT has a gate length of 44 ⁇ m.
  • FIG. 26 provides a graph 2600 of the experimental off-state breakdown characteristics of an example DC-MOS-HEMT (e.g., device 400) in accordance with one or more embodiments described herein. As shown in graph 2500, a breakdown of over 700 V is achieved at a drain current criterion of 1 ⁇ A/mm. The subject DC-MOS-HEMT has a gate-to-drain distance of 15 ⁇ m.
  • FIG. 27 provides a graph 2700 of the experimental IV characteristics of a DC-MOS-HEMT configured as a field-effect rectifier (e.g., semiconductor device 2200) in accordance with one or more embodiments described herein. As shown in graph 2700, rectifying characteristics is achieved. In the forwards state, the rectifier begins to conduct at a low voltage, and in reverse state, the rectifier blocks a high voltage.
  • the subject rectifier configured from a DC-MOS-HEMT has an anode-to-cathode distance of 15 ⁇ m.
  • FIGs. 28-30 illustrate methods in accordance with certain aspects of this disclosure. While, for purposes of simplicity of explanation, the methods are shown and described as a series of acts, it is to be understood and appreciated that this disclosure is not limited by the order of acts, as some acts may occur in different orders and/or concurrently with other acts from that shown and described herein. For example, those skilled in the art will understand and appreciate that methods can alternatively be represented as a series of interrelated states or events, such as in a state diagram. Moreover, not all illustrated acts may be required to implement methods in accordance with certain aspects of this disclosure. Additionally, it is to be further appreciated that the method disclosed hereinafter and throughout this disclosure is capable of being stored on an article of manufacture to facilitate transporting and transferring such methods to computers.
  • FIG. 28 presented is a flow diagram of an example method 2800 for fabricating an E-mode semiconductor device in accordance with one or more embodiments described herein.
  • method 2800 can be employed to fabricate a DC-MOS-HEMT, such as E-mode semiconductor device 400. Repetitive description of like elements employed in respective embodiments is omitted for sake of brevity.
  • a heterostructure is formed (e.g., heterostructure 900) using a suitable semiconductor fabrication technique, such as but not limited to, MOCVD, MBE, HVPE, and other suitable techniques.
  • the heterostructure can include a buffer layer (e.g., buffer layer 406) , a lower channel layer (e.g., lower channel layer 408b) on and adjacent to the buffer layer, an insertion layer (e.g., insertion layer 409) on and adjacent to the lower channel layer, an upper channel layer (e.g., upper channel layer 408a) on the insertion layer, and a barrier layer (e.g., barrier layer 410) on the upper channel layer.
  • the heterostructure 900 is composed of various layers including III-nitrides.
  • the lower channel layer 408b includes GaN
  • the insertion layer 409 includes AlN
  • the upper channel layer 408a includes GaN
  • the barrier layer 410 includes AlGaN.
  • the insertion layer 409 has a larger bandgap relative to the bandgap of the lower channel layer 408b and the barrier layer 410 has a larger bandgap relative to the upper channel layer 408b.
  • a source electrode e.g., source electrode 416) and a drain electrode (e.g., drain electrode 420) are formed on and adjacent to the barrier layer of the heterostructure.
  • a passivation layer (e.g., passivation layer 412) is formed on and adjacent to the barrier layer and between the source electrode and the drain electrode, and at 2808, a recess (e.g., gate recess 1202) is formed through the passivation layer, the barrier layer and a first portion of the upper channel layer, wherein a second portion of the upper channel layer remains below the recess.
  • FIG. 29 presents a flow diagram of another example method 2900 for fabricating an E-mode semiconductor device in accordance with one or more embodiments described herein.
  • method 2900 can be employed to fabricate a DC-MOS-HEMT, such as E-mode semiconductor device 400. Repetitive description of like elements employed in respective embodiments is omitted for sake of brevity.
  • a heterostructure is formed (e.g., heterostructure 900) using a suitable semiconductor fabrication technique, such as but not limited to, MOCVD, MBE, HVPE, and other suitable techniques.
  • the heterostructure can include a buffer layer (e.g., buffer layer 406) , a lower channel layer (e.g., lower channel layer 408b) on and adjacent to the buffer layer, an insertion layer (e.g., insertion layer 409) on and adjacent to the lower channel layer, an upper channel layer (e.g., upper channel layer 408a) on the insertion layer, and a barrier layer (e.g., barrier layer 410) on the upper channel layer.
  • the heterostructure 900 is composed of various layers including III-nitrides.
  • the lower channel layer 408b includes GaN
  • the insertion layer 409 includes AlN
  • the upper channel layer 408a includes GaN
  • the barrier layer 410 includes AlGaN.
  • the insertion layer 409 has a larger bandgap relative to the bandgap of the lower channel layer 408b and the barrier layer 410 has a larger bandgap relative to the upper channel layer 408b.
  • a source electrode e.g., source electrode 416) and a drain electrode (e.g., drain electrode 420) are formed on and adjacent to the barrier layer of the heterostructure.
  • a passivation layer e.g., passivation layer 412 is formed on and adjacent to the barrier layer and between the source electrode and the drain electrode, and at 2908, a recess (e.g., gate recess 1202) is formed through the passivation layer, the barrier layer and a first portion of the upper channel layer, wherein a second portion of the upper channel layer remains below the recess.
  • a gate dielectric layer (e.g., gate dielectric layer 414) is formed on and adjacent to a wall of the recess and the passivation layer.
  • a gate electrode (e.g., gate electrode 418) is formed within the recess and adjacent to the gate dielectric layer formed within the recess.
  • an upper channel e.g., upper channel 422a
  • a lower channel e.g., lower channel 422b
  • the method can further include electrically connecting the upper channel and the lower channel resulting in merged conduction of the upper channel and the lower channel when a positive voltage is applied to gate electrode.
  • on-state resistance of less than about 7.0 ⁇ mm is achieved based on the merged conduction of the upper channel and the lower channel.
  • FIG. 30 presents a flow diagram of another example method 3000 for fabricating an E-mode semiconductor device in accordance with one or more embodiments described herein.
  • method 3000 can be employed to fabricate a DC-MOS-HEMT, such as E-mode semiconductor device 1500. Repetitive description of like elements employed in respective embodiments is omitted for sake of brevity.
  • a heterostructure (e.g., heterostructure 1600) is formed using a suitable semiconductor fabrication technique, such as but not limited to, MOCVD, MBE, HVPE, and other suitable techniques.
  • the heterostructure can include a first buffer layer (e.g., buffer layer 406) , a lower channel layer (e.g., lower channel layer 408b) on and adjacent to the first buffer layer, an insertion layer (e.g., insertion layer 409) on and adjacent to the lower channel layer, and a second buffer layer (e.g., buffer layer 1502) on and adjacent to the insertion layer.
  • the heterostructure 1600 is composed of various layers including III-nitrides.
  • a mask structure (e.g., mask 1702) is formed on the second buffer layer.
  • an upper channel layer (e.g., upper channel layer 408a) is formed on and adjacent to the second buffer layer and around the mask structure.
  • a barrier layer (e.g., barrier layer 410) is formed on and adjacent to the upper channel layer and around the mask structure.
  • the mask structure is removed and a gate recess (e.g., recess 1902) is established through the upper channel layer and the barrier layer.
  • a gate structure e.g., including gate dielectric layer 414 and gate electrode 418) is formed within the gate recess.
  • exemplary and/or “demonstrative” is used herein to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples.
  • any aspect or design described herein as “exemplary” and/or “demonstrative” is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor is it meant to preclude equivalent exemplary structures and techniques known to those of ordinary skill in the art.

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Abstract

L'invention concerne un transistor HEMT à double canal (DC) à enrichissement. Selon un mode de réalisation, l'invention concerne un dispositif à semi-conducteur qui comprend un substrat et une hétérostructure formée sur le substrat. L'hétérostructure peut comprendre une couche de canal inférieure, une couche de canal supérieure, une couche d'insertion formée entre la couche de canal inférieure et la couche de canal supérieure, et une ou plusieurs couches barrière formées sur la couche de canal supérieure. Le dispositif à semi-conducteur comprend en outre un évidement formé à l'intérieur de la ou des couches barrière et d'au moins une première partie de la couche de canal supérieure, une structure de grille formée à l'intérieur de l'évidement. Selon divers modes de réalisation, la structure de grille a une couche diélectrique de grille formée sur une paroi de l'évidement et adjacente à celle-ci et une électrode de grille formée sur la couche diélectrique d'électrode et adjacente à celle-ci.
PCT/CN2016/088062 2015-07-01 2016-07-01 Transistor à haute mobilité électronique à double canal à enrichissement WO2017000906A1 (fr)

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CN112397583A (zh) * 2019-08-13 2021-02-23 新唐科技股份有限公司 增强型高电子迁移率晶体管器件
US20210272794A1 (en) * 2018-07-05 2021-09-02 Nippon Telegraph And Telephone Corporation Layered Material Laminate Structure and Method for Producing Same
WO2024009047A1 (fr) * 2022-07-08 2024-01-11 Commissariat A L'energie Atomique Et Aux Energies Alternatives Dispositif quantique a qubits de semi-conducteur comprenant des grilles disposees dans un semi-conducteur

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CN110047910B (zh) * 2019-03-27 2020-07-31 东南大学 一种高耐压能力的异质结半导体器件
CN110534557B (zh) * 2019-07-30 2021-03-09 中国科学技术大学 常关型场效应晶体管及其制备方法
CN111162117A (zh) * 2020-01-02 2020-05-15 杭州电子科技大学 一种抗单粒子烧毁的GaN器件
US11855199B2 (en) * 2020-10-29 2023-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. High Electron Mobility Transistor (HEMT) with a back barrier layer
CN113990950A (zh) * 2020-12-01 2022-01-28 深圳市晶相技术有限公司 一种半导体器件及其应用与制造方法
CN118476032A (zh) * 2022-03-25 2024-08-09 华为技术有限公司 氮化镓场效应晶体管的结构和制备方法

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CN107863360A (zh) * 2017-10-26 2018-03-30 西安交通大学 双沟道hemt太赫兹探测器
CN107863360B (zh) * 2017-10-26 2020-08-18 西安交通大学 双沟道hemt太赫兹探测器
US20210272794A1 (en) * 2018-07-05 2021-09-02 Nippon Telegraph And Telephone Corporation Layered Material Laminate Structure and Method for Producing Same
CN112397583A (zh) * 2019-08-13 2021-02-23 新唐科技股份有限公司 增强型高电子迁移率晶体管器件
CN112397583B (zh) * 2019-08-13 2023-07-28 新唐科技股份有限公司 增强型高电子迁移率晶体管器件
WO2024009047A1 (fr) * 2022-07-08 2024-01-11 Commissariat A L'energie Atomique Et Aux Energies Alternatives Dispositif quantique a qubits de semi-conducteur comprenant des grilles disposees dans un semi-conducteur
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