WO2016206563A1 - 一种dpd系统 - Google Patents

一种dpd系统 Download PDF

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Publication number
WO2016206563A1
WO2016206563A1 PCT/CN2016/086030 CN2016086030W WO2016206563A1 WO 2016206563 A1 WO2016206563 A1 WO 2016206563A1 CN 2016086030 W CN2016086030 W CN 2016086030W WO 2016206563 A1 WO2016206563 A1 WO 2016206563A1
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WO
WIPO (PCT)
Prior art keywords
bit sequence
frequency band
signal
dpd
length
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PCT/CN2016/086030
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English (en)
French (fr)
Inventor
熊军
肖鹏
王杰丽
段滔
Original Assignee
大唐移动通信设备有限公司
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Application filed by 大唐移动通信设备有限公司 filed Critical 大唐移动通信设备有限公司
Priority to EP16813679.4A priority Critical patent/EP3316537B1/en
Priority to US15/738,799 priority patent/US10091037B2/en
Priority to KR1020187002217A priority patent/KR101867567B1/ko
Priority to JP2017566752A priority patent/JP2018518916A/ja
Publication of WO2016206563A1 publication Critical patent/WO2016206563A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
    • H04L25/4927—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using levels matched to the quantisation levels of the channel
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03343—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/005—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B1/0475—Circuits with means for limiting noise, interference or distortion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/62—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission for providing a predistortion of the signal in the transmitter and corresponding correction in the receiver, e.g. for improving the signal/noise ratio

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a DPD system.
  • the search of the LUT table address generally adopts a uniform quantization technique.
  • r n,m
  • represents the amplitude of the input signal
  • Q( ⁇ ) is the quantization factor
  • w m,q ,m 1...M
  • the input address of the LUT table is determined according to the amplitude Q(r n,m ) quantized by the input signal, that is, the DUT table is obtained by searching the LUT table according to the input signal amplitude
  • the DPD coefficient is expressed as LUT m (
  • the prior art is generally adapted to a single-band DPD system, and the single-band system is designed for a certain frequency band.
  • the single-band LUT table address is obtained directly from the signal amplitude intercept, and is not suitable for the multi-band DPD system.
  • the embodiment of the invention provides a DPD system for implementing multi-band DPD processing by generating a lookup table address suitable for multiple frequency bands.
  • a DPD system includes: a table lookup unit and a DPD processing unit, where the lookup table unit includes: first to fourth address conversion tables, first to Nth lookup tables, and a DPD coefficient combining module;
  • a first address conversion table configured to obtain a first bit sequence of a second length according to a bit sequence of a first length corresponding to an amplitude value of the first path signal of the first frequency band, where the first length is greater than the second a second address conversion table, configured to obtain a second bit sequence corresponding to the second length according to the bit sequence of the first length corresponding to the amplitude value of the first path signal of the second frequency band;
  • a third address conversion table configured to obtain a third bit sequence corresponding to the second length according to the bit sequence of the first length corresponding to the amplitude value of the second path signal of the first frequency band, and the second path of the first frequency band The signal is obtained after delaying the first signal of the first frequency band;
  • a fourth address conversion table configured to obtain a fourth bit sequence of the second length according to the bit sequence of the first length corresponding to the amplitude value of the second path signal of the second frequency band, and the second path of the second frequency band The signal is obtained after delaying the first signal of the second frequency band;
  • the ith lookup table in the first to the Nth lookup table is configured to combine the bit sequence of the second length corresponding to one channel of the first frequency band and the bit sequence of the second length corresponding to one channel of the second frequency band.
  • the i-th lookup table address searching for the ith DPD coefficient according to the i-th lookup table address, 1 ⁇ i ⁇ N;
  • a DPD coefficient combining module configured to process the first to Nth DPD coefficients to obtain one DPD coefficient
  • a DPD processing unit configured to perform DPD processing on the signal in the first frequency band according to the DPD coefficient processed by the DPD coefficient processing module.
  • M 1;
  • a first lookup table configured to search for a first DPD coefficient according to the first table lookup address formed by the first bit sequence and the second bit sequence; wherein, according to the order of the bits from high to low, the first A lookup table address includes a first bit sequence and the second bit sequence;
  • the second lookup table address includes a third bit sequence and the fourth bit sequence.
  • M 2;
  • a first lookup table configured to search for a first DPD coefficient according to the first table lookup address formed by the first bit sequence and the second bit sequence; wherein, according to the order of the bits from high to low, the first A lookup table address includes the first a bit sequence and the second bit sequence;
  • a second lookup table configured to search for a second DPD coefficient according to the second table lookup address formed by the first bit sequence and the second bit sequence; wherein, according to the order of the bits from high to low, the The second lookup table address includes the first bit sequence and the second bit sequence;
  • a third lookup table specifically configured to search for a third DPD coefficient according to the third table lookup sequence formed by the third bit sequence and the fourth bit sequence; wherein, according to the order of the bits from high to low, the The triple lookup table address includes the third bit sequence and the fourth bit sequence;
  • a fourth lookup table specifically configured to search for a fourth DPD coefficient according to the fourth look-up table formed by the third bit sequence and the fourth bit sequence; wherein, according to the order of the bits from high to low, the The four lookup table address includes the third bit sequence and the fourth bit sequence.
  • the intercepting unit is further included; the intercepting unit is configured to:
  • the intercepting unit is specifically configured to:
  • a first switch and a second switch are respectively disposed at an input end of the first frequency band signal and an input end of the second frequency band signal; the first switch selectively connects the first contact and a second contact, the second switch selectively connecting the third contact and the fourth contact;
  • the first frequency band signal When the first switch is connected to the first contact, the first frequency band signal is input to a single frequency band lookup table of a first frequency band; when the first switch is connected to a second contact, the first frequency band signal Input to the first address translation table and the second address translation table;
  • the second frequency band signal When the second switch is connected to the third contact, the second frequency band signal is input to a single frequency band lookup table of the second frequency band; when the second switch is connected to the fourth contact, the second frequency band signal It is input to the third address conversion table and the fourth address conversion table.
  • control module is configured to:
  • the input signal is a single-band signal of the first frequency band, controlling the first switch to connect the first contact;
  • the first to fourth address translation tables include a correspondence between the bit sequence of the first length and the bit sequence of the second length, where:
  • the value range of the bit sequence of the first length is divided into first to Eth sub-ranges of equal size, and the range of values of the bit sequence of the second length is divided into first to Eth of unequal sizes a sub-range; the j-th sub-range of the value range of the bit sequence of the first length is in one-to-one correspondence with the j-th sub-range of the value range of the bit sequence of the second length, and the plurality of bits in the former
  • the sequence corresponds to a bit sequence in the latter, E is an integer greater than 1, 1 ⁇ j ⁇ E;
  • the range of values of the bit sequence of the first length is divided into first to Eth sub-ranges of different sizes, and the range of values of the bit sequence of the second length is divided into first to the first An E sub-range; the j-th sub-range of the value range of the bit sequence of the first length is in one-to-one correspondence with the j-th sub-range of the value range of the bit sequence of the second length, and the plurality of the former
  • E is an integer greater than 1, 1 ⁇ j ⁇ E.
  • E 3;
  • the second sub-range is the smallest
  • the second sub-range is the largest.
  • each of the first to Nth lookup tables includes a maximum of 64 ⁇ 64 DPD coefficients, and the second length is 6 bits, and the first to Nth lookup tables obtained by the combination are both It is 12 bits.
  • the first frequency band is an F frequency band
  • the second frequency band is an A frequency band
  • the first frequency band is the A frequency band
  • the second frequency band is the F frequency band.
  • the first to the fourth address conversion table respectively obtain a bit sequence with a smaller number of bits according to the bit sequence corresponding to the amplitude value of the signal of the different frequency band; the first to the Nth lookup tables are respectively according to the first to fourth address conversion tables.
  • the DPD coefficient combining module Combining two bit sequences in the obtained bit sequence to obtain first to Nth lookup table addresses, searching first to Nth DPD coefficients according to the first to Nth lookup table addresses; the DPD coefficient combining module will be the first
  • the processing to the Nth DPD coefficient obtains one DPD coefficient, thereby enabling the DPD processing unit to perform DPD processing on the signal of the first frequency band according to the DPD coefficient processed by the DPD coefficient processing module.
  • the embodiment of the present invention obtains N search addresses according to the four address translation tables, thereby obtaining N DPD coefficients in the lookup table according to the N search addresses, and according to the N DPDs.
  • the coefficients obtain the final DPD coefficients for processing the signals, thereby providing a lookup address generation scheme for the multi-band DPD system, thereby implementing multi-band DPD processing.
  • FIG. 1 is a schematic structural diagram of a DPD system according to an embodiment of the present invention.
  • 2a-2b are schematic diagrams showing the construction of a multi-band lookup table according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram showing the principle design of the amplitude of non-uniform quantization according to an embodiment of the present invention
  • 4a-4b are schematic diagrams showing storage locations corresponding to input digital amplitudes of F-band and A-band according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of a L-bit address 0-64 corresponding to an L-band LUT AMP (0 to 2048) according to an embodiment of the present invention
  • FIG. 6 is a schematic diagram of a lookup address obtained according to an output of an address translation table according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of DPD processing when the F-band and A-band memory depths are 1 in the embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of DPD processing when the F-band and A-band memory depths are 2 in the embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of another DPD system according to an embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a DPD system according to an embodiment of the present invention.
  • the system includes: a table lookup unit 101 and a DPD processing unit 102.
  • a first address conversion table configured to obtain a first bit sequence of a second length according to a bit sequence of a first length corresponding to an amplitude value of the first path signal of the first frequency band, where the first length is greater than the second length;
  • a second address conversion table configured to use a bit sequence of a first length corresponding to an amplitude value of the first path signal of the second frequency band Column, obtaining a corresponding second bit sequence of the second length;
  • a third address conversion table configured to obtain a third bit sequence corresponding to the second length according to the bit sequence of the first length corresponding to the amplitude value of the second path signal of the first frequency band, and the second path of the first frequency band The signal is obtained after delaying the first signal of the first frequency band;
  • a fourth address conversion table configured to obtain a fourth bit sequence of the second length according to the bit sequence of the first length corresponding to the amplitude value of the second path signal of the second frequency band, and the second path of the second frequency band The signal is obtained after delaying the first signal of the second frequency band.
  • the ith lookup table in the first to the Nth lookup table is configured to combine the bit sequence of the second length corresponding to one channel of the first frequency band and the bit sequence of the second length corresponding to one channel of the second frequency band.
  • the i-th lookup table address searching for the ith DPD coefficient according to the i-th lookup table address, 1 ⁇ i ⁇ N;
  • a DPD coefficient combining module configured to process the first to Nth DPD coefficients to obtain one DPD coefficient
  • the DPD processing unit 102 is configured to perform DPD processing on the signal in the first frequency band according to the DPD coefficient processed by the DPD coefficient processing module.
  • the N address search table obtains N search addresses according to the four address translation tables
  • the N DPD coefficients in the lookup table are obtained according to the N search addresses
  • the final DPD coefficients are obtained according to the N DPD coefficients. Processing, thereby providing a lookup address generation scheme for the multi-band DPD system, thereby implementing multi-band DPD processing.
  • the first frequency band and the second frequency band respectively represent two different frequency bands.
  • the first frequency band is the F frequency band
  • the second frequency band is the A frequency band
  • the first frequency band is the A frequency band
  • the second frequency band is the F frequency band.
  • the embodiments of the present invention do not limit this.
  • the following is an example in which the first frequency band is the F frequency band and the second frequency band is the A frequency band.
  • 2a-2b are schematic diagrams showing the construction of a multi-band lookup table according to an embodiment of the present invention.
  • the F-band signal and the A-band signal have an amplitude level of 64 in the entire dynamic range.
  • F_LUT represents a lookup table of the F-band
  • A_LUT represents a lookup table of the A-band
  • F_LUT is obtained by performing DPD training on the signal of the F-band
  • the A_LUT is DPD based on the signal of the A-band. Trained. Since the F-band signal and the A-band signal have an amplitude level of 64 over the entire dynamic range, both F_LUT and A_LUT contain 64 DPD coefficients.
  • the first model and the second model are used to process the DPD coefficients in the F_LUT and the A_LUT, respectively, to obtain FA_LUT_1 and FA_LUT_2.
  • the first model and the second model are models in which there is no cross term.
  • the DPD coefficients numbered 0 in the A_LUT are respectively calculated with the DPD coefficients numbered from 0 to 63 in the F_LUT, and the DPD coefficients numbered from 0 to 63 in the FA_LUT_1 are obtained. And so on, you can get the DPD coefficient from FA_LUT_1 numbered 64 to number 4095. Similarly, as shown in FIG. 2b, DPD coefficients numbered from 0 to 4095 in FA_LUT_2 can be obtained.
  • the first model can be:
  • n n 1 * 64 + n 2 ;
  • LUT (n, m) is the operation result of the DPD coefficient in the F_LUT and the DPD coefficient in the A_LUT;
  • the second model can be:
  • R represents the largest nonlinear order
  • p n 3 * 64 + n 4 ;
  • z 2_LUT (p, q) is the operation result of the DPD coefficient in the F_LUT and the DPD coefficient in the A_LUT;
  • the DPD coefficients in the F_LUT and the A_LUT are processed using the first model, the second model, the third model, and the fourth model, respectively, to obtain FA_LUT_1, FA_LUT_2, FA_LUT_3, and FA_LUT_4.
  • the first model and the second model are models without cross terms
  • the third model and the fourth model are models without cross terms.
  • the implementation principle is the same as that of the FA_LUT when the memory depth is 1, and will not be described here.
  • the first model, the second model, the third model, and the fourth model are used to process the DPD coefficients in the A_LUT and the F_LUT, respectively, to obtain AF_LUT_1, AF_LUT_2, AF_LUT_3, and AF_LUT_4.
  • the first to fourth address conversion tables in the embodiment of the present invention may be four identical address conversion tables, wherein the amplitude values of the signals of the first length of the input of the first to fourth address conversion tables are all 11 bits. Obtaining a corresponding second length of the first bit sequence, the second bit sequence, the third bit sequence, and the fourth bit sequence are all 6 bits, and further according to the first bit sequence, the second bit sequence, the third bit sequence, and The two bit sequences in the fourth bit sequence are combined to obtain that the first to N-th lookup table addresses have 12 bits in length, thereby being able to match 4096 results in the first through Nth lookup tables.
  • the following describes how the input signal is converted to a 6-bit output by the address translation table.
  • the embodiment of the present invention is that the bit sequence of the amplitude value of the first channel of the first frequency band, the second channel signal of the first frequency band, the first channel signal of the second frequency band, and the second channel signal of the second frequency band is 15 bits.
  • the first path signal of the first frequency band, the second path signal of the first frequency band, the first path signal of the second frequency band, and the second The bit sequence of the amplitude value of the second signal of the frequency band is truncated to obtain the first path signal of the first frequency band, the second path signal of the first frequency band, the first path signal of the second frequency band, and the second frequency band
  • a bit sequence of the first length corresponding to the amplitude value of the second path signal is 15 bits.
  • the intercepting unit respectively intercepts the first path signal of the first frequency band, the second path signal of the first frequency band, the first path signal of the second frequency band, and the amplitude value of the second path signal of the second frequency band.
  • the highest 1 bit and the lowest 3 bits of the bit sequence obtain the first path signal of the first frequency band, the second path signal of the first frequency band, the first path signal of the second frequency band, and the second path signal of the second frequency band.
  • the amplitude value corresponds to a bit sequence of a first length; the bit sequence of the first length is 11 bits.
  • Embodiments of the present invention employ a non-uniform quantization method.
  • the value range of the bit sequence of the first length is divided into first to Eth sub-ranges of equal size, and the value range of the bit sequence of the second length is divided into the first of different sizes Up to the Eth sub-range;
  • the j-th sub-range of the value range of the bit sequence of the first length corresponds to the j-th sub-range of the value range of the bit sequence of the second length, and the former a plurality of bit sequences corresponding to one of the latter, E being an integer greater than 1, 1 ⁇ j ⁇ E;
  • the range of values of the bit sequence of the first length is divided into first to Eth sub-ranges of different sizes, and the range of values of the bit sequence of the second length is divided into first to the first An E sub-range; the j-th sub-range of the value range of the bit sequence of the first length is in one-to-one correspondence with the j-th sub-range of the value range of the bit sequence of the second length, and the plurality of the former
  • E is an integer greater than 1, 1 ⁇ j ⁇ E.
  • the Peak Average Rectified (PAR) of the signal correction generally reaches 7 dBc or more, and the mean value is above 5000.
  • the quantization is performed by 6 bits, and the quantization precision needs to be emphasized.
  • a more detailed distribution method is adopted for the amplitude components of some sensitive distributions, and a method of increasing the granularity of the quantization precision is adopted for the general signal.
  • the large signal is the main compression part of the power amplifier. For this reason, the quantization degree of the large signal also needs to be more accurate, so the large signal also needs to improve the quantization precision.
  • the "small signal large signal quantization refinement principle” take the minimum signal 0.1%, accounting for 25% of the amplitude distribution probability, taking the maximum signal 0.1%, accounting for 25% of the amplitude distribution probability, taking the intermediate signal (80%) Up to 50% of the probability of amplitude distribution.
  • the number of distributions between the two is 1638. These 6000 to 10000 are set using 16 (25%) amplitude levels.
  • Figure 3 shows the schematic diagram of the amplitude principle design of non-uniform quantization. The maximum amplitude of the input signal is related to the physical layer scaling and the signal PAR.
  • the foregoing division manners in the embodiments of the present invention are all exemplary manners.
  • the quantization refinement in the compression process of the large signal and the small signal can be realized, and the quantization of the intermediate signal in the compression process is more refined.
  • the division of the low-effect effect can be adopted.
  • the division of the bit sequence of the first length and the range of the bit sequence of the second length are all divided in a non-uniform manner.
  • the amplitude value of the larger range of intermediate signals corresponds to the value of the bit sequence of the second length of the smaller range.
  • the embodiments of the present invention do not limit this.
  • the non-uniform quantization provided by the embodiment of the present invention is especially suitable for a multi-band DPD system.
  • the non-uniform quantization device can further reflect the power amplifier characteristics, and the DPD test performance is relatively uniform and the ACPR can be effectively improved.
  • Figure 4a-4b is a schematic diagram of the storage location corresponding to the input digital amplitude of the F-band and the A-band.
  • the small signal corresponds to an amplitude level table every 52 amplitudes
  • the intermediate signal is every 461 amplitudes.
  • the large signal corresponds to an amplitude level table every 54 amplitudes.
  • 16384 signals are input, and the corresponding amplitude level table output is 64.
  • the amplitude of each input signal is found in the nearest amplitude in the amplitude level table, and its index n1/n2: 0 to 63 is found.
  • the training sequence amplitude (the maximum length of the training sequence is 15bit, after the minimum of 3bit, the maximum amplitude does not exceed 2048) and the comparison of the values of the 64 amplitude scale tables.
  • the values of the 64 amplitude level tables are compared in turn, and the closest value is taken, and the index is taken.
  • the F-band LUT AMP (0 to 2048) corresponds to the LUT address 0 to 64, wherein AMP is Abbreviation for amplitude. .
  • the F-band cuts off the lowest 3-bit input signal to get the LUT AMP.
  • the maximum amplitude of the LUT AMP is 995.
  • the default LUT equal to 64 address is selected between 995 and 2048, which corresponds to the maximum output 64 of the LUT table address.
  • the A-band cuts off the lowest 3-bit input signal and obtains the LUT AMP.
  • the maximum 685 corresponds to 64.
  • the default 685 to 2048 selects the address with the LUT equal to 64, which corresponds to the LUT table address.
  • the maximum output is 64, which is 6 bits.
  • the 6-bit output corresponding to the 6-bit and A-band input signal amplitude corresponding to the output of the F-band input signal amplitude is obtained.
  • the schematic diagram of the search address obtained according to the output of the address conversion table combines the obtained 6-bit output of the F-band input signal amplitude with the 6-bit output corresponding to the A-band input signal amplitude to obtain a 12-bit output, that is, 0 to 4096.
  • M is a memory depth
  • k is a nonlinear factor
  • l is a cross time term
  • L is a maximum time cross term in the channel
  • Q represents a nonlinear order
  • x 1 is an input signal of the first channel
  • y 1 (n) is the output signal of the first channel
  • c is the predistortion parameter
  • n is the sampling time.
  • M is a memory depth
  • k is a nonlinear factor
  • l is a cross time term
  • L is a maximum time cross term in the channel
  • Q represents a nonlinear order
  • x 2 is an input signal of the second channel
  • y 2 (n) is the output signal of the second channel
  • c is the predistortion parameter
  • n is the sampling time.
  • FIG. 7 is a schematic diagram of the DPD processing when the F-band and the A-band memory depth are 1, and the architecture includes:
  • address translation tables namely address translation table 1, address translation table 2, address translation table 3 and address translation table 4;
  • FA_LUT_1 is obtained by processing DPD coefficients in F_LUT and A_LUT based on the first model
  • FA_LUT_2 is obtained by processing DPD coefficients in F_LUT and A_LUT based on the second model.
  • the following describes the processing of the F-band as an example.
  • the processing of the A-band is similar to the F-band.
  • Y1_D represents an F-band signal
  • Y1_D' is a signal after Y1_D delay processing
  • Y2_D represents the A-band signal
  • Y2_D' is the signal after the Y2_D delay processing.
  • the lookup address of FA-LUT1 includes a first bit sequence and the second bit sequence in order of high to low bits.
  • the 6-bit sequence is used as the upper 6-bit address of the search address of A-LUT1;
  • the 6-bit sequence is used as the lower 6-bit address of the A-LUT1 search address;
  • the lookup address of the FA-LUT 2 includes a first bit sequence and the second bit sequence in order of high to low bits.
  • FA-LUT1 and FA-LUT2 are respectively checked to obtain two DPD coefficients, and two DPD coefficients are processed to obtain a DPD coefficient. DPD processing is performed on the F-band signal.
  • Figure 8 is a schematic diagram of the DPD processing architecture when the F-band and A-band memory depth is 2.
  • the architecture shows the D-band processing of the F-band when the F-band and A-band memory depth is 2, where the cross-term A channel is advanced 1- Taps.
  • the architecture includes:
  • address translation tables namely address translation table 1, address translation table 2, address translation table 3 and address translation table 4;
  • FA_LUT_1, FA_LUT_2, FA_LUT_3, FA_LUT_4 Four lookup tables, namely FA_LUT_1, FA_LUT_2, FA_LUT_3, FA_LUT_4; wherein FA_LUT_1 and FA_LUT_2 are F-band memory item lookup tables, and FA_LUT_3 and FA_LUT_4 are F-band cross-term lookup tables.
  • FA_LUT_1 is obtained by processing the DPD coefficients in the F_LUT and the A_LUT based on the first model
  • FA_LUT_2 is obtained by processing the DPD coefficients in the F_LUT and the A_LUT based on the second model
  • FA_LUT_3 is based on the third model pair in the F_LUT and the A_LUT
  • the DPD coefficient is processed
  • FA_LUT_4 is based on
  • the fourth model is obtained by processing the DPD coefficients in the F_LUT and the A_LUT.
  • the following describes the processing of the F-band as an example.
  • the processing of the A-band is similar to the F-band.
  • Y1_D represents an F-band signal
  • Y1_D' is a signal after Y1_D delay processing
  • Y2_D represents the A-band signal
  • Y2_D' is the signal after the Y2_D delay processing.
  • the above high 6 bits and lower 6 bits are spliced into a 12-bit address as a lookup address of FA_LUT_1.
  • the above high 6 bits and lower 6 bits are spliced into a 12-bit address as a lookup address of FA_LUT_3.
  • the above high 6 bits and lower 6 bits are spliced into a 12-bit address as a lookup address of FA_LUT_2.
  • the search address of FA_LUT_1 the search address of FA_LUT_2, the search address of FA_LUT_3, and the search address of FA_LUT_4, the FA_LUT_1, FA_LUT_2, FA_LUT_3, and FA_LUT_4 are respectively checked to obtain four DPD coefficients, and four DPD coefficients are processed.
  • a DPD coefficient is obtained for the D-band signal for DPD processing.
  • the structure of the DPD system provided in FIG. 1 in the embodiment of the present invention is applicable not only to multi-band DPD processing but also to single-band DPD processing, and at the input end of the first frequency band signal of the look-up unit.
  • the input ends of the second frequency band signals are respectively provided with a first switch and a second switch.
  • FIG. 9 is a schematic structural diagram of another DPD system according to an embodiment of the present invention.
  • the first switch selectively connects the contact 1 and the contact 2, the second switch selectively connecting the contact 3 and the contact 4.
  • the first switch When the first switch is connected to the contact 1, the first frequency band signal is input to the single frequency band lookup table in which the first frequency band signal is input to the first frequency band; when the first switch is connected to the contact 2 The first frequency band signal is input to the first address conversion table and the second address conversion table; when the second switch is connected to the contact 3, the second frequency band signal is input to the second a single band lookup table of the frequency band; when the second switch is connected to the contact 4, the second frequency band signal is input to the third address conversion table and the fourth address conversion table.
  • the first switch is connected to the contact 1 and the second switch is connected to the contact 3, so that in the case of the single-band signal, the processing of the address conversion table is not required, but directly According to the amplitude value of the signal, the single-band lookup table of the first frequency band or the single-band lookup table of the second frequency band is searched to obtain the DPD coefficient, thereby completing the DPD processing; if the signal to be processed is the multi-band signal, the first switch is performed.
  • the contact 2 is connected and the second switch is connected to the contact 4, so that in the case of the multi-band signal, the processing of the address conversion table is performed, and after the corresponding search address is generated, the DPD coefficient is obtained according to the search address, thereby completing the DPD processing.
  • the first-level crossover project of the 2D-DPD is added, and only one level of the LUT table needs to be added, and the multiplier is not needed, which greatly saves the number of multipliers.
  • To increase the level 1 cross-project only one level of LUT table needs to be added, and no address conversion table is needed, which lays a foundation for flexible expansion of 2D-DPD.
  • the first to the fourth address conversion table respectively obtain a bit sequence with a smaller number of bits according to the bit sequence corresponding to the amplitude value of the signal of the different frequency band; the first to the Nth lookup tables are respectively according to the first to fourth address conversion tables.
  • the DPD coefficient combining module Combining two bit sequences in the obtained bit sequence to obtain first to Nth lookup table addresses, searching first to Nth DPD coefficients according to the first to Nth lookup table addresses; the DPD coefficient combining module will be the first
  • the processing to the Nth DPD coefficient obtains one DPD coefficient, thereby enabling the DPD processing unit to perform DPD processing on the signal of the first frequency band according to the DPD coefficient processed by the DPD coefficient processing module. Since the N address search table obtains N search addresses according to the four address translation tables, the N DPD coefficients in the lookup table are obtained according to the N search addresses, and the final DPD coefficients are obtained according to the N DPD coefficients. Processing, thereby providing a lookup address generation scheme for the multi-band DPD system, thereby implementing multi-band DPD processing.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

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Abstract

公开了一种DPD系统。本发明实施例提供的DPD系统包括查表单元和DPD处理单元，第一至第N查找表分别根据第一至第四地址转换表得到的比特序列中的两个比特序列合并得到第一至第N查表地址，根据第一至第N查表地址查找第一至第N DPD系数，并通过DPD系数合并模块得到一个DPD系数，从而使DPD处理单元能够根据该DPD系数对第一频段的信号进行DPD处理。本发明实施例根据四个地址转换表得到查找地址，并根据查找地址获得查找表中的DPD系数，得到最终的DPD系数，用于对信号进行处理，从而针对多频段DPD系统提供了一种查找地址的生成方案，实现了多频段的DPD处理。

Description

一种DPD系统
本申请要求在2015年06月23日提交中国专利局、申请号为201510350367.0、发明名称为“一种DPD系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及通信技术领域，尤其涉及一种DPD系统。
背景技术
现有数字预失真(Digital PreDistortion，DPD)技术中，由于DPD的查找表(Look-Up-Table，LUT)表信息的分布采用均匀量化分布，因此LUT表地址的查找一般都采用均匀量化技术。
对于DPD系统，如果是基于记忆多项式模型，对信号的预失真处理的数学模型为：
Figure PCTCN2016086030-appb-000001
公式(1)中，LUTm(|x(n-m)|)的表达式为：
Figure PCTCN2016086030-appb-000002
公式(1)中，rn,m＝|x(n-m)|表示输入信号的幅度，Q(·)是量化因子；公式(2)中，wm,q,m＝1...M,q＝1...Q是DPD自适应滤波计算得到的DPD系数。
由此可知，LUT表的输入地址是根据输入信号量化后的幅度Q(rn,m)来决定的，即，根据输入信号幅度|x(n-m)|为索引查找LUT表得到DPD系数，该DPD系数在公式(1)中表示为LUTm(|x(n-m)|)。相应地，在进行DPD系数更新时，根据输入信号幅度|x(n-m)|为索引存入DPD系数。
然而，现有技术一般适应于单频段DPD系统，单频段系统针对某一个频段进行设计，单频段的LUT表地址是直接对信号幅度截位得到，不适合用于多频段DPD系统。
发明内容
本发明实施例提供一种DPD系统，用以通过生成适用于多频段的查找表地址，进而实现多频段的DPD处理。
本发明实施例提供的一种DPD系统，包括：查表单元和DPD处理单元，所述查表单元包括：第一至第四地址转换表、第一至第N查找表以及DPD系数合并模块；其中，第一至第N查找表为多频段查找表，N＝2M，M为记忆深度，M为正整数；
第一地址转换表，用于根据第一频段的第一路信号的幅度值对应的第一长度的比特序列得到对应的第二长度的第一比特序列，其中，所述第一长度大于第二长度；第二地址转换表，用于根据第二频段的第一路信号的幅度值对应的第一长度的比特序列，得到对应的第二长度的第二比特序列；
第三地址转换表，用于根据第一频段的第二路信号的幅度值对应的第一长度的比特序列，得到对应的第二长度的第三比特序列，所述第一频段的第二路信号是对所述第一频段的第一路信号延时后得到的；
第四地址转换表，用于根据第二频段的第二路信号的幅度值对应的第一长度的比特序列，得到对应的第二长度的第四比特序列，所述第二频段的第二路信号是对所述第二频段的第一路信号延时后得到的；
所述第一至第N查找表中的第i查找表，用于根据第一频段的一路信号对应的第二长度的比特序列以及第二频段的一路信号对应的第二长度的比特序列合并得到第i查表地址，根据所述第i查表地址查找第i DPD系数，1≤i≤N；
DPD系数合并模块，用于将所述第一至第N DPD系数处理得到一个DPD系数；
DPD处理单元，用于根据所述DPD系数处理模块处理得到的DPD系数对所述第一频段的信号进行DPD处理。
较佳地，M＝1；
第一查找表，具体用于根据所述第一比特序列和所述第二比特序列构成的第一查表地址查找第一DPD系数；其中，按照比特位从高到低的顺序，所述第一查表地址包括第一比特序列和所述第二比特序列；
第二查找表，具体用于根据所述第三比特序列和所述第四比特序列构成的第二查表地址查找第二DPD系数；其中，按照比特位从高到低的顺序，所述第二查表地址包括第三比特序列和所述第四比特序列。
较佳地，M＝2；
第一查找表，具体用于根据所述第一比特序列和所述第二比特序列构成的第一查表地址查找第一DPD系数；其中，按照比特位从高到低的顺序，所述第一查表地址包括第一 比特序列和所述第二比特序列；
第二查找表，具体用于根据所述第一比特序列和所述第二比特序列构成的第二查表地址查找第二DPD系数；其中，按照比特位从高到低的顺序，所述第二查表地址包括所述第一比特序列和所述第二比特序列；
第三查找表，具体用于根据所述第三比特序列和所述第四比特序列构成的第三查表地址查找第三DPD系数；其中，按照比特位从高到低的顺序，所述第三查表地址包括所述第三比特序列和所述第四比特序列；
第四查找表，具体用于根据所述第三比特序列和所述第四比特序列构成的第四查表地址查找第四DPD系数；其中，按照比特位从高到低的顺序，所述第四查表地址包括所述第三比特序列和所述第四比特序列。
较佳地，还包括截位单元；所述截位单元用于：
对所述第一频段的第一路信号、第一频段的第二路信号、第二频段的第一路信号以及第二频段的第二路信号的幅度值的比特序列进行截位，得到所述第一频段的第一路信号、第一频段的第二路信号、第二频段的第一路信号以及第二频段的第二路信号的幅度值对应的第一长度的比特序列。
较佳地，所述截位单元具体用于：
分别截去所述第一频段的第一路信号、第一频段的第二路信号、第二频段的第一路信号以及第二频段的第二路信号的幅度值的比特序列的最高1比特和最低的3比特，得到所述第一频段的第一路信号、第一频段的第二路信号、第二频段的第一路信号以及第二频段的第二路信号的幅度值对应的第一长度的比特序列；所述第一长度的比特序列为11比特。
较佳地，在所述查表单元的第一频段信号的输入端和第二频段信号的输入端分别设置有第一开关和第二开关；所述第一开关选择性连接第一触点和第二触点，所述第二开关选择性连接第三触点和第四触点；
当所述第一开关连接所述第一触点，所述第一频段信号被输入至第一频段的单频段查找表；当所述第一开关连接第二触点，所述第一频段信号被输入至所述第一地址转换表和所述第二地址转换表；
当所述第二开关连接所述第三触点，所述第二频段信号被输入至第二频段的单频段查找表；当所述第二开关连接第四触点，所述第二频段信号被输入至所述第三地址转换表和所述第四地址转换表。
较佳地，所述控制模块用于：
若确定所述输入信号为第一频段的单频段信号，则控制所述第一开关连接所述第一触点；
若确定所述输入信号为第二频段的单频段信号，则控制所述第二开关连接所述第三触 点；
若确定所述输入信号为多频段信号，则控制所述第一开关连接所述第二触点，且所述第二开关连接所述第四触点。
较佳地，所述第一至第四地址转换表中包括所述第一长度的比特序列与第二长度的比特序列的对应关系，其中：
所述第一长度的比特序列的取值范围被划分为大小相等的第一至第E子范围，所述第二长度的比特序列的取值范围被划分为大小不等的第一至第E子范围；所述第一长度的比特序列的取值范围的第j子范围与所述第二长度的比特序列的取值范围的第j子范围一一对应，且，前者中的多个比特序列与后者中的一个比特序列相对应，E为大于1的整数，1≤j≤E；或者
所述第一长度的比特序列的取值范围被划分为大小不等的第一至第E子范围，将所述第二长度的比特序列的取值范围被划分为大小相等的第一至第E子范围；所述第一长度的比特序列的取值范围的第j子范围与所述第二长度的比特序列的取值范围的第j子范围一一对应，且，前者中的多个比特序列与后者中的一个比特序列相对应，E为大于1的整数，1≤j≤E。
较佳地，E＝3；
若所述第二长度的比特序列的取值范围按照比特序列取值从小到大的顺序被划分为大小相等的第一至第三子范围，则第二子范围最小；或者
若所述第一长度的比特序列的取值范围按照比特序列取值从小到大的顺序被划分为第一至第三子范围，则第二子范围最大。
较佳地，所述第一至第N查找表中的每个查找表中最多包含64×64个DPD系数，所述第二长度为6比特，合并得到的第一至第N查表地址均为12比特。
较佳地，所述第一频段为F频段，第二频段为A频段；或者，
所述第一频段为A频段，第二频段为F频段。
本发明实施例提供的DPD系统包括查表单元和DPD处理单元，所述查表单元包括：第一至第四地址转换表、第一至第N查找表以及DPD系数合并模块；其中，N＝2M，M为记忆深度。其中，第一至第四地址转换表分别根据不同频段信号的幅度值所对应的比特序列得到比特位数更少的比特序列；第一至第N查找表分别根据第一至第四地址转换表得到的比特序列中的两个比特序列合并得到第一至第N查表地址，根据所述第一至第N查表地址查找第一至第N DPD系数；DPD系数合并模块将所述第一至第N DPD系数处理得到一个DPD系数，从而使DPD处理单元能够根据所述DPD系数处理模块处理得到的DPD系数对所述第一频段的信号进行DPD处理。由于本发明实施例根据四个地址转换表得到N个查找地址，从而根据N个查找地址获得查找表中的N个DPD系数，并根据N个DPD 系数得到最终的DPD系数，用于对信号进行处理，从而针对多频段DPD系统提供了一种查找地址的生成方案，进而实现了多频段的DPD处理。
附图说明
图1为本发明实施例提供的一种DPD系统的结构示意图；
图2a-图2b为本发明实施例中多频段查找表的构建示意图；
图3为本发明实施例非均匀量化的幅度原理设计示意图；
图4a-图4b为本发明实施例F频段和A频段输入数值幅度对应的存储位置示意图；
图5所示为本发明实施例F频段LUT AMP(0～2048)对应LUT地址0～64示意图；
图6所示为本发明实施例根据地址转换表的输出得到的查找地址示意图；
图7为本发明实施例F频段和A频段记忆深度为1时DPD处理的架构示意图；
图8为本发明实施例F频段和A频段记忆深度为2时DPD处理的架构示意图；
图9为本发明实施例提供的另一种DPD系统的结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
为了使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施例作进一步地详细描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
图1为本发明实施例提供的一种DPD系统的结构示意图，该系统包括：查表单元101和DPD处理单元102，所述查表单元101包括：第一至第四地址转换表、第一至第N查找表以及DPD系数合并模块；其中，第一至第N查找表为多频段查找表，N＝2M，M为记忆深度，取值为正整数。
下面分别描述每个模块的功能：
第一地址转换表，用于根据第一频段的第一路信号的幅度值对应的第一长度的比特序列得到对应的第二长度的第一比特序列，其中，所述第一长度大于第二长度；
第二地址转换表，用于根据第二频段的第一路信号的幅度值对应的第一长度的比特序 列，得到对应的第二长度的第二比特序列；
第三地址转换表，用于根据第一频段的第二路信号的幅度值对应的第一长度的比特序列，得到对应的第二长度的第三比特序列，所述第一频段的第二路信号是对所述第一频段的第一路信号延时后得到的；
第四地址转换表，用于根据第二频段的第二路信号的幅度值对应的第一长度的比特序列，得到对应的第二长度的第四比特序列，所述第二频段的第二路信号是对所述第二频段的第一路信号延时后得到的。
所述第一至第N查找表中的第i查找表，用于根据第一频段的一路信号对应的第二长度的比特序列以及第二频段的一路信号对应的第二长度的比特序列合并得到第i查表地址，根据所述第i查表地址查找第i DPD系数，1≤i≤N；
DPD系数合并模块，用于将所述第一至第N DPD系数处理得到一个DPD系数；
DPD处理单元102，用于根据所述DPD系数处理模块处理得到的DPD系数对所述第一频段的信号进行DPD处理。
由于本发明实施例根据四个地址转换表得到N个查找地址，从而根据N个查找地址获得查找表中的N个DPD系数，并根据N个DPD系数得到最终的DPD系数，用于对信号进行处理，从而针对多频段DPD系统提供了一种查找地址的生成方案，进而实现了多频段的DPD处理。
本发明实施例中第一频段和第二频段分别表示两种不同的频段。比如，第一频段为F频段，第二频段为A频段；或者，第一频段为A频段，第二频段为F频段。本发明实施例对此不做限制。
下面第一频段为F频段、第二频段为A频段为例来介绍。
如图2a-图2b所示，为本发明实施例中多频段查找表的构建示意图。
本发明实施例中，F频段信号和A频段信号在整个动态范围内的幅度等级为64。如图2a和图2b中所示，F_LUT表示F频段的查找表，A_LUT表示A频段的查找表，F_LUT是根据对F频段的信号进行DPD训练得到的，A_LUT是根据对A频段的信号进行DPD训练得到的。由于F频段信号和A频段信号在整个动态范围内的幅度等级为64，因此F_LUT和A_LUT中均包含64个DPD系数。当记忆深度为1时，使用第一模型和第二模型分别对F_LUT和A_LUT中的DPD系数进行处理，得到FA_LUT_1和FA_LUT_2。其中，第一模型和第二模型均为不存在交叉项的模型。
如图2a所示，根据第一模型，将A_LUT中编号为0的DPD系数分别与F_LUT中编号为0到编号为63的DPD系数进行运算，得到FA_LUT_1中编号为0到编号为63的DPD系数，以此类推，可得到FA_LUT_1中编号为64到编号为4095的DPD系数。同理，如图2b所示，可得到FA_LUT_2中编号为0到编号为4095的DPD系数。
具体地，第一模型可以为：
Figure PCTCN2016086030-appb-000003
其中，Q表示最大非线性阶数，n＝n1*64+n2；
z1,LUT(n,m)为F_LUT中的DPD系数和A_LUT中的DPD系数的运算结果；
|y1,LUT(n1)|为F_LUT中编号为n1的信号幅度；
|y2,LUT(n2)|为A_LUT中编号为n2的信号幅度。
第二模型可以为：
Figure PCTCN2016086030-appb-000004
其中，R表示最大非线性阶数，p＝n3*64+n4；
z2_LUT(p,q)为F_LUT中的DPD系数和A_LUT中的DPD系数的运算结果；
|y1,LUT(n3)|为F_LUT中编号为n3的信号幅度；
|y2,LUT(n4)|为A_LUT中编号为n4的信号幅度。
当记忆深度为2时，使用第一模型、第二模型、第三模型和第四模型分别对F_LUT和A_LUT中的DPD系数进行处理，得到FA_LUT_1、FA_LUT_2、FA_LUT_3、FA_LUT_4。其中，第一模型和第二模型均为不存在交叉项的模型，第三模型和第四模型均为不存在交叉项的模型。其中，实现原理与记忆深度为1时得到FA_LUT的原理相同，在此不再赘述。
同理，当记忆深度为2时，使用第一模型、第二模型、第三模型和第四模型分别对A_LUT和F_LUT中的DPD系数进行处理，得到AF_LUT_1、AF_LUT_2、AF_LUT_3、AF_LUT_4。
本发明实施例中的第一至第四地址转换表可以为四个相同的地址转换表，其中，第一至第四地址转换表的输入的第一长度的信号的幅度值均为11个比特，得到对应的第二长度的第一比特序列、第二比特序列、第三比特序列和第四比特序列均为6个比特，进而根据第一比特序列、第二比特序列、第三比特序列和第四比特序列中的两个比特序列合并得到第一至第N查表地址的长度均有12个比特，从而能够与第一至第N查找表中的4096个结果相匹配。
下面针对输入信号如何通过地址转换表转换为6bit的输出进行介绍。
由于第一频段的第一路信号、第一频段的第二路信号、第二频段的第一路信号以及第二频段的第二路信号的幅度值的比特序列为15比特，本发明实施例中首先通过截位单元对所述第一频段的第一路信号、第一频段的第二路信号、第二频段的第一路信号以及第二 频段的第二路信号的幅度值的比特序列进行截位，得到所述第一频段的第一路信号、第一频段的第二路信号、第二频段的第一路信号以及第二频段的第二路信号的幅度值对应的第一长度的比特序列。
具体地，截位单元分别截去所述第一频段的第一路信号、第一频段的第二路信号、第二频段的第一路信号以及第二频段的第二路信号的幅度值的比特序列的最高1比特和最低的3比特，得到所述第一频段的第一路信号、第一频段的第二路信号、第二频段的第一路信号以及第二频段的第二路信号的幅度值对应的第一长度的比特序列；所述第一长度的比特序列为11比特。
本发明实施例采用一种非均匀量化方式。
具体地，所述第一长度的比特序列的取值范围被划分为大小相等的第一至第E子范围，所述第二长度的比特序列的取值范围被划分为大小不等的第一至第E子范围；所述第一长度的比特序列的取值范围的第j子范围与所述第二长度的比特序列的取值范围的第j子范围一一对应，且，前者中的多个比特序列与后者中的一个比特序列相对应，E为大于1的整数，1≤j≤E；或者
所述第一长度的比特序列的取值范围被划分为大小不等的第一至第E子范围，将所述第二长度的比特序列的取值范围被划分为大小相等的第一至第E子范围；所述第一长度的比特序列的取值范围的第j子范围与所述第二长度的比特序列的取值范围的第j子范围一一对应，且，前者中的多个比特序列与后者中的一个比特序列相对应，E为大于1的整数，1≤j≤E。
进一步地，对于中频信号来说，信号修正的峰值平均值(Peak Average Rectified，PAR)一般达到7dBc以上，均值在5000以上，此时仅仅通过6bit来量化，量化精度需要有侧重。针对某些敏感分布的幅度分量采用更细致的分布方式，对于一般信号采用增加量化精度颗粒度的方法。
(1)针对小信号，由于小信号的幅度小，此时采用颗粒度大的分布方式使得量化误差增加，所以小信号需要提高量化精度。
(2)大信号是功放的主要压缩部分，为此对大信号的量化程度也需要更精确，所以大信号也需要提高量化精度。
(3)由于小信号和大信号的量化精度提高，所以均值附近的信号需要增大量化的颗粒度。
根据“小信号大信号量化精细化原则”，取最小信号0.1％，占到幅度分布概率的25％，取最大信号0.1％，占到幅度分布概率的25％，取中间信号(80％)占到幅度分布概率的50％。依据这个原则，如果训练序列的长度是16384，信号最大幅度为AMAX＝10000(如果大于10000也按照10000计算)，中间信号最大数值如果采用6000，那么6000到10000 之间分布的数量是1638个。这6000到10000采用16(25％)个幅度等级来设定。中间信号最大数值AMID＝6000，中间信号最小数值AMIN＝1000，那么这个等级的数据通过32(50％)个幅度等级来设定。这0到1000采用16(25％)个幅度等级来设定。如图3所示为非均匀量化的幅度原理设计示意图。输入信号的最大幅度和物理层定标以及信号PAR有关。
针对上述大信号、中间信号以及小信号的情形，本发明实施例中取E＝3；同时为实现非均匀量化，即实现大信号和小信号在压缩过程中的量化精细化较高，而中间信号在压缩过程中的量化精细化较低的效果，本发明实施例中可采用两种方式：
方式一：
将所述第一长度的比特序列的取值范围被划分为大小相等的第一至第三子范围，所述第二长度的比特序列的取值范围被划分为大小不等的第一至第三子范围，且第二子范围最小。
方式二：
将所述第一长度的比特序列的取值范围被划分为大小不等的第一至第三子范围，所述第二长度的比特序列的取值范围被划分为大小相等的第一至第三子范围，且第二子范围最大。本发明实施例中的上述划分方式均为示例性方式，具体过程中凡是能够实现实现大信号和小信号在压缩过程中的量化精细化较高，而中间信号在压缩过程中的量化精细化较低的效果效果的划分方式均可采用，例如，也可以不采用均匀方式划分，即第一长度的比特序列的取值范围和第二长度的比特序列的取值范围均采用非均匀方式划分，且在划分的过程中使得较大范围的中间信号的幅度值对应较小范围的第二长度的比特序列的取值。本发明实施例对此不做限制。
本发明实施例提供的这种非均匀量化尤其适应于多频段DPD系统，采用这种非均匀量化装置，能够更加反映功放特性，DPD的测试性能相对均匀量化ACPR能有效改善。
图4a-图4b为F频段和A频段输入数值幅度对应的存储位置示意图，由图4a-图4b可以看出，小信号每隔52个幅度对应一个幅度等级表，中间信号每隔461个幅度对应一个幅度等级表，大信号每隔54个幅度对应一个幅度等级表。这样输入16384个信号，对应的幅度等级表输出为64个。每一次输入信号的幅度都寻找幅度等级表中最接近的幅度，找到其索引n1/n2:0～63。
下面介绍地址转换表的处理方式。
取训练序列幅度(训练序列最大幅度15bit，截取最低3bit以后，最大幅度不超过2048)和64个幅度等级表的数值比较。依次比较64个幅度等级表的数值，看最接近的那个数值，则取其索引，如图5所示，为F频段LUT AMP(0～2048)对应LUT地址0～64示意图，其中，AMP是幅度(amplitude)的缩写。。F频段截掉最低3bit输入信号后得到LUT AMP，此时 LUT AMP最大幅度是995，此时默认995～2048之间都选择LUT等于64的地址，就对应到了LUT表地址的最大输出64。同理，A频段截掉最低3bit输入信号后得到LUT AMP，此时大幅度是685就对应到了64，此时默认685～2048之间都选择LUT等于64的地址，就对应到了LUT表地址的最大输出64，即输出6bit。
通过上述处理过程后，得到F频段输入信号幅度对应输出的6bit与A频段输入信号幅度对应输出的6bit。如图6所示，为根据地址转换表的输出得到的查找地址示意图，将得到的F频段输入信号幅度对应输出的6bit与A频段输入信号幅度对应输出的6bit进行合并，得到12bit的输出，即0～4096。
如果资源够用，则采用下述有一个延时，则频段F信号的预失真架构如下：
Figure PCTCN2016086030-appb-000005
其中，所述M为记忆深度，k为非线性因子，l为交叉时间项，L为通道内的最大时间交叉项，Q表示非线性阶数，x1为第一通道的输入信号、y1(n)为第一通道的输出信号、c为预失真参数，n为采样时刻。
如果资源够用，则采用下述有一个延时，则频段A信号的预失真架构如下：
Figure PCTCN2016086030-appb-000006
其中，所述M为记忆深度，k为非线性因子，l为交叉时间项，L为通道内的最大时间交叉项，Q表示非线性阶数，x2为第二通道的输入信号、y2(n)为第二通道的输出信号，c为预失真参数，n为采样时刻。
为更清楚地解释本发明，下面分别以双频段记忆深度为1和记忆深度为2的情形进行具体介绍。
(1)在记忆深度为1的情况下，针对于双频段中的DPD处理过程(不存在交叉项)图7为F频段和A频段记忆深度为1时DPD处理的架构示意图，该架构包括：
4个地址转换表，即地址转换表1、地址转换表2、地址转换表3和地址转换表4；
2个查找表，即FA_LUT_1、FA_LUT_2；其中，FA_LUT_1是基于第一模型对F_LUT和A_LUT中的DPD系数进行处理得到的；FA_LUT_2是基于第二模型对F_LUT和A_LUT中的DPD系数进行处理得到的。
在采用该架构的情况下，下面以F频段为例介绍其处理过程，A频段的处理过程与F频段类似。
如图7所示，Y1_D表示F频段信号，Y1_D’是Y1_D延时处理后的信号；
Y2_D表示A频段信号，Y2_D’是Y2_D延时处理后的信号。
对Y1_D取11bit幅度值，根据该11bit幅度值查地址转换表1得到6bit序列，将该6bit序列作为F-LUT1的查找地址的高6比特位；
对Y2_D取11bit幅度值，根据该11bit幅度值查地址转换表1得到6bit序列，将该6bit序列作为F-LUT1的查找地址的低6比特位；
按照比特位从高到低的顺序，FA-LUT1的查找地址包括第一比特序列和所述第二比特序列。
同理：
对Y1_D’取11bit幅度值，根据该11bit幅度值查地址转换表1得到6bit序列将该6bit序列作为A-LUT1的查找地址的高6比特位；
对Y2_D’取11bit幅度值，根据该11bit幅度值查地址转换表1得到6bit序列，将该6bit序列作为A-LUT1的查找地址的低6比特位；
按照比特位从高到低的顺序，FA-LUT2的查找地址包括第一比特序列和所述第二比特序列。
根据上述得到的FA-LUT1的查找地址和FA-LUT2的查找地址，分别查FA-LUT1和FA-LUT2，得到两个DPD系数，并通过对两个DPD系数进行处理，得到一个DPD系数，用于F频段信号进行DPD处理。
(2)在记忆深度为2的情况下，针对于双频段中的DPD处理过程(存在交叉项)
图8为F频段和A频段记忆深度为2时DPD处理的架构示意图，该架构示出了F频段和A频段记忆深度为2时F频段的DPD处理过程，其中，交叉项A通道提前1-taps。
如图8所示，该架构包括：
4个地址转换表，即地址转换表1、地址转换表2、地址转换表3和地址转换表4；
4个查找表，即FA_LUT_1、FA_LUT_2、FA_LUT_3、FA_LUT_4；其中，FA_LUT_1和FA_LUT_2为F频段的记忆项查找表，FA_LUT_3和FA_LUT_4为F频段的交叉项查找表。FA_LUT_1是基于第一模型对F_LUT和A_LUT中的DPD系数进行处理得到的；FA_LUT_2是基于第二模型对F_LUT和A_LUT中的DPD系数进行处理得到的；FA_LUT_3是基于第三模型对F_LUT和A_LUT中的DPD系数进行处理得到的；FA_LUT_4是基于 第四模型对F_LUT和A_LUT中的DPD系数进行处理得到的。
本发明实施例中，查找表的个数N＝2*M，M为记忆深度。
在采用该架构的情况下，下面以F频段为例介绍其处理过程，A频段的处理过程与F频段类似。
如图8中所示，Y1_D表示F频段信号，Y1_D’是Y1_D延时处理后的信号；
Y2_D表示A频段信号，Y2_D’是Y2_D延时处理后的信号。
对Y1_D取11bit幅度值，根据该11bit幅度值查地址转换表1得到6bit序列，将该6bit序列进行一次延时处理后，作为FA_LUT_1的查找地址的高6比特位；
对Y2_D取11bit幅度值，根据该11bit幅度值查地址转换表1得到6bit序列，将该6bit序列进行一次延时处理后，作为FA_LUT_1的查找地址的低6比特位；
将上述高6比特位和低6比特位拼接成12比特地址，作为FA_LUT_1的查找地址。
对Y1_D取11bit幅度值，根据该11bit幅度值查地址转换表1得到6bit序列，将该6bit序列进行一次延时处理后，作为FA_LUT_3的查找地址的高6比特位；
对Y2_D取11bit幅度值，根据该11bit幅度值查地址转换表1得到6bit序列，将该6bit序列作为FA_LUT_3的查找地址的低6比特位；
将上述高6比特位和低6比特位拼接成12比特地址，作为FA_LUT_3的查找地址。
同理：
对Y1_D’取11bit幅度值，根据该11bit幅度值查地址转换表1得到6bit序列，将该6bit序列进行一次延时处理后，作为FA_LUT_2的查找地址的高6比特位；
对Y2_D’取11bit幅度值，根据该11bit幅度值查地址转换表1得到6bit序列，将该6bit序列进行一次延时处理后，作为FA_LUT_2的查找地址的低6比特位；
将上述高6比特位和低6比特位拼接成12比特地址，作为FA_LUT_2的查找地址。
对Y1_D’取11bit幅度值，根据该11bit幅度值查地址转换表1得到6bit序列，将该6bit序列进行一次延时处理后，作为FA_LUT_4的查找地址的高6比特位；
对Y2_D’取11bit幅度值，根据该11bit幅度值查地址转换表1得到6bit序列，将该6bit序列作为FA_LUT_4的查找地址的低6比特位；
将上述高6比特位和低6比特位拼接成12比特地址，作为FA_LUT_4的查找地址。
根据上述得到的FA_LUT_1的查找地址、FA_LUT_2的查找地址、FA_LUT_3的查找地址和FA_LUT_4的查找地址，分别查FA_LUT_1、FA_LUT_2、FA_LUT_3、FA_LUT_4，得到四个DPD系数，并通过对四个DPD系数进行处理，得到一个DPD系数，用于F频段信号进行DPD处理。优选地，为使本发明实施例中图1提供的DPD系统的结构不仅适用多频段的DPD处理，也适用于单频段的DPD处理，在所述查表单元的第一频段信号的输入端和第二频段信号的输入端分别设置有第一开关和第二开关。
图9所示，为本发明实施例提供的另一种DPD系统的结构示意图。所述第一开关选择性连接触点1和触点2，所述第二开关选择性连接触点3和触点4。当所述第一开关连接所述触点1，所述第一频段信号被输入至所述第一频段信号被输入至第一频段的单频段查找表；当所述第一开关连接触点2，所述第一频段信号被输入至所述第一地址转换表和所述第二地址转换表；当所述第二开关连接所述触点3，所述第二频段信号被输入至第二频段的单频段查找表；当所述第二开关连接触点4，所述第二频段信号被输入至所述第三地址转换表和所述第四地址转换表。
具体地，若待处理的信号为单频段信号，则将第一开关连接触点1且第二开关连接触点3，从而使得单频段信号的情况下，无需经过地址转换表的处理，而直接根据信号的幅度值对第一频段的单频段查找表或第二频段的单频段查找表进行查找，得到DPD系数，进而完成DPD处理；若待处理的信号为多频段信号，则将第一开关连接触点2且第二开关连接触点4，从而使得多频段信号的情况下，需经过地址转换表的处理，生成相应的查找地址后，根据查找地址得到DPD系数，进而完成DPD处理。采用本发明实施例所述的方案之后，增加2D-DPD的一级交叉项目，只需要增加一级LUT表，无需增加乘法器，很大的程度上节省了乘法器的数量。增加一级交叉项目，只需要增加一级LUT表，无需增加地址转换表，从而为2D-DPD的灵活扩展奠定了基础。
从上述内容可以看出：
本发明实施例提供的DPD系统包括查表单元和DPD处理单元，所述查表单元包括：第一至第四地址转换表、第一至第N查找表以及DPD系数合并模块；其中，N＝2M，M为记忆深度。其中，第一至第四地址转换表分别根据不同频段信号的幅度值所对应的比特序列得到比特位数更少的比特序列；第一至第N查找表分别根据第一至第四地址转换表得到的比特序列中的两个比特序列合并得到第一至第N查表地址，根据所述第一至第N查表地址查找第一至第N DPD系数；DPD系数合并模块将所述第一至第N DPD系数处理得到一个DPD系数，从而使DPD处理单元能够根据所述DPD系数处理模块处理得到的DPD系数对所述第一频段的信号进行DPD处理。由于本发明实施例根据四个地址转换表得到N个查找地址，从而根据N个查找地址获得查找表中的N个DPD系数，并根据N个DPD系数得到最终的DPD系数，用于对信号进行处理，从而针对多频段DPD系统提供了一种查找地址的生成方案，进而实现了多频段的DPD处理。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明实施例的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (11)

  1. 一种数字预失真DPD系统，其特征在于，包括：查表单元和DPD处理单元，所述查表单元包括：第一至第四地址转换表、第一至第N查找表以及DPD系数合并模块；其中，第一至第N查找表为多频段查找表，N＝2M，M为记忆深度，M为正整数；
    第一地址转换表，用于根据第一频段的第一路信号的幅度值对应的第一长度的比特序列得到对应的第二长度的第一比特序列，其中，所述第一长度大于第二长度；第二地址转换表，用于根据第二频段的第一路信号的幅度值对应的第一长度的比特序列，得到对应的第二长度的第二比特序列；
    第三地址转换表，用于根据第一频段的第二路信号的幅度值对应的第一长度的比特序列，得到对应的第二长度的第三比特序列，所述第一频段的第二路信号是对所述第一频段的第一路信号延时后得到的；
    第四地址转换表，用于根据第二频段的第二路信号的幅度值对应的第一长度的比特序列，得到对应的第二长度的第四比特序列，所述第二频段的第二路信号是对所述第二频段的第一路信号延时后得到的；
    所述第一至第N查找表中的第i查找表，用于根据第一频段的一路信号对应的第二长度的比特序列以及第二频段的一路信号对应的第二长度的比特序列合并得到第i查表地址，根据所述第i查表地址查找第i DPD系数，1≤i≤N；
    DPD系数合并模块，用于将所述第一至第N DPD系数处理得到一个DPD系数；
    DPD处理单元，用于根据所述DPD系数处理模块处理得到的DPD系数对所述第一频段的信号进行DPD处理。
  2. 如权利要求1所述的DPD系统，其特征在于，M＝1；
    第一查找表，具体用于根据所述第一比特序列和所述第二比特序列构成的第一查表地址查找第一DPD系数；其中，按照比特位从高到低的顺序，所述第一查表地址包括第一比特序列和所述第二比特序列；
    第二查找表，具体用于根据所述第三比特序列和所述第四比特序列构成的第二查表地址查找第二DPD系数；其中，按照比特位从高到低的顺序，所述第二查表地址包括第三比特序列和所述第四比特序列。
  3. 如权利要求1所述的DPD系统，其特征在于，M＝2；
    第一查找表，具体用于根据所述第一比特序列和所述第二比特序列构成的第一查表地址查找第一DPD系数；其中，按照比特位从高到低的顺序，所述第一查表地址包括第一比特序列和所述第二比特序列；
    第二查找表，具体用于根据所述第一比特序列和所述第二比特序列构成的第二查表地 址查找第二DPD系数；其中，按照比特位从高到低的顺序，所述第二查表地址包括所述第一比特序列和所述第二比特序列；
    第三查找表，具体用于根据所述第三比特序列和所述第四比特序列构成的第三查表地址查找第三DPD系数；其中，按照比特位从高到低的顺序，所述第三查表地址包括所述第三比特序列和所述第四比特序列；
    第四查找表，具体用于根据所述第三比特序列和所述第四比特序列构成的第四查表地址查找第四DPD系数；其中，按照比特位从高到低的顺序，所述第四查表地址包括所述第三比特序列和所述第四比特序列。
  4. 如权利要求1-3中任一项所述的DPD系统，其特征在于，还包括截位单元；所述截位单元用于：
    对所述第一频段的第一路信号、第一频段的第二路信号、第二频段的第一路信号以及第二频段的第二路信号的幅度值的比特序列进行截位，得到所述第一频段的第一路信号、第一频段的第二路信号、第二频段的第一路信号以及第二频段的第二路信号的幅度值对应的第一长度的比特序列。
  5. 如权利要求4所述的DPD系统，其特征在于，所述截位单元具体用于：
    分别截去所述第一频段的第一路信号、第一频段的第二路信号、第二频段的第一路信号以及第二频段的第二路信号的幅度值的比特序列的最高1比特和最低的3比特，得到所述第一频段的第一路信号、第一频段的第二路信号、第二频段的第一路信号以及第二频段的第二路信号的幅度值对应的第一长度的比特序列；所述第一长度的比特序列为11比特。
  6. 如权利要求1-3中任一项所述的DPD系统，其特征在于，在所述查表单元的第一频段信号的输入端和第二频段信号的输入端分别设置有第一开关和第二开关；所述第一开关选择性连接第一触点和第二触点，所述第二开关选择性连接第三触点和第四触点；
    当所述第一开关连接所述第一触点，所述第一频段信号被输入至第一频段的单频段查找表；当所述第一开关连接第二触点，所述第一频段信号被输入至所述第一地址转换表和所述第二地址转换表；
    当所述第二开关连接所述第三触点，所述第二频段信号被输入至第二频段的单频段查找表；当所述第二开关连接第四触点，所述第二频段信号被输入至所述第三地址转换表和所述第四地址转换表。
  7. 如权利要求6所述的DPD系统，其特征在于，还包括控制模块，所述控制模块用于：
    若确定所述输入信号为第一频段的单频段信号，则控制所述第一开关连接所述第一触点；
    若确定所述输入信号为第二频段的单频段信号，则控制所述第二开关连接所述第三触 点；
    若确定所述输入信号为多频段信号，则控制所述第一开关连接所述第二触点，且所述第二开关连接所述第四触点。
  8. 如权利要求1-3中任一项所述的DPD系统，其特征在于，所述第一至第四地址转换表中包括所述第一长度的比特序列与第二长度的比特序列的对应关系，其中：
    所述第一长度的比特序列的取值范围被划分为大小相等的第一至第E子范围，所述第二长度的比特序列的取值范围被划分为大小不等的第一至第E子范围；所述第一长度的比特序列的取值范围的第j子范围与所述第二长度的比特序列的取值范围的第j子范围一一对应，且，前者中的多个比特序列与后者中的一个比特序列相对应，E为大于1的整数，1≤j≤E；或者
    所述第一长度的比特序列的取值范围被划分为大小不等的第一至第E子范围，将所述第二长度的比特序列的取值范围被划分为大小相等的第一至第E子范围；所述第一长度的比特序列的取值范围的第j子范围与所述第二长度的比特序列的取值范围的第j子范围一一对应，且，前者中的多个比特序列与后者中的一个比特序列相对应，E为大于1的整数，1≤j≤E。
  9. 如权利要求8所述的DPD系统，其特征在于，E＝3；
    若所述第二长度的比特序列的取值范围按照比特序列取值从小到大的顺序被划分为大小相等的第一至第三子范围，则第二子范围最小；或者
    若所述第一长度的比特序列的取值范围按照比特序列取值从小到大的顺序被划分为第一至第三子范围，则第二子范围最大。
  10. 如权利要求1-3中任一项所述的DPD系统，其特征在于，所述第一至第N查找表中的每个查找表中最多包含64×64个DPD系数，所述第二长度为6比特，合并得到的第一至第N查表地址均为12比特。
  11. 如权利要求1-3中任一项所述的DPD系统，其特征在于，所述第一频段为F频段，第二频段为A频段；或者，
    所述第一频段为A频段，第二频段为F频段。
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