WO2016203648A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2016203648A1 WO2016203648A1 PCT/JP2015/067766 JP2015067766W WO2016203648A1 WO 2016203648 A1 WO2016203648 A1 WO 2016203648A1 JP 2015067766 W JP2015067766 W JP 2015067766W WO 2016203648 A1 WO2016203648 A1 WO 2016203648A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
Definitions
- the present disclosure relates to a semiconductor device, and is applicable to, for example, a semiconductor device having an ESD (Electro-Static-Discharge) protection circuit.
- ESD Electro-Static-Discharge
- a plurality of input / output cells corresponding to a plurality of external terminals are arranged in the peripheral portion of the semiconductor integrated circuit device (LSI chip).
- a plurality of power supply cells are arranged for a plurality of input / output cells in order to reduce and stabilize the power supply impedance.
- An ESD protection circuit is built in the input / output cell and the power cell.
- the semiconductor device includes an ESD protection circuit that is long in the arrangement direction of the input / output cells outside the input / output cells.
- the ESD protection circuit includes a resistor, a capacitor, an inverter, and an N-channel transistor.
- an increase in chip area can be suppressed.
- FIG. 6 is a schematic layout diagram of a semiconductor device according to a comparative example.
- FIG. 3 is a circuit diagram of the input / output cell of FIG. 2.
- FIG. 3 is a circuit diagram of the power cell in FIG. 2.
- FIG. 5 is a layout diagram of an ESD protection circuit within a broken line A in FIG. 4.
- FIG. 2 is a schematic layout diagram of a first example of an IO area in FIG. 1.
- FIG. 4 is a schematic layout diagram of a second example of the IO region in FIG. 1.
- 4A and 4B are diagrams for explaining a semiconductor device according to an embodiment.
- 1 is a schematic layout diagram of a semiconductor device according to a first embodiment.
- FIG. 10 is a block diagram of the IO area of FIG. 9.
- the circuit diagram of the ESD protection circuit of FIG. is a layout diagram of the ESD protection circuit of FIG. 9.
- FIG. 10 is a layout diagram of the ESD protection circuit of FIG. 9.
- FIG. 10 is a layout diagram of a first ESD protection circuit of a semiconductor device according to Modification 1;
- FIG. 10 is a circuit diagram of an IO region of a semiconductor device according to Modification 2.
- FIG. 16 is a layout diagram of the IO area in FIG. 15.
- FIG. 10 is a layout diagram of an IO region of a semiconductor device according to Modification 3.
- FIG. 10 is a layout diagram of an IO region of a semiconductor device according to Modification 4; The layout figure which saw through the pad of FIG.
- FIG. 10 is a connection diagram of a power supply line and a ground line in an IO region of a semiconductor device according to Modification Example 5.
- FIG. 22 is a layout diagram of the IO area of FIG. 21.
- FIG. 10 is a layout diagram of an IO region of a semiconductor device according to Modification 6;
- FIG. 24 is a circuit diagram of the IO region in FIG. 23.
- region of FIG. FIG. 24 is a layout diagram for explaining means for solving the problem of the IO region of FIG. 23.
- FIG. 6 is a schematic layout diagram of a semiconductor device according to a second embodiment.
- FIG. 28 is a circuit diagram of the IO region in FIG. 27.
- FIG. 1 is a plan view showing a schematic layout of a semiconductor device according to a comparative example.
- the semiconductor device 10S includes an input / output cell 11 and power supply cells 12 and 13 on the outer periphery of the chip.
- An area where the input / output cell 11 and the power supply cells 12 and 13 are arranged is called an IO area.
- the IO region is close to the chip end portions 21, 22, 23, 24, and is along four sides formed by the chip end portions 21, 22, 23, 24 in plan view. Two sides formed by the chip end portions 21 and 23 extend along the X direction. Two sides formed by the chip end portions 22 and 24 extend along the Y direction.
- the input / output cell 11 is a region for forming an input / output circuit connected to one input / output pad.
- the power cells 12 and 13 are regions for forming an ESD protection circuit for protecting the semiconductor device from ESD and noise and wiring for supplying power or GND (ground potential) to the inside of the chip.
- the power source cells 12 and 13 are arranged in a distributed manner for each of the plurality of input / output cells 11 and are arranged adjacent to each other between the input / output cell 11 and the input / output cell 11 in order to uniformly reduce the power source impedance.
- the semiconductor device 10S has one power supply domain, the power supply cells 12 and 13 are arranged at three locations in the IO region facing one chip side.
- FIG. 2 is a block diagram of the IO region of FIG. 1, showing the connection relationship between the power supply cells and input / output cells and the power supply.
- the input / output cell 11 includes an input / output circuit 111 connected to an input / output terminal (I / O) 112.
- the power cell 12 includes an ESD protection circuit 121 corresponding to the power terminal (VDD) 122
- the power cell 13 includes an ESD protection circuit 121 corresponding to the ground terminal (VSS) 123.
- the input / output terminal 112, the power supply terminal 122, and the ground terminal 123 are disposed on the input / output cell 11 and the power supply cells 12 and 13, respectively, but are disposed apart from the input / output cell 11 and the power supply cells 12 and 13, respectively. Also good.
- the input / output terminal 112, the power supply terminal 122, and the ground terminal 123 are connected to bonding wires or the like and are also referred to as an input / output pad, a power supply pad, and a ground pad, respectively
- FIG. 3 is a circuit diagram of the input / output cell of FIG.
- the input / output circuit 111 constituting the input / output cell 11 includes an output circuit including a P-channel transistor Q 2 and an N-channel transistor Q 3 that transmit an output signal to a signal wiring 216 connected to the input / output terminal 112, and an input / output terminal 112.
- an input circuit INV3 including an inverter INV1 for receiving an input signal input via a signal wiring 216, and diodes D1 and D2 constituting an ESD protection circuit.
- the P-channel transistor Q2 is connected between the power wiring 211 and the signal wiring 216
- the N-channel transistor Q3 is connected between the signal wiring 216 and the ground wiring 212
- the inverter INV3 is connected to the power wiring 211 and the ground wiring 212.
- the anode of the diode D 1 is connected to the signal wiring 216
- the cathode is connected to the power supply wiring 211.
- the anode of the diode D 2 is connected to the ground wiring 212, and the cathode is connected to the signal wiring 216.
- the diode D1 passes a surge current from the input / output terminal 112 to the power supply terminal 122 via the signal wiring 216 and the power supply wiring 211, and the diode D2 passes from the ground terminal 123 to the input / output terminal 112 via the ground wiring 212 and the signal wiring 216.
- the surge current that goes is made to flow.
- the output circuit may be a so-called open drain type that does not have the P-channel type transistor Q2. Further, the input / output circuit may not include either the output circuit or the input circuit.
- FIG. 4 is a circuit diagram of the power cell of FIG.
- the ESD protection circuit 121 that constitutes the power cells 12 and 13 discharges the surge voltage at high speed with a time constant circuit (also referred to as RC timer) 126 that detects a positive surge voltage, an inverter INV1 that is a buffer circuit. Therefore, the N-channel transistor Q1 having a large size and a diode D3 are included.
- the RC timer 126 is composed of an integrating circuit composed of a resistor R1 and a capacitor C1. One end of the resistor R1 is connected to the power supply terminal 122 via the power supply wiring 211, and the other end is connected to one end of the capacitor C1 and the input of the inverter INV1.
- One end of the capacitor C1 is connected to the other end of the resistor R1 and the input of the inverter INV1, and the other end is connected to the ground terminal 123 via the ground wiring 212.
- the charge voltage of the capacitor C1 is supplied to the input terminal of the inverter INV1.
- the output of the inverter INV1 is connected to the gate of the N channel type transistor Q1.
- the inverter INV1 operates by receiving an operating voltage from the power supply terminal 122 through the power supply wiring 211.
- the drain of the N-channel transistor Q1 is connected to the power supply terminal 122 via the power supply wiring 211, the source is connected to the ground terminal 123 via the ground wiring 212, and the back gate is connected to the ground terminal 123 via the ground wiring 212. Is done.
- a diode D3 for discharging a negative surge voltage is provided between the power supply terminal 122 and the ground terminal 123.
- the anode of the diode D3 is connected to the ground wiring 212, and the cathode is connected to the power supply wiring 211.
- the diode D3 allows a surge current to flow from the ground terminal 123 toward the power supply terminal 122 via the ground wiring 212 and the power supply wiring 211.
- the inverter INV1 maintains a high level from when a positive surge voltage is generated at the power supply terminal 122 until the charge voltage of the capacitor C1 reaches the logic threshold voltage of the inverter circuit INV1, and the N-channel transistor Q1 is turned on to discharge the surge voltage.
- the inverters INV1 and INV3 are each composed of a P-channel transistor and an N-channel transistor.
- the P-channel transistor Q2, the N-channel transistors Q1 and Q3, and the P-channel and N-channel transistors of the inverters INV1 and INV3 are so-called MOSFETs, but the gate is not limited to metal.
- the gate insulating film is not limited to the oxide film.
- FIG. 5 is a layout diagram of the ESD protection circuit within the broken line A in FIG. 4, which matches the direction of the power cell disposed on the lower side (chip end portion 21) side of FIG.
- An N-channel transistor Q1, an inverter INV1, and an RC timer 126 are arranged in this order from the chip end side.
- the power cells 12 and 13 have a length in the X direction (cell width (W)) shorter than a length in the Y direction (cell height (H)).
- FIG. 6 is a schematic layout diagram of the first example of the IO region of FIG. 1, and shows a case where the height of the power cell is matched to the height of the input / output cell.
- FIG. 7 is a schematic layout diagram of the second example of the IO region of FIG. 1, and shows a case where the width of the power cell matches the width of the input / output cell.
- the power cells 12 and 13 are larger than the input / output cell 11. For this reason, the input / output cell 11 and the power cells 12 and 13 having different cell sizes are mixedly arranged.
- ESD protection circuits power cells to be placed will increase due to multifunctional products and increased number of power domain separation. Furthermore, an increase in the number of pins (input / output pad neck) increases the chip area.
- An ESD protection circuit needs to be placed because there is resistance in the power supply wiring and ground wiring in the IO region, but the ESD protection circuit that should be placed in the IO region by the input / output pad neck is placed inside the IO region. It is also necessary. However, this complicates the design due to the pressure in the chip internal area, the connection with the peripheral wiring in the IO area, the generation of irregularities, and the like.
- a power cell incorporating an ESD protection circuit has a larger cell size than an input / output cell, and the cell width increases when the cell height is matched with the input / output cell.
- input / output cells having a large cell size in terms of specifications, and when they are combined with the cell widths of other input / output cells, a portion (unevenness) protruding from the IO region occurs.
- FIG. 8 is a layout diagram showing the configuration of the semiconductor device according to the embodiment.
- the semiconductor device 10 includes a plurality of input / output circuits (IO) arranged in series in the X direction and an ESD protection circuit (on the chip end (EDG)) side of the plurality of input / output circuits (IO). ESD).
- the ESD protection circuit (ESD) includes a resistor (R), a capacitor (C), an inverter (INV), and an N-channel transistor (NMOS). Since an ESD protection circuit larger than the input / output circuit is not arranged in the input / output circuit row, an increase in chip area can be suppressed.
- FIG. 9 is a plan view showing a schematic layout of the semiconductor device according to the first embodiment.
- the semiconductor device 10A includes an input / output cell 11 and power supply cells 12A and 13A on the outer periphery of a chip formed of one semiconductor substrate.
- An area where the input / output cell 11 and the power cells 12A and 13A are arranged is referred to as an IO area.
- the IO region is close to the chip end portions 21, 22, 23, 24, and is along four sides formed by the chip end portions 21, 22, 23, 24 in plan view. Two sides formed by the chip end portions 21 and 23 extend along the X direction. Two sides formed by the chip end portions 22 and 24 extend along the Y direction.
- the input / output cell 11 is a region for forming an input / output circuit connected to one input / output pad.
- the power cells 12A and 13A are a region for forming a diode D3 for protecting the semiconductor device from ESD and noise and a wiring for supplying power or GND (ground potential) to the inside of the chip. Since it is necessary to reduce the power supply impedance evenly, the power supply cells 12 ⁇ / b> A and 13 ⁇ / b> A are distributed for each of the plurality of input / output cells 11, and are disposed adjacent to each other between the input / output cells 11 and 11.
- the ESD protection circuit 124 is disposed closer to the outside (chip end portions 21, 22, 23, 24 side) than the input / output cell 11 and the power supply cells 12A, 13A, and extends along the four sides of the chip end portion, respectively. To do. Note that corner cells 16 are provided at four corners of the chip of the semiconductor device 10A. The corner cell 16 includes power supply wiring and ground wiring.
- the semiconductor device 10A includes an internal circuit inside the IO region. Similarly to the semiconductor device 10S, the semiconductor device 10A has one power supply domain, and the power supply cells 12A and 13A are arranged one by one in the IO region along one chip side.
- the number of power cells 12A and 13A is not limited to this, and is defined by the discharge characteristics of the protection elements, the wiring impedance, and the like in each semiconductor technology.
- the semiconductor device 10A is equivalent to the semiconductor device 10S except for the power cell and the ESD protection circuit, the number of power cells 12A and 13A in the semiconductor device 10A is the same as the number of power cells 12 and 13 in the semiconductor device 10S. The number can be less than the number, which can contribute to the elimination of the pad neck.
- FIG. 10 is a circuit diagram showing the connection relationship between the power source cell and the input / output cell and the power source according to the first embodiment, and is adapted to the direction of the IO region arranged on the lower side (chip end portion 21) side of FIG. .
- FIG. 11 is a circuit diagram of the ESD protection circuit 124 of FIG.
- the input / output cell 11 includes an input / output circuit 111 connected to an input / output terminal (I / O) 112.
- the power cell 12A includes a wiring 217 connected to a power wiring 211 for supplying power from the power terminal (VDD) 122 to the inside of the chip and a diode D3 which is an ESD protection circuit.
- the power cell 13A includes a wiring 218 connected to a ground wiring 212 for supplying a ground potential from the ground terminal (VSS) 123 to the inside of the chip.
- the power supply cell 12A includes the diode D3 in the ESD protection circuit 121 of FIG. 4, but does not include other circuits of the ESD protection circuit 121.
- the power cell 13A does not include the ESD protection circuit 121. That is, the ESD protection circuit 124 is located outside the input / output cell 11 and the power supply cells 12A and 13A.
- the ESD protection circuit 124 is the same as the circuit within the broken line A of the ESD protection circuit 121 in FIG. 4 and is connected to the power supply wiring 213 and the ground wiring 214.
- the power supply wiring 211, the ground wiring 212, the power supply wiring 213, and the ground wiring 214 extend along the X direction, and are arranged in this order from the chip end 21 to the ground wiring 214, the power supply wiring 213, the ground wiring 212, and the power supply wiring 211.
- the power supply wiring 211 and the power supply wiring 213 are connected, and the ground wiring 212 and the ground wiring 214 are connected.
- the input / output terminal (I / O) 112, the power supply terminal 122, and the ground terminal 123 are arranged so as to overlap the input / output cell 11 and the power supply cells 12A and 13A in plan view, respectively.
- the power cells 12A and 13A may be arranged apart from each other in plan view.
- FIG. 12 is a layout diagram of the ESD protection circuit of FIG. 11, which matches the direction of the ESD protection circuit 124 disposed on the lower side (chip end portion 21) side of FIG.
- FIG. 13 is a layout diagram of the ESD protection circuit of FIG. 11 and shows a case where two ESD protection circuits are arranged.
- the N-channel transistor Q1, the inverter INV1, and the RC timer 126 are arranged in this order from the chip end 24 side.
- the N-channel transistor Q1, the inverter INV1, and the RC timer 126 may be arranged in this order from the chip end 22 side.
- the ESD protection circuit 124 has a length in the X direction (cell width (W)) longer than a length in the Y direction (cell height (H)). That is, the cells of the ESD protection circuit 124 have a horizontally long shape with a suppressed height.
- One ESD protection circuit 124 faces the plurality of input / output cells 11.
- the ESD protection circuits 124 are arranged in a plurality of columns along the X direction.
- the ESD protection circuit 124 disposed on the right side (chip end portion 22), upper side (chip end portion 23), and left side (chip end portion 24) side of FIG. 9 is also an ESD protection circuit 124 disposed on the chip end portion 21 side. Arranged similarly.
- the ESD protection circuit 124 is arranged outside the IO area in FIG. 9, it may be arranged inside the IO area.
- the ESD protection circuit 124 is disposed in the immediate vicinity of all the input / output cells, the specified value of the ESD design constraint (the power supply line of the IO region and the peripheral wiring resistance of the ground line) can be greatly relaxed. Can do. Further, the power supply cell 12A disposed between the input / output cells is provided with a power supply lead-in metal wiring and a diode D3 between the power supply line and the ground line, and no ESD protection circuit 124 is provided. The power cell 13A is provided with ground lead-in metal wiring, and no ESD protection circuit 121 is provided.
- the power cells 12A and 13A can be made smaller than the area of the input / output cell 11, and the cell width and cell height of the power cells 12A and 13A can be matched with the cell width and cell height of the input / output cell 11. It becomes possible. This is an effect of reducing the ESD protection circuit, and the number of cases in which the ESD protection circuit is dealt with inside the IO region is greatly reduced. Problems that complicate the design, such as compression of the chip internal region, connection with the peripheral wiring in the IO region, and generation of uneven portions, which are incidental to this, can be solved. Further, the area of the ESD protection circuit arranged in the power source cell in the IO region of the comparative example can be reduced, and the length around one chip can be shortened accordingly. As a result, the problem of area increase due to the input / output pad neck is solved, and the chip area can be reduced.
- FIG. 14 is a layout diagram of the ESD protection circuit of the semiconductor device according to the first modification, and is adapted to the direction of the ESD protection circuit arranged on the lower side (chip end portion 21) side of FIG.
- the semiconductor device according to the first modification shares the RC timer possessed by the two ESD protection circuits. From the chip end 24 side, the N-channel transistor Q1, the inverter INV1, the RC timer 126, the inverter INV1, and the N-channel transistor Q1 are arranged in this order.
- the first ESD protection circuits 124A in FIG. 14 are arranged in a plurality of columns along the X direction.
- the ESD protection circuit 124A disposed on the right side (chip end portion 22), upper side (chip end portion 23), and left side (chip end portion 24) side of FIG. 9 also includes the ESD protection circuit 124A disposed on the chip end portion 21 side. Arranged similarly.
- the total area of the RC timer 126 occupied by the chip of the modification 1 can be halved compared to the first embodiment. For example, if the RC timer 126 occupies 30% of the area of the ESD protection circuit 124 as shown in FIG. 13, the area of the ESD protection circuit 124A of Modification 1 is reduced by 15% as shown in FIG. Can do.
- FIG. 15 is a circuit diagram of the IO region of the semiconductor device according to the second modification, which is aligned with the direction of the IO region arranged on the lower side (chip end portion 21) side of FIG.
- FIG. 16 is a layout diagram of the IO area of FIG.
- the semiconductor device according to the modification 2 includes an input / output cell 11 ⁇ / b> A different from the normal input / output cell 11.
- the input / output cell 11 ⁇ / b> A has a function composed of logic circuits such as a Schmitt trigger NOR (NOR) 114 and an inverter 115.
- NOR Schmitt trigger NOR
- the NOR 114 and the inverter 115 are connected to the power supply wiring 211 and the ground wiring 212.
- the input / output cell 11A has a larger area than the input / output cell 11.
- the cell width of the input / output cell 11A is matched to the cell width of the input / output cell 11
- the cell height of the input / output cell 11A becomes higher than the cell height of the input / output cell 11.
- the ESD protection circuit 124 is not disposed at a position where the input / output cell 11A is disposed, it is possible to absorb a portion where the height of the input / output cell 11A is increased.
- the protruding portion is disposed so as to be absorbed in the region where the ESD protection circuit 124 is disposed.
- the input cell 11A arranged on the chip end 21 side the input cell 11A arranged on the right side (chip end 22), upper side (chip end 23), and left side (chip end 24) side of FIG. Be placed.
- FIG. 17 is a layout diagram of the IO region of the semiconductor device according to the modified example 3, which is aligned with the direction of the IO region arranged on the lower side (chip end portion 21) side of FIG.
- the semiconductor device according to Modification 3 is an example in which an input / output terminal 112, a power supply terminal 122, and a ground terminal 123 are arranged between the ESD protection circuit 124 and the chip end 21.
- the widths of the input / output terminal 112, the power supply terminal 122, and the ground terminal 123 are the same as or smaller than the input / output cell 11.
- the input / output cell 11, the power cells 12A and 13A, and the ESD protection circuit 124 of the semiconductor device of Modification 3 are the same as those in the first embodiment.
- the power supply voltage (VDD1) of the power supply wiring 211 connected to the power supply terminal 122 and the ground voltage (VSS1) of the ground wiring 212 connected to the ground terminal 123 are
- the power supply voltage (VDD2) of the power supply wiring 221 and the ground voltage (VSS2) of the ground wiring 222 are used in the internal circuit.
- the wiring of the power supply voltage (VDD2) and the ground voltage (VSS2) is arranged in addition to the wiring of the power supply voltage (VDD1) and the ground voltage (VSS1).
- the power supply voltage (VDD2) and the ground voltage (VSS2) may be generated from the power supply voltage (VDD1) and the ground voltage (VSS1) by a step-down circuit, or supplied from the outside through the power supply terminal and the ground terminal. Also good.
- FIG. 18 is a layout diagram of the IO region of the semiconductor device according to the modified example 4, which is aligned with the direction of the IO region arranged on the lower side (chip end portion 21) side of FIG.
- FIG. 19 is a layout view seen through the pad of FIG.
- FIG. 20 is a layout diagram in which the pad of FIG. 18 is removed.
- the input / output cell 11 is narrower than the modification example 3 (the cell height is larger), and the input / output terminal 112, the power supply terminal 122, and the ground terminal 123 are staggered in the IO region.
- the widths of the input terminal 112, the power supply terminal 122, and the ground terminal 123 according to Modification 4 are larger than the widths of the input / output cell 11 and the power supply cells 12A and 13A. Accordingly, one input / output terminal 112 or power supply terminal 122 or power supply terminal 123 overlaps the three cells adjacent to the input / output cell 11 or the power supply cell 12A or the power supply cell 13A in plan view. One power supply terminal 122 overlaps the adjacent input / output cell 11 and power supply cell 13A in plan view.
- the input / output cell 11, power supply cells 12A and 13A, and the ESD protection circuit 124 of the semiconductor device of Modification 4 are the same as those of Embodiment 1 and Modification 3 except for the cell shape.
- the chip area can be reduced because the input / output pad neck can be improved by the staggered arrangement.
- FIG. 21 is a connection diagram of the power supply wiring and the ground wiring in the IO region of the semiconductor device according to the modified example 5, which is adapted to the direction of the IO region arranged on the lower side (chip end portion 21) side of FIG.
- FIG. 22 is a layout diagram of the IO area of FIG.
- the fifth modification the arrangement of the power supply wiring 213 and the ground wiring 214 of the ESD protection circuit 124 of the first embodiment is changed, and the arrangement of the N-channel transistor and the P-channel transistor is changed accordingly.
- the fifth modification is the same as the first embodiment.
- Ground wirings 212 and 214 are arranged and connected on the inner side of the side where the input / output cell 11 and the ESD protection circuit 124 are adjacent to each other.
- the input / output cell 11 and the ESD protection circuit 124 and the pad 122 overlap in plan view, but in order to make it easy to see, only one of the overlapping portions is shown in FIG. 22.
- the arrangement of the input / output cell 11 and the ESD protection circuit 124 is shown on the left side of the drawing, and the arrangement of the pad 122 is shown on the right side thereof.
- Each of the regions to be arranged extends along the X direction.
- the power supply wiring 211 of the input / output cell 11 and the power supply wiring 213 of the ESD protection circuit 124 are connected by a wiring 215.
- the wiring 215 is a low-resistance metal that is an upper layer than the metal of the power supply wirings 211 and 213, and is arranged in a space between the pads 122.
- the power supply wiring and ground wiring arranged on the right side (chip end portion 22), top side (chip end portion 23), left side (chip end portion 24) side of FIG. 9 are also arranged on the chip end portion 21 side. Arranged in the same way as the wiring.
- the wiring structure can easily cope with design constraints such as resistance value and current density. Further, since the ground wiring can be easily connected and can be connected by the same layer of metal, a greater effect can be obtained in a product having a small total number of wirings.
- FIG. 23 is a layout diagram of the IO region of the semiconductor device according to the modified example 6, which matches the direction of the IO region arranged on the lower side (chip end portion 21) side of FIG.
- FIG. 24 is a circuit diagram of the IO region of FIG.
- the semiconductor device includes a plurality of power source regions (power source domains).
- the semiconductor device according to Modification 6 includes a power supply domain PD1 that operates with a power supply (VDD1) and ground (VSS1), and a power supply domain PD2 that operates with a power supply (VDD2) and ground (VSS2).
- a domain PD1 and a power domain PD2 are provided.
- Each of the power domain PD1 and the power domain PD2 includes an input / output cell 11, power cells 12A and 13A, and an ESD protection circuit 124 as in the first embodiment.
- the semiconductor device according to Modification 6 includes a bridge cell (bridge circuit) 14 between the power domain PD1 and the power domain PD2 in the IO region.
- the bridge cell 14 includes bidirectional diodes D4 and D5 that connect the ground wiring 212 of the power domain PD1 and the ground wiring 222 of the power domain PD2.
- the anode of the diode D4 is connected to the ground wiring 212, and the cathode is connected to the ground wiring 222.
- the anode of the diode D5 is connected to the ground wiring 222, and the cathode is connected to the ground wiring 212.
- the power supply wiring 211 and the power supply wiring 221 are separated.
- FIG. 25 is a layout diagram for explaining the problem of the IO area of FIG.
- FIG. 26 is a layout diagram for explaining means for solving the problem of the IO area of FIG.
- the width of the ESD protection circuit 124 is the same as that of the power cells 12A and 13A and the bridge cell 14. It becomes wider than the width, and the dead space 15 is generated. In this case, it may be better to use the power cells 12 and 13 including the ESD protection circuit 124 as in the comparative example of FIG.
- FIG. 27 is a schematic layout diagram of the semiconductor device according to the second embodiment.
- FIG. 28 is a circuit diagram of the IO region of FIG. 27, which is aligned with the direction of the IO region arranged on the lower side (chip end portion 21) side of FIG.
- the semiconductor device 10B has four types of power domains, two types of power domains to which the technology according to the first embodiment is applied at the upper left and lower right of the chip in the drawing, and a power domain to which the technology according to the comparative example is applied to the lower left and right sides. There are two types. That is, the semiconductor device 10B includes four power supply domains PD1, PD2, PD3, and PD4 on one semiconductor substrate.
- the IO regions of the power supply domains PD1 and PD3 are provided on the outer periphery of the chip in the same manner as in the first embodiment (input / output cell 11, input / output terminal 112, power supply cells 12A and 13A, power supply terminal 122, ground terminal 123 and ESD protection). Circuit 124).
- the IO regions of the power supply domains PD2 and PD4 are provided with IO regions (input / output cell 11, input / output terminal 112, power supply cells 12 and 13, power supply terminal 122 and ground terminal 123) similar to the comparative example on the outer periphery of the chip.
- a bridge cell (bridge circuit) 14 is provided at each boundary of the IO regions of the power domains PD1, PD2, PD3, and PD4.
- the area of the IO region of power supply domains PD2 and PD4 is smaller than the area of the IO region of power supply domains PD1 and PD3.
- the length of the power supply domains PD2 and PD4 in the direction along the chip end is smaller than the length of the power supply domains PD1 and PD3 in the direction along the chip end.
- the input / output cell 11 of the power domain PD1 is connected to the power wiring 211 and the ground wiring 212
- the power cell 12A is connected to the power wiring 211 and the ground wiring 212
- the power cell 13A is connected to the ground wiring 212.
- the ESD protection circuit 124 is connected to the power supply wiring 213 and the ground wiring 212.
- the power supply wiring 211, the ground wiring 212, and the power supply wiring 213 extend along the Y direction (the direction in which the side of the chip end 22 extends), and the power supply wiring 213, the ground wiring 212, and the power supply wiring 211 are formed from the chip end 22. Arranged in order.
- the power domain PD1 also includes a portion in which the input / output cell 11 and the power cells 12A and 13A are arranged in series in the X direction.
- the power wiring 211, the ground wiring 212, and the power wiring 213 are arranged in the X direction (the chip end 21 is It extends along the direction in which the sides to be extended extend.
- the input / output cell 11 of the power domain PD2 is connected to the power wiring 221 and the ground wiring 222
- the power cell 12 is connected to the power wiring 221 and the ground wiring 222
- the power cell 13 is connected to the power wiring 221 and the ground wiring 222.
- the power supply wiring 221 and the ground wiring 222 extend along the Y direction, and are arranged in order of the ground wiring 222 and the power supply wiring 221 from the chip end portion 22.
- a bridge cell 14 is provided between the power domain PD1 and the power domain PD2.
- the bridge cell 14 includes bidirectional diodes D4 and D5 that connect the ground wiring 212 of the power domain PD1 and the ground wiring 222 of the power domain PD2.
- the anode of the diode D4 is connected to the ground wiring 212, and the cathode is connected to the ground wiring 222.
- the anode of the diode D5 is connected to the ground wiring 222, and the cathode is connected to the ground wiring 212.
- the power supply wiring 211 and the power supply wiring 221 are separated.
- the input / output terminal (I / O) 112, the power supply terminal 122, and the ground terminal 123 of the power domain PD1 are arranged so as to overlap the input / output cell 11 and the power cells 12A and 13A, respectively, in plan view. You may arrange
- the input / output terminal (I / O) 112, the power supply terminal 122, and the ground terminal 123 of the power domain PD2 are arranged so as to overlap the input / output cell 11 and the power supply cells 12 and 13, respectively, in plan view. You may arrange
- the IO area of the power domain PD3 has the same configuration as the IO area of the power domain PD1.
- the IO area of the power domain PD4 has the same configuration as the IO area of the power domain PD2.
- the IO region of the power domain PD4 is arranged at the corner of the chip, and has a portion facing the chip end 21 and a portion facing the chip end 24.
- corner cells 16 are provided at the four corners of the chip of the semiconductor device 10B.
- the corner cells 16 in the same power supply domain include power supply wiring and ground wiring for the power supply domain.
- the semiconductor device 10B includes an internal circuit inside the IO region.
- the ESD protection circuit according to the comparative example By arranging the ESD protection circuit according to the comparative example in the small power domain and the ESD protection circuit according to the first embodiment in the large power domain, an increase in the chip area can be suppressed.
- the ESD protection circuit of the comparative example By partially arranging the ESD protection circuit of the comparative example in series with the input / output circuit according to the scale of the power domain, for example, the analog by using the ESD protection circuit of the comparative example for the power domain for the analog circuit The influence of circuit noise can be suppressed.
- Example 1 and Modifications 1 to 6 can be combined as appropriate. Further, the first to fifth modifications of the first embodiment can be used as the second modification of the second embodiment. Further, the second embodiment and the first to fifth modifications can be appropriately combined.
Abstract
Description
その他の課題と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。
すなわち、半導体装置は入出力セルの配列方向に長いESD保護回路を入出力セルの外側に備える。ESD保護回路は抵抗と容量とインバータとNチャネル型トランジスタとで構成される。
図1は比較例に係る半導体装置の概略レイアウトを示す平面図である。半導体装置10Sはチップの外周部に入出力セル11および電源セル12、13を備える。入出力セル11および電源セル12、13が配置される領域をIO領域という。IO領域はチップ端部21、22、23、24に近接して、平面視でチップ端部21、22、23、24が構成する4つの辺に沿っている。チップ端部21、23が構成する2つの辺はX方向に沿って伸びている。チップ端部22、24が構成する2つの辺はY方向に沿って伸びている。入出力セル11は1つの入出力パッドに接続される入出力回路の形成領域である。電源セル12、13はESDやノイズから半導体装置を保護するESD保護回路およびチップ内部へ電源またはGND(接地電位)を供給する配線の形成領域である。電源インピーダンスを均等に小さくする必要から、電源セル12、13は、複数の入出力セル11毎に分散して配置され、入出力セル11と入出力セル11の間へ隣接して配置される。半導体装置10Sは電源ドメインが1つであるが、電源セル12、13は1つのチップ辺に対向するIO領域に3か所ずつ配置されている。
次に、比較例に係る半導体装置の課題を解決する実施形態に係る半導体装置について説明する。
図8は実施形態に係る半導体装置の構成を示すレイアウト図である。半導体装置10は、X方向に直列に配置される複数の入出力回路(IO)と、複数の入出力回路(IO)の外側(チップ端部(EDG))側に配置されるESD保護回路(ESD)と、を備える。ESD保護回路(ESD)は、抵抗(R)と、容量(C)と、インバータ(INV)と、Nチャネル型トランジスタ(NMOS)と、を備える。
入出力回路よりも大きいESD保護回路を入出力回路列に配置しないので、チップ面積の増加を抑制することができる。
実施例1のESD保護回路のセルレイアウトを変更した例(変形例1)について説明する。
図14は変形例1に係る半導体装置のESD保護回路のレイアウト図であり、図9の下辺(チップ端部21)側に配置されるESD保護回路の向きに合わせている。変形例1に係る半導体装置は二つのESD保護回路で持つRCタイマを共有化する。チップ端部24側からNチャネル型トランジスタQ1、インバータINV1、RCタイマ126、インバータINV1、Nチャネル型トランジスタQ1の順に配置されている。図14の第1のESD保護回路124AはX方向に沿って複数縦列に配置される。図9の右辺(チップ端部22)、上辺(チップ端部23)、左辺(チップ端部24)側に配置されるESD保護回路124Aもチップ端部21側に配置されるESD保護回路124Aと同様に配置される。
実施例1の入出力セルに別機能を追加した例(変形例2)について説明する。
図15は変形例2に係る半導体装置のIO領域の回路図であり、図9の下辺(チップ端部21)側に配置されるIO領域の向きに合わせている。図16は図15のIO領域のレイアウト図である。変形例2に係る半導体装置は通常の入出力セル11と異なる入出力セル11Aを備える。入出力セル11Aは入出力セル11の機能に加えて、シュミットトリガのノア(NOR)114やインバータ115等の論理回路で構成される機能を備える。ノア114およびインバータ115は電源配線211と接地配線212とに接続される。この結果、入出力セル11Aは入出力セル11よりも面積が大きくなる。例えば、入出力セル11Aのセル幅を入出力セル11のセル幅に合わせると、入出力セル11Aのセル高さが入出力セル11のセル高さよりも高くなる。しかし、入出力セル11Aが配置される箇所にESD保護回路124を配置しないようにすることにより、入出力セル11Aの高さが高くなった部分を吸収することが可能となる。面積の異なる様々な仕様の入出力セルにおいてセル幅を合せた場合や細幅化を行った際、チップ内側へ突き出るセルが存在する。この突出し部をESD保護回路124の配置領域で吸収するように配置する。図9の右辺(チップ端部22)、上辺(チップ端部23)、左辺(チップ端部24)側に配置される入力セル11Aもチップ端部21側に配置される入力セル11Aと同様に配置される。
実施例1のパッドの位置を変更した例(変形例3)について説明する。
図17は変形例3に係る半導体装置のIO領域のレイアウト図であり、図9の下辺(チップ端部21)側に配置されるIO領域の向きに合わせている。変形例3に係る半導体装置は入出力端子112、電源端子122および接地端子123をESD保護回路124とチップ端21との間に配置した例である。入出力端子112、電源端子122および接地端子123の幅は、入出力セル11と同程度か小さい幅である。変形例3の半導体装置の入出力セル11、電源セル12A、13AおよびESD保護回路124は実施例1と同様である。図9の右辺(チップ端部22)、上辺(チップ端部23)、左辺(チップ端部24)側に配置される入出力端子112、電源端子122および接地端子123もチップ端部21側に配置される入出力端子112、電源端子122および接地端子123と同様に配置される。
実施例1のパッドを千鳥配置にした例(変形例4)について説明する。
図18は変形例4に係る半導体装置のIO領域のレイアウト図であり、図9の下辺(チップ端部21)側に配置されるIO領域の向きに合わせている。図19は図18のパッドを透視したレイアウト図である。図20は図18のパッドを取り除いたレイアウト図である。変形例4に係る半導体装置は、入出力セル11を変形例3よりも細幅化(セル高さは大きく)して、入出力端子112、電源端子122、接地端子123をIO領域に千鳥配置(ジグザグ状に配置)して構成される。変形例4に係る入力端子112、電源端子122、接地端子123の幅は入出力セル11、電源セル12A、13Aの幅よりも大きい。よって、1つの入出力端子112または電源端子122または電源端子123は、入出力セル11または電源セル12Aまたは電源セル13Aが隣接する3つのセルに平面視で重なるようになる。1つの電源端子122は隣接する入出力セル11と電源セル13Aに平面視で重なる。変形例4の半導体装置の入出力セル11、電源セル12A、13AおよびESD保護回路124はセル形状を除いて実施例1、変形例3と同様である。図9の右辺(チップ端部22)、上辺(チップ端部23)、左辺(チップ端部24)側に配置される入出力端子112、電源端子122および接地端子123もチップ端部21側に配置される入出力端子112、電源端子122および接地端子123と同様に配置される。
実施例1の電源配線/接地配線の配置を変更した例(変形例5)について説明する。
図21は変形例5に係る半導体装置のIO領域の電源配線と接地配線の結線図であり、図9の下辺(チップ端部21)側に配置されるIO領域の向きに合わせている。図22は図21のIO領域のレイアウト図である。変形例5では、実施例1のESD保護回路124の電源配線213と接地配線214の配置を入れ替え、それに伴いNチャネル型トランジスタおよびPチャネル型トランジスタなど配置を替えている。これ以外については、変形例5は実施例1と同様である。入出力セル11とESD保護回路124が隣接する側のそれぞれの内側に接地配線212、214を配置接続する。図22のレイアウト例では、入出力セル11およびESD保護回路124と、パッド122とは平面視で重なるが、見やすくするために、図22では重なる部分ではいずれか一方のみを記載している。図の左側に入出力セル11とESD保護回路124の配置を示し、その右側にパッド122の配置を示している。入出力セル11に接続する電源配線211を配置する領域、入出力セル11に接続する接地配線212およびESD保護回路124に接続する接地配線214の領域、ESD保護回路124に接続する電源配線213を配置する領域はそれぞれX方向に沿って伸びる。入出力セル11の電源配線211とESD保護回路124の電源配線213同士を配線215で接続する。配線215は、電源配線211、213のメタルよりも上層の低抵抗のメタルであり、パッド122間のスペースに配置される。図9の右辺(チップ端部22)、上辺(チップ端部23)、左辺(チップ端部24)側に配置される電源配線および接地配線もチップ端部21側に配置される電源配線および接地配線と同様に配置される。
電源ドメインが複数の例(変形例6)について説明する。
図23は変形例6に係る半導体装置のIO領域のレイアウト図であり、図9の下辺(チップ端部21)側に配置されるIO領域の向きに合わせている。図24は図23のIO領域の回路図である。変形例3のようにIO領域で使用する電源と内部回路で使用する電源を異ならせる場合、半導体装置内は複数の電源領域(電源ドメイン)を備えることになる。変形例6に係る半導体装置では、電源(VDD1)および接地(VSS1)で動作する電源ドメインPD1と、電源(VDD2)および接地(VSS2)で動作する電源ドメインPD2とを備え、IO領域にも電源ドメインPD1と電源ドメインPD2を備える。電源ドメインPD1および電源ドメインPD2のそれぞれは、実施例1と同様に入出力セル11、電源セル12A、13AおよびESD保護回路124を備える。変形例6に係る半導体装置は、IO領域の電源ドメインPD1と電源ドメインPD2との間にブリッジセル(ブリッジ回路)14を備える。ブリッジセル14は電源ドメインPD1の接地配線212と電源ドメインPD2の接地配線222とを接続する双方向のダイオードD4、D5を備える。ダイオードD4のアノードは接地配線212に接続され、カソードは接地配線222に接続される。ダイオードD5のアノードは接地配線222に接続され、カソードは接地配線212に接続される。電源配線211と電源配線221は分離されている。
図27は実施例2に係る半導体装置の概略レイアウト図である。図28は図27のIO領域の回路図であり、図27の下辺(チップ端部21)側に配置されるIO領域の向きに合わせている。半導体装置10Bには電源ドメインが4種類あり、図面上チップの左上と右下に実施例1に係る技術を適用した電源ドメインが2種類、左下と右辺に比較例に係る技術を適用する電源ドメインが2種類ある。すなわち、半導体装置10Bは一つの半導体基板上に4つの電源ドメインPD1、PD2、PD3、PD4を備える。電源ドメインPD1、PD3のIO領域は、チップの外周部に実施例1と同様なIO領域(入出力セル11、入出力端子112、電源セル12A、13A、電源端子122、接地端子123およびESD保護回路124)を備える。電源ドメインPD2、PD4のIO領域は、チップの外周部に比較例と同様なIO領域(入出力セル11、入出力端子112、電源セル12、13、電源端子122および接地端子123)を備える。電源ドメインPD1、PD2、PD3、PD4のIO領域のそれぞれの境界にはブリッジセル(ブリッジ回路)14を備える。電源ドメインPD2、PD4のIO領域の面積は電源ドメインPD1、PD3のIO領域の面積よりも小さい。言い換えると、電源ドメインPD2、PD4のIO領域がチップ端部に沿う方向の長さは電源ドメインPD1、PD3のIO領域がチップ端部に沿う方向の長さよりも小さい。
11・・・入出力セル
111・・・入出力回路
D1、D2・・・ダイオード
Q2・・・Pチャネル型トランジスタ
Q3・・・Nチャネル型トランジスタ
INV3・・・インバータ
112・・・入出力端子(入出力パッド)
12、13・・・電源セル
121・・・ESD保護回路
122・・・電源端子(電源パッド)
123・・・接地端子(接地パッド)
12A・・・電源セル
124・・・ESD保護回路
126・・・RCタイマ
R1・・・抵抗
C1・・・容量
INV1・・・インバータ
Q1・・・Nチャネル型トランジスタ
13A・・・電源セル
D3・・・ダイオード
14・・・ブリッジセル(ブリッジ回路)
16・・・コーナセル
21、22、23、24・・・チップ端部
D4、D5・・・ダイオード
Claims (20)
- 半導体装置は、
第1のパッドに接続される第1の入出力回路と、
前記第1の入出力回路に対しチップ端部が構成する1つの辺に沿う方向に配置され、第2のパッドに接続される第2の入出力回路と、
前記第1および第2の入出力回路の外側の前記チップ端部の近傍に配置される第1のESD保護回路と、
を備え、
前記第1のESD保護回路は、第1の抵抗と、第1の容量と、第1のインバータと、第1のNチャネル型トランジスタと、を備える。 - 請求項1の半導体装置において、
第1の電源パッドに接続される第1の電源配線と、
第1の接地パッドに接続される第1の接地配線と、
を備える。 - 請求項2の半導体装置において、
前記第1および第2の入出力回路は、それぞれ、信号配線にアノードが接続され第1の電源配線にカソードが接続される第1のダイオードと、第1の接地配線にアノードが接続され前記信号配線にカソードが接続される第2のダイオードと、前記信号配線に接続される出力回路または入力回路と、を備える。 - 請求項3の半導体装置において、
前記第1の抵抗の一端は前記第1の電源配線に接続され、
前記第1の抵抗の他端は前記第1の容量の一端に接続され、
前記第1の容量の他端は前記第1の接地配線に接続され、
前記第1の抵抗の他端は第1のインバータの入力に接続され、
前記第1のインバータの出力は第1のNチャネル型トランジスタのゲート電極に接続され、
前記第1のNチャネル型トランジスタは前記第1の電源配線と前記第1の接地配線との間に電流経路を構成するようにされる。 - 請求項4の半導体装置において、
前記第1の入出力回路と前記第2の入出力回路との間に配置され、前記第1の接地配線にアノードが接続され前記第1の電源配線にカソードが接続される第3のダイオードを備える。 - 請求項2の半導体装置において、
前記第1のESD保護回路に対し前記1つの辺に沿う方向に配置される第2のESD保護回路を備え、
前記第2のESD保護回路は、前記第1の電源配線に一端が接続される第2の抵抗と、前記第2の抵抗の他端に一端が接続され前記第1の接地配線に他端が接続される第2の容量と、前記第2の抵抗の他端が入力される第2のインバータと、前記第2のインバータの出力にゲート電極が接続され前記第1の電源配線と前記第1の接地配線との間に電流経路を構成する第2のNチャネル型トランジスタと、を備える。 - 請求項2の半導体装置において、
前記第1の保護回路に対し前記1つの辺に沿う方向に配置される第3のESD保護回路を備え、
前記第3のESD保護回路は、前記第1の抵抗の他端が入力される第3のインバータと、前記第3のインバータの出力にゲート電極が接続され前記第1の電源配線と前記第1の接地配線との間に電流経路を構成する第3のNチャネル型トランジスタと、を備える。 - 請求項2の半導体装置において、
前記第1のパッドは平面視で前記第1の入出力回路が形成される領域に重なるように配置され、
前記第2のパッドは平面視で前記第2の入出力回路が形成される領域に重なるように配置される。 - 請求項8の半導体装置において、
前記第1のパッドは平面視で前記第1の入出力回路が形成される領域および前記第2の入出力回路が形成される領域に重なるように配置され、
前記第2のパッドは平面視で前記第2の入出力回路が形成される領域および前記第1の入出力回路が形成される領域に重なるように配置される。 - 請求項2の半導体装置において、
前記第1のパッドは平面視で前記第1のESD保護回路が形成される領域よりも前記1つの辺に近い側に配置され、
前記第2のパッドは平面視で前記第1のESD保護回路が形成される領域よりも前記1つの辺に近い側に配置される。 - 請求項5の半導体装置において、
前記第1の電源配線は、前記1つの辺に沿う方向に延在する第3および第4の電源配線を有し、
前記第1の接地配線は、前記1つの辺に沿う方向に延在する第3および第4の接地配線を有し、
前記第3の電源配線は前記第1のダイオードのカソードと前記第3のダイオードのカソードとに接続され、
前記第3の接地配線は前記第2のダイオードのアノードと前記第3のダイオードのアノードとに接続され、
前記第4の電源配線は前記第1の抵抗の一端と前記第1のNチャネル型トランジスタに接続され、
前記第4の接地配線は前記第1の容量の他端と前記第1のNチャネル型トランジスタとに接続される。 - 請求項11の半導体装置において、
前記チップ端部側から前記第4の接地配線、前記第4の電源配線、前記第3の接地配線、前記第3の電源配線の順に配置される。 - 請求項11の半導体装置において、
前記チップ端部側から前記第4の電源配線、前記第4の接地配線、前記第3の接地配線、前記第3の電源配線の順に配置される。 - 請求項2の半導体装置において、
第2の電源パッドに接続される第2の電源配線と、
第2の接地パッドに接続される第2の接地配線と、
前記第1の入出力回路に対しチップ縁辺に沿う方向に配置される第3のESD保護回路と、
を備え、
前記第3のESD保護回路は、前記第2の電源配線に一端が接続される第3の抵抗と、前記第3の抵抗の他端に一端が接続され前記第2の接地配線に他端が接続される第3の容量と、前記第3の抵抗の他端が入力される第3のインバータと、前記第3のインバータの出力にゲート電極が接続され前記第2の電源配線と前記第2の接地配線との間に電流経路構成する第2のNチャネル型トランジスタと、前記第2の接地配線にアノードが接続され前記第2の電源配線にカソードが接続される第4のダイオードと、を備え、 - 請求項14の半導体装置において、
前記第1の接地配線と前記第2の接地配線とを接続するブリッジ回路を備え、
前記ブリッジ回路は、前記第1の接地配線にアノードが接続され前記第2の接地配線にカソードが接続される第5のダイオードと、前記第2の接地配線にアノードが接続され前記第1の接地配線にカソードが接続される第6のダイオードと、を備える。 - 半導体装置は、
第1の電源パッドと第1の接地パッドとに接続される第1の電源ドメインと、
第2の電源パッドと第2の接地パッドとに接続される第2の電源ドメインと、
を備え、
前記第1の電源ドメインは、
第1のパッドに接続される第1の入出力回路と、
前記第1の入出力回路に対しチップ端部が構成する1つの辺に沿う方向に配置され、第2のパッドに接続される第2の入出力回路と、
前記第1および第2の入出力回路の前記チップ端部側の近傍に配置される第1のESD保護回路と、
を備え、
前記第1のESD保護回路は、第1の抵抗と、第1の容量と、第1のインバータと、第1のNチャネル型トランジスタと、を備え、
前記第2の電源ドメインは、
前記第1の入出力回路に対しチップ縁辺に沿う方向に配置される第2のESD保護回路と、
を備え、
前記第2のESD保護回路は、第2の抵抗と、第2の容量と、第2のインバータと、第2のNチャネル型トランジスタと、第4のダイオードと、を備え、
前記第1の電源ドメインと前記第2の電源ドメインの間に前記第1の接地配線と前記第2の接地配線とを接続するブリッジ回路を備える。 - 請求項16の半導体装置において、
第1の電源パッドに接続される第1の電源配線と、
第1の接地パッドに接続される第1の接地配線と、
を備え、
前記第1および第2の入出力回路は、それぞれ、信号配線にアノードが接続され第1の電源配線にカソードが接続される第1のダイオードと、第1の接地配線にアノードが接続され前記信号配線にカソードが接続される第2のダイオードと、前記信号配線に接続される出力回路または入力回路と、を備え、
前記第1の抵抗の一端は前記第1の電源配線に接続され、
前記第1の抵抗の他端は前記第1の容量の一端に接続され、
前記第1の容量の他端は前記第1の接地配線に接続され、
前記第1の抵抗の他端は第1のインバータの入力に接続され、
前記第1のインバータの出力は第1のNチャネル型トランジスタのゲート電極に接続され、
前記第1のNチャネル型トランジスタは前記第1の電源配線と前記第1の接地配線との間に電流経路を構成するようにされる。 - 請求項17の半導体装置において、
前記第1の入出力回路と前記第2の入出力回路との間に配置され、前記第1の接地配線にアノードが接続され前記第1の電源配線にカソードが接続される第3のダイオードを備える。 - 請求項17の半導体装置において、
前記第1の接地配線と前記第2の接地配線とを接続するブリッジ回路を備え、
前記ブリッジ回路は、前記第1の接地配線にアノードが接続され前記第2の接地配線にカソードが接続される第5のダイオードと、前記第2の接地配線にアノードが接続され前記第1の接地配線にカソードが接続される第6のダイオードと、を備え、 - 請求項16の半導体装置において、
前記第2の電源ドメインの前記1つの辺に沿う方向の長さは前記第1の電源ドメインの前記1つの辺に沿う方向の長さよりも小さい。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20210175172A1 (en) * | 2018-08-28 | 2021-06-10 | Socionext Inc. | Semiconductor integrated circuit device |
DE102022211502A1 (de) | 2021-10-29 | 2023-05-04 | Renesas Electronics Corporation | Halbleitervorrichtung |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10146388B2 (en) * | 2016-03-08 | 2018-12-04 | Synaptics Incorporated | Capacitive sensing in an LED display |
JP6998650B2 (ja) | 2016-08-10 | 2022-01-18 | 株式会社日本製鋼所 | 接合基板、弾性表面波素子、弾性表面波デバイスおよび接合基板の製造方法 |
JP7224094B2 (ja) | 2017-06-26 | 2023-02-17 | 太陽誘電株式会社 | 弾性波共振器、フィルタおよびマルチプレクサ |
WO2020017183A1 (ja) | 2018-07-20 | 2020-01-23 | ソニー株式会社 | 微小粒子測定用スペクトロメータ、該微小粒子測定用スペクトロメータを用いた微小粒子測定装置及び微小粒子測定用光電変換システムの校正方法 |
JP7268728B2 (ja) * | 2019-05-23 | 2023-05-08 | 株式会社ソシオネクスト | 半導体装置 |
US20210296306A1 (en) | 2020-03-18 | 2021-09-23 | Mavagail Technology, LLC | Esd protection for integrated circuit devices |
US11296503B1 (en) * | 2020-12-29 | 2022-04-05 | Vanguard International Semiconductor Corporation | Electrostatic discharge protection circuits and semiconductor circuits |
CN113437062B (zh) * | 2021-06-23 | 2023-05-12 | 吉安砺芯半导体有限责任公司 | 静电防护主动触发电路及电子设备 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0689973A (ja) * | 1992-07-24 | 1994-03-29 | Kawasaki Steel Corp | 半導体集積回路 |
JP2003530698A (ja) * | 2000-04-10 | 2003-10-14 | モトローラ・インコーポレイテッド | 静電放電(esd)保護回路 |
JP2005536046A (ja) * | 2002-08-09 | 2005-11-24 | フリースケール セミコンダクター インコーポレイテッド | 静電気放電保護回路及び動作方法 |
WO2006011292A1 (ja) * | 2004-07-28 | 2006-02-02 | Matsushita Electric Industrial Co., Ltd. | 半導体装置 |
JP2013021249A (ja) * | 2011-07-14 | 2013-01-31 | Toshiba Corp | 半導体集積装置 |
JP2013183107A (ja) * | 2012-03-02 | 2013-09-12 | Renesas Electronics Corp | 半導体装置 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6078068A (en) * | 1998-07-15 | 2000-06-20 | Adaptec, Inc. | Electrostatic discharge protection bus/die edge seal |
JP2003031669A (ja) * | 2001-07-13 | 2003-01-31 | Ricoh Co Ltd | 半導体装置 |
JP4763324B2 (ja) * | 2005-03-30 | 2011-08-31 | Okiセミコンダクタ株式会社 | 静電保護回路及び該静電保護回路を含む半導体装置 |
JP5312849B2 (ja) * | 2008-06-06 | 2013-10-09 | ルネサスエレクトロニクス株式会社 | 集積回路 |
JP2010010419A (ja) | 2008-06-27 | 2010-01-14 | Nec Electronics Corp | 半導体装置 |
JP2010147282A (ja) * | 2008-12-19 | 2010-07-01 | Renesas Technology Corp | 半導体集積回路装置 |
US7911752B1 (en) * | 2009-10-29 | 2011-03-22 | Ememory Technology Inc. | Programming PAD ESD protection circuit |
JP2012253266A (ja) * | 2011-06-06 | 2012-12-20 | Sony Corp | 半導体集積回路 |
JP5896682B2 (ja) | 2011-10-18 | 2016-03-30 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
CN103151346B (zh) * | 2011-12-07 | 2016-11-23 | 阿尔特拉公司 | 静电放电保护电路 |
CN105229782B (zh) | 2013-05-21 | 2018-05-08 | 瑞萨电子株式会社 | 半导体集成电路装置 |
-
2015
- 2015-06-19 CN CN201580078318.4A patent/CN107408533B/zh active Active
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0689973A (ja) * | 1992-07-24 | 1994-03-29 | Kawasaki Steel Corp | 半導体集積回路 |
JP2003530698A (ja) * | 2000-04-10 | 2003-10-14 | モトローラ・インコーポレイテッド | 静電放電(esd)保護回路 |
JP2005536046A (ja) * | 2002-08-09 | 2005-11-24 | フリースケール セミコンダクター インコーポレイテッド | 静電気放電保護回路及び動作方法 |
WO2006011292A1 (ja) * | 2004-07-28 | 2006-02-02 | Matsushita Electric Industrial Co., Ltd. | 半導体装置 |
JP2013021249A (ja) * | 2011-07-14 | 2013-01-31 | Toshiba Corp | 半導体集積装置 |
JP2013183107A (ja) * | 2012-03-02 | 2013-09-12 | Renesas Electronics Corp | 半導体装置 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20210175172A1 (en) * | 2018-08-28 | 2021-06-10 | Socionext Inc. | Semiconductor integrated circuit device |
US11699660B2 (en) * | 2018-08-28 | 2023-07-11 | Socionext Inc. | Semiconductor integrated circuit device |
DE102022211502A1 (de) | 2021-10-29 | 2023-05-04 | Renesas Electronics Corporation | Halbleitervorrichtung |
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