WO2016197403A1 - 基于氧化物半导体薄膜晶体管的goa电路 - Google Patents

基于氧化物半导体薄膜晶体管的goa电路 Download PDF

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WO2016197403A1
WO2016197403A1 PCT/CN2015/082010 CN2015082010W WO2016197403A1 WO 2016197403 A1 WO2016197403 A1 WO 2016197403A1 CN 2015082010 W CN2015082010 W CN 2015082010W WO 2016197403 A1 WO2016197403 A1 WO 2016197403A1
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Prior art keywords
thin film
film transistor
electrically connected
node
gate
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PCT/CN2015/082010
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English (en)
French (fr)
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戴超
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深圳市华星光电技术有限公司
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Priority to US14/777,521 priority Critical patent/US9767751B2/en
Priority to KR1020177013215A priority patent/KR101933333B1/ko
Priority to GB1706061.7A priority patent/GB2545856B/en
Priority to JP2017542113A priority patent/JP6472065B2/ja
Publication of WO2016197403A1 publication Critical patent/WO2016197403A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a GOA circuit based on an oxide semiconductor thin film transistor.
  • LCD Liquid crystal display
  • PDAs personal digital assistants
  • digital cameras computer screens or laptop screens, etc.
  • the active matrix liquid crystal display comprises a plurality of pixels, each of which is electrically connected to a thin film transistor (TFT), a thin film transistor.
  • TFT thin film transistor
  • a gate is connected to the horizontal scanning line
  • a drain is connected to the vertical data line
  • a source is connected to the pixel electrode.
  • the Gate Driver on Array (GOA) technology utilizes an existing Array process of a thin film transistor liquid crystal display to fabricate a gate row scan driving circuit on a TFT array substrate to realize progressive scan of the gate. Drive mode.
  • GOA technology can reduce the bonding process of external integrated circuits (ICs), increase the productivity and reduce the cost of products, and make LCD panels more suitable for narrow-frame or borderless display products.
  • Indium Gallium Zinc Oxide is an amorphous oxide containing indium, gallium and zinc.
  • the carrier mobility is 20 to 30 times that of amorphous silicon, which can greatly improve the TFT to pixel electrode.
  • the charge and discharge rate increases the response speed of the pixel, achieving a faster refresh rate, and the faster response also greatly increases the line scan rate of the pixel, making ultra-high resolution possible in the TFT-LCD.
  • IGZO displays have higher energy efficiency levels and are more efficient due to the reduced number of transistors and improved light transmission per pixel.
  • oxide semiconductor thin film transistors such as IGZO
  • panel peripheral integrated circuits based on oxide semiconductor thin film transistors have also become a focus of attention.
  • the oxide semiconductor thin film transistor has a high carrier mobility, its threshold voltage value is about 0 V, and the swing of the subthreshold region is small, and the gate and source of many TFT elements in the GOA circuit are off state. Between the poles The voltage Vgs is usually 0V, which increases the design difficulty of the GOA circuit based on the oxide semiconductor thin film transistor.
  • Some scan driving circuits suitable for the amorphous silicon semiconductor thin film transistor are applied to the GOA circuit based on the oxide semiconductor thin film transistor. There will be some functional issues.
  • the oxide semiconductor thin film transistor sometimes has a tendency to decrease the threshold voltage to a negative value, which will directly lead to the failure of the GOA circuit based on the oxide semiconductor thin film transistor.
  • the threshold voltage of the oxide semiconductor thin film transistor will move to a negative value, which will cause the GOA circuit to fail; likewise, under the electrical stress of some light, the threshold voltage of the oxide semiconductor thin film transistor will go to Negative values move. Therefore, designing a GOA circuit based on an oxide semiconductor thin film transistor must consider the influence of the threshold voltage drift of the TFT.
  • an existing oxide semiconductor thin film transistor-based GOA circuit for the above problem includes a plurality of cascaded GOA unit circuits, and each stage of the GOA unit circuit includes: a pull-up control module 100 The pull-up module 200, the downlink module 300, the first pull-down module 400, the bootstrap capacitor module 500, and the pull-down maintenance module 600.
  • the existing oxide semiconductor thin film transistor-based GOA circuit still has a certain problem: the pull-down maintaining module 600 uses the first node Q(N) signal to control its pull-down and turn-off capability, and the component threshold voltage is positive.
  • the pull-down maintenance module 600 When the pull-down maintenance module 600 is weakened by the potential of the first node Q(N), it cannot be normally and effectively turned off, so that the first node Q(N) cannot be normally raised to a high potential during the action, thereby triggering the entire GOA circuit. Poor functional.
  • the present invention provides a GOA circuit based on an oxide semiconductor thin film transistor, comprising: a plurality of cascaded GOA unit circuits, each stage of the GOA unit circuit comprising: a pull-up control module, and a pull-up Module, downlink module, first pull-down module, bootstrap capacitor module, and pull-down maintenance module;
  • N be a positive integer, in addition to the first stage GOA unit circuit, in the Nth stage GOA unit circuit:
  • the pull-up control module includes: an eleventh thin film transistor, the gate of the eleventh thin film transistor receives a level-transmitting signal of the upper-stage N-1th GOA unit circuit, and the source is electrically connected to the constant voltage a potential, a drain electrically connected to the first node;
  • the pull-up module includes: a twenty-first thin film transistor, the twenty-first thin film transistor The gate is electrically connected to the first node, the source is electrically connected to the mth clock signal, and the drain outputs the scan driving signal;
  • the down-transmission module includes: a 22nd thin film transistor, the gate of the 22nd thin film transistor is electrically connected to the first node, the source is electrically connected to the mth clock signal, and the drain output is transmitted signal;
  • the first pull-down module includes: a forty-th thin film transistor, the gate and the source of the forty-th thin film transistor are electrically connected to the first node, and the drain is electrically connected to the forty-first thin film transistor a fourth eleventh thin film transistor, the gate of the forty-th thin film transistor is electrically connected to the m+2th clock signal, and the source input scan driving signal;
  • the bootstrap capacitor module includes: a capacitor, one end of the capacitor is electrically connected to the first node, and the other end is electrically connected to the scan driving signal;
  • the pull-down maintaining module includes at least a 51st thin film transistor, wherein a gate and a source of the 51st thin film transistor are electrically connected to a constant voltage high potential, and a drain is electrically connected to the fourth node; a fifty-two thin film transistor, the gate of the fifty-second thin film transistor is electrically connected to the first node, the drain is electrically connected to the fourth node, and the source is electrically connected to the first negative potential; a thin film transistor, the gate of the fifty-third thin film transistor is electrically connected to the fourth node, the source is electrically connected to the constant voltage high potential, the drain is electrically connected to the second node; the fifty-fourth thin film transistor, The gate of the fifty-fourth thin film transistor is electrically connected to the first node, the source is electrically connected to the second node, the drain is electrically connected to the fifth node, and the seventh thirty-th thin film transistor is The gate of the seventy-three thin film transistor is electrically connected to the fourth node, the source
  • the constant voltage low potential is lower than the first negative potential
  • All of the thin film transistors in each stage of the GOA unit circuit are oxide semiconductor thin film transistors.
  • the pull-down maintaining module further includes: a fifty-sixth thin film transistor, the gate of the fifty-sixth thin film transistor is connected to the level-transmitting signal of the upper-stage N-1th GOA unit circuit) or the upper-level Nth
  • the scan driving signal of the -1 stage GOA unit circuit is electrically connected to the fifth node, and the drain is electrically connected to the constant voltage low potential.
  • the pull-down maintaining module further includes: a fifty-sixth thin film transistor, the gate of the fifty-sixth thin film transistor is connected to the level-transmitting signal of the upper-stage N-1th GOA unit circuit or the upper-level N-th a scan driving signal of the first-stage GOA unit circuit, the source is electrically connected to the fifth node, the drain is electrically connected to the constant voltage low potential; and the fifty-seventh thin film transistor is connected to the gate of the fifty-seventh thin film transistor a level-transmitted signal of the upper-stage N-1th GOA unit circuit or a scan driving signal of the upper-stage N-1th-level GOA unit circuit, the source is electrically connected to the second node, and the drain is electrically connected to the Five nodes.
  • a fifty-sixth thin film transistor the gate of the fifty-sixth thin film transistor is connected to the level-transmitting signal of the upper-stage N-1th GOA unit circuit or the upper-level N-th a scan driving signal of the first
  • a gate of the eleventh thin film transistor is connected to a scan enable signal, and a gate of the fifty-fifth thin film transistor is connected Enter the scan enable signal.
  • a gate of the eleventh thin film transistor is connected to a scan enable signal, and a gate of the fifty-fifth thin film transistor is connected The scan enable signal is input, and the gate of the fifty-sixth thin film transistor is connected to the scan enable signal.
  • a gate of the eleventh thin film transistor is connected to a scan enable signal, and a gate of the fifty-fifth thin film transistor is connected
  • the scan enable signal is input, the gate of the fifty-sixth thin film transistor is connected to the scan enable signal, and the gate of the fifty-seventh thin film transistor is connected to the scan enable signal.
  • the fifty-first thin film transistor, the fifty-second thin film transistor, the fifty-third thin film transistor, the fifty-fourth thin film transistor, the seventy-third thin film transistor, and the seventy-fourth thin film transistor are formed.
  • a dual inverter, the fifty-first thin film transistor, the fifty-second thin film transistor, the fifty-third thin film transistor, and the fifty-fourth thin film transistor constitute a main inverter, and the seventy-third thin film transistor And the seventy-fourth thin film transistor constitutes an auxiliary inverter.
  • the clock signal includes four clock signals: a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal.
  • the m+2th clock signal is a first clock signal
  • the mth clock signal is a fourth clock signal
  • the m+th The two clock signals are the second clock signal.
  • All of the thin film transistors in each stage of the GOA unit circuit are IGZO thin film transistors.
  • the present invention also provides a GOA circuit based on an oxide semiconductor thin film transistor, comprising a plurality of cascaded GOA unit circuits, each stage GOA unit circuit comprising: a pull-up control module, a pull-up module, a downlink module, and a first Pull-down module, bootstrap capacitor module, and pull-down maintenance module;
  • N be a positive integer, in addition to the first stage GOA unit circuit, in the Nth stage GOA unit circuit:
  • the pull-up control module includes: an eleventh thin film transistor, the gate of the eleventh thin film transistor receives a level-transmitting signal of the upper-stage N-1th GOA unit circuit, and the source is electrically connected to the constant voltage a potential, a drain electrically connected to the first node;
  • the pull-up module includes: a 21st thin film transistor, a gate of the 21st thin film transistor is electrically connected to the first node, a source is electrically connected to the mth clock signal, and a drain output is scanned and driven. signal;
  • the down-transmission module includes: a 22nd thin film transistor, the gate of the 22nd thin film transistor is electrically connected to the first node, the source is electrically connected to the mth clock signal, and the drain output is transmitted signal;
  • the first pull-down module includes: a forty-th thin film transistor, the gate and the source of the forty-th thin film transistor are electrically connected to the first node, and the drain is electrically connected to the forty-first thin film transistor a fourth eleventh thin film transistor, the gate of the forty-th thin film transistor is electrically connected to the m+2th clock signal, and the source input scan driving signal;
  • the bootstrap capacitor module includes: a capacitor, one end of the capacitor is electrically connected to the first node, and the other end is electrically connected to the scan driving signal;
  • the pull-down maintaining module includes at least a 51st thin film transistor, wherein a gate and a source of the 51st thin film transistor are electrically connected to a constant voltage high potential, and a drain is electrically connected to the fourth node; a fifty-two thin film transistor, the gate of the fifty-second thin film transistor is electrically connected to the first node, the drain is electrically connected to the fourth node, and the source is electrically connected to the first negative potential; a thin film transistor, the gate of the fifty-third thin film transistor is electrically connected to the fourth node, the source is electrically connected to the constant voltage high potential, the drain is electrically connected to the second node; the fifty-fourth thin film transistor, The gate of the fifty-fourth thin film transistor is electrically connected to the first node, the source is electrically connected to the second node, the drain is electrically connected to the fifth node, and the seventh thirteenth thin film transistor, the seventh The gate of the thirteen thin film transistor is electrically connected to the fourth node, the source is electrically
  • the constant voltage low potential is lower than the first negative potential
  • All of the thin film transistors in each stage of the GOA unit circuit are oxide semiconductor thin film transistors
  • the clock signal includes four clock signals: a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal;
  • the m+2th clock signal is a first clock signal
  • the m+2 clock signals are second clock signals
  • all the thin film transistors in each stage of the GOA unit circuit are IGZO thin film transistors.
  • the present invention provides a GOA circuit based on an oxide semiconductor thin film transistor by adding fifty-fifth and fiftyth respectively corresponding to the fourth, fifth, and second nodes in the pull-down maintaining module a fifty-seventh thin film transistor, wherein the gates of the fifty-fifth, fifty-sixth, and fifty-seventh thin film transistors are connected to a level-transmitted signal of the upper-stage N-1th GOA unit circuit or
  • the scan driving signal of the upper N-1th GOA unit circuit is controlled by the level transmission signal of the upper N-1th GOA unit circuit or the scan driving signal of the upper N-1th GOA unit circuit
  • Fifty-fifth, fifty-sixth, and fifty-seventh when the first node is not fully lifted, the potentials of the fourth, fifth, and second nodes are pulled down, so that the pull-down maintenance module is quickly turned off to ensure the first
  • the normal rise of the node potential ensures that the first node is at a high potential during the action, thus ensuring
  • FIG. 1 is a circuit diagram of a conventional GOA circuit based on an oxide semiconductor thin film transistor
  • FIG. 2 is a circuit diagram of a first embodiment of a GOA circuit based on an oxide semiconductor thin film transistor of the present invention
  • FIG. 3 is a circuit diagram of a second embodiment of a GOA circuit based on an oxide semiconductor thin film transistor of the present invention.
  • FIG. 4 is a circuit diagram of a third embodiment of a GOA circuit based on an oxide semiconductor thin film transistor of the present invention.
  • FIG. 5 is a circuit diagram of a fourth embodiment of a GOA circuit based on an oxide semiconductor thin film transistor of the present invention.
  • FIG. 6 is a circuit diagram of a fifth embodiment of a GOA circuit based on an oxide semiconductor thin film transistor of the present invention.
  • FIG. 7 is a circuit diagram of a sixth embodiment of a GOA circuit based on an oxide semiconductor thin film transistor of the present invention.
  • FIG. 8 is a circuit diagram of a first-stage GOA unit circuit of the first and fourth embodiments of the GOA circuit based on the oxide semiconductor thin film transistor of the present invention
  • Figure 9 is a circuit diagram of a first stage GOA unit circuit of the second and fifth embodiments of the GOA circuit based on the oxide semiconductor thin film transistor of the present invention.
  • Figure 10 is a circuit diagram of a first stage GOA unit circuit of the third and sixth embodiments of the GOA circuit based on the oxide semiconductor thin film transistor of the present invention
  • FIG. 11 is a waveform diagram of an input signal and a key node of a GOA circuit based on an oxide semiconductor thin film transistor of the present invention.
  • FIG. 2 is a circuit diagram of a first embodiment of a GOA circuit based on an oxide semiconductor thin film transistor according to the present invention, including a plurality of cascaded GOA unit circuits, each of which includes: a pull-up control module 100, the pull-up module 200, the downlink module 300, the first pull-down module 400, the bootstrap capacitor module 500, and the pull-down maintenance module 600.
  • N be a positive integer, except for the first stage GOA unit circuit, in the Nth stage GOA unit In the road:
  • the pull-up control module 100 includes: an eleventh thin film transistor T11, the gate of the eleventh thin film transistor T11 receives the graded signal ST(N-1) of the upper N-1th stage GOA unit circuit, The source is electrically connected to the constant voltage high potential DCH, and the drain is electrically connected to the first node Q(N).
  • the pull-up module 200 includes: a 21st thin film transistor T21, the gate of the 21st thin film transistor T21 is electrically connected to the first node Q(N), and the source is electrically connected to the mth clock.
  • the down-going module 300 includes: a twenty-second thin film transistor T22, the gate of the second twelve-th thin film transistor T22 is electrically connected to the first node Q(N), and the source is electrically connected to the mth clock.
  • Signal CK(m) the drain output stage transmits signal ST(N).
  • the clock signal includes four clock signals: a first clock signal CK(1), a second clock signal CK(2), a third clock signal CK(3), and a fourth clock signal CK(4).
  • the mth clock signal CK(m) is the third clock signal CK(3)
  • the m+2th clock signal CK(m+2) is the first clock signal CK(1)
  • the mth clock signal CK(m) is the fourth clock signal CK(4)
  • the m+2th clock signal CK(m+2) is the second clock signal CK(2).
  • the first pull-down module 400 includes: a fourth thin film transistor T40, the gate and the source of the fourth thin film transistor T40 are electrically connected to the first node Q(N), and the drain is electrically connected to the drain
  • the fourth eleventh thin film transistor T41, the fourth eleventh thin film transistor T41, the gate of the forty-first thin film transistor T41 is electrically connected to the m+2th clock signal CK(m+2), the source The pole input scan drive signal G(N).
  • the bootstrap capacitor module 500 includes a capacitor Cb. One end of the capacitor Cb is electrically connected to the first node Q(N), and the other end is electrically connected to the scan driving signal G(N).
  • the pull-down maintaining module 600 includes: a 51st thin film transistor T51, the gate and the source of the 51st thin film transistor T51 are electrically connected to the constant voltage high potential DCH, and the drain is electrically connected to the fourth a node S(N); a fifty-second thin film transistor T52, a gate of the fifty-second thin film transistor T52 is electrically connected to the first node Q(N), and a drain is electrically connected to the fourth node S(N)
  • the source is electrically connected to the first negative potential VSS;
  • the fifty-third thin film transistor T53, the gate of the fifty-third thin film transistor T53 is electrically connected to the fourth node S(N), and the source is electrically Connected to the constant voltage high potential DCH, the drain is electrically connected to the second node P(N); the fifty-fourth thin film transistor T54, the gate of the fifty-fourth thin film transistor T54 is electrically connected to the first node Q (N), the drain is electrically connected to the second node
  • the forty-second thin film transistor T42 Connected to the first negative potential VSS; the forty-second thin film transistor T42, the gate of the forty-second thin film transistor T42 is electrically connected to the second node P(N), and the drain is electrically connected to the first node Q (N), the source is electrically connected to the third node T(N); the thirty-second thin film transistor T32, the gate of the thirty-second thin film transistor T32 is electrically connected to the second node P(N), The drain is electrically connected to the scan driving signal G(N), the source is electrically connected to the first negative potential VSS, and the seventh fifteenth thin film transistor T75 is electrically connected to the gate of the seventy-fifth thin film transistor T75.
  • the source is electrically connected to the third node T (N), the drain is electrically connected to the constant voltage high potential DCH; the 76th thin film transistor T76, the 76th thin film transistor T76 The gate is electrically connected to the second node P(N), the drain is electrically connected to the third node T(N), and the source is electrically connected to the constant voltage low potential DCL.
  • the fifty-first thin film transistor T51, the fifty-second thin film transistor T52, the fifty-third thin film transistor T53, the fifty-fourth thin film transistor T54, the seventy-third thin film transistor T73, and the seventy-fourth The thin film transistor T74 constitutes a double inverter F1, wherein the fifty-first thin film transistor T51, the fifty-second thin film transistor T52, the fifty-third thin film transistor T53, and the fifty-fourth thin film transistor T54 constitute a main reverse
  • the phase device, the seventy-third thin film transistor T73, and the seventy-fourth thin film transistor T74 constitute an auxiliary inverter.
  • the constant voltage low potential DCL is lower than the first negative potential VSS.
  • All of the thin film transistors in each stage of the GOA unit circuit are oxide semiconductor thin film transistors.
  • the oxide semiconductor thin film transistor is an IGZO thin film transistor.
  • the gate of the eleventh thin film transistor T11 is connected to the scan enable signal STV, and the fifty-fifth film
  • the gate of the transistor T55 is connected to the scan enable signal STV, and the source of the 21st thin film transistor T21 and the source of the 22nd thin film transistor T22 are electrically connected to the first clock signal CK(1).
  • the gate of the forty-th thin film transistor T41 is electrically connected to the third clock signal CK(3), and the source is input to the first-stage scan driving signal G(1).
  • the working process of the first embodiment of the GOA circuit based on the oxide semiconductor thin film transistor of the present invention is: the scan enable signal STV starts the first stage GOA unit circuit, and the first stage GOA unit circuit The scan drive is sequentially performed step by step to the last stage GOA unit circuit.
  • N be a positive integer, taking the Nth stage GOA unit circuit as an example.
  • the level signal ST(N-1) of the upper N-1th GOA unit circuit is directed to the eleventh thin film transistor T11.
  • the first-stage GOA unit circuit supplies a high potential to the gates of the eleventh thin film transistor T11 and the fifty-fifth thin film transistor T55 by the scan enable signal STV
  • the eleventh thin film transistor T11 and the fifty-fifth thin film transistor T55 are turned on, and the constant voltage high potential DCH raises the first node Q(N) to a high potential through the eleventh thin film transistor T11, and charges the capacitor Cb, and at the same time
  • the fifty-five thin film transistor T55 pulls the potential of the fourth node S(N) to the first negative potential VSS, so that the first node N-1 can be utilized without the first node Q(N) being fully lifted.
  • the stage signal ST(N-1) of the stage GOA unit circuit controls the fifty-fifth thin film transistor T55 to be turned on, rapidly pulls down the potential of the fourth node S(N), and quickly turns off the pull-down maintaining module 600 to ensure the first node Q. (N) can be raised to a high potential, at which time the fourth node S(N) is low, the first node Q(N) is high, and the fiftyth in the main inverter of the dual inverter F1
  • the two thin film transistors T52 and the fifty-fourth thin film transistor T54 are both turned on, and the fifty-third thin film transistor T53 is turned off.
  • the seventy-fourth thin film transistor T74 in the auxiliary main inverter is turned on, the seventy-third thin film transistor T73 is turned off, and the potential of the second node P(N) is pulled down to be lower than the first negative potential VSS. Depressing the potential DCL, the forty-second, thirty-second, and seventy-sixth thin film transistors T42, T32, and T76 are turned off to ensure stable output of the first node Q(N) and the scan driving signal G(N). .
  • the level signal ST(N-1) of the upper N-1th GOA unit circuit is turned to a low level, the eleventh thin film transistor T11 is turned off, and the first node Q(N) is maintained at a high level by the capacitor Cb.
  • the potential is such that the twenty-first thin film transistor T21 and the twenty-second thin film transistor T22 are turned on.
  • the mth clock signal CK(m) supplies a high potential to the source of the twenty-first thin film transistor T21 and the source of the twenty-second thin film transistor T22, and is output through the drain of the twenty-first thin film transistor T21.
  • the first node Q(N) is discharged through the pull-down module 400, transitions to a low potential, the scanning ends, and the circuit enters an inactive period, at which time the first node Q(N) is at a low potential, and the main of the dual inverter F1
  • the fifty-second thin film transistor T52 and the fifty-fourth thin film transistor T54 in the inverter are both turned off, and the fifty-first thin film transistor T51 is turned on, so that the potential of the fourth node S(N) becomes a high potential
  • the fifty-third thin film transistor T53 is turned on, the seventy-fourth thin film transistor T74 in the auxiliary main inverter is turned off, and the seventy-third thin film transistor T73 is turned on to prevent the fifty-fourth thin film transistor T54 from leaking, so that the second node
  • the potential of P(N) is kept at the constant voltage high potential DCH, and then the forty-second, thirty-second, and seventy-sixth thin film transistors T
  • a fifty-fifth thin film transistor T55 is added to the key node four node S(N) of the pull-down maintaining module 600, and the fifty-fifth thin film transistor T55 is subjected to the first level N-1.
  • the stage pass signal ST(N-1) of the stage GOA unit circuit controls the potential of the fourth node S(N) to be pulled down to the first negative potential VSS, so that the first node Q(N) is not fully raised yet. Pulling down the potential of the fourth node S(N) point and quickly turning off the pull-down maintaining module 600 can avoid that the threshold voltage of the fifty-second thin film transistor T52 is biased, so that the first node Q(N) is not completely completed.
  • the pull-down maintenance module 600 cannot be properly shut down, which ultimately leads to a problem of poor function of the entire GOA circuit.
  • FIG. 3 and FIG. 11 is a second embodiment of the GOA circuit based on the oxide semiconductor thin film transistor of the present invention.
  • the second embodiment is different from the first embodiment in that the pull-down maintaining module 600 further includes: The fifty-sixth thin film transistor T56, the gate of the fifty-sixth thin film transistor T56 is connected to the level-transmitting signal ST(N-1) of the upper-stage N-1th GOA unit circuit, and the source is electrically connected to The fifth node K(N) is electrically connected to the constant voltage low potential DCL.
  • the fifth The sixteen thin film transistor T56 When the level signal ST(N-1) of the upper N-1th GOA unit circuit is high, the fifth The sixteen thin film transistor T56 is turned on, pulls the potential of the fifth node K(N) to the constant voltage low potential DCL, and then completes the fifth node K (N) without the first node Q(N) being fully lifted. The pull-down of the potential.
  • the gate of the eleventh thin film transistor T11 is connected to the scan enable signal STV, and the fifty-fifth film
  • the gates of the transistor T55 and the 56th thin film transistor T56 are connected to the scan enable signal STV, and the sources of the 21st thin film transistor T21 and the source of the 22nd thin film transistor T22 are electrically connected to the first
  • the gate clock signal CK(1), the gate of the forty-first thin film transistor T41 is electrically connected to the third clock signal CK(3), and the source input scan driving signal G(1).
  • the pull-down maintaining module 600 further includes: The fifty-seventh thin film transistor T57, the gate of the fifty-seventh thin film transistor T57 is connected to the level transmission signal ST(N-1) of the upper N-1th stage GOA unit circuit, and the source is electrically connected to The second node P(N) is electrically connected to the fifth node K(N).
  • the gate of the eleventh thin film transistor T11 is connected to the scan enable signal STV
  • the fiftyth The gates of the fifth thin film transistor T55, the fifty-sixth thin film transistor T56, and the fifty-seventh thin film transistor T57 are connected to the scan enable signal STV
  • the source is electrically connected to the first clock signal CK(1)
  • the gate of the 41st thin film transistor T41 is electrically connected to the third clock signal CK(3)
  • the source is input to the scan driving signal G ( 1).
  • the rest of the circuit structure and working process are the same as those in the first embodiment, and details are not described herein again.
  • FIG. 5, FIG. 8 and FIG. 11 is a fourth embodiment of a GOA circuit based on an oxide semiconductor thin film transistor according to the present invention.
  • the fourth embodiment is different from the first embodiment in that the fifty-fifth
  • the gate of the thin film transistor T55 is connected to the scan driving signal G(N-1) of the upper N-1th stage GOA unit circuit, that is, in the case where the first node Q(N) is not fully lifted, the previous one is utilized.
  • the scan driving signal G(N-1) of the stage N-1th GOA unit circuit controls the potential of the fifth node S(N) pulled down by the fifty-fifth thin film transistor T55.
  • the rest are the same as the first embodiment, and will not be described again here.
  • FIG. 6, FIG. 9 and FIG. 11, are the fifth embodiment of the GOA circuit based on the oxide semiconductor thin film transistor of the present invention.
  • the fifth embodiment is different from the second embodiment in that the fifty-fifth The gates of the thin film transistor T55 and the fifty-sixth thin film transistor T56 are connected to the scan driving signal G(N-1) of the upper N-1th stage GOA unit circuit, that is, the first node Q(N) is not completely completed.
  • the fifth driving circuit G55 and the fifty-sixth thin film transistor T56 are respectively controlled to pull down the fourth node S by using the scanning driving signal G(N-1) of the upper N-1th GOA unit circuit ( N) and the potential of the fifth node K(N).
  • the rest are the same as the second embodiment, and will not be described again here.
  • FIG. 7, FIG. 10 and FIG. 11 is a sixth embodiment of a GOA circuit based on an oxide semiconductor thin film transistor according to the present invention.
  • the sixth embodiment is different from the third embodiment in that the fifty-fifth The gates of the thin film transistor T55, the fifty-sixth thin film transistor T56, and the fifty-seventh thin film transistor T57 are connected to the scan driving signal G(N-1) of the upper N-1th stage GOA unit circuit, that is, at the first When the node Q(N) is not fully raised, the fifty-fifth thin film transistor T55 and the fifty-sixth thin film transistor are controlled by the scan driving signal G(N-1) of the upper N-1th GOA unit circuit.
  • T56 and the fifty-seventh thin film transistor T57 pull down the potentials of the fourth node S(N), the fifth node K(N), and the second node P(N), respectively.
  • the rest are related to the third implementation The examples are the same and will not be described here.
  • the present invention provides a GOA circuit based on an oxide semiconductor thin film transistor by adding fifty-fifth and fifty-sixth portions respectively corresponding to the fourth, fifth, and second nodes in the pull-down maintaining module.
  • a fifty-seventh thin film transistor wherein the gates of the fifty-fifth, fifty-sixth, and fifty-seventh thin film transistors are connected to the level-transmitted signal of the upper-stage N-1th-level GOA unit circuit or
  • the scan driving signal of the first-stage N-1th GOA unit circuit is controlled by the level-transmitting signal of the upper-stage N-1th GOA unit circuit or the scanning driving signal of the upper-stage N-1th GOA unit circuit.

Abstract

一种基于氧化物半导体薄膜晶体管的GOA电路，通过增设分别对应于下拉维持模块(600)中的第四、第五、第二节点(S(N)、K(N)、P(N))的第五十五、第五十六、第五十七薄膜晶体管(T55、T56、T57)，通过上一级第N-1级GOA单元电路的级传信号(ST(N-1))或上一级第N-1级GOA单元电路的扫描驱动信号(G(N-1))控制第五十五、第五十六、第五十七(T55、T56、T57)在第一节点(Q(N))还未完全抬升的情况下，下拉第四、第五、第二节点(S(N)、K(N)、P(N))的电位，实现快速地关闭下拉维持模块(600)，保证第一节点(Q(N))电位的正常抬升，确保在作用期间第一节点(Q(N))处于高电位，从而保证GOA电路的正常输出。

Description

基于氧化物半导体薄膜晶体管的GOA电路 技术领域
本发明涉及显示技术领域，尤其涉及一种基于氧化物半导体薄膜晶体管的GOA电路。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
主动矩阵式液晶显示器(Active Matrix Liquid Crystal Display，AMLCD)是目前最常用的显示装置，所述主动矩阵式液晶显示器包含多个像素，每个像素电性连接一个薄膜晶体管(TFT)，薄膜晶体管的栅极(Gate)连接至水平扫描线，漏极(Drain)连接至垂直方向的数据线，源极(Source)则连接至像素电极。在水平扫描线上施加足够的电压，会使得电性连接至该条水平扫描线上的所有TFT打开，从而数据线上的信号电压能够写入像素，控制不同液晶的透光度进而达到控制色彩与亮度的效果。阵列基板行驱动(Gate Driver on Array，GOA)技术是利用现有的薄膜晶体管液晶显示器的阵列(Array)制程将栅极行扫描驱动电路制作在TFT阵列基板上，实现对栅极逐行扫描的驱动方式。GOA技术能减少外接集成电路板(Integrated Circuit，IC)的焊接(bonding)工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)，是一种含有铟、镓和锌的非晶氧化物，载流子迁移率是非晶硅的20～30倍，可以大大提高TFT对像素电极的充放电速率，提高像素的响应速度，实现更快的刷新率，同时更快的响应也大大提高了像素的行扫描速率，使得超高分辨率在TFT-LCD中成为可能。另外，由于晶体管数量减少和提高了每个像素的透光率，IGZO显示器具有更高的能效水平，而且效率更高。
随着IGZO等氧化物半导体薄膜晶体管的发展，基于氧化物半导体薄膜晶体管的面板周边集成电路也成为关注的焦点。虽然氧化物半导体薄膜晶体管具有较高的载流子迁移率，但是其阈值电压值在0V左右，而且亚阈值区域的摆幅较小，而GOA电路在关态时很多TFT元件的栅极与源极之间 的电压Vgs通常为0V，这样就会增加基于氧化物半导体薄膜晶体管的GOA电路的设计难度，一些适用于非晶硅半导体薄膜晶体管的扫描驱动电路应用到基于氧化物半导体薄膜晶体管的GOA电路时就会存在一些功能性问题。另外，在某些外在因素的诱导和应力作用下，氧化物半导体薄膜晶体管有时候也会产生阈值电压往负值减小的趋势，这样将会直接导致基于氧化物半导体薄膜晶体管的GOA电路无法工作，例如，在高温下，氧化物半导体薄膜晶体管的阈值电压会往负值移动，这样会导致GOA电路失效；同样，在一些光照的电应力作用下，氧化物半导体薄膜晶体管的阈值电压会往负值移动。因此，设计基于氧化物半导体薄膜晶体管的GOA电路必须要考虑TFT阈值电压漂移的影响。
如图1所示，一种现有可行的针对上述问题的基于氧化物半导体薄膜晶体管的GOA电路，包括级联的多个GOA单元电路，每一级GOA单元电路均包括：上拉控制模块100、上拉模块200、下传模块300、第一下拉模块400、自举电容模块500、及下拉维持模块600。但该现有的基于氧化物半导体薄膜晶体管的GOA电路仍存在一定的问题：下拉维持模块600是利用第一节点Q(N)讯号来控制其下拉关闭的能力，在元件阈值电压偏正的情况时，下拉维持模块600受第一节点Q(N)电位控制的能力减弱，无法正常有效地关闭，从而导致作用期间第一节点Q(N)无法正常抬升到高电位，进而引发整个GOA电路的功能性不良。
发明内容
本发明的目的在于提供一种基于氧化物半导体薄膜晶体管的GOA电路，能够防止因为阈值电压偏正时导致的下拉维持模块无法正常关闭，保证GOA电路的正常输出。
为实现上述目的，本发明提供一种基于氧化物半导体薄膜晶体管的GOA电路，其特征在于，包括级联的多个GOA单元电路，每一级GOA单元电路均包括：上拉控制模块、上拉模块、下传模块、第一下拉模块、自举电容模块、及下拉维持模块；
设N为正整数，除第一级GOA单元电路以外，在第N级GOA单元电路中：
所述上拉控制模块包括：第十一薄膜晶体管，所述第十一薄膜晶体管的栅极接收上一级第N-1级GOA单元电路的级传信号，源极电性连接于恒压高电位，漏极电性连接于第一节点；
所述上拉模块包括：第二十一薄膜晶体管，所述第二十一薄膜晶体管 的栅极电性连接于第一节点，源极电性连接于第m条时钟信号，漏极输出扫描驱动信号；
所述下传模块包括：第二十二薄膜晶体管，所述第二十二薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第m条时钟信号，漏极输出级传信号；
所述第一下拉模块包括：第四十薄膜晶体管，所述第四十薄膜晶体管的栅极与源极均电性连接于第一节点，漏极电性连接于第四十一薄膜晶体管的漏极；第四十一薄膜晶体管，所述第四十一薄膜晶体管的栅极电性连接于第m+2条时钟信号，源极输入扫描驱动信号；
所述自举电容模块包括：电容，所述电容的一端电性连接于第一节点，另一端电性连接于扫描驱动信号；
所述下拉维持模块至少包括：第五十一薄膜晶体管，所述第五十一薄膜晶体管的栅极与源极均电性连接于恒压高电位，漏极电性连接于第四节点；第五十二薄膜晶体管，所述第五十二薄膜晶体管的栅极电性连接于第一节点，漏极电性连接于第四节点，源极电性连接于第一负电位；第五十三薄膜晶体管，所述第五十三薄膜晶体管的栅极电性连接于第四节点，源极电性连接于恒压高电位，漏极电性连接于第二节点；第五十四薄膜晶体管，所述第五十四薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于第五节点；第七十三薄膜晶体管)，所述第七十三薄膜晶体管的栅极电性连接于第四节点，源极电性连接于恒压高电位，漏极电性连接于第五节点；第七十四薄膜晶体管，所述第七十四薄膜晶体管的栅极电性连接于第一节点，源极电性连接于恒压低电位，漏极电性连接于第五节点；第五十五薄膜晶体管，所述第五十五薄膜晶体管的栅极接入上一级第N-1级GOA单元电路的级传信号或上一级第N-1级GOA单元电路的扫描驱动信号，源极电性连接于第四节点，漏极电性连接于第一负电位；第四十二薄膜晶体管，所述第四十二薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第一节点，漏极电性连接于第三节点；第三十二薄膜晶体管，所述第三十二薄膜晶体管的栅极电性连接于第二节点，源极电性连接于扫描驱动信号，漏极电性连接于第一负电位；第七十五薄膜晶体管，所述第七十五薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第三节点，漏极电性连接于恒压高电位；第七十六薄膜晶体管，所述第七十六薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第三节点，漏极电性连接于恒压低电位；
所述恒压低电位低于第一负电位；
所述每一级GOA单元电路中的所有薄膜晶体管均为氧化物半导体薄膜晶体管。
所述下拉维持模块还包括：第五十六薄膜晶体管，所述第五十六薄膜晶体管的栅极接入上一级第N-1级GOA单元电路的级传信号)或上一级第N-1级GOA单元电路的扫描驱动信号，源极电性连接于第五节点，漏极电性连接于恒压低电位。
所述下拉维持模块还包括：第五十六薄膜晶体管，所述第五十六薄膜晶体管的栅极接入上一级第N-1级GOA单元电路的级传信号或上一级第N-1级GOA单元电路的扫描驱动信号，源极电性连接于第五节点，漏极电性连接于恒压低电位；第五十七薄膜晶体管，所述第五十七薄膜晶体管的栅极接入上一级第N-1级GOA单元电路的级传信号或上一级第N-1级GOA单元电路的扫描驱动信号，源极电性连接于第二节点，漏极电性连接于第五节点。
在所述的基于氧化物半导体薄膜晶体管的GOA电路的第一级GOA单元电路中，所述第十一薄膜晶体管的栅极接入扫描启动信号，所述第五十五薄膜晶体管的栅极接入扫描启动信号。
在所述的基于氧化物半导体薄膜晶体管的GOA电路的第一级GOA单元电路中，所述第十一薄膜晶体管的栅极接入扫描启动信号，所述第五十五薄膜晶体管的栅极接入扫描启动信号，所述第五十六薄膜晶体管的栅极接入扫描启动信号。
在所述的基于氧化物半导体薄膜晶体管的GOA电路的第一级GOA单元电路中，所述第十一薄膜晶体管的栅极接入扫描启动信号，所述第五十五薄膜晶体管的栅极接入扫描启动信号，所述第五十六薄膜晶体管的栅极接入扫描启动信号，所述第五十七薄膜晶体管的栅极接入扫描启动信号。
所述下拉维持电路中，第五十一薄膜晶体管、第五十二薄膜晶体管、第五十三薄膜晶体管、第五十四薄膜晶体管、第七十三薄膜晶体管、及第七十四薄膜晶体管构成一双重反相器，所述第五十一薄膜晶体管、第五十二薄膜晶体管、第五十三薄膜晶体管、及第五十四薄膜晶体管构成主反相器，所述第七十三薄膜晶体管、及第七十四薄膜晶体管构成辅助反相器。
所述时钟信号包括四条时钟信号：第一时钟信号、第二时钟信号、第三时钟信号、及第四时钟信号。
当所述第m条时钟信号为第三时钟信号时，所述第m+2条时钟信号为第一时钟信号，当所述第m条时钟信号为第四时钟信号时，所述第m+2条时钟信号为第二时钟信号。
所述每一级GOA单元电路中的所有薄膜晶体管均为IGZO薄膜晶体管。
本发明还提供一种基于氧化物半导体薄膜晶体管的GOA电路，包括级联的多个GOA单元电路，每一级GOA单元电路均包括：上拉控制模块、上拉模块、下传模块、第一下拉模块、自举电容模块、及下拉维持模块；
设N为正整数，除第一级GOA单元电路以外，在第N级GOA单元电路中：
所述上拉控制模块包括：第十一薄膜晶体管，所述第十一薄膜晶体管的栅极接收上一级第N-1级GOA单元电路的级传信号，源极电性连接于恒压高电位，漏极电性连接于第一节点；
所述上拉模块包括：第二十一薄膜晶体管，所述第二十一薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第m条时钟信号，漏极输出扫描驱动信号；
所述下传模块包括：第二十二薄膜晶体管，所述第二十二薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第m条时钟信号，漏极输出级传信号；
所述第一下拉模块包括：第四十薄膜晶体管，所述第四十薄膜晶体管的栅极与源极均电性连接于第一节点，漏极电性连接于第四十一薄膜晶体管的漏极；第四十一薄膜晶体管，所述第四十一薄膜晶体管的栅极电性连接于第m+2条时钟信号，源极输入扫描驱动信号；
所述自举电容模块包括：电容，所述电容的一端电性连接于第一节点，另一端电性连接于扫描驱动信号；
所述下拉维持模块至少包括：第五十一薄膜晶体管，所述第五十一薄膜晶体管的栅极与源极均电性连接于恒压高电位，漏极电性连接于第四节点；第五十二薄膜晶体管，所述第五十二薄膜晶体管的栅极电性连接于第一节点，漏极电性连接于第四节点，源极电性连接于第一负电位；第五十三薄膜晶体管，所述第五十三薄膜晶体管的栅极电性连接于第四节点，源极电性连接于恒压高电位，漏极电性连接于第二节点；第五十四薄膜晶体管，所述第五十四薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于第五节点；第七十三薄膜晶体管，所述第七十三薄膜晶体管的栅极电性连接于第四节点，源极电性连接于恒压高电位，漏极电性连接于第五节点；第七十四薄膜晶体管，所述第七十四薄膜晶体管的栅极电性连接于第一节点，源极电性连接于恒压低电位，漏极电性连接于第五节点；第五十五薄膜晶体管，所述第五十五薄膜晶体管的栅极接 入上一级第N-1级GOA单元电路的级传信号或上一级第N-1级GOA单元电路的扫描驱动信号，源极电性连接于第四节点，漏极电性连接于第一负电位；第四十二薄膜晶体管，所述第四十二薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第一节点，漏极电性连接于第三节点；第三十二薄膜晶体管，所述第三十二薄膜晶体管的栅极电性连接于第二节点，源极电性连接于扫描驱动信号，漏极电性连接于第一负电位；第七十五薄膜晶体管，所述第七十五薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第三节点，漏极电性连接于恒压高电位；第七十六薄膜晶体管，所述第七十六薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第三节点，漏极电性连接于恒压低电位；
所述恒压低电位低于第一负电位；
所述每一级GOA单元电路中的所有薄膜晶体管均为氧化物半导体薄膜晶体管；
其中，所述时钟信号包括四条时钟信号：第一时钟信号、第二时钟信号、第三时钟信号、及第四时钟信号；
其中，当所述第m条时钟信号为第三时钟信号时，所述第m+2条时钟信号为第一时钟信号，当所述第m条时钟信号为第四时钟信号时，所述第m+2条时钟信号为第二时钟信号；
其中，所述每一级GOA单元电路中的所有薄膜晶体管均为IGZO薄膜晶体管。
本发明的有益效果：本发明提供了一种基于氧化物半导体薄膜晶体管的GOA电路，通过增设分别对应于下拉维持模块中的第四、第五、第二节点的第五十五、第五十六、第五十七薄膜晶体管，所述第五十五、第五十六、及第五十七薄膜晶体管的栅极均接入上一级第N-1级GOA单元电路的级传信号或上一级第N-1级GOA单元电路的扫描驱动信号，通过上一级第N-1级GOA单元电路的级传信号或上一级第N-1级GOA单元电路的扫描驱动信号控制第五十五、第五十六、及第五十七在第一节点还未完全抬升的情况下，下拉第四、第五、第二节点的电位，实现快速地关闭下拉维持模块，保证第一节点电位的正常抬升，确保在作用期间第一节点处于高电位，从而保证GOA电路的正常输出。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发 明加以限制。
附图中，
图1为一种现有的基于氧化物半导体薄膜晶体管的GOA电路的电路图；
图2为本发明基于氧化物半导体薄膜晶体管的GOA电路的第一实施例的电路图；
图3为本发明基于氧化物半导体薄膜晶体管的GOA电路的第二实施例的电路图；
图4为本发明基于氧化物半导体薄膜晶体管的GOA电路的第三实施例的电路图；
图5为本发明基于氧化物半导体薄膜晶体管的GOA电路的第四实施例的电路图；
图6为本发明基于氧化物半导体薄膜晶体管的GOA电路的第五实施例的电路图；
图7为本发明基于氧化物半导体薄膜晶体管的GOA电路的第六实施例的电路图；
图8为本发明基于氧化物半导体薄膜晶体管的GOA电路的第一和第四实施例的第一级GOA单元电路的电路图；
图9为本发明基于氧化物半导体薄膜晶体管的GOA电路的第二和第五实施例的第一级GOA单元电路的电路图；
图10为本发明基于氧化物半导体薄膜晶体管的GOA电路的第三和第六实施例的第一级GOA单元电路的电路图；
图11为本发明基于氧化物半导体薄膜晶体管的GOA电路的输入信号与关键节点的波形图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
本发明提供一种基于氧化物半导体薄膜晶体管的GOA电路。请参阅图2，图2为本发明基于氧化物半导体薄膜晶体管的GOA电路的第一实施例的电路图，包括级联的多个GOA单元电路，每一级GOA单元电路均包括：上拉控制模块100、上拉模块200、下传模块300、第一下拉模块400、自举电容模块500、及下拉维持模块600。
设N为正整数，除第一级GOA单元电路以外，在第N级GOA单元电 路中：
所述上拉控制模块100包括：第十一薄膜晶体管T11，所述第十一薄膜晶体管T11的栅极接收上一级第N-1级GOA单元电路的级传信号ST(N-1)，源极电性连接于恒压高电位DCH，漏极电性连接于第一节点Q(N)。
所述上拉模块200包括：第二十一薄膜晶体管T21，所述第二十一薄膜晶体管T21的栅极电性连接于第一节点Q(N)，源极电性连接于第m条时钟信号CK(m)，漏极输出扫描驱动信号G(N)。
所述下传模块300包括：第二十二薄膜晶体管T22，所述第二十二薄膜晶体管T22的栅极电性连接于第一节点Q(N)，源极电性连接于第m条时钟信号CK(m)，漏极输出级传信号ST(N)。
具体地，所述时钟信号包括四条时钟信号：第一时钟信号CK(1)、第二时钟信号CK(2)、第三时钟信号CK(3)、及第四时钟信号CK(4)。
当所述第m条时钟信号CK(m)为第三时钟信号CK(3)时，所述第m+2条时钟信号CK(m+2)为第一时钟信号CK(1)，当所述第m条时钟信号CK(m)为第四时钟信号CK(4)时，所述第m+2条时钟信号CK(m+2)为第二时钟信号CK(2)。
所述第一下拉模块400包括：第四十薄膜晶体管T40，所述第四十薄膜晶体管T40的栅极与源极均电性连接于第一节点Q(N)，漏极电性连接于第四十一薄膜晶体管T41的漏极；第四十一薄膜晶体管T41，所述第四十一薄膜晶体管T41的栅极电性连接于第m+2条时钟信号CK(m+2)，源极输入扫描驱动信号G(N)。
所述自举电容模块500包括：电容Cb，所述电容Cb的一端电性连接于第一节点Q(N)，另一端电性连接于扫描驱动信号G(N)。
所述下拉维持模块600包括：第五十一薄膜晶体管T51，所述第五十一薄膜晶体管T51的栅极与源极均电性连接于恒压高电位DCH，漏极电性连接于第四节点S(N)；第五十二薄膜晶体管T52，所述第五十二薄膜晶体管T52的栅极电性连接于第一节点Q(N)，漏极电性连接于第四节点S(N)，源极电性连接于第一负电位VSS；第五十三薄膜晶体管T53，所述第五十三薄膜晶体管T53的栅极电性连接于第四节点S(N)，源极电性连接于恒压高电位DCH，漏极电性连接于第二节点P(N)；第五十四薄膜晶体管T54，所述第五十四薄膜晶体管T54的栅极电性连接于第一节点Q(N)，漏极电性连接于第二节点P(N)，源极电性连接于第五节点K(N)；第七十三薄膜晶体管T73，所述第七十三薄膜晶体管T73的栅极电性连接于第四节点S (N)，源极电性连接于恒压高电位DCH，漏极电性连接于第五节点K(N)；第七十四薄膜晶体管T74，所述第七十四薄膜晶体管T74的栅极电性连接于第一节点Q(N)，源极电性连接于恒压低电位DCL，漏极电性连接于第五节点K(N)；第五十五薄膜晶体管T55，所述第五十五薄膜晶体管T55的栅极接入上一级第N-1级GOA单元电路的级传信号ST(N-1)，源极电性连接于第四节点S(N)，漏极电性连接于第一负电位VSS；第四十二薄膜晶体管T42，所述第四十二薄膜晶体管T42的栅极电性连接于第二节点P(N)，漏极电性连接于第一节点Q(N)，源极电性连接于第三节点T(N)；第三十二薄膜晶体管T32，所述第三十二薄膜晶体管T32的栅极电性连接于第二节点P(N)，漏极电性连接于扫描驱动信号G(N)，源极电性连接于第一负电位VSS；第七十五薄膜晶体管T75，所述第七十五薄膜晶体管T75的栅极电性连接于第一节点Q(N)，源极电性连接于第三节点T(N)，漏极电性连接于恒压高电位DCH；第七十六薄膜晶体管T76，所述第七十六薄膜晶体管T76的栅极电性连接于第二节点P(N)，漏极电性连接于第三节点T(N)，源极电性连接于恒压低电位DCL。
具体地，所述第五十一薄膜晶体管T51、第五十二薄膜晶体管T52、第五十三薄膜晶体管T53、第五十四薄膜晶体管T54、第七十三薄膜晶体管T73、及第七十四薄膜晶体管T74构成一双重反相器F1，其中，所述第五十一薄膜晶体管T51、第五十二薄膜晶体管T52、第五十三薄膜晶体管T53、及第五十四薄膜晶体管T54构成主反相器，所述第七十三薄膜晶体管T73、及第七十四薄膜晶体管T74构成辅助反相器。所述恒压低电位DCL低于第一负电位VSS。每一级GOA单元电路中的所有薄膜晶体管均为氧化物半导体薄膜晶体管，优选的，所述氧化物半导体薄膜晶体管为IGZO薄膜晶体管。
特别地，请参阅图8，在本发明的第一实施例的第一级GOA单元电路中，所述第十一薄膜晶体管T11的栅极接入扫描启动信号STV，所述第五十五薄膜晶体管T55的栅极接入扫描启动信号STV，所述第二十一薄膜晶体管T21的源极及第二十二薄膜晶体管T22的源极均电性连接于第一条时钟信号CK(1)，第四十一薄膜晶体管T41的栅极电性连接于第三条时钟信号CK(3)，源极输入第一级扫描驱动信号G(1)。
请同时参阅图2与图11，本发明基于氧化物半导体薄膜晶体管的GOA电路第一实施例的工作过程为：所述扫描启动信号STV启动第一级GOA单元电路，从第一级GOA单元电路向最后一级GOA单元电路依次逐级进行扫描驱动。设N为正整数，以第N级GOA单元电路为例，首先，上一级第N-1级GOA单元电路的级传信号ST(N-1)向第十一薄膜晶体管T11 与第五十五薄膜晶体管T55的栅极提供高电位(第一级GOA单元电路则由扫描启动信号STV向第十一薄膜晶体管T11与第五十五薄膜晶体管T55的栅极提供高电位)，第十一薄膜晶体管T11与第五十五薄膜晶体管T55导通，恒压高电位DCH通过第十一薄膜晶体管T11将第一节点Q(N)抬升到高电位，并对电容Cb充电，同时第五十五薄膜晶体管T55将第四节点S(N)的电位下拉至第一负电位VSS，这样可以在第一节点Q(N)还未完全抬升的情况下，利用上一级第N-1级GOA单元电路的级传信号ST(N-1)控制第五十五薄膜晶体管T55导通，迅速下拉第四节点S(N)的电位，快速地关闭下拉维持模块600，确保第一节点Q(N)能够抬升到高电位，此时第四节点S(N)为低电位，第一节点Q(N)为高电位，所述双重反相器F1的主反相器中的第五十二薄膜晶体管T52与第五十四薄膜晶体管T54均导通，第五十三薄膜晶体管T53断开，辅助主反相器中的第七十四薄膜晶体管T74导通，第七十三薄膜晶体管T73断开，第二节点P(N)的电位被拉低到比第一负电位VSS更低的恒压低电位DCL，第四十二、第三十二、第七十六薄膜晶体管T42、T32、T76断开，确保第一节点Q(N)和扫描驱动信号G(N)稳定的输出高电位。随后，上一级第N-1级GOA单元电路的级传信号ST(N-1)转为低电位，第十一薄膜晶体管T11断开，第一节点Q(N)通过电容Cb维持在高电位，使得第二十一薄膜晶体管T21与第二十二薄膜晶体管T22导通。接着，第m条时钟信号CK(m)向第二十一薄膜晶体管T21的源极与第二十二薄膜晶体管T22的源极提供高电位，并经由第二十一薄膜晶体管T21的漏极输出高电位的扫描驱动信号G(N)，第二十二薄膜晶体管T22的漏极输出高电位的级传信号ST(N)，同时第m条时钟信号CK(m)通过第二十一薄膜晶体管T21继续给电容Cb充电，使得第一节点Q(N)上升到一更高电位。然后，第m条时钟信号CK(m)变为低电位，第m+2条时钟信号CK(m+2)变为高电位，第四十一薄膜晶体管T41与第四十薄膜晶体管T40导通，第一节点Q(N)通过下拉模块400放电，转变为低电位，扫描结束，电路进入非作用期间，此时第一节点Q(N)为低电位，所述双重反相器F1的主反相器中的第五十二薄膜晶体管T52与第五十四薄膜晶体管T54均断开，第五十一薄膜晶体管T51导通，使得第四节点S(N)的电位变为高电位，第五十三薄膜晶体管T53导通，辅助主反相器中的第七十四薄膜晶体管T74断开，第七十三薄膜晶体管T73导通，防止第五十四薄膜晶体管T54漏电，使得第二节点P(N)的电位保持在恒压高电位DCH，进而第四十二、第三十二、第七十六薄膜晶体管T42、T32、T76均导通，下拉并维持第一节点Q(N)的 电位至恒压低电位DCL，扫描驱动信号G(N)的电位至第一负电位VSS。
在该第一实施例中，针对所述下拉维持模块600的关键节点四节点S(N)增设了第五十五薄膜晶体管T55，该第五十五薄膜晶体管T55受上一级第N-1级GOA单元电路的级传信号ST(N-1)控制下拉第四节点S(N)的电位至第一负电位VSS，这样可以在第一节点Q(N)还未完全抬升的情况下完成对第四节点S(N)点电位进行下拉，快速地关闭下拉维持模块600，能够避免因第五十二薄膜晶体管T52的阈值电压偏正时，导致在第一节点Q(N)还未完全抬升至高电位情况下，无法下拉第四节点S(N)的电位来关闭下拉维持模块600，进而使得第一节点Q(N)电位无法正常抬升，而第一节点Q(N)电位无法正常抬升又使得下拉维持模块600无法正常关闭，最终导致整个GOA电路功能不良的问题。
请同时参阅图3与图11，为本发明基于氧化物半导体薄膜晶体管的GOA电路的第二实施例，该第二实施例与第一实施例的区别在于，所述下拉维持模块600还包括：第五十六薄膜晶体管T56，所述第五十六薄膜晶体管T56的栅极接入上一级第N-1级GOA单元电路的级传信号ST(N-1)，源极电性连接于第五节点K(N)，漏极电性连接于恒压低电位DCL，当上一级第N-1级GOA单元电路的级传信号ST(N-1)为高电位时，该第五十六薄膜晶体管T56导通，将第五节点K(N)的电位下拉至恒压低电位DCL，进而在第一节点Q(N)还未完全抬升的情况下完成对第五节点K(N)的电位的下拉。
特别地，请参阅图9，在本发明的第二实施例的第一级GOA单元电路中，所述第十一薄膜晶体管T11的栅极接入扫描启动信号STV，所述第五十五薄膜晶体管T55和第五十六薄膜晶体管T56的栅极接入扫描启动信号STV，所述第二十一薄膜晶体管T21的源极及第二十二薄膜晶体管T22的源极均电性连接于第一条时钟信号CK(1)，第四十一薄膜晶体管T41的栅极电性连接于第三条时钟信号CK(3)，源极输入扫描驱动信号G(1)。其余电路结构与工作过程均与第一实施例相同，此处不再赘述。
请同时参阅图4与图11，为本发明基于氧化物半导体薄膜晶体管的GOA电路的第三实施例，该第三实施例与第二实施例的区别在于，所述下拉维持模块600还包括：第五十七薄膜晶体管T57，所述第五十七薄膜晶体管T57的栅极接入上一级第N-1级GOA单元电路的级传信号ST(N-1)，源极电性连接于第二节点P(N)，漏极电性连接于第五节点K(N)，当上一级第N-1级GOA单元电路的级传信号ST(N-1)为高电位时，该第五十六薄膜晶体管T56、第五十七薄膜晶体管T57均导通，将第五节点K(N) 和第二节点P(N)的电位均下拉至恒压低电位DCL，进而在第一节点Q(N)还未完全抬升的情况下完成对第五节点K(N)和第二节点P(N)的电位的下拉。
特别地，请参阅图10，在本发明的第三实施例中，在第一级GOA单元电路内，所述第十一薄膜晶体管T11的栅极接入扫描启动信号STV，所述第五十五薄膜晶体管T55、第五十六薄膜晶体管T56和第五十七薄膜晶体管T57的栅极接入扫描启动信号STV，所述第二十一薄膜晶体管T21的源极及第二十二薄膜晶体管T22的源极均电性连接于第一条时钟信号CK(1)，第四十一薄膜晶体管T41的栅极电性连接于第三条时钟信号CK(3)，源极输入扫描驱动信号G(1)。其余电路结构与工作过程均与第一实施例相同，此处不再赘述。
请同时参阅图5、图8与图11，为本发明基于氧化物半导体薄膜晶体管的GOA电路的第四实施例，该第四实施例与第一实施例的区别在于，所述第五十五薄膜晶体管T55的栅极接入上一级第N-1级GOA单元电路的扫描驱动信号G(N-1)，即在第一节点Q(N)还未完全抬升的情况下，利用上一级第N-1级GOA单元电路的扫描驱动信号G(N-1)控制第五十五薄膜晶体管T55下拉第四节点S(N)的电位。其余均与第一实施例相同，此处不再赘述。
请同时参阅图6、图9与图11，为本发明基于氧化物半导体薄膜晶体管的GOA电路的第五实施例，该第五实施例与第二实施例的区别在于，所述第五十五薄膜晶体管T55和第五十六薄膜晶体管T56的栅极接入上一级第N-1级GOA单元电路的扫描驱动信号G(N-1)，即在第一节点Q(N)还未完全抬升的情况下，利用上一级第N-1级GOA单元电路的扫描驱动信号G(N-1)控制第五十五薄膜晶体管T55和第五十六薄膜晶体管T56分别下拉第四节点S(N)和第五节点K(N)的电位。其余均与第二实施例相同，此处不再赘述。
请同时参阅图7、图10与图11，为本发明基于氧化物半导体薄膜晶体管的GOA电路的第六实施例，该第六实施例与第三实施例的区别在于，所述第五十五薄膜晶体管T55、第五十六薄膜晶体管T56、第五十七薄膜晶体管T57的栅极接入上一级第N-1级GOA单元电路的扫描驱动信号G(N-1)，即在第一节点Q(N)还未完全抬升的情况下，利用上一级第N-1级GOA单元电路的扫描驱动信号G(N-1)控制第五十五薄膜晶体管T55、第五十六薄膜晶体管T56、及第五十七薄膜晶体管T57分别下拉第四节点S(N)、第五节点K(N)、及第二节点P(N)的电位。其余均与第三实施 例相同，此处不再赘述。
综上所述，本发明提供了一种基于氧化物半导体薄膜晶体管的GOA电路，通过增设分别对应于下拉维持模块中的第四、第五、第二节点的第五十五、第五十六、第五十七薄膜晶体管，所述第五十五、第五十六、及第五十七薄膜晶体管的栅极均接入上一级第N-1级GOA单元电路的级传信号或上一级第N-1级GOA单元电路的扫描驱动信号，通过上一级第N-1级GOA单元电路的级传信号或上一级第N-1级GOA单元电路的扫描驱动信号控制第五十五、第五十六、及第五十七在第一节点还未完全抬升的情况下，下拉第四、第五、第二节点的电位，实现快速地关闭下拉维持模块，保证第一节点电位的正常抬升，确保在作用期间第一节点处于高电位，从而保证GOA电路的正常输出。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (17)

  1. 一种基于氧化物半导体薄膜晶体管的GOA电路，包括级联的多个GOA单元电路，每一级GOA单元电路均包括：上拉控制模块、上拉模块、下传模块、第一下拉模块、自举电容模块、及下拉维持模块；
    设N为正整数，除第一级GOA单元电路以外，在第N级GOA单元电路中：
    所述上拉控制模块包括：第十一薄膜晶体管，所述第十一薄膜晶体管的栅极接收上一级第N-1级GOA单元电路的级传信号，源极电性连接于恒压高电位，漏极电性连接于第一节点；
    所述上拉模块包括：第二十一薄膜晶体管，所述第二十一薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第m条时钟信号，漏极输出扫描驱动信号；
    所述下传模块包括：第二十二薄膜晶体管，所述第二十二薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第m条时钟信号，漏极输出级传信号；
    所述第一下拉模块包括：第四十薄膜晶体管，所述第四十薄膜晶体管的栅极与源极均电性连接于第一节点，漏极电性连接于第四十一薄膜晶体管的漏极；第四十一薄膜晶体管，所述第四十一薄膜晶体管的栅极电性连接于第m+2条时钟信号，源极输入扫描驱动信号；
    所述自举电容模块包括：电容，所述电容的一端电性连接于第一节点，另一端电性连接于扫描驱动信号；
    所述下拉维持模块至少包括：第五十一薄膜晶体管，所述第五十一薄膜晶体管的栅极与源极均电性连接于恒压高电位，漏极电性连接于第四节点；第五十二薄膜晶体管，所述第五十二薄膜晶体管的栅极电性连接于第一节点，漏极电性连接于第四节点，源极电性连接于第一负电位；第五十三薄膜晶体管，所述第五十三薄膜晶体管的栅极电性连接于第四节点，源极电性连接于恒压高电位，漏极电性连接于第二节点；第五十四薄膜晶体管，所述第五十四薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于第五节点；第七十三薄膜晶体管，所述第七十三薄膜晶体管的栅极电性连接于第四节点，源极电性连接于恒压高电位，漏极电性连接于第五节点；第七十四薄膜晶体管，所述第七十四薄膜晶体管的栅极电性连接于第一节点，源极电性连接于恒压低电位，漏极电性连 接于第五节点；第五十五薄膜晶体管，所述第五十五薄膜晶体管的栅极接入上一级第N-1级GOA单元电路的级传信号或上一级第N-1级GOA单元电路的扫描驱动信号，源极电性连接于第四节点，漏极电性连接于第一负电位；第四十二薄膜晶体管，所述第四十二薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第一节点，漏极电性连接于第三节点；第三十二薄膜晶体管，所述第三十二薄膜晶体管的栅极电性连接于第二节点，源极电性连接于扫描驱动信号，漏极电性连接于第一负电位；第七十五薄膜晶体管，所述第七十五薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第三节点，漏极电性连接于恒压高电位；第七十六薄膜晶体管，所述第七十六薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第三节点，漏极电性连接于恒压低电位；
    所述恒压低电位低于第一负电位；
    所述每一级GOA单元电路中的所有薄膜晶体管均为氧化物半导体薄膜晶体管。
  2. 如权利要求1所述的基于氧化物半导体薄膜晶体管的GOA电路，其中，所述下拉维持模块还包括：第五十六薄膜晶体管，所述第五十六薄膜晶体管的栅极接入上一级第N-1级GOA单元电路的级传信号或上一级第N-1级GOA单元电路的扫描驱动信号，源极电性连接于第五节点，漏极电性连接于恒压低电位。
  3. 如权利要求1所述的基于氧化物半导体薄膜晶体管的GOA电路，其中，所述下拉维持模块还包括：第五十六薄膜晶体管，所述第五十六薄膜晶体管的栅极接入上一级第N-1级GOA单元电路的级传信号或上一级第N-1级GOA单元电路的扫描驱动信号，源极电性连接于第五节点，漏极电性连接于恒压低电位；第五十七薄膜晶体管，所述第五十七薄膜晶体管的栅极接入上一级第N-1级GOA单元电路的级传信号或上一级第N-1级GOA单元电路的扫描驱动信号，源极电性连接于第二节点，漏极电性连接于第五节点。
  4. 如权利要求1所述的基于氧化物半导体薄膜晶体管的GOA电路，其中，在第一级GOA单元电路中，所述第十一薄膜晶体管的栅极接入扫描启动信号，所述第五十五薄膜晶体管的栅极接入扫描启动信号。
  5. 如权利要求2所述的基于氧化物半导体薄膜晶体管的GOA电路，其中，在第一级GOA单元电路中，所述第十一薄膜晶体管的栅极接入扫描启动信号，所述第五十五薄膜晶体管的栅极接入扫描启动信号，所述第五十六薄膜晶体管的栅极接入扫描启动信号。
  6. 如权利要求3所述的基于氧化物半导体薄膜晶体管的GOA电路，其中，在第一级GOA单元电路中，所述第十一薄膜晶体管的栅极接入扫描启动信号，所述第五十五薄膜晶体管的栅极接入扫描启动信号，所述第五十六薄膜晶体管的栅极接入扫描启动信号，所述第五十七薄膜晶体管的栅极接入扫描启动信号。
  7. 如权利要求1所述的基于氧化物半导体薄膜晶体管的GOA电路，其中，所述下拉维持电路中，第五十一薄膜晶体管、第五十二薄膜晶体管、第五十三薄膜晶体管、第五十四薄膜晶体管、第七十三薄膜晶体管、及第七十四薄膜晶体管构成一双重反相器，所述第五十一薄膜晶体管、第五十二薄膜晶体管、第五十三薄膜晶体管、及第五十四薄膜晶体管构成主反相器，所述第七十三薄膜晶体管、及第七十四薄膜晶体管构成辅助反相器。
  8. 如权利要求1所述的基于氧化物半导体薄膜晶体管的GOA电路，其中，所述时钟信号包括四条时钟信号：第一时钟信号、第二时钟信号、第三时钟信号、及第四时钟信号。
  9. 如权利要求8所述的基于氧化物半导体薄膜晶体管的GOA电路，其中，当所述第m条时钟信号为第三时钟信号时，所述第m+2条时钟信号为第一时钟信号，当所述第m条时钟信号为第四时钟信号时，所述第m+2条时钟信号为第二时钟信号。
  10. 如权利要求1所述的基于氧化物半导体薄膜晶体管的GOA电路，其中，所述每一级GOA单元电路中的所有薄膜晶体管均为IGZO薄膜晶体管。
  11. 一种基于氧化物半导体薄膜晶体管的GOA电路，包括级联的多个GOA单元电路，每一级GOA单元电路均包括：上拉控制模块、上拉模块、下传模块、第一下拉模块、自举电容模块、及下拉维持模块；
    设N为正整数，除第一级GOA单元电路以外，在第N级GOA单元电路中：
    所述上拉控制模块包括：第十一薄膜晶体管，所述第十一薄膜晶体管的栅极接收上一级第N-1级GOA单元电路的级传信号，源极电性连接于恒压高电位，漏极电性连接于第一节点；
    所述上拉模块包括：第二十一薄膜晶体管，所述第二十一薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第m条时钟信号，漏极输出扫描驱动信号；
    所述下传模块包括：第二十二薄膜晶体管，所述第二十二薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第m条时钟信号，漏极输出 级传信号；
    所述第一下拉模块包括：第四十薄膜晶体管，所述第四十薄膜晶体管的栅极与源极均电性连接于第一节点，漏极电性连接于第四十一薄膜晶体管的漏极；第四十一薄膜晶体管，所述第四十一薄膜晶体管的栅极电性连接于第m+2条时钟信号，源极输入扫描驱动信号；
    所述自举电容模块包括：电容，所述电容的一端电性连接于第一节点，另一端电性连接于扫描驱动信号；
    所述下拉维持模块至少包括：第五十一薄膜晶体管，所述第五十一薄膜晶体管的栅极与源极均电性连接于恒压高电位，漏极电性连接于第四节点；第五十二薄膜晶体管，所述第五十二薄膜晶体管的栅极电性连接于第一节点，漏极电性连接于第四节点，源极电性连接于第一负电位；第五十三薄膜晶体管，所述第五十三薄膜晶体管的栅极电性连接于第四节点，源极电性连接于恒压高电位，漏极电性连接于第二节点；第五十四薄膜晶体管，所述第五十四薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于第五节点；第七十三薄膜晶体管，所述第七十三薄膜晶体管的栅极电性连接于第四节点，源极电性连接于恒压高电位，漏极电性连接于第五节点；第七十四薄膜晶体管，所述第七十四薄膜晶体管的栅极电性连接于第一节点，源极电性连接于恒压低电位，漏极电性连接于第五节点；第五十五薄膜晶体管，所述第五十五薄膜晶体管的栅极接入上一级第N-1级GOA单元电路的级传信号或上一级第N-1级GOA单元电路的扫描驱动信号，源极电性连接于第四节点，漏极电性连接于第一负电位；第四十二薄膜晶体管，所述第四十二薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第一节点，漏极电性连接于第三节点；第三十二薄膜晶体管，所述第三十二薄膜晶体管的栅极电性连接于第二节点，源极电性连接于扫描驱动信号，漏极电性连接于第一负电位；第七十五薄膜晶体管，所述第七十五薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第三节点，漏极电性连接于恒压高电位；第七十六薄膜晶体管，所述第七十六薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第三节点，漏极电性连接于恒压低电位；
    所述恒压低电位低于第一负电位；
    所述每一级GOA单元电路中的所有薄膜晶体管均为氧化物半导体薄膜晶体管；
    其中，所述时钟信号包括四条时钟信号：第一时钟信号、第二时钟信号、第三时钟信号、及第四时钟信号；
    其中，当所述第m条时钟信号为第三时钟信号时，所述第m+2条时钟信号为第一时钟信号，当所述第m条时钟信号为第四时钟信号时，所述第m+2条时钟信号为第二时钟信号；
    其中，所述每一级GOA单元电路中的所有薄膜晶体管均为IGZO薄膜晶体管。
  12. 如权利要求11所述的基于氧化物半导体薄膜晶体管的GOA电路，其中，所述下拉维持模块还包括：第五十六薄膜晶体管，所述第五十六薄膜晶体管的栅极接入上一级第N-1级GOA单元电路的级传信号或上一级第N-1级GOA单元电路的扫描驱动信号，源极电性连接于第五节点，漏极电性连接于恒压低电位。
  13. 如权利要求11所述的基于氧化物半导体薄膜晶体管的GOA电路，其中，所述下拉维持模块还包括：第五十六薄膜晶体管，所述第五十六薄膜晶体管的栅极接入上一级第N-1级GOA单元电路的级传信号或上一级第N-1级GOA单元电路的扫描驱动信号，源极电性连接于第五节点，漏极电性连接于恒压低电位；第五十七薄膜晶体管，所述第五十七薄膜晶体管的栅极接入上一级第N-1级GOA单元电路的级传信号或上一级第N-1级GOA单元电路的扫描驱动信号，源极电性连接于第二节点，漏极电性连接于第五节点。
  14. 如权利要求11所述的基于氧化物半导体薄膜晶体管的GOA电路，其中，在第一级GOA单元电路中，所述第十一薄膜晶体管的栅极接入扫描启动信号，所述第五十五薄膜晶体管的栅极接入扫描启动信号。
  15. 如权利要求12所述的基于氧化物半导体薄膜晶体管的GOA电路，其中，在第一级GOA单元电路中，所述第十一薄膜晶体管的栅极接入扫描启动信号，所述第五十五薄膜晶体管的栅极接入扫描启动信号，所述第五十六薄膜晶体管的栅极接入扫描启动信号。
  16. 如权利要求13所述的基于氧化物半导体薄膜晶体管的GOA电路，其中，在第一级GOA单元电路中，所述第十一薄膜晶体管的栅极接入扫描启动信号，所述第五十五薄膜晶体管的栅极接入扫描启动信号，所述第五十六薄膜晶体管的栅极接入扫描启动信号，所述第五十七薄膜晶体管的栅极接入扫描启动信号。
  17. 如权利要求11所述的基于氧化物半导体薄膜晶体管的GOA电路，其中，所述下拉维持电路中，第五十一薄膜晶体管、第五十二薄膜晶体管、第五十三薄膜晶体管、第五十四薄膜晶体管、第七十三薄膜晶体管、及第七十四薄膜晶体管构成一双重反相器，所述第五十一薄膜晶体管、第五十 二薄膜晶体管、第五十三薄膜晶体管、及第五十四薄膜晶体管构成主反相器，所述第七十三薄膜晶体管、及第七十四薄膜晶体管构成辅助反相器。
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CN104392701A (zh) * 2014-11-07 2015-03-04 深圳市华星光电技术有限公司 用于氧化物半导体薄膜晶体管的扫描驱动电路
CN104409055A (zh) * 2014-11-07 2015-03-11 深圳市华星光电技术有限公司 用于氧化物半导体薄膜晶体管的扫描驱动电路

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CN104882108A (zh) 2015-09-02
KR101933333B1 (ko) 2018-12-27
GB2545856A (en) 2017-06-28
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GB2545856B (en) 2021-03-24
KR20170068582A (ko) 2017-06-19

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