WO2016194092A1 - Dispositif de mémoire à semi-conducteurs, son procédé de fabrication, et dispositif de fabrication de dispositif de mémoire à semi-conducteurs - Google Patents

Dispositif de mémoire à semi-conducteurs, son procédé de fabrication, et dispositif de fabrication de dispositif de mémoire à semi-conducteurs Download PDF

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WO2016194092A1
WO2016194092A1 PCT/JP2015/065691 JP2015065691W WO2016194092A1 WO 2016194092 A1 WO2016194092 A1 WO 2016194092A1 JP 2015065691 W JP2015065691 W JP 2015065691W WO 2016194092 A1 WO2016194092 A1 WO 2016194092A1
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phase change
change material
film
memory device
layer
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PCT/JP2015/065691
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English (en)
Japanese (ja)
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健三 黒土
小林　孝
笹子　佳孝
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株式会社日立製作所
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/10—Phase change RAM [PCRAM, PRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/066—Shaping switching materials by filling of openings, e.g. damascene method
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H10N70/8265—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe

Definitions

  • the present invention relates to a semiconductor memory device, a manufacturing method thereof, and a manufacturing apparatus of a semiconductor memory device, and more particularly to an electrically rewritable phase change memory, a manufacturing method thereof, and a manufacturing apparatus thereof.
  • phase change memory using a phase change material as a recording layer.
  • the phase change memory stores the difference in resistance of each state (crystalline phase and amorphous phase) of the phase change material as information, and the conventional memory that stores information by the difference in the amount of charge accumulated in the stacked gate structure.
  • the thickness for holding the charge in the memory portion is not required, and since the operating voltage is low, the thickness for the insulating film is also not required, so compared to the case of the memory cell with a stacked gate structure, There are few restrictions on miniaturization.
  • phase change memory In the phase change memory, the difference in resistance value between the amorphous phase and the crystal phase is large, and the difference between these resistance values is used as a read signal, so that the sensing operation is easy and the read speed is high. Therefore, the phase change memory is expected to provide a high-density (large capacity) and high-speed memory device in the future.
  • the recording layer includes a second portion having a relatively higher nitrogen content than the first portion, thereby stabilizing the crystalline state and the amorphous state and reducing power consumption.
  • a configuration of a non-volatile storage device configured as described above is disclosed.
  • phase change material of the phase change memory cell for example, chalcogenide represented by Ge 2 Sb 2 Te 5 is known to be suitable. It has been pointed out that such phase change materials generally have low thermal stability.
  • Patent Document 2 discloses a sidewall protective film 123 made of a silicon nitride film on the sidewall of the chalcogenide material layer 114 in order to prevent the chalcogenite material from sublimating due to its low thermal stability in the manufacturing process of the phase change memory cell. Techniques for forming the are disclosed.
  • the phase change material layer is concerned about deterioration of phase change characteristics due to oxidation due to its low thermal stability.
  • a conductive electrode 33 and a base electrode 32 made of a metal material are formed on the upper and lower surfaces of the phase change material layer 31, respectively.
  • the phase change region is formed in a dome shape with the surface of the phase change material layer 31 in contact with the base electrode 32 as the center.
  • the area of the surface of the phase change material layer 31 on the base electrode 32 side is equal to the area of the base electrode 32 on the phase change material layer 31 side.
  • the phase change region formed around the contact surface with the base electrode 32 is isolated from the end face of the phase change material layer 31 to prevent deterioration of phase change characteristics due to oxidation. Is possible.
  • phase change memory has been attracting attention from the viewpoint of increasing the capacity of the memory.
  • the phase change material is oxidized when the gap fill portion 14 is formed.
  • the rewriting characteristics of the phase change material are deteriorated, and the number of rewritable times is reduced.
  • the phase change memory cell disclosed in Patent Document 2 is a planar type, and cannot solve the problem of oxidation of the phase change material at the time of manufacturing the above-described three-dimensional type phase change memory. That is, in the three-dimensional type phase change memory, there is a problem that the phase change region is easily oxidized as compared with the planar type phase change memory, and the rewrite characteristics of the phase change material may be deteriorated.
  • an object of the present invention is to provide a semiconductor memory device having excellent rewriting characteristics and high reliability, a manufacturing method thereof, and a manufacturing device thereof.
  • a preferred embodiment of the semiconductor memory device is a semiconductor memory device having a memory chain in which a plurality of phase change memory cells having a phase change material film are connected in series, wherein the phase change material film includes An insulating layer having oxidation resistance is formed on the main surface side of the center side of the memory chain.
  • a stacked body is formed by alternately stacking select gate electrodes and interphase insulating films on the lower electrode, and penetrates the stacked body.
  • a memory hole is formed, a phase change material is formed in a vacuum state in a region in the memory hole to form a phase change material layer, and an insulating layer having oxidation resistance is formed on a main surface of the phase change material layer It is characterized by forming.
  • a phase change material film forming chamber for forming a phase change material layer by forming a phase change material on an object in a vacuum state
  • An insulator forming chamber for forming an insulating material having oxidation resistance in a vacuum state on the object on which the change material layer is formed, and the phase change material layer formed in the phase change material deposition chamber.
  • a transfer chamber for transferring the object to the insulator forming chamber while maintaining a vacuum state.
  • a highly reliable semiconductor memory device having excellent rewrite characteristics, a manufacturing method thereof, and a manufacturing device thereof can be realized.
  • FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. It is a cross-sectional schematic diagram which shows 1 process of the manufacturing process of the three-dimensional type phase change memory of a comparative example. It is a figure which shows the relationship between the oxygen content of a phase change material, and the frequency
  • 1 is a bird's-eye view showing an overall configuration of a three-dimensional phase change memory according to Embodiment 1.
  • FIG. 1 is a bird's-eye view showing an overall configuration of a three-dimensional phase change memory according to Embodiment 1.
  • FIG. 3 is a diagram illustrating a partial equivalent circuit of the three-dimensional type phase change memory according to the first embodiment.
  • FIG. 3 is a diagram illustrating a partial equivalent circuit of the three-dimensional type phase change memory according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view showing a step of the manufacturing process for the three-dimensional type phase change memory according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view showing a step of the manufacturing process for the three-dimensional type phase change memory according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view showing a step of the manufacturing process for the three-dimensional type phase change memory according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view showing a step of the manufacturing process for the three-dimensional type phase change memory according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view showing a step of the manufacturing process for the three-dimensional type phase change memory according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view showing a step of the manufacturing process for the three-dimensional type phase change memory according to the first embodiment. It is a figure which shows the relationship between the nitrogen / Ar gas flow ratio at the time of the sputter film-forming of GeSbTe which is a phase change material, and the rewrite frequency
  • FIG. 3 is a schematic cross-sectional view showing a step of the manufacturing process for the three-dimensional type phase change memory according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view showing a step of the manufacturing process for the three-dimensional type phase change memory according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view showing a step of the manufacturing process for the three-dimensional type phase change memory according to the first embodiment.
  • 1 is a schematic diagram illustrating a schematic configuration of a manufacturing apparatus for a three-dimensional type phase change memory (semiconductor memory device) according to Embodiment 1.
  • FIG. 1 is a schematic diagram illustrating a schematic configuration of a manufacturing apparatus for a three-dimensional type phase change memory (semiconductor memory device) according to Embodiment 1.
  • FIG. 1 is a schematic diagram illustrating a schematic configuration of a manufacturing apparatus for a three-dimensional type phase change memory (semiconductor memory device) according to Embodiment 1.
  • FIG. FIG. 10 is a schematic cross-sectional view showing one step in a manufacturing process for the three-dimensional phase change memory according to the second embodiment.
  • FIG. 10 is a schematic cross-sectional view showing one step in the manufacturing process of the three-dimensional phase change memory according to Example 3.
  • the phase change material used for the recording layer of the phase change memory includes a high resistance phase (amorphous phase, hereinafter referred to as an amorphous phase) having a high electrical resistance and a crystal phase (amorphous phase lower than the high resistance phase).
  • the crystal phase has a low resistance (hereinafter referred to as a crystal phase).
  • the phase change memory stores information by making the difference in resistance between the amorphous phase and the crystalline phase correspond to “0” and “1”.
  • the electric resistance value hereinafter referred to as a unit resistance value
  • a unit resistance value is approximately 2 to 3 digits higher than that in the crystalline phase.
  • a state in which the phase change material is amorphous and the resistance of the memory portion is high is referred to as a reset state
  • a state in which the phase change material is a crystal and the resistance of the memory portion is low is referred to as a set state.
  • 0 is a reset state, that is, an amorphous phase
  • “1” is a set state, that is, a crystal phase.
  • Reading information from the phase change memory is performed by applying a low voltage to the phase change material, measuring a current value passing through the phase change material, reading a resistance value of the phase change material, and identifying the information. At this time, since the voltage applied to the phase change material is low, the phase state of the phase change material does not change.
  • the rewriting of the phase change memory is performed by causing a current to flow through the phase change material itself or a heater adjacent thereto to generate Joule heat in the phase change material.
  • phase change part for example, a phase change material layer
  • a pulse that rapidly cools the phase change material after heating it above the melting point is applied.
  • the melting point of the phase change material is, for example, about 600 ° C.
  • the rapid cooling time is, for example, about 3 nsec (nanoseconds).
  • the temperature of the phase change part is locally maintained at a temperature not lower than the crystallization temperature and not higher than the melting point.
  • the temperature at this time is 400 ° C., for example.
  • the time required for crystallization varies depending on the composition of the phase change material, but is, for example, 50 nsec.
  • crystallization of the phase change material is referred to as a set operation, and amorphization of the phase change material is referred to as a reset operation.
  • a current that flows through the memory cell when performing the reset operation is referred to as a reset current.
  • FIGS. 3, 13, and 14 are referred to.
  • FIG. 13 is a schematic view showing a cross section in one step of the method of manufacturing the three-dimensional phase change memory.
  • the channel 19 of the X chain selection element 64 is formed on a silicon wafer (not shown). Between the X chain selection element 64 and the upper electrode 17, a cell selection gate electrode 15 and an interlayer insulating film are formed. 16 is formed.
  • the memory hole 52 is formed so as to penetrate the upper electrode 17 and the stacked body of the cell selection gate electrode 15 and the interlayer insulating film 16.
  • a gate insulating film 18 is formed on the side wall of the memory hole 52, and a polysilicon channel 13 is formed on one main surface of the gate insulating film 18.
  • the phase change material layer 11 is formed on one main surface of the polysilicon channel 13. Further, in the next step, as shown in FIG. 3, an insulating gap fill portion 14 is formed so as to be in direct contact with one main surface of the phase change material layer 11. Oxidation is a problem.
  • the gap fill portion 14 is roughly classified into an insulating film formed by curing an insulating film coating material or an insulating film formed by a CVD method.
  • the gap fill portion 14 is formed by coating a coating material for an insulating film on the phase change material layer 11 by a spin coating method.
  • the phase change material layer 11 is applied around the contact surface with the gap fill portion 14 due to moisture contained in the insulating film coating material or moisture released when the insulating film coating material is cured. It is oxidized in the mold insulating film forming process and the subsequent wiring process.
  • the film forming atmosphere is an oxidizing atmosphere, and the silicon wafer is heated to about 400 ° C., so that the phase change material layer 11 is oxidized in the process of forming the gap fill portion 14.
  • phase change material layer 11 is oxidized in this way, phase change characteristics are lost in the oxidized region.
  • Fig. 4 shows the relationship between the oxygen content of the phase change material and the number of times the phase change memory can be rewritten.
  • the number of rewritable times in the phase change memory decreases as the oxygen content of the phase change material increases as shown in FIG. That is, as the gap fill portion 14 is formed, the phase change material is oxidized, so that the rewritable characteristics of the phase change material deteriorate, and in particular, the number of rewritable times decreases.
  • FIG. 5 shows an enlarged view of the region 101 shown in FIG.
  • FIG. 5 shows a region 121 where the phase changes during the rewrite operation of the phase change memory.
  • the phase change region 121 is a phase in which the phase state changes to an amorphous phase or a crystalline phase in “0” writing or “1” writing, that is, in a reset operation or a set operation.
  • the resistance ratio between the reset state and the set state becomes small.
  • the resistance ratio between the set state and the reset state becomes small.
  • the main surface of the phase change material layer 11 on the side wall side of the memory chain (main surface on the left side in FIG. 5) is changed to the main surface on the center side of the memory chain (main surface on the right side in FIG. 5).
  • the entire region in the thickness direction up to) needs to be the phase change region 121.
  • the main surface on the center side of the memory chain is easily oxidized when the gap fill portion 14 is formed. It is a problem to prevent the phase change region from being reduced.
  • FIG. 6 shows an analysis result of thermal desorption gas mass analysis (TDS) of the GeSbTe film.
  • TDS thermal desorption gas mass analysis
  • FIG. 2 shows the result of Ge analysis.
  • TDS thermal desorption gas mass analysis
  • the chalcogenide material has extremely low thermal stability, which is a problem in the stability during the manufacture and use of the phase change memory cell.
  • FIG. 1 is a schematic plan view showing a schematic structure of the planar memory
  • FIG. 2 is a cross-sectional view taken along the line II ′ of FIG.
  • the memory cell 41 of the planar memory is formed at the intersection of the bit line 42 and the word line 43. Selection of the memory cell 41 is performed by a selection element (not shown) provided for each memory cell, for example, a diode element.
  • a selection element not shown
  • the conductive electrode 33 is formed on the main surface of the phase change material layer 31. A region between the stacked body of the base electrode 32, the phase change material layer 31 and the conductive electrode 33 is filled with an interlayer insulating film 35.
  • a bit line 34 is formed on the upper surfaces of the interlayer insulating film 35 and the conductive electrode 33.
  • main surface refers to a surface perpendicular to the stacking direction 36 (vertical direction in FIG. 2) of the phase change material layer 31 on the base electrode 32.
  • the main surface In the configuration shown in FIG. 2, of the two main surfaces of the phase change film, the main surface that is not in contact with the phase change film base (the base electrode 32 in the configuration of FIG. 2) is referred to as the surface.
  • the other main surface facing the main surface (that is, the surface) on the side where the conductive electrode 33 is formed is a surface in contact with the base. That is, the base surface is a surface on which the phase change material layer 31 is applied, and is formed on the base surface of the phase change material layer 31 before the phase change material 31 is formed.
  • the base electrode 32 is the base.
  • phase change material layer 31 In such a planar phase change memory, sublimation of the phase change material layer 31 is prevented by the conductive electrode 33 formed on the main surface of the phase change material layer 31 for the following reason. That is, in the configuration shown in FIG. 2, even if the phase change material is heated and a part of the phase change material is slightly sublimated, the conductive electrode 33, the base electrode 32, and the interlayer insulating film 35 are not substantially deformed.
  • the gas pressure of the phase change material jumps in the phase change memory.
  • the temperature required for sublimation increases accordingly, so that when the sublimation temperature becomes equal to the heating temperature, a thermodynamic equilibrium state is reached. Once the thermodynamic equilibrium is reached, the phase change material will no longer sublime.
  • the end face of the phase change material is open, the area of the end face is smaller than the area of the main surface suppressed by the conductive electrode 33 and the base electrode 32, and thus the same as described above. For this reason, the rate at which the phase change material sublimes decreases.
  • the “end face” refers to a plane perpendicular to the main surface.
  • the temperature used in the chemical vapor deposition method is about 400 to 700 ° C.
  • FIG. 7 is a bird's-eye view showing the overall configuration of the three-dimensional phase change memory according to the first embodiment
  • FIG. 8 is a schematic diagram showing a part of a cross section of the three-dimensional phase change memory shown in FIG.
  • a Y chain selection element 62 and an X chain selection element 64 are provided in this order from the lower electrode 63 side.
  • the memory chain 61 is provided in a plurality of rows between the upper electrode 17 and the X chain selection element 64.
  • a plurality of cell selection gate electrodes 15 and interlayer insulating films 16 are alternately stacked between the upper electrode 17 and the lower electrode 63, and penetrate through these stacked bodies and the upper electrode 17 in the stacking direction. Thus, a memory hole 52 is formed.
  • phase change material film 55 In the memory hole 52, the gate insulating film 18, the polysilicon channel 13, and a stacked layer 55 of a phase change material layer and an insulating layer having oxidation resistance (hereinafter referred to as a phase change material film 55) are sequentially formed from the side wall side. ) A stack 55 of phase change material and protective film is stacked in order from the side wall side of the memory hole 52, and a gap fill portion 14 is formed in a region surrounded by the phase change material film 55.
  • the phase change memory cell 51 is provided for each layer of the cell selection gate electrode 15 in the stacked body formed of the gate insulating film 18, the polysilicon channel 13, and the phase change material film 55 formed in the memory hole 52. ing. That is, the phase change material film 55 is connected to the cell selection gate electrode 15 via the gate insulating film 18.
  • the memory chain 61 is configured by connecting a plurality of such phase change memory cells 51 in series in the stacking direction of the cell selection gate electrode 15 and the interlayer insulating film 16.
  • the main surface of the phase change material film 55 refers to a surface extending in the stacking direction of the cell selection gate electrode 15 and the interlayer insulating film 16.
  • FIG. 8 shows a direction 53 perpendicular to the end face of the phase change material film 55 and a direction 54 perpendicular to the main surface of the phase change material film 55.
  • FIG. 9 is a diagram illustrating a part of an equivalent circuit of the three-dimensional type phase change memory according to the first embodiment.
  • the memory cell 51 is configured by connecting a phase change unit 231 and a polysilicon MOS 232 in parallel.
  • the selection method of the memory chain 61 will be described with reference to FIG. 10 by taking as an example the case of a reset operation (that is, a write operation, a “0” write operation, a high resistance operation).
  • the memory chain 61 is selected using an X chain selection element 64 and a Y chain selection element 62 (see FIG. 7).
  • a selection operation is performed by applying an on voltage or an off voltage to the gate electrodes X1, X2, and X3 of the selection element.
  • a selection operation is performed by applying an on voltage or an off voltage to the gate electrodes Y1, Y2, and Y3 of the selection element.
  • the X chain selection element 64 and the Y chain selection element 62 are double gate polysilicon MOS. That is, since there are two gate electrodes for each MOS and the channel thickness of the MOS is thin, the MOS is turned on only when an on-voltage is applied to the two gate electrodes. In other cases, that is, when an on-voltage is applied to one of the gate electrodes and an off-voltage is applied to the other, or when an off-voltage is applied to both of the two gate electrodes, the MOS is turned off. For example, when the source voltage of the MOS is ⁇ 7.5, an example of the on voltage is 0V, and an example of the off voltage is ⁇ 7.5V.
  • the X chain selection element 64 and the Y chain selection element 62 are connected in series. When both are turned on, electrons pass from the lower electrode 63 through the Y chain selection element 62, the X chain selection element 64, and the memory chain 61. To the upper electrode 17. Needless to say, the direction of current flow is opposite to the direction of electrons. At this time, a pulse current is applied to the selected memory cell 221 in the memory chain 61, and the selected memory cell 221 is written.
  • An off voltage is applied to the cell selection gate electrode 15 connected to the selected memory cell 221 so as not to induce a channel in the polysilicon MOS 232 of the selected memory cell 221, so that no current flows through the polysilicon MOS 232, and the phase change unit 231 Current is passed through.
  • an on-voltage is applied to the cell selection gate electrode 15 connected to the non-selected memory cell, and a channel is induced in the polysilicon MOS 232 of the selected memory cell, thereby causing a current to flow in the polysilicon MOS 232 and causing the phase change portion 231 to flow. Do not pass current.
  • the channel 19 and the interlayer insulating film 16 of the X chain selection element 64 are formed on a Y chain selection element 62 (not shown).
  • the upper electrode is formed on the uppermost interlayer insulating film 16 of the stacked body. 17 is laminated. Note that the material and manufacturing method of the cell selection gate electrode 15 and the interlayer insulating film 16 are not described in detail, but can be formed using materials and manufacturing methods used in general semiconductor processes.
  • the memory hole 52 is opened so as to penetrate the upper electrode 17 and the stacked body of the cell selection gate electrode 15 and the interlayer insulating film 16 to the upper surface of the channel 19 in the stacking direction of the stacked body.
  • the gate insulating film 18 and the polysilicon channel 13 are formed sequentially from the side wall side of the memory hole 52. Thereafter, the gate insulating film 18 and the polysilicon channel 13 under the memory hole 52 are removed by anisotropic etch back. At the same time, the gate insulating film 18 near the upper electrode 17 is removed. After performing anisotropic etch back, the polysilicon channel 13 is formed again in the memory hole 52. A schematic cross-sectional view at this time is shown in FIG.
  • a silicon oxide film is preferably used as the gate insulating film 18.
  • a silicon oxide film is widely used as a gate insulating film of a MOSFET, and has an effect that can be stably applied to manufacture of a three-dimensional phase change memory.
  • a high-k insulating film can be used as the gate insulating film 18.
  • By using a high-k insulating film it becomes possible to increase the driving force of the cell selection MOS, and it is possible to increase the number of memory cells included in the memory chain (that is, increase the number of stacked memory cells). A larger-capacity phase change memory can be realized.
  • the formation temperature of the gate insulating film 18 is desirable that the formation temperature of the gate insulating film 18 is low in a so-called memory chain stacked structure in which a plurality of memory chains are stacked in the Z direction. Thereby, when forming the gate insulating film 18 included in the upper memory chain, it is possible to reduce the thermal load on the phase change material 11 that is already formed and included in the lower memory chain.
  • a method for forming the gate insulating film 18 an insulating film formed by a deposition insulating film, plasma CVD, plasma oxidation of a cell selection gate electrode, or thermal oxidation thermal oxidation can be used.
  • FIG. 14 is a schematic cross-sectional view around the memory chain at the time after the phase change material layer 11 is formed.
  • Chalcogenide is a material containing at least one element of sulfur, selenium, and tellurium.
  • the chalcogenide that is currently considered promising as a phase change material is an alloy composed of Ge (germanium), Sb (antimony), and Te (tellurium), and a GeSbTe alloy, particularly a Ge 2 Sb 2 Te 5 alloy may be used.
  • the Ge 2 Sb 2 Te 5 alloy is a material that has been successfully commercialized in DVD-RAM, and can reduce the time and cost required for product development. Furthermore, as the phase change material, an alloy mainly composed of InGeSbTe, ZnGeSbTe, BiGeSbTe, or Sb, particularly InSb, AgInSbTe, or AgInSb can be used. Above all, by using a phase change material with excellent retention characteristics such as InGeSbTe, ZnGeSbTe, BiGeSbTe, it becomes possible to increase the upper limit of the environmental temperature where phase change memory can be used, and it can be used for a wider range of applications. Therefore, it becomes possible to increase the sales volume.
  • CVD Chemical Vapor Deposition
  • ALD Atomic Layer Deposition
  • sputtering or sol-gel method.
  • CVD has an advantage that the film formation rate is fast and the phase change memory can be manufactured in a short time. Furthermore, CVD is superior in film thickness uniformity (coverage) for deep hole memory holes compared to sputtering.
  • the film of the phase change material is formed in a vacuum state.
  • the film formation temperature of CVD is preferably a low temperature of 130 to 200 ° C. By lowering the temperature, the phase change material is deposited in an amorphous state, and the film thickness uniformity is increased. Note that the inventors have confirmed that when the phase change material is formed in a crystalline state, non-uniformity in film thickness accompanying crystal grain growth is observed.
  • ALD has the advantage that it can realize a phase change memory with low power consumption and little variation in rewrite current, and low power consumption. Furthermore, ALD is excellent in coverage. In the case of sputtering, since it can be performed by the same manufacturing process as that of the planar type phase change memory, there is an advantage that the development period of the phase change memory can be shortened.
  • the sol-gel method has an advantage that the manufacturing cost can be reduced.
  • phase change material layer 11 formed in the memory hole 52 is nitrided.
  • nitriding layer 12 is formed on main surface 111 thereof.
  • phase change material film 55 having nitriding layer 12 and phase change material layer 11 which are insulating layers having oxidation resistance is formed.
  • a schematic cross-sectional view at this point is shown in FIG.
  • 11 is a phase change material layer
  • 12 is a nitridation treatment layer formed by nitriding treatment of the phase change material layer
  • 55 is a phase change material layer 11 and a nitridation treatment layer 12.
  • It is a phase change material film comprised.
  • the phase change material layer 11 and the nitriding layer 12 are shown as separate layers.
  • the nitriding layer 12 is a series of layers that are continuous with the phase change material layer 11. It is.
  • a remote plasma having a nitriding action or a method of generating radicals or plasma having a nitriding action in the vicinity of the phase change material layer 11 can be used.
  • remote plasma is preferably used.
  • the phase change material precursor contains nitrogen, and this precursor is decomposed.
  • the phase change material precursor contains nitrogen, and this precursor is decomposed.
  • a method of generating nitrogen radicals and a method of generating plasma and radicals by electrolysis using a cracker while flowing ammonia.
  • radical generation temperature can be reduced and the amount of radicals generated can be increased.
  • radicals having a nitriding action include N and NH 2 .
  • the main surface of the phase change material layer 11 is covered with an oxidation-resistant insulator, that is, a nitrided phase change material. For this reason, the thermal stability of the phase change material layer 11 is improved, and the oxidation resistance of the phase change material layer 11 is improved when a gap fill portion 14 described later is formed.
  • the thermal stability is improved by the nitriding treatment is explained for the same reason as described in the planar phase change memory. That is, in the configuration shown in FIG. 15 after the nitriding treatment, the nitriding treatment layer 12 and the polysilicon channel 13 sandwiching the phase change material layer 11 are not substantially deformed even if a part of the phase change material is sublimated.
  • the gas pressure of the phase change material vaporized by sublimation rises rapidly in the phase change memory. For this reason, due to the increase in sublimation temperature accompanying the increase in gas pressure, a thermodynamic equilibrium state is reached, and the phase change material does not sublime further.
  • the inventors of the present invention have confirmed that the nitrided phase change material maintains thermal stability even at 400 ° C. and does not cause sublimation.
  • the other main surface with respect to the main surface on which the nitriding layer 12 is formed is a surface in contact with the base, and the base is the polysilicon channel 13 in FIG. .
  • FIG. 16 is an example showing the relationship between the nitrogen / Ar gas flow rate ratio during sputtering deposition of GeSbTe, which is a phase change material, and the number of rewritable times of the phase change memory to which the obtained GeSbTe film is applied.
  • the flow rate ratio of nitrogen / Ar gas introduced into the sputtering chamber is increased when the phase change material is formed by the sputtering method, the number of rewritable phases of the phase change memory decreases.
  • the nitrogen concentration in the phase change region needs to be approximately the same as the nitrogen content ratio of the film formation obtained when the nitrogen / Ar gas flow rate ratio is 0.5% or less. is there.
  • the nitrogen content ratio in the entire phase change material layer when the nitrogen / Ar gas flow ratio is 0.5% is estimated to be approximately 20 at% or less.
  • the nitrogen / Ar gas flow ratio is set to 0.5%. It is necessary to make it the same as the nitrogen concentration of the film formation obtained sometimes.
  • the surface 551 that is, the main surface on the center side of the memory chain 61 among the main surfaces of the phase change material film 55, which is a main surface on the gap fill portion 14 formation side described later.
  • the nitrogen concentration of the nitriding layer 12 formed in the above is higher than the average nitrogen concentration of the entire phase change material film 55.
  • the nitrogen concentration of the nitriding layer 12 is preferably 20 at% or more.
  • the present inventors have confirmed through experiments that nitrogen contained in the phase change material layer 11 is swept out of the phase change region from the phase change region by performing a rewrite operation of the phase change memory. . That is, even if the nitrogen concentration in the phase change region exceeds the nitrogen concentration suitable for rewriting in the phase change memory immediately after the completion of manufacturing (that is, before the start of the first energization), for example, the memory chip test process or the customer It is considered that the nitrogen concentration in the phase change region decreases and reaches a nitrogen concentration suitable for rewriting by performing the rewriting operation at the initial time of starting use.
  • the gap fill portion 14 is formed in a region surrounded by the phase change material film 55.
  • a schematic cross-sectional view at this point is shown in FIG.
  • a coating method formation of an insulating film by curing a coating material for an insulating film
  • a CVD method can be employed as a method of forming the gap fill portion 14.
  • a coating method is preferably used.
  • the coating material for the insulating film a material having low temperature curability is preferably used.
  • the film forming temperature of the gap fill portion can be reduced to, for example, 200 ° C., and the deterioration of the phase change material during the manufacture of the phase change memory can be reduced. I can do it.
  • phase change material it is preferable to use a material having a low water content as the insulating film coating material or the gap fill portion 14 after the curing reaction thereof.
  • the gap fill portion 14 it is sufficient if it has at least an insulating property, and for example, a material made of SiO 2 is suitably used. If the constituent material of the gap fill part 14 is conductive, a current flows through the gap fill part 14, the resistance of the memory cell in the reset state (high resistance state) is lowered, and the resistance ratio is lowered. As a constituent material of the gap fill portion 14, it is needless to say that other insulating films mainly composed of SiO 2 and insulating films formed of Al 2 O 3 or low-k materials can be used. Yes.
  • the film formation atmosphere during the formation of the insulating film is an oxidizing atmosphere, and the silicon wafer is heated to about 400 ° C. during the film formation.
  • the phase change material 11 is oxidized in the film forming process of the fill portion 14.
  • the temperature at the time of film formation by the CVD method can be lowered to about 300 ° C., in this case, the density of the obtained insulating film (gap fill portion 14) is lowered and formed on the upper surface of the insulating film. Adhesiveness with a layer to be formed is reduced. In this case, since the residual stress of the insulating film increases, film peeling easily occurs during manufacturing. As a result, the yield of the phase change memory decreases.
  • phase change material layer 11 is exposed by the etch back, the phase change region of the phase change memory due to the exposure of the end face is slight because there is no phase change region in the vicinity of the end face.
  • the nitriding treatment of the phase change material can be performed again after the end face is exposed. By doing so, it is possible to increase the number of times the phase change memory can be rewritten, thereby realizing a highly reliable phase change memory.
  • an interlayer insulating film 16 is further formed on the surface from which unnecessary portions have been removed by etch back.
  • a schematic cross-sectional view at this point is shown in FIG. Thereafter, the phase change memory is manufactured by a normal semiconductor manufacturing process.
  • the phase change material film 55 of the three-dimensional type phase change memory cell according to the first embodiment has a main surface 551 adjacent to the gap fill portion 14 among the main surfaces (that is, the phase change).
  • the nitriding layer 12 is formed on the main surface of the material film 55 on the main surface on the center side of the memory chain 61.
  • phase change material layer 11 it is desirable to reduce the heat load after the phase change material layer 11 is formed. This makes it possible to prevent sublimation of the phase change material constituting the phase change material layer 11, non-uniform composition, and a decrease in density, thereby realizing a highly reliable phase change memory.
  • the polysilicon channel 13 is used as the channel of the cell selection MOS.
  • other semiconductors are used as the channel of the cell selection MOS. It goes without saying that it is possible.
  • an oxide semiconductor in particular, indium gallium zinc oxide (IGZO), In 2 O 3 , SrTiO 3 , KTaO 3 , TiO 2 , Ge, GaAs, GaP, GaN, carbon (graphene, fullerene) , Diamond), chalcogenide semiconductors, in particular ZnTe, layered chalcogenides, transition metal dichalcogenides, and organic semiconductors, in particular porphyrins.
  • the three-dimensional phase change memory manufacturing apparatus 170 includes a phase change material film forming chamber 171 that forms a phase change material layer by forming a phase change material in a vacuum state, and a nitride that is an oxidation-resistant insulator. Is formed in a vacuum state.
  • the nitride forming chamber 181 performs nitriding treatment on the main surface of the phase change material layer 11 formed in the phase change material film forming chamber 171 or forms a nitride layer on the main surface.
  • the phase change material film forming chamber 171 and the nitride forming chamber 181 are connected by a transfer chamber 174 so that a vacuum state can be maintained.
  • the transfer chamber 174 further includes a load / unload chamber 173, and a deposition target such as a silicon wafer is introduced into the transfer chamber 174 from the evacuated load / unload chamber 173 and provided in the transfer chamber 174.
  • the robot arm 175 is transported toward the phase change material film forming chamber 171 and the nitride forming chamber 181.
  • a deposition target such as a silicon wafer is introduced from the evacuated load / unload chamber 173, and then the inside of the transfer chamber 174, the phase change material deposition chamber 171 and the nitride formation chamber 181 is in a high vacuum state.
  • a deposition target such as a silicon wafer is introduced from the evacuated load / unload chamber 173, and then the inside of the transfer chamber 174, the phase change material deposition chamber 171 and the nitride formation chamber 181 is in a high vacuum state.
  • the main surface of the phase change material layer 11 is formed in the nitride formation chamber 181 while maintaining the vacuum state. Is nitrided or a nitride layer is formed on this main surface.
  • phase change material film 55 having the nitrided layer 12 is formed.
  • nitride layer 241 is formed on the surface of phase change material layer 11, phase change material film 55 having phase change material layer 11 and nitride layer 241 is formed.
  • phase change material layer 11 is not oxidized in the subsequent steps until the phase change material layer 11 is stabilized.
  • a phase change memory can be manufactured. As a result, a highly reliable phase change memory can be realized.
  • the three-dimensional phase change memory manufacturing apparatus 180 shown in FIG. 21 has a configuration including a nitridation chamber 172 for nitriding the main surface of the phase change material layer 11 as the nitride forming chamber 181.
  • the configuration of is the same as that of the phase change memory manufacturing apparatus 170 shown in FIG.
  • FIG. 22 is a schematic diagram of a manufacturing apparatus 190 that can manufacture a more reliable three-dimensional phase change memory.
  • the three-dimensional phase change memory manufacturing apparatus 190 includes a phase change material film forming chamber 171, a nitriding chamber 172, a precleaning chamber 191, a heat treatment chamber 192, and a protective film CVD film forming chamber 193. .
  • a silicon wafer as a film formation target is introduced into the load / unload chamber 173, and evacuation is performed in the load / unload chamber 173.
  • the subsequent steps are performed in a reduced pressure atmosphere.
  • the silicon wafer is transferred to the transfer chamber 174.
  • the transfer chamber 174 is kept in a high vacuum state.
  • the silicon wafer is transferred to the pre-cleaning chamber 191 by the robot arm 175 in the transfer chamber 174.
  • the natural oxide film layer formed on the polysilicon of the polysilicon channel 13 which is the base for forming the phase change material layer is removed.
  • the interface resistance between the polysilicon channel 13 and the phase change material layer 11 can be reduced, and the phase change with low operating voltage and low power consumption. Memory can be realized.
  • the method for removing the natural oxide film layer As a method for removing the natural oxide film layer, it is preferable to use isotropic etching using plasma. By using plasma, it is possible to remove the natural oxide film of polysilicon that is insensitive to the hole bottom. Needless to say, the method for removing the natural oxide film layer formed on the polysilicon can be performed by hydrofluoric acid cleaning. When hydrofluoric acid cleaning is used, the process until the hydrofluoric acid cleaning step is performed under atmospheric pressure, and after the cleaning, the silicon wafer is transferred to the phase change material film formation chamber 171 via the load / unload chamber 173. good. Thereby, the whole manufacturing apparatus can be reduced in size and an inexpensive manufacturing apparatus can be realized.
  • the silicon wafer is transferred to the phase change material film forming chamber 171 by the robot arm 175.
  • the phase change material layer 11 is deposited on the polysilicon channel 13 by the phase change material deposition chamber 171.
  • the silicon wafer is transferred to the nitriding chamber 172 by the robot arm 175.
  • the main surface of the phase change material layer 11 is nitrided by the nitridation chamber 172.
  • the phase change material film 55 having the nitriding layer 12 is formed.
  • the total film thickness of the phase change material layer 11 and the nitriding layer 12 is slightly higher than that of the phase change material layer 11 before nitriding. To increase.
  • the silicon wafer is transferred to the heat treatment chamber 192 by the robot arm 175.
  • the heat treatment chamber 192 is kept at a high temperature in advance, and the temperature of the transferred silicon wafer rises quickly.
  • the silicon wafer is annealed in vacuum by being held in a high-temperature heat treatment chamber 192 for a predetermined time.
  • the phase change material film 55 (the phase change material layer 11 and the nitriding layer 12) is held at a high temperature, thereby releasing impurities such as hydrogen contained therein (degas in vacuum) and increasing the density. If the density of the phase change material layer 11 is low, voids are generated along with rewriting, and stable rewriting becomes difficult.
  • the present inventors have experimented with hydrogen forward scattering analysis (HFS) and Rutherford backscattering analysis (RBS) that the phase change material formed by the CVD method contains hydrogen. Have confirmed. Furthermore, the present inventors have experimentally confirmed by thermal thermal spectroscopy (TDS) analysis that hydrogen contained in the phase change material layer 11 is released by the heat treatment.
  • the temperature for the heat treatment is preferably about 400 ° C., for example. If the heat treatment temperature is too high, the phase change material sublimes, and if it is too low, the reduction of impurities is insufficient.
  • the manufacturing time can be shortened when the heat treatment is performed after the nitriding treatment as compared with the case where the heat treatment is performed before and after the nitriding treatment.
  • the heat treatment is preferably performed after the nitriding treatment.
  • the heat treatment can be performed before the nitriding treatment, or that the heat treatment can be performed before and after the nitriding treatment.
  • the heat treatment can be performed before the nitriding treatment, deformation of the phase change material layer 11 and the nitriding treatment layer 12 can be reduced when impurities such as hydrogen are released.
  • the heat treatment temperature before nitriding is desirably about 200 ° C. If the heat treatment temperature is too high, the phase change material will sublime, and if it is too low, the reduction of impurities will be insufficient. Further, by performing before and after the nitriding treatment, the amount of impurities contained in the phase change material layer can be further reduced, and a phase change memory with higher reliability can be realized.
  • the silicon wafer is transferred to the protective film CVD chamber 193 by the robot arm 175.
  • the gap fill portion 14 is formed in the region surrounded by the phase change material film 55 by the protective film CVD chamber 193.
  • the method of forming the gap fill portion 14 is not limited to CVD.
  • the gap fill portion 14 may be formed by ALD or a coating method.
  • the amount of oxidation of the phase change material can be reduced by consistently performing the steps before and after the phase change material film forming step in a reduced pressure atmosphere. As a result, a phase change memory having a large number of rewritable times can be realized.
  • Example 2 an example of a three-dimensional phase change memory having a phase change part with more excellent heat resistance and oxidation resistance will be described with reference to FIGS.
  • FIG. 23 is a schematic cross-sectional view in one step of the manufacturing method of the three-dimensional type phase change memory according to the second embodiment.
  • Example 2 as shown in FIG. 23, the nitride layer 241 is formed so as to be in contact with the main surface 111 on the center side of the memory chain 61 among the main surfaces of the phase change material layer 11. Thereby, phase change material film 55 having phase change material layer 11 and nitride layer 241 is formed.
  • the nitride layer 241 can be formed by the nitride forming chamber 181 of the three-dimensional phase change memory manufacturing apparatus 170 shown in FIG.
  • the nitride constituting the nitride layer 241 may be an insulating material formed in a non-oxidizing atmosphere.
  • SiN silicon nitride
  • the nitride layer 241 may have any so-called oxidation resistance that prevents the phase change material layer 11 from being oxidized during the film formation, and may be insulative.
  • As the nitride in addition to SiN, AlN, GaN, CrN, MgN, ZrN, MoN, and nitrides containing these and other elements can be used.
  • the constituent material of the film formed on the main surface of the phase change material layer 11 is not limited to nitride, and is formed in a non-oxidizing atmosphere. Any insulating material may be used. For example, chalcogenide that is in an amorphous state and can maintain a high resistance state even through a manufacturing process such as ZnTe can be used.
  • the nitride layer 241 is provided in direct contact with the main surface 111 of the phase change material layer 11, the heat resistance and oxidation resistance of the phase change material layer 11 are more efficiently improved. Can be improved.
  • Example 2 is the same as Example 1 except that a nitride layer 241 is formed instead of the nitriding layer 12 as a region having an insulating material having oxidation resistance, and other phase changes are performed. Description of the configuration and manufacturing method of the memory is omitted.
  • Example 3 an example of a three-dimensional type phase change memory having a phase change part with more excellent heat resistance and oxidation resistance and capable of being manufactured in a short period will be described with reference to FIG.
  • FIG. 24 is a schematic cross-sectional view in one step of the manufacturing method of the three-dimensional type phase change memory according to the third embodiment.
  • a nitride fill portion 242 is formed so as to be in contact with the main surface 111 of the phase change material layer 11. That is, the region surrounded by the phase change material layer 11 in the memory hole 52 is filled with the nitride fill portion 242.
  • the nitride fill portion 242 prevents oxidation of the phase change material layer 11 and improves thermal stability, and it is necessary to form the gap fill portion 14 after the nitride fill portion 242 formation step. Absent. That is, the time required for manufacturing can be shortened by omitting the step of forming the gap fill portion 14.
  • the nitride fill portion 242 can be formed, for example, by a coating method or a CVD method.
  • the third embodiment is different from the first and second embodiments except that a nitride fill portion 242 is formed instead of the nitridation treatment layer 12 or the nitride layer 241 as a region having an oxidation resistant insulator.
  • a nitride fill portion 242 is formed instead of the nitridation treatment layer 12 or the nitride layer 241 as a region having an oxidation resistant insulator.
  • Phase change material layer 111 ... Main surface (main surface) of phase change material layer 11, 12 ... Nitrided layer, 13 ... Polysilicon channel, 131 ... Main surface of polysilicon channel 13, 14 ... Gap fill Part 15, cell selection gate electrode 16, 35 interlayer insulating film 17 upper electrode 18 gate insulating film 19 channel 32 base electrode 33 conductive electrode 36 laminating direction 41 Memory cell, 42 bit line, 43 word line, 51 phase change memory cell, 52 memory hole, 53 direction perpendicular to end face of phase change material film 55, main surface of phase change material film 55 , 55: phase change material film, 551: main surface of phase change material film 55, 61: memory chain, 62 ...
  • phase change memory semiconductor memory device 171 ... phase change material deposition chamber, 172 ... nitriding chamber, 173 ... load / unload chamber, 174 ... transfer chamber, 175 ... robot arm, 181 ... nitride forming chamber, 191 ... precleaning chamber, 192 ... heat treatment chamber, 193 ... Protective film CVD deposition chamber, 221... Selected memory cell, 231... Phase change portion, 232... Polysilicon MOS, X1, X2, X3, Y1, Y2, Y3... Gate electrode, 241. Fill part

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Abstract

L'invention concerne un dispositif de mémoire à semi-conducteurs présentant une excellente réinscriptibilité et une haute fiabilité. Le dispositif de mémoire à semi-conducteurs comprend une chaîne de mémoire 61 dans laquelle une pluralité de cellules de mémoire à changement de phase 51 comportant un film de matériau à changement de phase 55 sont connectées en série, le film de matériau à changement de phase 55 comportant une couche isolante résistant à l'oxydation 12 formée sur le côté surface principale du côté central de la chaîne de mémoire 61.
PCT/JP2015/065691 2015-05-29 2015-05-29 Dispositif de mémoire à semi-conducteurs, son procédé de fabrication, et dispositif de fabrication de dispositif de mémoire à semi-conducteurs WO2016194092A1 (fr)

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