TWI325166B - Programmable resistive ram and manufacturing method - Google Patents

Description

1325166 IX. Invention Description: [Priority] This application claims the priority of US Provisional Application No. 60/757,275. The application date is January 9, 2006. The inventor’s family name is: Method of Resistance Random Access Memory Device with Resistor-on-electrodes Structure o [Technical Field of the Invention]

The present invention relates to integrated circuit non-volatile memory, and more particularly to programmable resistive non-volatile memory, such as phase-change memory. [Prior Art] Non-volatile memory can store data without the need to continuously supply power. Therefore, non-volatile memory is not only useful in integrated circuits with non-volatile storage as the main integrated circuit, but also in power circuit integrated circuits other than data storage. Bu

A multi-function circuit that combines multiple functions with a variety of functions will lead to the creation of a program. If the multi-function integrated circuit was originally designed to produce non-volatile energy, the manufacturing procedure must be changed to make the road. In the state of good thinking, this kind of change is for the integrated electric meter, that is, the long electric material, non-volatile The problem of the basic setting of the memory is still in the non-volatile memory and the remaining two ideal states. The smaller the __the second capacitive problem is, the better the 4 is, so that the manufacturing process is in the manufacturing process. 】 Memory fine ^ γ to form - a method with a non-volatile body circuit. This method is used to access a circuit of a particular memory cell prior to forming a non-volatile programmable element to electrically couple the programmable resistive element. In view of the fact that the sequence of steps in this embodiment is not used to form a process for forming an access circuit, the step of forming a programmable resistive element is to take the electricity of a particular non-volatile memory cell. Each column is to access the conductive columns of the memory cells, and the column system is substantially perpendicular to the conduction mode. The combination of the selected row and column is less than the selected row and column. And to = have at least one etch stop signal difference? ί: remove the second conductive row layer. The thickness of the sidewall is up to the nanometer. I walked through the material. The access circuit also includes the respective conductive resistors H in the integrated circuit; a small portion of the electrical layer is formed in some embodiments that can be programmed to form an interlayer dielectric layer after forming the conductive columns. A step of. The step of forming an electrically conductive row of at least one first dielectric t im non-volatile memory cell before the formation of the conductive row is performed, wherein at least one of the etching end signal differences is obtained, And an etching option; the bismuth dielectric layer is at least partially covering the second dielectric layer, and the second is forming at least one ί 10 nm to 50 nm. In some embodiments, the first dielectric layer is formed. In the less one = point signal difference, ^ different embodiments are related to the formation of the meaning; between the ir1 dielectric layer and 匕us. In some embodiments, the method of "signaling the grammar" is to electrically connect the conductive lines and the programmable 'taste:!; bottom: =, in the hole, to guide; the step of conducting the structure in the holes: shape The holes are formed in the holes to form a dielectric liner to form the conductive columns and to conduct electricity only by the embodiment. A 耘 电阻 电阻 电阻 电阻 电阻 电阻 电阻 电阻 电阻 电阻 电阻 电阻 电阻 电阻 电阻 削 削 削 削 削 削 削 削 削 削 削 削 削 削 削 削 削 削 削 削 削 削 削 削 削 削 削 削Each of the embodiments includes mechanical grinding on the second dielectric layer, chemical machine = part of the third dielectric layer, until the integrated circuit = circuit with cells of non-volatile memory cells' includes: Accessing the non-volatile memory-conducting conductive rafts via rows and 7 1325166 ί. The integrated circuit also includes a programmable resistance element of the non-volatile memory cells. Each stylized resistive element is electrically connected to the conductive column and the conductive row. This programmable resistance element is located vertically above the conductive column 盥g ::. In some embodiments, the programmable resistive element comprises at least one of: chalcogenide, PrxCayMn〇3, PrSrMn03, ZrOx, TCNQ, and PCBM. In some embodiments, the circuit includes a first dielectric layer of electrically conductive columns such that the electrically conductive rows are above the first dielectric layer | ^ at least partially adjacent to the electrically conductive rows and at least partially Adjacent to the electrical layer, a second dielectric layer at least partially covering the second strip; and a layer indirect point (4) to the layer of the material, the layer comprising the electrically conductive substrate electrically conductively connecting the conductive lines and The stylized resistor is electrically conductive only through the programmable resistive element. Conductive connection of the conductive columns and can be used, some of the implementation of the first, the dielectric layer includes the following groups - the oxidized stone eve (SiOx) and the mediation of the mine, the electric shore including the lower two 丄fi low The material of 3; the second layer includes at least one of the following groups: nitrite Xi (Six (SiOxNy), and oxidized stone Xi (X〇x)) 1 = Shi Xi group J at least - Yu ( It is called Jiedi Electric; oxidized hair (Sl〇xNy), and nitriding (Si • lead = only |, including at least the following groups: Titanium Titanium (TlN),) Titanium (τιΝ/Τι) double layer, nitrided (TaN), tungsten (w, 匕 匕 匕 氧化 氧化 氧化 氧化 Li Li Li Li Li Li Li Li Li Li Li Li Li Li Li Li 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 Li Li Li Li Li Li And a dielectric substrate comprising at least one of the following groups: cesium (SiOx), bismuth oxynitride (Si〇xN), gas = barium titanate (SrTi03) Wwxj, Μ and in some embodiments 'this circuit further includes a fourth dielectric layer which is at least 8 1325166 4 knives located in the programmable dielectric element and the conduction system including the following dielectric layer (SiOxNvY less Emulsified Shi Xi (Si〇X), Nitrous Oxide O (A1〇x) (SlNX), Titanate Pin (SrTi〇3), and Oxygen In some embodiments, the conductive line includes first and first Second, the first and second conductive row layers have a stepped surface, and the two rows of layers include at least one of the following groups: a nitride/chin (TiN/Ti) double layer, a crane/titanium nitride (y/^ N) double layer, copper aluminum/titanium nitride (A1Cu/TiN) double layer, etched 曰曰 曰曰 以及 and metal lithium, and the second conductive layer layer includes the lower jaw, 】, at least one of the group : Steel aluminum, titanium nitride / copper aluminum (TiN / A1Cu) double layer, titanium nitride / titanium / copper aluminum (TiN / Ti / AlCu) three layers, tungsten, metal bismuth, and doped polycrystalline [Embodiment] Various embodiments provide a rapid manufacturing method for a memory. Volatile built-in suffix uses a resistive element. "Resistance element & eight-resistance memory (RRAM), polymerization Memory, and phase-converted Ik machine access memory (pCRAM). Figure 1 is an illustration of a process flow diagram for adding a programmable memory to an integrated circuit. of The last step. This non-volatile electric current is formed on the electrode that has already been fabricated. Prior to this, the resistance one: in the general procedure of the remaining part of the circuit, is not filthy. In the transistor/column selection completion step 2, the function of the non-volatile storage of the stylized resistor in the integrated circuit is: a column access circuit including a programmable resistor RAM. After the transistor\step, this The programmable resistance element is made = 2 before the programmable resistance element, only 15 general processes are in step = actual 9 1325166 'in metal deposition 4, metal lithography 6, and metal engraving 8, through each line A conductive line that accesses the programmable resistor RAM is formed. The etch control in the metal etch 8 forms a stepped cross-section from the conductive rows that reduces the contact resistance between the metal lines and the programmable resistive elements. The via lithography 14, the via etch 16, and the wet immersion 18, ' form a via that allows the conductive material to connect the column access circuitry to the programmable resistive element and cause the conductive material to survive Take the circuit connected to the programmable resistance element. The via holes are self-aligned in the via etch 16 technique. The insulator and conductor structures of fixed width in the via are formed by two etching steps, namely metal etching 8 and via etching. Metal deposit 20 and metal spacer etch 22 form a conductor material for connecting the column access circuitry to the programmable resistive element. Dielectric deposition 24 and dielectric etchback 26 form a dielectric layer that is used to connect the column access circuitry to the conductor material of the programmable resistive element and to connect the row access circuitry to The conductor material of the programmable resistance element forms an isolation between the conductor materials. To adjust the electrical properties of the resistive element, the thickness of the metal and dielectric spacer structures in the via window can be varied, while the metal and dielectric spacers are attached to the metal deposit 20, the metal spacer etch 22, and the dielectric deposition 24 And forming in dielectric etchback 26 and the like. Metal deposit 28 forms a conductor material for connecting the column access circuitry to the programmable resistive element. The chemical mechanical polishing 30 and the chemical mechanical polishing cleaning are performed 32 steps before the actual programmable resistance element is formed. Finally, the programmable resistive element is formed by steps such as resistive deposition 34, resistive lithography 36, and resistive etching 38. The final step in this process is done when the process leaves 40. Due to the metal step profile formed by the three self-aligned processes, the opening of the via hole is located on the metal column, and the small electrode system in the via is in contact with the column access circuit, and each memory cell line follows or The level design criteria for the transistor are almost followed. In certain embodiments, the non-volatile memory cell region is less than 8.5 F2 and the F system is a feature size. These three self-aligned processes, 1325166, also improve yield and form electrodes prior to forming resistive elements. Since the resistive element is finally manufactured, processes that may damage the resistive element such as grinding, etching, high temperature processing, cleaning, etc. are all performed before the formation of the resistive element. This process also makes it relatively easy to add a built-in memory to an integrated circuit having other functions because the basic steps compatible with conventional semiconductor processes have been performed prior to the formation of the programmable resistive element. In addition, the process of the resistive element is relatively simplified, and it is only necessary to form a resistive element over the previously formed electrode. Figure 2 is a cross-sectional view showing the initial step of the lithographic process of the conductive row. This conductive row accesses the programmable resistive elements along the rows.

The dielectric layer 56, the conductive layer 58, the conductive layer 60, and the dielectric layer 62 are deposited on the interlayer dielectric (ILD) 52' junction 54 and the local interconnect (LIC, not shown in the figure. Above the surface of the common source). The column selection circuit 50, located between the interlayer dielectric 52 and the contact 54, includes circuitry along the columns, a programmable resistor memory (eg, a column select transistor), and a non-volatile memory product of the programmable resistor. A circuit outside the body circuit. Exemplary materials for dielectric layer 5〃6 are Si〇x and low dielectric materials. The example material of the conductive layer 58 is titanium nitride, titanium (Ti), atmosphere, or nitriding titanium (w 绍化 ί doped two and metal =

In Li, the material of the conductive layer 58 is different from the conductive layer 60, and the first layer of the conductive layer 60 is different. ^ (〇TiN/Ti/AlCuT ore, metal scrap, bismuth and recording dress + eve. The material has a good 'sticky to the conductive layer 58: Ba矽, etc.: the material of the conductive layer 60, the last name will stop at the conductive Attached to 'and in the conductive layer 6 〇 by the name / (111) chaotic titanium), (titanium nitride) / (tungsten / titanium nitride), 屮 5166 (n + doped polysilicon) and so on. (10) is a), oxidation is nitrogen cut (ah), material pair of oxynitride layer 62 and titanic acid error (sm〇3). The dielectric sound 62, the resistance, and the resistance of 7 ° have a good adhesion. And the change, θ is as follows, the detailed example material is the material of the resistive element for the phase transition resistance element of the GST or the doped 1 dielectric layer 62, and the nitrogen oxynitride is the oxidized stone 峨 (峨) , Nitride Xi (XNx), for Pr Ca 1U / 'cause is thermal conductivity considerations. Example 2 of 62) Implicit, resistive element, dielectric layer fossil (SiO is), and titanic acid ($ 匕石, (SiNx), nitrox and crystallization factors. 1 3), The reason is adhesion to yttrium, in TCNQ, PCBM, copper-TCNQ, carbon 60 Τ "χτ, memristive element, dielectric sound = 6〇-tcnq and other polymers (called), oxynitride (Sl0Ns) VI The material of the example is 'Oxidized Oxide, the original is started with 1 test ^. 2 in Guan Yu / J Yan! " Micro (four) material, material electricity * photoresist 6 4 you μ, B & example, line spacing Connected to the transistor and connected to the ^^^^': the direction of the distance is perpendicular to ^^: :::^: electricity. The interpole of the transistor, or the multi-faceted edge of the transistor is shown in the photoresist layer. The upper sidewall surname structure is related to the structure, and the photoresist layer covers the layer and the memory dielectric layer 62 and the conductive layer 60 are etched using a photodiode. 64 μ and a suitable etch 62 For the material of the dielectric layer 62 being oxidized or oxidized by oxynitride: the example of the money 12 1325166 is a reactive ion etching using carbon tetrafluoride, trifluorodecane, argon, and nitrogen. Wait, An opening is formed in the dielectric layer 62. For the material in which the dielectric layer 62 is tantalum nitride: an etching example is: reactive ion etching using carbon tetrafluoride, trifluorodecane, difluorodecane, Fluoromethane, oxygen, argon, etc., to form openings in the dielectric layer 62. For the dielectric layer 62 is a material for oxidation: the example is a reactive ion residue, which uses carbon tetrafluoride, Trichloride, trifluorocarbon, carbon monoxide, oxygen, argon, etc., to form openings in the dielectric layer 62. The conductive layer 60 is etched using a suitable compound and stopped by etching selectivity or etching the end point signal The conductive layer 58. • A specific example of etching the conductive layer varies with the material of the conductive layer 60, as follows: For the conductive layer 60 / the conductive layer 58 is aluminum copper / titanium nitride: etching example It is a reactive ion etching using chlorine gas, boron trichloride, argon gas, nitrogen gas or the like to form an opening in the conductive layer 60, and the etching is stopped at the conductive layer 58 by an etching end point signal. For the conductive layer 60/ Conductive layer 58 is tungsten/titanium nitride The example of etching is reactive ion etching using sulfur hexafluoride, oxygen, nitrogen, argon, etc. to form openings in the conductive layer 60, which utilizes high etch selectivity of tungsten and titanium nitride. For the conductive layer 60 / the conductive layer 58 is a tungsten germanium / n + doped polysilicon: the etching example is reactive ion etching, which uses chlorine gas, nitrogen gas, helium / oxygen, carbon tetrafluoride, oxygen, and Or argon or the like to form an opening in the conductive layer 60, which uses an end point signal to stop the etching on the conductive layer 58. The polymer sidewalls are formed by the following exemplary compounds: octafluorocyclobutane (C4F8), six Fluorine-1,3-butadiene (C4F6), carbon tetrafluoride, fluorocarbon, trifluorodecane, difluoromethane, argon, nitrogen, and/or oxygen, etc., at appropriate power, pressure, and Performed under other parameters. The thickness of the polymer sidewalls is between 10 nm and 200 nm. The polymer sidewalls are re-etched using reactive 13 1325166 ions, using the appropriate compound as the dielectric layer 62 and the conductive layer 60. Figure 4 is a cross-sectional view showing the lithography starting step of the via window to electrically connect the programmable resistive memory and the conductive column, and electrically connect the programmable resistive memory and the conductive row, wherein the conductive column The programmable resistive memory is accessed along the columns, and the conductive traces access the programmable resistive memory along each row. Conductive layer 58 is etched and stops at dielectric layer 56. The sidewall polymer and the remaining photoresist act as a mask for the metal line lithography process. The specific etching example of conductive layer 58 varies with the material of conductive layer 58, as follows: For conductive layer 58 / dielectric layer 56 is titanium nitride / cerium oxide: etching examples include Reactive ion etching using chlorine gas, boron trichloride, argon gas, and/or nitrogen gas to form an opening in the conductive layer 58 utilizing high etching selectivity between titanium nitride and germanium dioxide . For the conductive layer 58 / dielectric layer 56 is n + doped polysilicon / dioxide dioxide: the remaining examples include reactive ion remnants, which use desertified hydrogen, chlorine, nitrogen, helium / oxygen Oxygen, and/or argon, etc., to form openings in the conductive layer 58 and use a high etch selectivity between the polysilicon and the cerium oxide. The residual polymer is stripped using oxygen, nitrogen, and/or oxygen/hydrogen plasma. Under the influence of the sidewall polymer, the wire becomes a self-aligning step. The step width depends on the thickness of the polymer sidewalls. Dielectric layer 68 is deposited over dielectric layer 56, conductive layer 58, conductive layer 60, and dielectric J62. The material of the dielectric layer 68 is SiNx, SiOxNy, SiOx, or the like. Dielectric layer 68 acts as a dry etch stop layer for dielectric layer 70. The dielectric layer 68 is selectively wet etched to form an opening in the stepped conductive layer 58 after further via etching, such that there is a wet etch between the dielectric layer 68 and the dielectric layer 54 14 1325166. Selective. In one embodiment, the material of dielectric layer 68/dielectric layer 56 is tantalum nitride/yttria. Dielectric layer 68 can have a thickness from 10 nanometers to 50 nanometers. A dielectric layer 70 is deposited over the dielectric layer 68. Dielectric layer 70 can be germanium oxide, low dielectric material, hafnium oxynitride, and/or hafnium nitride. The dielectric layer '70 is mainly a dielectric metal dielectric material (IMD). The dielectric layer 70 can be formed by high density plasma chemical vapor deposition (HDPCVD), spin on glass (SOG), plasma enhanced chemical vapor deposition (PECVD), and/or spin coating methods. Chemical mechanical polishing (CMP) is used sexually. The material of the dielectric layer 70 is different from the material of the dielectric layer 68. Dielectric Layer 70/Dielectric • An exemplary material for layer 68 is tantalum oxide/tantalum nitride. After planarization of the dielectric layer 70, via lithography is performed. The spacing can be the same as the spacing between the transistor contacts and the metal lines. A portion of the exposed window is superposed on the wires 58/60. The boundary layer lithography process begins with photoresist 72. Figure 5 is a cross-sectional view showing the sidewall structure in the via window, which is formed by electrically connecting the programmable resistive memory and the conductive row, and the conductive traces access the programmable resistor along each row. Memory. The etching of the via window is stopped by the dielectric layer 68 using a via photoresist. Due to the high etch selectivity between the dielectric layer 70 and the dielectric layer 68, the dielectric layer 56, the conductive layer 58, the conductive layer 60, and the dielectric layer 62, the etching process is damaged to the dielectric layer 70 to avoid . The specific example of etching of the dielectric layer 70 may vary depending on the material of the dielectric layer 70, as follows: For the dielectric layer 70/dielectric layer 68 is a material of tantalum oxide/tantalum nitride: etching Examples include reactive ion etching using octafluorocyclobutane (C4F8), hexafluoro-1,3-butadiene (C4F6), trifluorodecane, carbon tetrafluoride, argon, oxygen, and/or Or nitrogen or the like to form an opening in the dielectric layer 70 and stop at the dielectric layer 68 by the high etching selectivity of yttrium oxide to tantalum nitride. The residual polymer is stripped using oxygen, nitrogen, and/or nitrogen/hydrogen plasma. Dielectric # / 浸浸适#Solution #1 and carry out the wet remnant. The dielectric layer 58 is not integrated, and the conductive layer 58 is formed on the step of the conductive layer W with the dielectric layer 56. Forming an opening on the same but a specific example, as the dielectric layer 68 is etched to form an opening, 68=n is a tantalum nitride/yttrium oxide, and an opening is formed, which uses a hot phosphoric acid. The high etch selectivity of the dielectric layer is stopped at the dielectric layer = bismuth bismuth oxide. If the material of the material and the dielectric layer 68 may be the same or not, the shape of the layer 68; ^=4. In the same way, the dipping time of the job is relatively short, and the dielectric conductive layer is electrically formed on the dielectric layer 56 and the conductive layer 58 and the structure 74 can be improved by the chemical layer. Degree of shape. Conductive electrodeposition and other methods are used to: phase deposition, organometallic chemical vapor deposition, or crystallization; 二τΚΓ^Γτ material, the second structure% of the material can be nitrogen (TaN), ^ rt, 〇, chaotic titanium / Titanium (TiN/Ti) double layer, nitrided 钽Hr. , (W), aluminum (A1), lithium niobium oxide (LiNb〇3), oxidized 矽 矽 气 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 : Electricity: and doped polycrystalline germanium. The specific material of the conductive structure 74 varies depending on the material as follows: Tomb 1 or the G 2 擦 之 G Τ Τ Τ Τ Τ Τ Τ 。 。 。 。 。 。 。. Examples include titanium nitride, nitride buttons, tungsten, or lithium ruthenium oxide. In the case where the lightning resistance element is a material of PrxCayMn〇3, a dry example of the conductive material 包括'Ζ includes lithium lanthanum oxide, YBaCuO, LaCaMn03, or Ming.

For the polymer § Remembrance resistance elements are TCNQ, PCBM, Cu-TCNQ 16

For the material of 丄JZDiOO: Examples of conductive structure 74 include the example of electricity: the structure of the money is made using a high bombardment reactive ion double, to 4 4 carbon eight, and / or a suitable compound to form ^直气, "The polymer layer on the i layer is depleted of oxygen, and the nitrogen is used as a cross section, and the electrons are connected to each other." It is listed in the Husband and the household & the resistance memory and the conductive column, these conductive 'human ^bt / ί? access to the programmable resistance memory. " electric,, '. 6-series deposition Yu Jie ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 56 above, and has a good shape of the electric flow layer / guide "structure 74 and dielectric layer. Dielectric = 6 diit cut, dielectric structure 76 has good adhesion to the resistance element. The change, as described below: another example will be based on the difference in the resistance of the material, the doped GST and other phase conversion resistance elements: ΪΪ2 to oxygen cut, nitrogen oxygen _, and nitrogen _ to think that PrAMn01 Material: medium total, etc., test (four) material (four), nitrogen cut, or titanic acid

For the polymer, remember and use the long day or carbon sixty-TCNQ TCNQ, PCBM, Cu.TCNQ often. Milk oxidized oxide, nitriding sand, or oxidized, the consideration is that the U-U is bombarded with high bombardment and no mask is used. The material of the electrical structure 76 and the dielectric layer 56 is different for the dielectric structure 7 = 6 ^ 矽 / 矽 :: rhyme = emulsified 矽 / 矽 矽 or nitrogen Examples of oxygen etching J include reactive ion etching, which uses carbon tetrafluoride, trifluorodecane, argon, and/or nitrogen to form an opening in dielectric structure 76 and dielectric layer 56, and Stop at junction 54 and generate column selection circuit 50. For the dielectric structure 76/dielectric layer 56 is alumina/yttria: examples of etching include reactive ion etching using carbon tetrafluoride, boron trichloride, 'nitrogen trifluoride, carbon monoxide, oxygen And/or argon or the like to form an opening in the dielectric structure 76, and transfer reactive ion etching using carbon tetrafluoride, trifluoromethane, argon, and/or nitrogen to form an opening in the dielectric layer 56. And stopping at the contact 54 to generate the column selection circuit 50. Depending on the nature of the compound, the etch rate of the conductive structure 74 is lower when the dielectric structure 76 and the dielectric layer 56 are etched. Thereby, the conductive structure 74 is exposed. The dielectric structure 76 prevents the conductive structure 74 from forming a leakage current to the column selection circuit 50. The thickness of the dielectric structure 76 is between 5 nm and 100 nm (i.e., the width of the sidewalls of the dielectric structure 76 is between 5 nm and 100 nm). The remaining polymer is stripped using oxygen, nitrogen, and/or nitrogen/hydrogen plasma. Conductive electrode 78 is filled into the void defined by dielectric structure 76. This conductive electrode 78 is connected to the junction 54 of the column selection circuit 50. A conductive electrode 78 is deposited over the dielectric layer 70, the conductive structure 74, the dielectric structure 76, the dielectric layer 56, and the contacts 54 of the column select circuit 50. The conductive electrode 78 may be chemical vapor deposited tungsten, or chemical vapor deposited titanium nitride, physical vapor deposited nitride button/electrodeposited copper, etc., and is thick enough to cover the entire surface. Figure 7 is a cross-sectional view > which shows the results of removal of excess material by chemical mechanical polishing. The chemical mechanical polishing performed on the conductive electrode 78 plays an important role in productivity. The conductive electrode 78 is ground until the conductive structure 74 is exposed and further ground until it contacts the dielectric layer 70. 18 1325166 The dielectric layer 70 is ground until the outer portion is exposed until the dielectric layer 62 is exposed. Electro-slip 68, and further study of the chemical mechanical polishing slurry does not have a pin dielectric structure 76, a conductive electrode 78, and a level 3 70, a dielectric layer 68, and a selective selective etch rate. The % structure 74 of the slurry is particularly well-known in certain embodiments after being ground and intercalated as cerium oxide. The widths of the 74 are the same to obtain the same electrical g 76 and the electrically conductive structure. After the grinding step, a brushing cleansing shoe, an open circuit between the second 78 and the electrically conductive structure 74 is performed. It can be ensured that the conductive electrode in Fig. 8 is a cross-sectional view showing the non-volatile material of each non-volatile memory cell, and the specific example of the storage resistance element deposition process will follow The type of volatile memory element changes, for example, the resistance of the resistor is not for the phase-conversion resistor element.

GexSbyTez (GST), N2-doped GST, Ge, g dry materials include the use of different crystalline phase transition phenomena to determine the electrical enthalpy and y or any other for resistive memory resistor components: resistive materials. PrCaMnOg, PrSrMn03, ZrOx, or any of the other materials include (different polarity) to change and maintain the resistance state of the 'material use voltage pulse for the polymer memory resistance element: resistance element boast>> steel-TCNQ, Silver-TCNQ, carbon sixty-TCNQ, ^ examples of material encapsulation of TCNQ, PCBM, TCNQ-PCBM, or any; ^ with metal sinking pulse or a current density control of the bistable ° two and ~ material. % 疋 resistance state: More broadly, the resistance element may include any dexterous and bistable or multi-stable 4 degree 'current polarity' or any electrical characteristic pressure; the thickness of the resistance element 80 will be the same as the rod state. The electric field electrode 78 is electrically connected to the conductive structure 74 by J' and the electrical structure 74. The moment 19 1325166 between the conductive pole 78 and the conductive conductor is adjustable and varies with the width of the dielectric structure 76. In some embodiments, the resistive element has a cover layer to protect against air. The characteristic properties of the contact are changed. In some embodiments, the pattern of resistive elements is defined by a square lithography process. The length dimension is perpendicular to the direction of the conductive rows, and the conductive traces are comprised of conductive layer 60 and conductive layer 58. The length of the resistive element begins in a region defined by the conductive electrode 78, through the dielectric structure 76, the conductive structure 74, and ends in the region defined by the dielectric layer 62. Before the element, a trimming or shrinking process can be used, such as a wet dipping coating. The specific example of the etching compound in the resistive element etching step will vary depending on the material of the resistive element, as follows: For resistive elements such as GST or GST doped with N2: examples of etching compounds include carbon tetrafluoride, chlorine, argon, oxygen, trifluorodecane, and/or nitrogen, etc. Resistive elements such as PrCaMn03, etc.: examples of etching compounds include argon, carbon tetrafluoride, and/or oxygen, etc., for etching with high bombardment. For resistive memory resistance elements such as copper-TCNQ, etc.: Examples of etching compounds include Oxygen, argon, and/or carbon tetrafluoride to make a blanket with a hard mask of the overlay. Figure 9 is a top view of a programmable resistive non-volatile memory cell array. It is located under the corresponding conductive structure 74, dielectric structure 76, and conductive electrode 78. The horizontal position of the contact 54 is indicated by a broken line. The exposed portion of the dielectric layer 68 is visible in the figure. And parallel to the conductive rows 58, 60 and the dielectric layer 62. The exposed portion of the dielectric layer 62 is also shown adjacent to the exposed portion of the dielectric layer 68, and the exposed portion of the dielectric layer 70 is adjacent to The dielectric layer 68 and the exposed portion of the dielectric layer 62. As shown in Fig. 8, the resistive element 80 is electrically connected 20 1325166 to the conductive electrode 78 and the conductive structure 74. Embodiments of the memory cell include the resistive element 8, Material package Chalcogenide materials and other materials. Dimensions = include the following four elements: oxygen (0), sulfur (8), code and strontium (Te), forming the part of the element family on the periodic table.) - chalcogens and - more positively charged elements or bismuth bismuth compound alloys include combinations of chalcogenide compounds with other materials; : = metals, etc. - chalcogenide alloys usually include

Often, chalcogenide alloys include one of the following elements: 2; recording (Sb), gallium (Ga), indium (f), and silver (Ag) H = spine-based memory materials have been described in the technical documents, $金: gallium / recording, steel / recording, indium / bismuth, brocade / 碲, 锗 / 碲, wrong / recorded ^ 锦 / 碲, gallium / 砸 / broken, tin / recorded / 碌, indium / recorded / wrong, silver /Copper/Jin/娣/碌,锗/录/砸/hoof, and hoof/锗/锑/sulphur. In the 锗/录/蹄人, you can try a wide range of alloy compositions. This component can have the following two characteristics, indicating iTeaGebSb^o^w. One researcher described the most useful alloy system in that the average enthalpy concentration contained in the deposited material is well below 7〇%, typically below 60%, and the bismuth content in the general type alloy ranges from The lowest is 23% to the highest 58%, and the best system is between 48% and 58%. The concentration of cerium is above about 5% and its average range in the material ranges from a minimum of 8% to a dare! 30% 'generally less than 50%. Optimally, the range of 锗 is between 8% and 40%. The main component remaining in this ingredient is hydrazine. The above percentages are atomic percentages, which is a total of 100% for all constituent elements. (Ovshinky '112 patent, column 1 〇 ~ η ) Special alloys evaluated by another researcher include Ge2Sb2Te5, GeSb2Te4, and GeSb4Te7. (Noboru Yamada, ''Potential of Ge-Sb-Te Phase-change Optical Disks for High-Data-Rate Recording,,, iST/fi1 v.JiOP, pp. 28-37 (1997)) More generally, transition metals A mixture or alloy such as complex (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt), and the above 21 1325166 may be combined with 锗/锑/碲 to form One phase transition alloys include programmable resistance properties. A special example of a memory material that can be used is described in the Ovshinsky '112 patent, Blocks 11-13, examples of which are incorporated herein by reference. The phase inversion material is switchable between the first structural state in which the material is in a generally amorphous state and the second structural state in a generally crystalline solid state in the cell active channel region. These materials are at least bistable. The term "amorphous" is used to refer to a relatively unordered structure that is more unordered than one of the single crystals, with detectable features such as higher resistance values than the crystalline state. The term "crystalline" is used to refer to a relatively ordered structure that is more ordered than amorphous and therefore includes detectable features such as lower resistance than amorphous. Typically, the phase inversion material can be electrically switched to all detectable different states between the partially crystalline fully crystalline state and the fully amorphous state. Other materials that are affected by changes in amorphous and crystalline states include atomic order, free electron density, and activation energy. The material can be switched to a different solid state, or can be switched to a mixture of two or more solids, providing a gray-scale portion from amorphous to crystalline. The electrical properties of this material may also change. The phase change alloy can be switched from one phase to another by applying an electrical pulse. Previous observations indicate that a shorter, larger amplitude pulse tends to change the phase of the phase change material to a substantially amorphous state. A longer, lower amplitude pulse tends to change the phase of the phase change material to a substantially crystalline state. The energy in the shorter, larger amplitude pulses is large enough to break the bond of the crystalline structure while being short enough to prevent the atoms from re-arranging into a crystalline state. In the absence of undue experimentation, an appropriate pulse amount curve that is particularly suitable for a particular phase change alloy can be determined. In the subsequent part of this article, this phase-converting material is referred to as GST, and we also need to understand that other types of phase-converting materials can be used. One of the materials described in this document for use in PCRAM is Ge2Sb2Te5. Other programmable memory materials 22 1325166 that may be used in other embodiments of the invention include 'G2 doped N2, GexSby, or other materials that are converted by different crystalline states to determine electrical resistance; PrxCayMn03, PrSrMnO, ZrOx, TiOx, NiOx, W0X, doped SrTi03 or other materials that use electrical pulses to change the electrical resistance state; or other substances that use an electrical pulse to change the resistance state, TCNQ (7,7,8,8-tetracyanoquinodimethane), PCBM (methanofullerene 6,6-phenyl C61-butyric acid methyl ester), TCNQ-PCBM, Cu-TCNQ, Ag-TCNQ, C60-TCNQ, TCNQ doped with other substances, or any other polymeric material including A bistable or multi-stable resistance state controlled by electrical pulses. Next, four types of resistive memory materials are briefly described. The first type is a chalcogenide material such as GexSbyTez, where x:y:z = 2:2:5, or other components are X: 0~5; y·· 〇~5; z: 〇~1 Hey. GeSbTe doped with nitrogen, niobium, titanium or other elements can also be used. An exemplary method for forming a chalcogenide material is by pVD ruthenium plating or magnetron sputtering, the reaction gas is argon, nitrogen, and/or oxygen, and the pressure is 1 mTorr to 1 Torr. mTorr. This deposition step is generally carried out at room temperature. A collimator with a length to width ratio of 丨~5 can be used to improve its filling performance. In order to improve its filling performance, a DC bias of tens to hundreds of volts can also be used. On the other hand, it is also feasible to use a DC bias and a collimator in combination with φ. A post-deposition annealing treatment may be selectively performed in a vacuum or in a nitrogen atmosphere to improve the crystalline state of the lanthanide material. The temperature of this annealing treatment is typically between 1 Torr. 〇 to 400 ° C, and the annealing time is less than 30 minutes 0 The thickness of the chalcogenide material depends on the design of the cell structure. In general, the thickness of the chalcogenide greater than 8 nm may have phase transition characteristics such that the material exhibits at least a bistable resistance state. The second memory material suitable for use in embodiments of the present invention is a super giant magnetoresistive (CMR) material, such as PlxCayMn〇3, where x:y = 〇5: 〇5, or other component is X: 〇~ 1; y: 0~1. Super giant magnetoresistance including manganese oxide 23 1325166 material can also be used. - An exemplary method for forming a giant magnetoresistive material, using PVD money, or magnetron sputtering, wherein the reaction gas is argon, nitrogen, and/or helium, at a pressure of 1 mTorr to 100 mTorr. The temperature of this deposition step can range from room temperature to 60 (TC, depending on post-treatment conditions. A collimator with an aspect ratio can be used to improve its filling performance. In order to rewrite its filling performance' It is also possible to use a DC bias of tens to hundreds of volts. It is also possible to use a DC bias and a collimator on the other side. It is possible to apply tens of Gauss to 1 Tesla (tesla, 1〇). The magnetic field between the 〇〇〇Gauss) to improve its magnetic crystalline state. A post-deposition annealing treatment can be selectively performed in a vacuum or in a nitrogen atmosphere to improve the crystalline state of the giant magnetoresistive material. The temperature is typically between 400 ° C and 600 ° C, and the annealing time is less than 2 hours. The thickness of the super giant magnetoresistive material is determined by the design of the memory cell structure. The thickness is between 10 nm and 200 nm. The giant magnetoresistive material can be used as the core material. A YBCO (YBACu〇3, a high-temperature superconductor material) buffer layer is usually used to improve the crystallization state of the giant magnetoresistive material. This YBCO deposition system is Thickness system before deposition of super giant magnetoresistive materials . 30 nm to 200 nm in a second memory material s have dual element based compound, a 1 ^ WT < 7- a 'Nix〇y e.g., TixOy,

24 1325166 A post-deposition annealing treatment is performed to improve the oxygen atom distribution within the metal oxide. The temperature of this annealing treatment is typically between 400 ° C and 6 Torr. 〇 , and the annealing time is less than 2 hours. An alternative method of formation is to use PVD sputtering or magnetron tube plating. The reaction gases are argon/oxygen, argon/nitrogen/oxygen, pure oxygen f ammonia/oxygen, helium/nitrogen/oxygen, etc., pressure It is 1 mT〇rr to 1〇〇3Τ〇ΓΓ 'its dry metal oxides are such as Ni, Ti, Al, w, 7n,

> Oil B II 1~5. This deposition step is generally carried out at room temperature. A length to width ratio is available, and a straightener can be used to improve its fill performance. In order to improve its intrusion into the table, U uses a DC bias of tens to hundreds of volts. It is also possible to use a DC bias and a collimator if necessary. In the environment, e is selectively annealed in a vacuum or nitrogen atmosphere or an oxygen/nitrogen mixed loop to improve the oxygen in the metal oxide. The temperature of this annealing treatment is typically between 40 (TC and 60 〇. 〇二 & fire time is less than 2 hours. 垆^ or _^ formation method, using a high temperature oxidation system (such as a high temperature to fast fans) Heat treatment (RTP) is carried out. This temperature is between 2 辛 xin and pure oxygen or gas/oxygen gas mixture at a pressure of U2 To rr. The time can be from a few minutes to a few days. Pure oxygen type is plasma oxidation. A radio frequency or DC voltage source plasma is mixed with helium/oxygen gas or argon/nitrogen/oxygen gas, such as Ni, 1 to 1〇0 mT〇1T. Oxidation of the metal surface, for example, to Weng, Ba Bu W, Ζί1, ΖΓ, CU, etc. The oxidation time is from a few seconds. The oxidation temperature is from room temperature to about 3 〇〇t: 'Electroelectric oxidation The ten kinds of five-remembered materials are polymer materials, such as TCNQ, which is mixed with copper, carbon, etc., or PCBM-TCNQ mixed polymer. One uses thermal evaporation, electron beam evaporation, or atomic beam epitaxy. System, ί indoor, = _ order evaporation. A solid TCNQ and dopant pellets are co-steamed in a single row The solid TCNQ and dopant pellets are placed in a crane 25 1325166 boat or a button boat or a ceramic vessel. A large current or electron beam is then applied to melt the reactants so that the materials are mixed and deposited on the wafer. Above, the dam is using a reactive substance or gas. The deposition is carried out at a pressure of 10 Torr to 10 10 Torr. The wafer temperature is between room temperature and 200 ° C. A post-deposition annealing treatment is carried out in a vacuum or in a nitrogen atmosphere to improve the composition distribution of the polymer material. The temperature of the annealing treatment is typically between room temperature and 30 Å (:, and the annealing time is less than 1 hour). Another technique for forming a layer of polymer-based memory materials

The spin coater and the doped TCNQ solution were used at a speed of less than 1000 rpm. After spin coating, the wafer is allowed to stand (typically at room temperature, or below 200 Torr) for a sufficient time to form a solid state. This rest time can range from a few minutes to a few days, depending on the temperature and conditions. Figure 10 is a cross-sectional view showing the current path through the conductive columns, the programmable resistive elements, and the conductive rows, wherein the conductive columns access the programmable resistive memory along the columns, and the conductive The line accesses the programmable resistor memory along each line. In the figure, the magnitude of the current flow along the column selection circuit 50, through a contact 54, the conductive electrode 78, the resistive element 8G, the conductive structure 74, and the conductive row 60 is controlled by the state of the resistive element 8〇. . The particular resistors are typically controlled by column select circuit 5 and row select circuitry (not shown), while row select circuitry is coupled to conductive row 6 〇. An exemplary embodiment of a phase-converted memory is as follows: sn ί 氧化 夕 , , , , , , , , , 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Conductive row 58 is comprised of titanium nitride having a thickness of about 20 nanometers and 60:i consisting of aluminum copper having a thickness of about 250 nanometers. The deposition of P, CVD built-in tools:] into. Electro-phase stripping can be performed by the conventional TCP reactive ion surface engraving guide 26 1325166. The dielectric layer 68 is composed of tantalum nitride having a thickness of about 20 nm. Dielectric layer 70 is composed of cerium oxide having a thickness of between 350 and 6 nanometers. Shen Ji, Cheng Ke, by the traditional IMD method, and using plasma enhanced chemical vapor deposition of tantalum nitride, high density plasma chemical vapor deposition + plasma enhanced chemical vapor deposition of cerium oxide, and Chemical mechanical polishing of oxides. Via etching and stripping can be performed using conventional high plasma density MERIE tools. The conductive structure 74 is composed of titanium nitride having a thickness of 5 to 400 nm. The deposition step can be carried out by conventional titanium nitride chemical vapor deposition or ionic metal physical vapor deposition. The engraving and stripping of the electrically conductive structure 74 can be carried out using conventional TCP reactive ion etching tools. The dielectric structure 76 is composed of cerium oxide having a thickness of 5 to 100 nm. The deposition can be carried out by conventional plasma enhanced oxides. The reticle engraving of the dielectric structure 76 can be performed by the conventional high plasma density MERIE tool. The conductive electrode 78 is composed of tungsten having a thickness of 400 to 650 nm. The deposition step can be carried out using a conventional crane metal chemical vapor deposition. The flattening step is accomplished by conventional tungsten metal chemical mechanical polishing. – Resistive element 80 consists of an n2-doped GST with a thickness between 5 and 50 nm. The deposition can be accomplished by conventional physical vapor deposition sputtering and heat treatment at 250 °C. The etching of the resistive element 8 〇 can be accomplished by a conventional TCP reactive ion etching tool. Figure 11 is a block diagram of the integrated circuit, including a non-volatile, resistive memory cell array and other circuitry. The integrated circuit is a memory array, ni00, which uses memory cells with a resistive element on a ferroconductor substrate. The address is transferred to row decoder 1103 and column decompressor 11 via row 1105. The sensed amplification and data input structure in 1106 is input to the 7/:2 to f decoder 1103 via the data bus 27 U25166. The data is derived from the internal or external data source of the integrated circuit 1150 from the integrated circuit 1150. The data input to the line 1111 and transmitted to the data input block of the block 1106 is blocked by the data rounding line 1115, and transmitted to the internal or external resources of the product = the output = output 埠, or transmitted to the integrated body The circuit 1150's volatile storage L electrical circuit 1150 may also include other circuits than the function of the target S (not shown). (Figure mi, t: nj 5 controller uses the bias to arrange the state program To give money to the _, such as reading, on the integrated circuit, this product can be implemented in the same component operation. In another - real!: j糸 a computer program to control this and pan Use the special purpose logic circuit in the %^ of the destination processor. In this paper, each layer = the plane is n=., in some cases, the layers are flat, and the characteristics of the layer in the direct sequence There are many embossed structures to make ί: ί; in some cases, each uses == the other layer of the production layer; the clever layer, or the system is located on the other layer "above" 堇" Between the cover layers, or in the upper layer * has - the interlayer (the first layer is located in the other two layers "between the lower layer of the basin Between the layers, the interlayer does not affect its relative relationship. The factory ... /, the next eight times, there is another -

The invention L has been described with reference to the preferred embodiment, and the A conversion method and the system have been suggested in the description, ΐϊί. Alternatives and tampering styles will be used by those skilled in the art/and, in addition, according to the structure and method of the present invention, all are true. In particular, the same as the above-mentioned 28% and the substantially same result of the present invention are not in the system. Therefore, all such alternatives and modifications are set! "The scope of the patents and the texts of the equivalents are all based on the patent application and printing [simple description of the schema] Resist the Zhao Dijia 1 Figure 2 - A process diagram showing the accessibility of a programmable resistance record f to a programmable electrical layer = a stepped profile to a plurality of memory lines accessing the fourth picture, The lithography of the via window is shown, and the cross section of the image of the second panel is accessed, and the side in the via window is used to electrically connect the programmable resistor memory to the σ state systemized resistor. The conductive line of the memory. The left and right sides are accessed by each of the blocks. Figure 6 is a cross-sectional view showing the conductive area in the via window. The programmable resistive memory is electrically connected to the m resistance via each column. The conductive column of the memory. Take the mt of the j%-type electric material. The cross-sectional view shows that the chemical mechanical polishing removes the excess material and the non-chemical resistance element is read and stored in each cell array. Draw a programmable resistance non-volatile memory fine 29; and access the heart = remember du, which is too interesting to be programmed by each: Two

[Main component symbol description] 50 column selection circuit 52 interlayer dielectric 54 contact 56, 62 dielectric layer 58, 60 conductive layer 64 conductive line photoresist 68, 70 dielectric layer 72 photoresist 74 conductive structure 76 dielectric structure 78 Conductive electrode 80 Resistive element 1100 Memory array 1101 Column decoder 1103 Row decoder 1105 Bus 1107 Data bus 1108 Bias arrangement supply voltage 1109 Bias arrangement state 1111 Data input line 1115 Data wheel outlet 1150 Integrated circuit 30

Claims (1)

1325166 X. Patent application to form a circuit having a non-volatile memory cell integrated circuit, forming a circuit for accessing a specific non-volatile memory cell, and forming a cell and a conductive column to access the non-column along the columns Volatile cells: ^^ access to the non-volatile memory of the non-volatile memory cells of the programmable resistance elements, in order to facilitate the conductive connection between the conductive columns and the conductive lines, each of which can be programmed: The package includes a memory refining circuit. 2. The method according to claim 1, further comprising: the electric field of the H-distribution circuit and the formation of the first conductive layer And a layer-forming second conductive row layer at least partially covering the first conductive row to '1 in the second sea_^. A conductive row layer and the second conductive row layer system includes the following The difference between the end point signal difference and the momentary selectivity. The method of claim 1, wherein the conductive is listed on the conductive row of the fruit. , the electric material 4·^^(4)1, which forms the lead 31 to form a first conductive row layer; and the layer forming-second conductive row layer at least partially covering the first conductive row %m conductive The formation of row b produces a stepped side of the first conductive layer and the first conductive layer. The method of claim 5, wherein the stepped side removes excess material of the second conductive row layer; and the plurality of sidewalls at least partially cover the second conductive row layer; Exceeding the sidewall of the first conductive layer and the conductive material. The method of the present invention, wherein the step of forming the method comprises: forming a dielectric material into the circuit at least partially in the circuit programmable resistor element 9 The method of claim 1, wherein the step of forming the circuit f forms the conductive columns to form an interlayer dielectric layer; and then forming at least a dielectric layer before the nb conductive germanium step The layers, the cells are electrically connected to access the excess material of the _ memory-removing layer of conductive layers along the columns until the at least one 32 1325166 dielectric layer is reached. 10. The method of claim 1, wherein the forming the circuit system comprises: forming at least one first dielectric layer after forming the conductive columns and before forming the conductive lines; and Forming at least a second dielectric layer, the second dielectric layer at least partially covering the conductive lines and at least partially adjacent to the first dielectric layer; and forming at least a third dielectric layer substantially covering the a second dielectric layer; wherein the second dielectric layer and the third dielectric layer comprise the following: an etch end signal difference and an etch selectivity difference. The method of the first aspect of the invention, wherein the forming of the electricity is performed, and the remaining conductive steps are followed to form at least a first dielectric layer; An electrical layer, the second dielectric layer is at least partially covered by the second conductive line and at least partially adjacent to the first dielectric; the dish is less--: a decorative 刿 t 曰 曰 括 括 括 括 括The difference between the endpoint 尨唬 and the etch selectivity. 12. The method of claim 1, wherein the method comprises: forming the electricity at least before the step of forming the plurality of conductive columns, forming at least a first-dielectric i to form the conductive steps to form at least a second dielectric layer, the conductive lines are at least partially adjacent to at least a portion of the cover layer; and the material system at least partially covers the second dielectric 33 1325166, forming a second dielectric layer and The third dielectric bank reaches the first dielectric layer, and at least partially exposes the day = vertical to the layer indirect point to the conductive columns and the programmable: electricity: Road 2: further claims L patent scope item * The method, wherein the hole forming the dielectric layer penetrating the dielectric layer is adjacent to the conductive lines to at least be adjacent to the conductive germanium and form a layer indirectly between the conductive columns and the conductive resistor And the method described in the first item of the conductive path, wherein the hole (4) forming the electrical bottom is connected to the axis (four) row to form a layer of electricity and the programmable Between the resistance elements, and conductively connect the leads Line resistance and the plurality of programmable elements; and Wei to the drapes, so that only through-conductive columns. The resistive elements are electrically conductively connected to the conductive traces. The method of claim 15, wherein the dielectric lining is between 5 nanometers and 1 nanometer. The method of claim 1 wherein the electricity 34 1325166 is formed to form a hole penetrating the dielectric material adjacent to the #connecting the conductive columns and the electrically conductive and/or electrically conductive rows to conduct electricity The conductive lines and the programmable resistor elements are electrically connected to form a conductive structure in the holes to 'guide the programmable resistance elements. Electrically connecting the conductive columns and 18. The steps of the method of claim </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> forming the electrical at least one first dielectric after forming the conductive columns and before a layer; forming at least one second dielectric layer in the forming of the conductive lines, the second conductive lines and at least partially adjacent to the cladding layer to form at least a third dielectric layer At least partially covering the second dielectric forming layer indirect point, comprising: forming a hole penetrating the dielectric layer adjacent to the conductive lines, forming a conductive substrate in the holes to electrically connect the hole And a plurality of programmable resistive elements; a conductive dielectric substrate is formed in the holes to electrically connect the conductive columns and the conductive substrate only through the resistive elements; The holes are electrically connected to the strips and the programmable resistive elements; and the phantom is subjected to chemical mechanical polishing to the non-selective second dielectric layer, the second w electrical layer, and the conductive lining Bottom, the dielectric substrate, and The conductive structures. The method of claim 1, wherein the step of forming the path comprises: forming at least a first dielectric layer after the forming step of the conductive columns and before the forming step of the conductive lines; 〆 35 1325166 哕 'second dielectric layer' the second dielectric layer at least partially covering π / row and at least partially adjacent to the first dielectric layer; layer / at least a third dielectric layer is at least Partially covering the indirect point of the second dielectric forming layer, including: a hole penetrating the dielectric layer adjacent to the conductive lines, and the second pair of ' electrically conductively connecting the conductive electric bobbins In the holes, the conductive columns and the conductive base are connected only through the programmable openings mt; and the electrically conductive HI holes are electrically connected to the conductive columns. The method of claim 1, wherein the electrical circuit is formed and the at least one second dielectric layer is formed, and the first-to-electricity is at least partially The partial cover layer forms at least a third dielectric layer which is at least partially "the first The second dielectric forming layer indirect point comprises: forming a hole penetrating the dielectric layer (4) to form the conductive substrate in the hole, and electrically connecting the row to the programmable resistors The conductive materials form a dielectric substrate in the holes, and electrically connect the conductive columns with a resistive element and a conductive structure in the holes to electrically connect the conductive layers. Arranging the programmable resistance elements; and grinding the knives of the second dielectric layer and the third dielectric layer until the portions no longer cover the conductive lines. The patent (4) is referred to in item 1. The method, wherein the step of forming the red-type resistive element is the last step in the process. i2. Two integrated circuits having non-volatile memory cells, including: η 4丨^^ taking a specific non-volatile a circuit for memorizing cells, the circuit comprising: a conductive column for accessing the non-volatile memory cells by each column, and 2) a conductive row for accessing the non-volatile memory cells by using each row; and the non-volatile memory cell Process resistance element, each A programmable resistor 7G is electrically connected to the conductive columns and is vertically disposed on the conductive columns and the conductive lines in the programmable resistor elements of the conductive beans. The integrated circuit, wherein the programmable resistor 兀* comprises at least one of the following: prxcayMn03, TSrMn03, Zr〇x, TCNQ, and PCBM. ϋ· The integrated circuit according to claim 22 of the patent application scope The circuit includes: a germanium layer covering the conductive columns, wherein the conductive lines are above the first dielectric layer; and a second dielectric layer at least partially adjoining the conductive portions Adjacent to the first dielectric layer; the electric sub-primary/a third dielectric layer covering at least the second dielectric layer; and the layer indirectly connected to the conductive lines, comprising: the conductive substrate is electrically conductive Connecting the conductive lines and the programmable 37 丄 resistance elements; the barriers allow the conductive columns to be connected to the conductive substrate only through the programmable semiconductors; and the electrical connections The conductive columns and the programmable A Hi application for the integrated circuit described in item 24 of the patent scope, the first of the beans; electricity; at least one of: oxygen cut (10) to (Siis^ layer includes at least one of the following groups: nitrided shigu / first - U Xi (Si〇xNy), and oxidized stone Xi (SiOx); r cl first; 1 electrical layer includes at least one of the following groups. 4 servant Xi dielectric constant than 3 materials, nitrogen · And tantalum nitride (SiNx); ^ The conductive substrate comprises at least one of the following groups (ΤιΝ), titanium (butadiene), titanium nitride/titanium (TiN/Ti)雔Μ-tungsten (W), button r Δ1, C) Further layer, tantalum nitride _(TaN), oxygen 钌 钌 钟 钟 锐 ( (LlNb〇3), silver oxide (ΐΓ〇χ), i^Xi.YB: CU〇' LaCaMn〇3 '10 u and doped polycrystalline germanium; and at least one of the nitrogen dioxide = 1 group: oxidized stone eve (&amp; 〇xNy), bismuth (&amp; Νχ), and titanic acid鳃 (^ 〇 3). In the road, please refer to the integrated circuit described in Item 24 of the patent scope, wherein the electro-mechanical and the ί v 电 位于 位于 少 少 少 少 少 少 少 少 少 少 少 程式 程式 程式 程式 程式 程式 程式 , , , , , The first electrical layer comprises at least 4 of the following groups: gas cut (S10x), gas 38 oxidized stone (SiOxNy), nitrided stone (3 丨), tin cinnamate (SrTi03), and alumina (A10x) . 28. The integrated circuit of claim 22, wherein the conductive lines comprise: a first conductive row layer; and a second conductive row layer at least partially covering the first conductive row layer; The first conductive row layer and the second conductive row layer have a stepped profile feature. 29. The integrated circuit of claim 28, wherein the first conductive layer layer comprises at least one of the group consisting of titanium nitride (TiN), titanium (Ti), titanium nitride/titanium (TiN/Ti) double layer, tungsten/titanium nitride (W/TiN) double layer, steel aluminum/titanium nitride (AlCu/TiN) double layer, doped polysilicon, and metal telluride; and the second The conductive layer layer includes at least one of the following groups: Tong Ming, titanium nitride/copper aluminum (TiN/AlCu) double layer, titanium nitride/titanium/copper aluminum (TiN/Ti/AlCu) three layers, tungsten, Metal telluride, and doped polysilicon. 30. An integrated circuit having non-volatile memory cells, formed by the following processes: forming a circuit for accessing a particular non-volatile memory cell, comprising: forming a conductive column 'which is accessed via columns The non-volatile memory cells; and forming a conductive row that accesses the non-volatile memory cells via rows; and then forming the programmable resistance elements of the non-volatile memory cells to each The programmable resistance elements are electrically connected to the conductive lines of the conductive lines. ~ 39