WO2016176884A1 - Tft基板的制作方法及其结构 - Google Patents

Tft基板的制作方法及其结构 Download PDF

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Publication number
WO2016176884A1
WO2016176884A1 PCT/CN2015/079907 CN2015079907W WO2016176884A1 WO 2016176884 A1 WO2016176884 A1 WO 2016176884A1 CN 2015079907 W CN2015079907 W CN 2015079907W WO 2016176884 A1 WO2016176884 A1 WO 2016176884A1
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Prior art keywords
layer
via hole
semiconductor layer
drain
source
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Ceased
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PCT/CN2015/079907
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English (en)
French (fr)
Inventor
石龙强
韩佰祥
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/759,190 priority Critical patent/US9978778B2/en
Publication of WO2016176884A1 publication Critical patent/WO2016176884A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/22—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using physical deposition, e.g. vacuum deposition or sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3434—Deposited materials, e.g. layers characterised by the chemical composition being oxide semiconductor materials
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a TFT substrate structure and a method of fabricating the same.
  • OLED organic light emitting diodes
  • OLEDs can be classified into passive OLEDs (PMOLEDs) and active OLEDs (AMOLEDs) according to the type of driving; among them, AMOLED devices are current driven, and their requirements for thin film transistor (TFT) current are very strict. Therefore, AMOLED products must use pixel compensation circuits to reduce current variations due to TFT instability during the entire drive process. Dual gate TFTs are widely used in circuit driving due to good electrical stability.
  • PMOLEDs passive OLEDs
  • AMOLEDs active OLEDs
  • TFT thin film transistor
  • the existing AMOLED pixel compensation circuit generally involves a plurality of TFTs connected in series, as shown in FIG. 1 , a double-gate TFT pixel compensation circuit is connected in series between the data lines V data and the voltage lines V dd .
  • FIG. 2 is a TFT substrate structure corresponding to the double-gate TFT pixel compensation circuit shown in FIG. 1
  • FIG. 3 is a TFT component and a data line in the TFT substrate structure shown in FIG. And the distribution and connection diagram of the voltage supply lines.
  • the TFT substrate structure includes a substrate 100, a first metal layer, a gate insulating layer 300, a semiconductor layer, an etch stop layer 500, and a second metal layer, which are sequentially disposed from bottom to top.
  • a passivation layer 700 and a third metal layer the first metal layer includes a first bottom gate 210 and a second bottom gate 230;
  • the semiconductor layer includes a first semiconductor layer 420 disposed at intervals And a second semiconductor layer 440;
  • the second metal layer includes a first source 610, a connection electrode 620, and a second drain 630;
  • the third metal layer includes a first top gate 820 disposed at intervals And a second top gate 840.
  • the etch barrier layer 500 is provided with a first through hole 510, a second through hole 520, a third through hole 530, and a fourth through hole 540; the first source 610 passes through the first through hole 510 and the One end of the first semiconductor layer 420 is in contact; the connection electrode 620 is in contact with the other end of the first semiconductor layer 420 through the second via 520 while passing through the third via 530 and the second half One end of the conductor layer 440 is in contact; the second drain 630 is in contact with the other end of the second semiconductor layer 440 through the fourth via 540.
  • the first bottom gate 210, the first semiconductor layer 420, the first source 610, the connection electrode 620, and the first top gate 820 constitute a first dual gate TFT;
  • the second semiconductor layer 440, the connection electrode 620, the second drain 630, and the second top gate 840 constitute a second dual gate TFT.
  • connection electrode 620 serves as both the first drain of the first dual gate TFT and the second source of the second dual gate TFT, thereby bonding the first dual gate TFT with The second double-gate TFTs are connected in series.
  • the design rules of the connection electrodes 620 are designed. Rule) is small, and bridging between the two double-gate TFTs through the connection electrode 620 causes the design rule of the second metal layer to be smaller, which is disadvantageous for the production of a high aperture ratio and high resolution display panel. .
  • An object of the present invention is to provide a method for fabricating a TFT substrate by disposing a connection electrode connecting two double-gate TFTs on a third metal layer, thereby avoiding signals such as connecting electrodes and data lines and voltage supply lines in the prior art.
  • the problem that the lines are collectively disposed on the second metal layer to cause the design rule of the connection electrode and the second metal layer to be small is advantageous for the production of a display panel having a high aperture ratio and a high resolution.
  • Another object of the present invention is to provide a TFT substrate structure which has a simple structure, a high aperture ratio and a high resolution.
  • the present invention first provides a method for fabricating a TFT substrate, which includes the following steps:
  • Step 1 providing a substrate, depositing a first metal layer on the substrate, and patterning the first metal layer by a photolithography process to form a first bottom gate and a second bottom gate;
  • Step 2 depositing a gate insulating layer on the first bottom gate, the second bottom gate, and the substrate;
  • Step 3 depositing a metal oxide layer on the gate insulating layer, and patterning the metal oxide layer by a photolithography process to form a first semiconductor layer and a second semiconductor layer;
  • the first semiconductor layer includes a first channel region, and a first source contact region and a first drain contact region respectively located on opposite sides of the first channel region;
  • the second semiconductor layer includes a second channel a second source contact region and a second drain contact region respectively located on opposite sides of the second channel region;
  • Step 4 depositing a layer on the first semiconductor layer, the second semiconductor layer, and the gate insulating layer Etching the barrier layer, and forming a first via hole and a second via hole respectively on the etch barrier layer by a photolithography process for respectively exposing the first source contact region and the second drain contact region;
  • Step 5 depositing a second metal layer on the etch barrier layer, and patterning the second metal layer by a photolithography process to form a first source and a second drain;
  • the first source is in contact with the first source contact region through the first via hole;
  • the second drain is in contact with the second drain contact region through the second via hole;
  • Step 6 Depositing a passivation layer on the first source, the second drain, and the etch barrier layer, and forming a third pass on the passivation layer and the etch barrier layer by a photolithography process a hole and a fourth through hole for exposing the first drain contact region and the second source contact region;
  • Step 7 depositing a third metal layer on the passivation layer, and patterning the third metal layer by a photolithography process to form a first top gate, a connection electrode, and a second top gate;
  • connection electrodes are respectively in contact with the first drain contact region and the second source contact region through the third via hole and the fourth via hole.
  • the first metal layer is deposited by physical vapor deposition, and the material of the first metal layer is copper, aluminum, or molybdenum.
  • the photolithography process in the step 1 includes photoresist, exposure, development, and wetness. Etching, and photoresist removal process; the step 2 deposits the gate insulating layer by plasma enhanced chemical vapor deposition, and the material of the gate insulating layer is silicon oxide or silicon nitride.
  • the step 3 is to deposit the metal oxide layer by physical vapor deposition, the material of the metal oxide layer is indium gallium zinc oxide; the photolithography process in the step 3 includes photoresist, exposure, development, and wet Etching, and photoresist removal process.
  • the step 6 is to deposit the passivation layer by chemical vapor deposition, the material of the passivation layer is silicon oxide or silicon nitride, and the photolithography process in the step 6 includes photoresist, exposure, development, dry etching, And removing the photoresist process; the step 7 deposits the third metal layer by physical vapor deposition, the material of the third metal layer is copper, aluminum, or molybdenum, and the photolithography process in the step 7 includes coating photoresist , exposure, development, wet etching, and photoresist removal processes.
  • the present invention also provides a TFT substrate structure including a substrate, a first metal layer, a gate insulating layer, a semiconductor layer, an etch barrier layer, a second metal layer, a passivation layer, and the like from bottom to top.
  • a third metal layer the first metal layer includes a first bottom gate and a second bottom gate;
  • the semiconductor layer includes a first semiconductor layer and a second semiconductor layer;
  • the second metal layer includes a first source and a second drain;
  • the third metal layer includes a first top gate, a connection electrode, and a second top gate;
  • a first via hole and a second via hole are formed on the etch barrier layer; a third via hole and a fourth via hole are formed on the passivation layer and the etch barrier layer; and the first source passes The first via hole is in contact with one end of the first semiconductor layer, and the connection electrode is in contact with the other end of the first semiconductor layer through the third via hole, and is in contact with one end of the second semiconductor layer through the fourth via hole; The second drain is in contact with the other end of the second semiconductor layer through the second via hole;
  • the first bottom gate, the first semiconductor layer, the first source, the connection electrode, and the first top gate constitute a first dual gate TFT;
  • the second bottom gate, the second semiconductor layer, and the connection electrode The second drain and the second top gate constitute a second double gate TFT;
  • the connection electrode simultaneously serves as a first drain of the first dual gate TFT and a second source of the second dual gate TFT
  • the first double gate TFT is connected in series with the second double gate TFT.
  • the first semiconductor layer includes a first channel region, and a first source contact region and a first drain contact region respectively located on opposite sides of the first channel region;
  • the second semiconductor layer includes a second channel And a second source contact region and a second drain contact region respectively located on opposite sides of the second channel region.
  • the first via hole, the third via hole, the fourth via hole, and the second via hole are respectively used to expose the first source contact region, the first drain contact region, the second source contact region, and the second Drain contact area.
  • the first source is in contact with the first source contact region through the first via hole
  • the connection electrode respectively passes through the third via hole, and the fourth via hole and the first drain contact region
  • the second source The contact regions are in contact
  • the second drain is in contact with the second drain contact region through the second via.
  • the material of the semiconductor layer is a metal oxide.
  • the present invention also provides a TFT substrate structure comprising: a substrate, a first metal layer, a gate insulating layer, a semiconductor layer, an etch barrier layer, a second metal layer, a passivation layer, and a first layer arranged from bottom to top a third metal layer;
  • the first metal layer includes a first bottom gate and a second bottom gate;
  • the semiconductor layer includes a first semiconductor layer and a second semiconductor layer; and
  • the second The metal layer includes a first source and a second drain;
  • the third metal layer includes a first top gate, a connection electrode, and a second top gate;
  • a first via hole and a second via hole are formed on the etch barrier layer; a third via hole and a fourth via hole are formed on the passivation layer and the etch barrier layer; and the first source passes The first via hole is in contact with one end of the first semiconductor layer, and the connection electrode is in contact with the other end of the first semiconductor layer through the third via hole, and is in contact with one end of the second semiconductor layer through the fourth via hole; The second drain is in contact with the other end of the second semiconductor layer through the second via hole;
  • the first bottom gate, the first semiconductor layer, the first source, the connection electrode, and the first top gate constitute a first dual gate TFT;
  • the second bottom gate, the second semiconductor layer, and the connection electrode First
  • the second drain and the second top gate constitute a second double gate TFT;
  • the connection electrode simultaneously serves as a first drain of the first dual gate TFT and a second source of the second dual gate TFT, thereby Connecting the first dual gate TFT and the second dual gate TFT in series;
  • the first semiconductor layer includes a first channel region, and a first source contact region and a first drain contact region respectively located at two sides of the first channel region;
  • the second semiconductor layer includes a second a channel region, and second source contact regions and second drain contact regions respectively located on opposite sides of the second channel region;
  • the first via hole, the third via hole, the fourth via hole, and the second via hole are respectively used to expose the first source contact region, the first drain contact region, the second source contact region, and a second drain contact region;
  • the material of the semiconductor layer is a metal oxide.
  • the present invention provides a method for fabricating a TFT substrate by disposing a connection electrode connecting two double-gate TFTs on a third metal layer, thereby avoiding connecting electrodes and data lines in the prior design.
  • the problem that the voltage lines and the like are collectively disposed on the second metal layer to cause the design rule of the connection electrode and the second metal layer to become smaller is advantageous for improving the aperture ratio and resolution of the display panel.
  • the invention provides a TFT substrate structure which has a simple structure, a high aperture ratio and a high resolution.
  • FIG. 1 is a circuit diagram of a conventional dual gate TFT pixel compensation circuit
  • FIG. 2 is a schematic diagram of a TFT substrate structure corresponding to the dual gate TFT pixel compensation circuit shown in FIG. 1;
  • FIG. 3 is a schematic view showing the distribution and connection of a TFT component, a data line, and a voltage supply line in the TFT substrate structure shown in FIG. 2;
  • FIG. 4 is a schematic view showing a step 1 of a method for fabricating a TFT substrate of the present invention
  • step 2 is a schematic diagram of step 2 of a method for fabricating a TFT substrate of the present invention
  • FIG. 6 is a schematic diagram of step 3 of a method for fabricating a TFT substrate according to the present invention.
  • step 4 is a schematic diagram of step 4 of a method for fabricating a TFT substrate of the present invention.
  • step 5 of a method for fabricating a TFT substrate of the present invention is a schematic diagram of step 5 of a method for fabricating a TFT substrate of the present invention.
  • step 6 is a schematic diagram of step 6 of the method for fabricating a TFT substrate of the present invention.
  • FIG. 10 is a schematic view showing a step 7 of a method for fabricating a TFT substrate of the present invention. and a schematic cross-sectional view showing a structure of a TFT substrate of the present invention;
  • FIG. 11 is a schematic view showing the distribution and connection of a TFT component, a data line, and a voltage supply line in the TFT substrate structure shown in FIG.
  • the present invention provides a method for fabricating a TFT substrate, including the following steps:
  • Step 1 as shown in FIG. 4, a substrate 1 is provided, a first metal layer is deposited on the substrate 1, and the first metal layer is patterned by a photolithography process to form first spaced bottom gates 21 And with the second bottom gate 23.
  • the substrate 1 is a glass substrate.
  • the first metal layer is deposited by a physical vapor deposition (PVD); preferably, the material of the first metal layer is copper, aluminum, or molybdenum.
  • PVD physical vapor deposition
  • the lithography process includes photoresisting, exposure, development, wet etching, and photoresist removal processes.
  • Step 2 As shown in FIG. 5, a gate insulating layer 3 is deposited on the first bottom gate 21, the second bottom gate 23, and the substrate 1.
  • the gate insulating layer 3 is deposited by plasma enhanced chemical vapor deposition (PECVD); preferably, the material of the gate insulating layer 3 is silicon oxide or silicon nitride. .
  • PECVD plasma enhanced chemical vapor deposition
  • Step 3 depositing a metal oxide layer on the gate insulating layer 3, and patterning the metal oxide layer by a photolithography process to form the first semiconductor layer 41 disposed at intervals And a second semiconductor layer 43.
  • the first semiconductor layer 41 includes a first channel region 412 and a first source contact region 414 and a first drain contact region 416 respectively located on opposite sides of the first channel region 412;
  • the second semiconductor layer 43 includes a second channel region 432 and a second source contact region 434 and a second drain contact region 436 respectively located on opposite sides of the second channel region 432.
  • the metal oxide layer is deposited by physical vapor deposition.
  • the material of the metal oxide layer is Indium Gallium Zinc Oxide (IGZO).
  • the lithography process includes photoresisting, exposure, development, wet etching, and photoresist removal processes.
  • Step 4 depositing an etch stop layer 5 on the first semiconductor layer 41, the second semiconductor layer 43, and the gate insulating layer 3, and etching the barrier layer through a photolithography process
  • the first via hole 51 and the second via hole 52 are respectively formed on the fifth surface for exposing the first source contact region 414 and the second drain contact region 436, respectively.
  • the step 4 deposits the etch stop layer 5 by chemical vapor deposition (CVD).
  • CVD chemical vapor deposition
  • the lithography process includes photoresisting, exposure, development, dry etching, and photoresist removal processes.
  • Step 5 depositing a second metal layer on the etch stop layer 5, and patterning the second metal layer by a photolithography process to form a first source 61 and a space Two drains 62.
  • the first source 61 is in contact with the first source contact region 414 through the first via 51; the second drain 62 is in contact with the second drain contact region 436 through the second via 52.
  • the step 5 deposits the second metal layer by physical vapor deposition; preferably, the material of the second metal layer is copper, aluminum, or molybdenum.
  • the lithography process includes photoresisting, exposure, development, wet etching, and photoresist removal processes.
  • Step 6 depositing a passivation layer 7 on the first source 61, the second drain 62, and the etch barrier layer 5, and passing the photolithography process on the passivation layer 7
  • the third via hole 73 and the fourth via hole 74 are formed on the etch barrier layer 5 for exposing the first drain contact region 416 and the second source contact region 434, respectively.
  • the passivation layer 7 is deposited by chemical vapor deposition; preferably, the material of the passivation layer 7 is silicon oxide or silicon nitride.
  • the lithography process includes photoresisting, exposure, development, dry etching, and photoresist removal processes.
  • Step 7 depositing a third metal layer on the passivation layer 7, and patterning the third metal layer by a photolithography process to form a first top gate 82 and a connection electrode disposed at intervals 83, and a second top gate 84.
  • connection electrode 83 is in contact with the first drain contact region 416 and the second source contact region 434 through the third via hole 73 and the fourth via hole 74, respectively.
  • the third metal layer is deposited by physical vapor deposition; preferably, the material of the third metal layer is copper, aluminum, or molybdenum.
  • the lithography process includes photoresisting, exposure, development, wet etching, and photoresist removal processes.
  • the first source 61 and the second drain 62 are disposed on the second metal layer, and the connection electrode 83 and the first and second top gates 82 and 84 are disposed on the first
  • the three-metal layer avoids the connection between the electrode and the data line and the voltage line in the existing design.
  • the problem that the design rule of the connection electrode and the second metal layer becomes smaller is the same as that of the second metal layer, which is advantageous for improving the aperture ratio and resolution of the display panel.
  • the present invention further provides a TFT substrate structure prepared by the above manufacturing method, which comprises: a substrate 1, a first metal layer, a gate insulating layer 3, and a semiconductor layer disposed in order from bottom to top.
  • the first metal layer includes a first bottom gate 21 and a second bottom gate 23 which are spaced apart;
  • the semiconductor layer includes a first semiconductor layer 41 and a second semiconductor layer 43 which are spaced apart;
  • the second metal layer includes a first source 61 and a second drain 62 which are spaced apart;
  • the third metal layer includes a space
  • the first top gate 82, the connection electrode 83, and the second top gate 84 are disposed.
  • a first through hole 51 and a second through hole 52 are formed on the etch stop layer 5; a third through hole 73 and a fourth through hole 74 are formed in the passivation layer 7 and the etch stop layer 5;
  • the first source 61 is in contact with one end of the first semiconductor layer 41 through the first via 51, and the connection electrode 63 is in contact with the other end of the first semiconductor layer 41 through the third via 73 while passing through the first
  • the four via holes 74 are in contact with one end of the second semiconductor layer 43; the second drain electrode 62 is in contact with the other end of the second semiconductor layer 43 through the second via hole 52.
  • the first semiconductor layer 41 includes a first channel region 412 and a first source contact region 414 and a first drain contact region 416 respectively located on opposite sides of the first channel region 412;
  • the second semiconductor layer 43 includes a second channel region 432, and a second source contact region 434 and a second drain contact region 436 respectively located on the two sides of the second channel region 432;
  • the first via hole 51, the third via hole 27, the fourth via hole 74, and the second via hole 52 are respectively used to expose the first source contact region 414, the first drain contact region 416, and the second source.
  • the first source 61 is in contact with the first source contact region 414 through the first via 51, and the connection electrode 63 passes through the third via 73 and the fourth via 74 and the first drain contact region, respectively.
  • 416 is in contact with the second source contact region 434, and the second drain electrode 62 is in contact with the second drain contact region 436 through the second via 52.
  • the first bottom gate 21, the first semiconductor layer 41, the first source 61, the connection electrode 83, and the first top gate 82 constitute a first double gate TFT;
  • the second bottom gate 23 The second semiconductor layer 44, the connection electrode 83, the second drain 62, and the second top gate 84 constitute a second double gate TFT;
  • the connection electrode 83 simultaneously serves as a first drain of the first dual gate TFT, and a second source of the second double gate TFT, thereby connecting the first dual gate TFT and the second dual gate TFT in series.
  • the substrate 1 is a glass substrate.
  • the material of the first metal layer is copper, aluminum, or molybdenum.
  • the material of the gate insulating layer 3 is silicon oxide or silicon nitride.
  • the material of the semiconductor layer is a metal oxide.
  • the metal oxide is indium gallium zinc oxide.
  • the material of the etch barrier layer 5 is silicon oxide or silicon nitride.
  • the material of the second metal layer is copper, aluminum, or molybdenum.
  • the material of the passivation layer 7 is silicon oxide or silicon nitride.
  • the material of the third metal layer is copper, aluminum, or molybdenum.
  • the method for fabricating the TFT substrate of the present invention by connecting the connection electrodes connecting the two double-gate TFTs to the third metal layer, signals connecting the electrodes, the data lines, the voltage supply lines, and the like in the prior design are avoided.
  • the problem that the lines are collectively disposed on the second metal layer to cause the design rule of the connection electrode and the second metal layer to become smaller is advantageous for improving the aperture ratio and resolution of the display panel.
  • the TFT substrate structure of the present invention has a simple structure and a high aperture ratio and high resolution.

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Abstract

一种TFT基板的制作方法及其结构。该TFT基板的制作方法通过将连接两双栅极TFT的连接电极(83)设置于第三金属层，避免了现有设计中将连接电极与数据线、供电压线等讯号线共同设置于第二金属层从而导致该连接电极与第二金属层的设计规则变小的问题，有利于提高显示面板的开口率、及分辨率。提供一种TFT基板结构，其结构简单，具有高开口率及高分辨率。

Description

TFT基板的制作方法及其结构 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT基板结构及其制作方法。
背景技术
在显示技术领域，液晶显示器(Liquid Crystal Display，LCD)与有机发光二极管显示器(Organic Light Emitting Diode，OLED)等平板显示技术已经逐步取代CRT显示器。其中，OLED具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180°视角、使用温度范围宽，可实现柔性显示与大面积全色显示等诸多优点，被业界公认为是最有发展潜力的显示装置。
OLED按照驱动类型可分为无源OLED(PMOLED)和有源OLED(AMOLED)；其中，AMOLED器件为电流驱动，其对薄膜晶体管(Thin Film Transistor，TFT)电流的要求非常严格。所以，AMOLED产品必须采用像素补偿电路来减少整个驱动过程中由于TFT不稳定导致的电流变化。双栅极(Dual gate)TFT由于良好的电学稳定性广泛应用于电路驱动中。
现有的AMOLED像素补偿电路通常涉及到多个TFT串联，如图1所示的一种双栅极TFT像素补偿电路，在数据线Vdata与供电压线Vdd这两条讯号线之间串联了两个双栅极TFT：TFT1与TFT2；图2为对应图1所示的双栅极TFT像素补偿电路的TFT基板结构，图3为图2所示的TFT基板结构中TFT组件与数据线、及供电压线的分布及连接示意图。
如图2和图3所示，所述TFT基板结构包括从下到上依次设置的基板100、第一金属层、栅极绝缘层300、半导体层、刻蚀阻挡层500、第二金属层、钝化层700、及第三金属层；所述第一金属层包括间隔设置的第一底栅极210、及第二底栅极230；所述半导体层包括间隔设置的第一半导体层420、及第二半导体层440；所述第二金属层包括间隔设置的第一源极610、连接电极620、及第二漏极630；所述第三金属层包括间隔设置的第一顶栅极820、及第二顶栅极840。
所述刻蚀阻挡层500上设有第一通孔510、第二通孔520、第三通孔530、及第四通孔540；所述第一源极610通过第一通孔510与所述第一半导体层420的一端相接触；所述连接电极620通过第二通孔520与所述第一半导体层420的另外一端相接触，同时通过第三通孔530与所述第二半 导体层440的一端相接触；所述第二漏极630通过第四通孔540与所述第二半导体层440的另外一端相接触。
所述第一底栅极210、第一半导体层420、第一源极610、连接电极620、及第一顶栅极820构成第一双栅极TFT；所述第二底栅极230、第二半导体层440、连接电极620、第二漏极630、及第二顶栅极840构成第二双栅极TFT。
从图2和图3中可见，所述连接电极620同时充当第一双栅极TFT的第一漏极、以及第二双栅极TFT的第二源极，从而将第一双栅极TFT与第二双栅极TFT串连起来，然而，由于该连接电极620所在的第二金属层还分布有数据线Vdata、供电压线Vdd等讯号线，使得该连接电极620的设计规则(design rule)很小，而两个双栅极TFT之间再通过连接电极620桥接会导致该第二金属层的设计规则变得更小，不利于高开口率、及高分辨率的显示面板的制作。
发明内容
本发明的目的在于提供一种TFT基板的制作方法，通过将连接两双栅极TFT的连接电极设置于第三金属层，避免了现有设计中将连接电极与数据线、供电压线等讯号线共同设置于第二金属层从而导致该连接电极与第二金属层的设计规则变小的问题，有利于高开口率、及高分辨率的显示面板的制作。
本发明的目的还在于提供一种TFT基板结构，其结构简单，具有高开口率及高分辨率。
为实现上述目的，本发明首先提供一种TFT基板的制作方法，其特征在于，包括如下步骤：
步骤1、提供一基板，在所述基板上沉积第一金属层，并通过一道光刻制程图案化该第一金属层，形成间隔设置的第一底栅极、及与第二底栅极；
步骤2、在所述第一底栅极、第二底栅极、及基板上沉积栅极绝缘层；
步骤3、在所述栅极绝缘层上沉积一金属氧化物层，并通过一道光刻制程对该金属氧化物层进行图案化，形成间隔设置的第一半导体层、及第二半导体层；
所述第一半导体层包括第一沟道区、及分别位于该第一沟道区两侧的第一源极接触区与第一漏极接触区；所述第二半导体层包括第二沟道区、及分别位于该第二沟道区两侧的第二源极接触区与第二漏极接触区；
步骤4、在所述第一半导体层、第二半导体层、及栅极绝缘层上沉积一 刻蚀阻挡层，并通过一道光刻制程在该刻蚀阻挡层上分别形成第一通孔与第二通孔，分别用于暴露第一源极接触区与第二漏极接触区；
步骤5、在所述刻蚀阻挡层上沉积第二金属层，并通过一道光刻制程图案化该第二金属层，形成间隔设置的第一源极、及第二漏极；
所述第一源极通过第一通孔与第一源极接触区相接触；所述第二漏极通过第二通孔与第二漏极接触区相接触；
步骤6、在所述第一源极、第二漏极、及刻蚀阻挡层上沉积一钝化层，并通过一道光刻制程在该钝化层和刻蚀阻挡层上分别形成第三通孔与第四通孔，用于暴露第一漏极接触区与第二源极接触区；
步骤7、在所述钝化层上沉积第三金属层，并通过一道光刻制程图案化该第三金属层，形成间隔设置的第一顶栅极、连接电极、及第二顶栅极；
所述连接电极分别通过第三通孔、及第四通孔与第一漏极接触区、及第二源极接触区相接触。
所述步骤1采用物理气相沉积法沉积所述第一金属层，所述第一金属层的材料为铜、铝、或钼，所述步骤1中的光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程；所述步骤2采用等离子增强化学气相沉积法沉积所述栅极绝缘层，所述栅极绝缘层的材料为氧化硅或氮化硅。
所述步骤3采用物理气相沉积法沉积所述该金属氧化物层，所述金属氧化物层的材料为铟镓锌氧化物；所述步骤3中的光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程。
所述步骤4采用化学气相沉积法沉积所述刻蚀阻挡层，所述刻蚀阻挡层的材料为氧化硅或氮化硅，所述步骤4中的光刻制程包括涂光阻、曝光、显影、干蚀刻、及去光阻制程；所述步骤5采用物理气相沉积法沉积所述第二金属层，所述第二金属层的材料为铜、铝、或钼，所述步骤5中的光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程。
所述步骤6采用化学气相沉积法沉积所述钝化层，所述钝化层的材料为氧化硅或氮化硅，所述步骤6中的光刻制程包括涂光阻、曝光、显影、干蚀刻、及去光阻制程；所述步骤7采用物理气相沉积法沉积所述第三金属层，所述第三金属层的材料为铜、铝、或钼，所述步骤7中的光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程。
本发明还提供一种TFT基板结构，其包括从下到上依次设置的：基板、第一金属层、栅极绝缘层、半导体层、刻蚀阻挡层、第二金属层、钝化层、及第三金属层；所述第一金属层包括间隔设置的第一底栅极、及第二底栅极；所述半导体层包括间隔设置的第一半导体层、及第二半导体层；所述 第二金属层包括间隔设置的第一源极、及第二漏极；所述第三金属层包括间隔设置的第一顶栅极、连接电极、及第二顶栅极；
所述刻蚀阻挡层上形成有第一通孔与第二通孔；所述钝化层和刻蚀阻挡层上形成有第三通孔、及第四通孔；所述第一源极通过第一通孔与第一半导体层的一端相接触，所述连接电极通过第三通孔与第一半导体层的另外一端相接触，同时通过第四通孔与第二半导体层的一端相接触；所述第二漏极通过第二通孔与所述第二半导体层的另外一端相接触；
所述第一底栅极、第一半导体层、第一源极、连接电极、及第一顶栅极构成第一双栅极TFT；所述第二底栅极、第二半导体层、连接电极、第二漏极、及第二顶栅极构成第二双栅极TFT；所述连接电极同时充当第一双栅极TFT的第一漏极、及第二双栅极TFT的第二源极，从而将第一双栅极TFT与第二双栅极TFT串联起来。
所述第一半导体层包括第一沟道区、及分别位于该第一沟道区两侧的第一源极接触区与第一漏极接触区；所述第二半导体层包括第二沟道区、及分别位于该第二沟道区两侧的第二源极接触区与第二漏极接触区。
所述第一通孔、第三通孔、第四通孔、及第二通孔分别用于暴露第一源极接触区、第一漏极接触区、第二源极接触区、及第二漏极接触区。
所述第一源极通过第一通孔与第一源极接触区相接触，所述连接电极分别通过第三通孔、及第四通孔与第一漏极接触区、及第二源极接触区相接触，所述第二漏极通过第二通孔与所述第二漏极接触区相接触。
所述半导体层的材料为金属氧化物。
本发明还提供一种TFT基板结构，包括从下到上依次设置的：基板、第一金属层、栅极绝缘层、半导体层、刻蚀阻挡层、第二金属层、钝化层、及第三金属层；所述第一金属层包括间隔设置的第一底栅极、及第二底栅极；所述半导体层包括间隔设置的第一半导体层、及第二半导体层；所述第二金属层包括间隔设置的第一源极、及第二漏极；所述第三金属层包括间隔设置的第一顶栅极、连接电极、及第二顶栅极；
所述刻蚀阻挡层上形成有第一通孔与第二通孔；所述钝化层和刻蚀阻挡层上形成有第三通孔、及第四通孔；所述第一源极通过第一通孔与第一半导体层的一端相接触，所述连接电极通过第三通孔与第一半导体层的另外一端相接触，同时通过第四通孔与第二半导体层的一端相接触；所述第二漏极通过第二通孔与所述第二半导体层的另外一端相接触；
所述第一底栅极、第一半导体层、第一源极、连接电极、及第一顶栅极构成第一双栅极TFT；所述第二底栅极、第二半导体层、连接电极、第 二漏极、及第二顶栅极构成第二双栅极TFT；所述连接电极同时充当第一双栅极TFT的第一漏极、及第二双栅极TFT的第二源极，从而将第一双栅极TFT与第二双栅极TFT串联起来；
其中，所述第一半导体层包括第一沟道区、及分别位于该第一沟道区两侧的第一源极接触区与第一漏极接触区；所述第二半导体层包括第二沟道区、及分别位于该第二沟道区两侧的第二源极接触区与第二漏极接触区；
其中，所述第一通孔、第三通孔、第四通孔、及第二通孔分别用于暴露第一源极接触区、第一漏极接触区、第二源极接触区、及第二漏极接触区；
其中，所述半导体层的材料为金属氧化物。
本发明的有益效果：本发明提供的一种TFT基板的制作方法，通过将连接两双栅极TFT的连接电极设置于第三金属层，避免了现有设计中将连接电极与数据线、供电压线等讯号线共同设置于第二金属层从而导致该连接电极与第二金属层的设计规则变小的问题，有利于提高显示面板的开口率、及分辨率。本发明提供的一种TFT基板结构，其结构简单，具有高开口率及高分辨率。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为现有的一种双栅极TFT像素补偿电路的电路图；
图2为对应图1所示的双栅极TFT像素补偿电路的TFT基板结构的示意图；
图3为图2所示的TFT基板结构中TFT组件与数据线、及供电压线的分布及连接示意图；
图4为本发明的TFT基板的制作方法步骤1的示意图；
图5为本发明的TFT基板的制作方法步骤2的示意图；
图6为本发明的TFT基板的制作方法步骤3的示意图；
图7为本发明的TFT基板的制作方法步骤4的示意图；
图8为本发明的TFT基板的制作方法步骤5的示意图；
图9为本发明的TFT基板的制作方法步骤6的示意图；
图10为本发明的TFT基板的制作方法步骤7的示意图暨本发明的TFT基板结构的剖面示意图；
图11为图10所示的TFT基板结构中TFT组件与数据线、及供电压线的分布及连接示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图4至图11，本发明提供一种TFT基板的制作方法，包括如下步骤：
步骤1、如图4所示，提供一基板1，在所述基板1上沉积第一金属层，并通过一道光刻制程图案化该第一金属层，形成间隔设置的第一底栅极21、及与第二底栅极23。
优选的，所述基板1为玻璃基板。
具体地，该步骤1采用物理气相沉积法(Physical Vapor Deposition，PVD)沉积所述第一金属层；优选的，所述第一金属层的材料为铜、铝、或钼。
所述光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程。
步骤2、如图5所示，在所述第一底栅极21、第二底栅极23、及基板1上沉积栅极绝缘层3。
具体地，该步骤2采用等离子增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)沉积所述栅极绝缘层3；优选的，所述栅极绝缘层3的材料为氧化硅或氮化硅。
步骤3、如图6所示，在所述栅极绝缘层3上沉积一金属氧化物层，并通过一道光刻制程对该金属氧化物层进行图案化，形成间隔设置的第一半导体层41、及第二半导体层43。
所述第一半导体层41包括第一沟道区412、及分别位于该第一沟道区412两侧的第一源极接触区414与第一漏极接触区416；所述第二半导体层43包括第二沟道区432、及分别位于该第二沟道区432两侧的第二源极接触区434与第二漏极接触区436。
具体地，该步骤3采用物理气相沉积法沉积所述金属氧化物层，优选的，所述金属氧化物层的材料为铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)。
所述光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程。
步骤4、如图7所示，在所述第一半导体层41、第二半导体层43、及栅极绝缘层3上沉积一刻蚀阻挡层5，并通过一道光刻制程在该刻蚀阻挡层5上分别形成第一通孔51与第二通孔52，分别用于暴露第一源极接触区414与第二漏极接触区436。
具体地，该步骤4采用化学气相沉积法(Chemical Vapor Deposition，CVD)沉积所述刻蚀阻挡层5。
所述光刻制程包括涂光阻、曝光、显影、干蚀刻、及去光阻制程。
步骤5、如图8所示，在所述刻蚀阻挡层5上沉积第二金属层，并通过一道光刻制程图案化该第二金属层，形成间隔设置的第一源极61、及第二漏极62。
所述第一源极61通过第一通孔51与第一源极接触区414相接触；所述第二漏极62通过第二通孔52与第二漏极接触区436相接触。
具体地，该步骤5采用物理气相沉积法沉积所述第二金属层；优选的，所述第二金属层的材料为铜、铝、或钼。
所述光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程。
步骤6、如图9所示，在所述第一源极61、第二漏极62、及刻蚀阻挡层5上沉积一钝化层7，并通过一道光刻制程在该钝化层7和刻蚀阻挡层5上形成第三通孔73与第四通孔74，分别用于暴露第一漏极接触区416与第二源极接触区434。
具体地，该步骤6采用化学气相沉积法沉积所述钝化层7；优选的，所述钝化层7的材料为氧化硅或氮化硅。
所述光刻制程包括涂光阻、曝光、显影、干蚀刻、及去光阻制程。
步骤7、如图10所示，在所述钝化层7上沉积第三金属层，并通过一道光刻制程图案化该第三金属层，形成间隔设置的第一顶栅极82、连接电极83、及第二顶栅极84。
所述连接电极83分别通过第三通孔73、及第四通孔74与第一漏极接触区416、及第二源极接触区434相接触。
具体地，该步骤7采用物理气相沉积法沉积所述第三金属层；优选的，所述第三金属层的材料为铜、铝、或钼。
所述光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程。
上述TFT基板的制作方法将所述第一源极61、及第二漏极62设置于第二金属层，而将所述连接电极83与第一、第二顶栅极82、84设置于第三金属层，避免了现有设计中将连接电极与数据线、供电压线等讯号线共 同设置于第二金属层从而导致该连接电极与第二金属层的设计规则变小的问题，有利于提高显示面板的开口率、及分辨率。
请参阅图10、图11，本发明还提供一种由上述制作方法制备的TFT基板结构，其包括从下到上依次设置的：基板1、第一金属层、栅极绝缘层3、半导体层、刻蚀阻挡层5、第二金属层、钝化层7、及第三金属层；所述第一金属层包括间隔设置的第一底栅极21、及第二底栅极23；所述半导体层包括间隔设置的第一半导体层41、及第二半导体层43；所述第二金属层包括间隔设置的第一源极61、及第二漏极62；所述第三金属层包括间隔设置的第一顶栅极82、连接电极83、及第二顶栅极84。
所述刻蚀阻挡层5上形成有第一通孔51与第二通孔52；所述钝化层7与刻蚀阻挡层5上形成有第三通孔73、及第四通孔74；所述第一源极61通过第一通孔51与第一半导体层41的一端相接触，所述连接电极63通过第三通孔73与第一半导体层41的另外一端相接触，同时通过第四通孔74与第二半导体层43的一端相接触；所述第二漏极62通过第二通孔52与所述第二半导体层43的另外一端相接触。
具体地，所述第一半导体层41包括第一沟道区412、及分别位于该第一沟道区412两侧的第一源极接触区414与第一漏极接触区416；所述第二半导体层43包括第二沟道区432、及分别位于该第二沟道区432两侧的第二源极接触区434与第二漏极接触区436；
所述第一通孔51、第三通孔27、第四通孔74、及第二通孔52分别用于暴露第一源极接触区414、第一漏极接触区416、第二源极接触区434、及第二漏极接触区436；
所述第一源极61通过第一通孔51与第一源极接触区414相接触，所述连接电极63分别通过第三通孔73、及第四通孔74与第一漏极接触区416、及第二源极接触区434相接触，所述第二漏极62通过第二通孔52与所述第二漏极接触区436相接触。
所述第一底栅极21、第一半导体层41、第一源极61、连接电极83、及第一顶栅极82构成第一双栅极TFT；所述第二底栅极23、第二半导体层44、连接电极83、第二漏极62、及第二顶栅极84构成第二双栅极TFT；所述连接电极83同时充当第一双栅极TFT的第一漏极、及第二双栅极TFT的第二源极，从而将第一双栅极TFT与第二双栅极TFT串联起来。
优选的，所述基板1为玻璃基板。
优选的，所述第一金属层的材料为铜、铝、或钼。
优选的，所述栅极绝缘层3的材料为氧化硅或氮化硅。
具体地，所述半导体层的材料为金属氧化物，优选的，所述金属氧化物为铟镓锌氧化物。
优选的，所述刻蚀阻挡层5的材料为氧化硅或氮化硅。
优选的，所述第二金属层的材料为铜、铝、或钼。
优选的，所述钝化层7的材料为氧化硅或氮化硅。
优选的，所述第三金属层的材料为铜、铝、或钼。
综上所述，本发明的TFT基板的制作方法，通过将连接两双栅极TFT的连接电极设置于第三金属层，避免了现有设计中将连接电极与数据线、供电压线等讯号线共同设置于第二金属层从而导致该连接电极与第二金属层的设计规则变小的问题，有利于提高显示面板的开口率、及分辨率。本发明的TFT基板结构，其结构简单，具有高开口率及高分辨率。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (12)

  1. 一种TFT基板的制作方法，包括如下步骤：
    步骤1、提供一基板，在所述基板上沉积第一金属层，并通过一道光刻制程图案化该第一金属层，形成间隔设置的第一底栅极、及第二底栅极；
    步骤2、在所述第一底栅极、第二底栅极、及基板上沉积栅极绝缘层；
    步骤3、在所述栅极绝缘层上沉积一金属氧化物层，并通过一道光刻制程对该金属氧化物层进行图案化，形成间隔设置的第一半导体层、及第二半导体层；
    所述第一半导体层包括第一沟道区、及分别位于该第一沟道区两侧的第一源极接触区与第一漏极接触区；所述第二半导体层包括第二沟道区、及分别位于该第二沟道区两侧的第二源极接触区与第二漏极接触区；
    步骤4、在所述第一半导体层、第二半导体层、及栅极绝缘层上沉积一刻蚀阻挡层，并通过一道光刻制程在该刻蚀阻挡层上分别形成第一通孔与第二通孔，分别用于暴露第一源极接触区与第二漏极接触区；
    步骤5、在所述刻蚀阻挡层上沉积第二金属层，并通过一道光刻制程图案化该第二金属层，形成间隔设置的第一源极、及第二漏极；
    所述第一源极通过第一通孔与第一源极接触区相接触；所述第二漏极通过第二通孔与第二漏极接触区相接触；
    步骤6、在所述第一源极、第二漏极、及刻蚀阻挡层上沉积一钝化层，并通过一道光刻制程在该钝化层和刻蚀阻挡层上形成第三通孔与第四通孔，分别用于暴露第一漏极接触区与第二源极接触区；
    步骤7、在所述钝化层上沉积第三金属层，并通过一道光刻制程图案化该第三金属层，形成间隔设置的第一顶栅极、连接电极、及第二顶栅极；
    所述连接电极分别通过第三通孔、及第四通孔与第一漏极接触区、及第二源极接触区相接触。
  2. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤1采用物理气相沉积法沉积所述第一金属层，所述第一金属层的材料为铜、铝、或钼，所述步骤1中的光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程；所述步骤2采用等离子增强化学气相沉积法沉积所述栅极绝缘层，所述栅极绝缘层的材料为氧化硅或氮化硅。
  3. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤3采用物理气相沉积法沉积所述金属氧化物层，所述金属氧化物层的材料为铟镓 锌氧化物；所述步骤3中的光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程。
  4. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤4采用化学气相沉积法沉积所述刻蚀阻挡层，所述刻蚀阻挡层的材料为氧化硅或氮化硅，所述步骤4中的光刻制程包括涂光阻、曝光、显影、干蚀刻、及去光阻制程；所述步骤5采用物理气相沉积法沉积所述第二金属层，所述第二金属层的材料为铜、铝、或钼，所述步骤5中的光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程。
  5. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤6采用化学气相沉积法沉积所述钝化层，所述钝化层的材料为氧化硅或氮化硅，所述步骤6中的光刻制程包括涂光阻、曝光、显影、干蚀刻、及去光阻制程；所述步骤7采用物理气相沉积法沉积所述第三金属层，所述第三金属层的材料为铜、铝、或钼，所述步骤7中的光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程。
  6. 一种TFT基板结构，包括从下到上依次设置的：基板、第一金属层、栅极绝缘层、半导体层、刻蚀阻挡层、第二金属层、钝化层、及第三金属层；所述第一金属层包括间隔设置的第一底栅极、及第二底栅极；所述半导体层包括间隔设置的第一半导体层、及第二半导体层；所述第二金属层包括间隔设置的第一源极、及第二漏极；所述第三金属层包括间隔设置的第一顶栅极、连接电极、及第二顶栅极；
    所述刻蚀阻挡层上形成有第一通孔与第二通孔；所述钝化层和刻蚀阻挡层上形成有第三通孔、及第四通孔；所述第一源极通过第一通孔与第一半导体层的一端相接触，所述连接电极通过第三通孔与第一半导体层的另外一端相接触，同时通过第四通孔与第二半导体层的一端相接触；所述第二漏极通过第二通孔与所述第二半导体层的另外一端相接触；
    所述第一底栅极、第一半导体层、第一源极、连接电极、及第一顶栅极构成第一双栅极TFT；所述第二底栅极、第二半导体层、连接电极、第二漏极、及第二顶栅极构成第二双栅极TFT；所述连接电极同时充当第一双栅极TFT的第一漏极、及第二双栅极TFT的第二源极，从而将第一双栅极TFT与第二双栅极TFT串联起来。
  7. 如权利要求6所述的TFT基板结构，其中，所述第一半导体层包括第一沟道区、及分别位于该第一沟道区两侧的第一源极接触区与第一漏极接触区；所述第二半导体层包括第二沟道区、及分别位于该第二沟道区两侧的第二源极接触区与第二漏极接触区。
  8. 如权利要求7所述的TFT基板结构，其中，所述第一通孔、第三通孔、第四通孔、及第二通孔分别用于暴露第一源极接触区、第一漏极接触区、第二源极接触区、及第二漏极接触区。
  9. 如权利要求8所述的TFT基板结构，其中，所述第一源极通过第一通孔与第一源极接触区相接触，所述连接电极分别通过第三通孔、及第四通孔与第一漏极接触区、及第二源极接触区相接触，所述第二漏极通过第二通孔与所述第二漏极接触区相接触。
  10. 如权利要求6所述的TFT基板结构，其中，所述半导体层的材料为金属氧化物。
  11. 一种TFT基板结构，包括从下到上依次设置的：基板、第一金属层、栅极绝缘层、半导体层、刻蚀阻挡层、第二金属层、钝化层、及第三金属层；所述第一金属层包括间隔设置的第一底栅极、及第二底栅极；所述半导体层包括间隔设置的第一半导体层、及第二半导体层；所述第二金属层包括间隔设置的第一源极、及第二漏极；所述第三金属层包括间隔设置的第一顶栅极、连接电极、及第二顶栅极；
    所述刻蚀阻挡层上形成有第一通孔与第二通孔；所述钝化层和刻蚀阻挡层上形成有第三通孔、及第四通孔；所述第一源极通过第一通孔与第一半导体层的一端相接触，所述连接电极通过第三通孔与第一半导体层的另外一端相接触，同时通过第四通孔与第二半导体层的一端相接触；所述第二漏极通过第二通孔与所述第二半导体层的另外一端相接触；
    所述第一底栅极、第一半导体层、第一源极、连接电极、及第一顶栅极构成第一双栅极TFT；所述第二底栅极、第二半导体层、连接电极、第二漏极、及第二顶栅极构成第二双栅极TFT；所述连接电极同时充当第一双栅极TFT的第一漏极、及第二双栅极TFT的第二源极，从而将第一双栅极TFT与第二双栅极TFT串联起来；
    其中，所述第一半导体层包括第一沟道区、及分别位于该第一沟道区两侧的第一源极接触区与第一漏极接触区；所述第二半导体层包括第二沟道区、及分别位于该第二沟道区两侧的第二源极接触区与第二漏极接触区；
    其中，所述第一通孔、第三通孔、第四通孔、及第二通孔分别用于暴露第一源极接触区、第一漏极接触区、第二源极接触区、及第二漏极接触区；
    其中，所述半导体层的材料为金属氧化物。
  12. 如权利要求11所述的TFT基板结构，其中，所述第一源极通过第一通孔与第一源极接触区相接触，所述连接电极分别通过第三通孔、及第 四通孔与第一漏极接触区、及第二源极接触区相接触，所述第二漏极通过第二通孔与所述第二漏极接触区相接触。
PCT/CN2015/079907 2015-05-06 2015-05-27 Tft基板的制作方法及其结构 Ceased WO2016176884A1 (zh)

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