WO2016173311A1 - 一种砷化镓基半导体器件的制作方法 - Google Patents

一种砷化镓基半导体器件的制作方法 Download PDF

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Publication number
WO2016173311A1
WO2016173311A1 PCT/CN2016/073992 CN2016073992W WO2016173311A1 WO 2016173311 A1 WO2016173311 A1 WO 2016173311A1 CN 2016073992 W CN2016073992 W CN 2016073992W WO 2016173311 A1 WO2016173311 A1 WO 2016173311A1
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insulating layer
region
substrate
manufacturing
etching
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PCT/CN2016/073992
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English (en)
French (fr)
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郭佳衢
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厦门市三安光电科技有限公司
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Publication of WO2016173311A1 publication Critical patent/WO2016173311A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching

Definitions

  • the present invention relates to a semiconductor process, and more particularly to a method of fabricating a gallium arsenide based semiconductor device.
  • HBT heterojunction bipolar transistor
  • a radio frequency power amplifier a plurality of bipolar transistors are formed on a gallium arsenide based wafer, and each bipolar transistor includes a base, an emitter and a collector, and between adjacent electrodes and electrodes.
  • the interior has formed height drops and sharp angles on the order of microns.
  • the metal layer is prone to cracks and flaking at the sharp corners due to the unevenness of the surface of the wafer, and the crack has the function of diffusion and spread, which makes the subsequent process difficult, and the rejection rate is high.
  • it greatly affects the electrical conductivity of the metal layer, making the fabricated semiconductor device poor in stability and short in service life.
  • the technical solution is hereby incorporated herein.
  • the object of the present invention is to overcome the deficiencies of the prior art and to provide a method of fabricating a gallium arsenide based semiconductor device.
  • a method for fabricating a gallium arsenide-based semiconductor device includes the following steps:
  • the substrate comprises a semiconductor wafer, the wafer is formed with at least one base region, an emitter region and a collector region, wherein a height difference between adjacent electrode regions is at a height difference Forming a convex tip angle;
  • step 3) and step 4 the photoetching process uses the same mask, wherein positive photoresist is used in step 3), negative photoresist is used in step 4), and step (4) is relative to step (3).
  • the etch critical dimension (CD) is reduced by 0.1-0.5 um.
  • the thickness of the insulating layer is 1.2-3 um, and in step 4), the etching thickness of the photolithography process is 0.1 - 0.3 um.
  • the insulating layer has an arc-shaped transition corresponding to a height difference region of the substrate.
  • step 4 after the outer convex corner is smoothed, the insulating layer forms a chamfered structure corresponding to the height drop region of the substrate, and the convex minimum angle is greater than 135°.
  • the base region, the emitter region and the collector region form a bipolar transistor structure, wherein the base region is located between the emitter and the collector, the wafer The surface is sequentially increased from the collector region to the height of the emitter region.
  • the substrate further comprises a conductive layer formed over each electrode region of the wafer;
  • the insulating layer is etched to expose the conductive layer.
  • the conductive layer is a metal, including Ti, Ni, Cu, Al, Pt, W, Mo, Cr
  • One of Au, or a combination of the above metals, is formed by magnetron sputtering, ion evaporation, arc ion evaporation or chemical vapor deposition.
  • the metal layer comprises Ti, Ni, Cu, Al, Pt, W, Mo, Cr, Au or a combination of the above metals, by magnetron sputtering, ion evaporation, arc It is formed by ion evaporation or chemical vapor deposition.
  • the insulating layer is a polyimide, which is formed by coating.
  • the insulating layer is etched by positive photoresist imaging to expose the electrode regions, and the same mask is used to adjust the etched corners by the negative photoresist and the yellow light energy, without increasing the cost of the mask.
  • FIG. 1 to FIG. 6 are schematic structural diagrams of respective process flows of the manufacturing method of the present invention.
  • a method for fabricating a gallium arsenide-based semiconductor device referring to FIG. 1, firstly, a gallium arsenide-based semiconductor wafer 1 is provided, and a plurality of bipolar transistor structures 11 are formed on the wafer 1, each bipolar transistor
  • the structure 11 includes an emitter region 111, a base region 112 and a collector region 113, wherein the base region 112 is located between the emitter region 11 and the collector region 113, and the height thereof is sequentially increased, and the adjacent electrode regions have The height drop is where the collector region 113 is at a valley and the maximum drop from the base region 112 is about 1-2 um. Due to the sharp change in height, a relatively steep terrain is formed and a convex angle is formed.
  • a conductive layer 2 is formed on the emitter region 111, the base region 112, and the collector region 113 of the wafer 1.
  • the conductive layer 2 may specifically be a metal, including one of Ti, Ni, Cu, Al, Pt, W, Mo, Cr, Au or a combination of the above metals, by magnetron sputtering, ion evaporation, arc ion Formed by evaporation or chemical vapor deposition.
  • the semiconductor wafer 1 and the conductive layer 2 form a substrate of the semiconductor device.
  • an insulating layer 3 matching or substantially matching the shape of the substrate of the structure shown in FIG. 2 is formed.
  • the insulating layer is a polyimide which is formed by coating and has a thickness of 1.2 to 3 um.
  • the thickness of the insulating layer 3 is substantially uniform to maintain uniform performance, so that it has a steep terrain and a height as a substrate. The convex corner of the difference.
  • the insulating layer 3 is etched by a photolithography process to expose the conductive layer 2 where the emitter region 111, the base region 112, and the collector region 113 are located. Specifically, a positive photoresist is coated on the insulating layer 3, and a photomask matching the conductive layer 2 is exposed and developed to form an etching window corresponding to the upper surface of the conductive layer 2, and a part of the insulating layer located in the window is removed. 3, to expose the conductive layer 2.
  • the remaining insulating layer 3 is etched by a photolithography process to smoothly transition the region of the insulating layer 3 corresponding to the height difference of the substrate surface.
  • a negative photoresist is coated on the structure shown in FIG. 4, and the reticle of the above step is used for exposure and development, and the exposure ⁇ is matched with the adjustment of the yellow light energy, and the etching critical dimension (CD) is reduced by 0.11-0.5 um.
  • CD etching critical dimension
  • the insulating layer 3 is etched away by a dry etching to a thickness of 0.1-0.3 um to remove the sharp corners, so that the region of the height drop, especially the base region 112 and the collector region 113, smoothly transitions to form a relatively gentle surface. .
  • the insulating layer 3 has an arc-shaped transition corresponding to the height drop region of the substrate.
  • the energy is adjusted so that the insulating layer 3 forms a chamfered structure corresponding to the height difference region of the substrate, wherein the convex minimum angle is greater than 135° to avoid the breakage caused by the stress concentration.
  • a metal layer 4 is formed above the above structure, and the metal layer includes Ti, Ni, Cu, Al, Pt, W, Mo, Cr, Au or a combination of the above metals, and is deposited by evaporation.
  • the method is formed, and is directly connected to the conductive layer 2 in the emitter region 111, the base region 112, and the collector region 113.
  • the metal layer 4 is formed on a relatively gentle surface, and cracks are less likely to occur, which facilitates the subsequent fabrication process.
  • the etched conductive layer 2 and the metal layer 4 may be strip-shaped structures that are perpendicular to each other and electrically connected to the electrode regions, and are respectively connected to the control circuit and the like at the periphery. Used to make wireless RF power amplifiers, the resulting device has stable performance.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Bipolar Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

一种砷化镓基半导体器件的制作方法，包括有以下步骤：提供一底材，底材包括一砷化镓基半导体晶片（1），晶片形成有至少一基极区（112）、发射极区（111）及集电极区（113），其中相邻电极区之间具有高度差并于高度落差处形成外凸尖角；于底材上形成一与底材形状相匹配或基本匹配的绝缘层（3）；通过光蚀刻工艺蚀刻绝缘层，以露出各电极区；通过光蚀刻工艺蚀刻剩余绝缘层，使绝缘层对应底材表面高度落差的区域平滑过渡；形成一金属层（4）。通过绝缘层表面的平缓化处理，避免了金属层产生裂痕的问题。

Description

说明书 发明名称：一种砷化镓基半导体器件的制作方法 技术领域
[0001] 本发明涉及半导体工艺， 特别是涉及一种砷化镓基半导体器件的制作方法。
背景技术
[0002] 在半导体器件的制作过程中， 常需要在半导体晶片上通过惨杂、 离子注入、 蚀 刻等工艺形成各种功能区， 而对异质结双极型晶体管 (HBT)的器件制作， 功能区 之间往往具有较为明显的高度差， 这就导致半导体晶片表面的地势较为陡峭并 具有高度落差形成的尖角。 例如， 在制作无线射频功率放大器吋， 在砷化镓基 晶片上形成有多个双极型三极管， 每个双极型三极管包括有基极、 发射极及集 电极， 相邻电极之间及电极内部都形成了微米数量级的高度落差和尖角。 在晶 片上后续形成金属层吋， 由于晶片表面的不平整， 金属层在尖角处极易出现裂 痕及剥落的情况， 而裂痕具有扩散蔓延的作用， 一方面使后续工艺难以进行， 废品率高； 另一方面极大地影响了金属层的导电性能， 使制作的半导体器件稳 定性差， 使用寿命短
技术问题
[0003] 上述问题的存在， 极大的影响和限制了半导体器件的良品率和生产效率。
问题的解决方案
技术解决方案
[0004] 在此处键入技术解决方本发明的目的在于克服现有技术之不足， 提供一种砷化 镓基半导体器件的制作方法。
[0005] 本发明解决其技术问题所采用的技术方案是： 一种砷化镓基半导体器件的制作 方法包括以下步骤：
[0006] 1) 提供一底材， 所述底材包括一半导体晶片， 晶片形成有至少一基极区、 发 射极区及集电极区， 其中相邻电极区之间具有高度差并于高度落差处形成外凸 尖角；
[0007] 2) 于底材上形成一与之形状相匹配或基本匹配的绝缘层， 其中所述绝缘层对 应所述底材高度落差区域亦配合形成有外凸尖角；
[0008] 3) 通过光蚀刻工艺蚀刻所述绝缘层， 以露出所述各电极区；
[0009] 4) 通过光蚀刻工艺蚀刻剩余绝缘层， 以平滑所述绝缘层的外凸尖角;
[0010] 5) 于上述结构上方形成一金属层。
作为一种优选， 步骤 3) 与步骤 4) 中， 光蚀刻工艺采用相同的光罩， 其中步骤 3) 中采用正光阻， 步骤 4) 中采用负光阻， 步骤 （4) 相对于步骤 （3) 其蚀刻 临界尺寸 （CD) 缩小 0.1-0.5 um。
[0012] 作为一种优选， 所述绝缘层的厚度是 1.2-3 um， 步骤 4) 中， 所述光蚀刻工艺的 蚀刻厚度是 0.1 -0.3 um。
作为一种优选， 步骤 4) 中， 所述外凸尖角平滑后， 所述绝缘层对应所述底材 的高度落差区域呈圆弧状过渡。
[0014] 作为一种优选， 步骤 4) 中， 所述外凸尖角平滑后， 所述绝缘层对应所述底材 的高度落差区域形成倒角结构， 外凸最小角度大于 135°。
[0015] 作为一种优选， 所述基极区、 发射极区及集电极区形成一双极型三极管结构， 其中所述基极区位于所述发射极和所述集电极之间， 所述晶片表面由所述集电 极区向所述发射极区其高度依次递增。
[0016] 作为一种优选， 所述底材还包括形成于所述晶片各电极区上方的导电层； 步骤
3) 中， 所述绝缘层经蚀刻后露出所述导电层。
[0017] 作为一种优选， 所述导电层是金属， 包括有 Ti、 Ni、 Cu、 Al、 Pt、 W、 Mo、 Cr
、 Au中的一种或上述金属的组合层， 是通过磁控溅镀、 离子蒸镀、 电弧离子蒸 镀或化学气相沉积的方式形成。
[0018] 作为一种优选， 所述金属层包括有 Ti、 Ni、 Cu、 Al、 Pt、 W、 Mo、 Cr、 Au或 上述金属的组合层， 是通过磁控溅镀、 离子蒸镀、 电弧离子蒸镀或化学气相沉 积的方式形成。
[0019] 作为一种优选， 所述绝缘层是聚亚酰胺， 通过涂覆的方式形成。
发明的有益效果
有益效果
[0020] 1、 在底材表面形成绝缘层， 绝缘层的形状与底材表面形状相匹配或基本匹配 以具有均匀的厚度， 保证其性能的均一性， 再通过光蚀刻的方式平滑绝缘层对 应底材高度落差区域的外凸尖角， 形成弧形或倒角结构， 使其平缓过渡， 形成 一个较为平缓的表面， 再在其上形成金属层， 避免了金属层在地势陡峭的尖角 处断裂的问题。
[0021] 2、 绝缘层通过正光阻成像进行蚀刻以裸露出各电极区， 使用同一张光罩通过 负光阻配合黄光能量调整蚀刻尖角处， 不增加光罩的成本。
对附图的简要说明
附图说明
[0022] 图 1-图 6依次为本发明制作方法各工艺流程的结构示意图。
本发明的实施方式
[0023] 以下结合附图及实施例对本发明作进一步详细说明。 本发明的各附图仅为示意 以更容易了解本发明， 其具体比例可依照设计需求进行调整。 文中所描述的图 形中相对元件的上下关系， 在本领域技术人员应能理解是指构件的相对位置而 言， 因此皆可以翻转而呈现相同的构件， 此皆应同属本说明书所揭露的范围。
[0024] 一种砷化镓基半导体器件的制作方法， 参考图 1， 首先是提供一砷化镓基半导 体晶片 1， 晶片 1上形成有多个双极型三极管结构 11， 每一双极型三极管结构 11 包括有发射极区 111、 基极区 112和集电极区 113， 其中基极区 112位于发射极区 1 11和集电极区 113之间， 其高度依次递增， 相邻电极区之间具有高度落差， 其中 集电极区 113处于一个低谷处， 与基极区 112之间最大的落差约为 l-2um左右。 由 于高度急剧变化， 形成了较为陡峭的地势并具有外凸尖角。
[0025] 参考图 2， 于晶片 1的发射极区 111、 基极区 112和集电极区 113上形成导电层 2。
导电层 2具体可以是金属， 包括有 Ti、 Ni、 Cu、 Al、 Pt、 W、 Mo、 Cr、 Au中的一 种或上述金属的组合层， 通过磁控溅镀、 离子蒸镀、 电弧离子蒸镀或化学气相 沉积的方式形成。 半导体晶片 1和导电层 2形成了半导体器件的底材。
[0026] 参考图 3， 于图 2所示结构的底材上形成一与之形状相匹配或基本匹配的绝缘层 3。 绝缘层是聚亚酰胺， 通过涂覆的方式形成， 厚度为 1.2-3 um。 绝缘层 3的厚度 基本上较为均匀以保持均一的性能， 故亦具有如底材一样陡峭的地势及高度落 差处的外凸尖角。
[0027] 参考图 4， 通过光蚀刻工艺蚀刻绝缘层 3， 以露出发射极区 111、 基极区 112和集 电极区 113所在的导电层 2。 具体的， 在绝缘层 3上涂覆正光阻， 以透光窗口与导 电层 2匹配的光罩进行曝光、 显影形成对应于导电层 2上方的蚀刻窗口， 并去除 位于该窗口内的部分绝缘层 3， 以裸露出导电层 2。
[0028] 参考图 5， 通过光蚀刻工艺蚀刻剩余绝缘层 3， 使绝缘层 3对应底材表面高度落 差的区域平滑过渡。 具体的， 在图 4所示结构的上方涂覆负光阻， 以上述步骤的 光罩进行曝光、 显影， 曝光吋配合黄光能量的调整， 蚀刻临界尺寸 （CD) 缩小 0 .1-0.5 um以将非曝光范围扩大至上一步骤中正蚀刻产生的尖角 A处。 接着， 通过 干蚀刻将绝缘层 3蚀刻掉 0.1-0.3 um的厚度， 以去除尖角， 使高度落差的区域， 尤 其是基极区 112和集电极区 113之间平滑过渡， 形成较为平缓的表面。 本实施例 中， 外凸尖角平滑后， 绝缘层 3对应底材的高度落差区域呈圆弧状过渡。 此外， 通过能量的调整， 以可使绝缘层 3对应底材的高度落差区域形成倒角结构， 其中 外凸最小角度大于 135°， 以避免应力集中造成的断裂。
[0029] 参考图 6， 于上述结构的上方形成一金属层 4， 金属层包括有 Ti、 Ni、 Cu、 Al、 Pt、 W、 Mo、 Cr、 Au或上述金属的组合层， 是通过蒸镀的方式形成， 并于发射 极区 111、 基极区 112和集电极区 113与导电层 2直接相接导通。 金属层 4形成于比 较平缓的表面上， 不易产生裂缝， 利于后续制作工艺的进行。
[0030] 本发明的半导体器件中， 蚀刻后的导电层 2及金属层 4可以是互相垂直并于各电 极区电性连接的条状结构， 并分别于周边与控制电路等结构相连接， 可以用于 制作无线射频功率放大器， 制得的器件性能稳定。
[0031] 上述实施例仅用来进一步说明本发明的一种砷化镓基半导体器件的制作方法， 但本发明并不局限于实施例， 凡是依据本发明的技术实质对以上实施例所作的 任何简单修改、 等同变化与修饰， 均落入本发明技术方案的保护范围内。

Claims

权利要求书
[权利要求 1] 一种砷化镓基半导体器件的制作方法， 其特征在于包括以下步骤：
1) 提供一底材， 所述底材包括一砷化镓基半导体晶片， 晶片形成有 至少一基极区、 发射极区及集电极区， 其中相邻电极区之间具有高度 差并于高度落差处形成外凸尖角；
2) 于底材上形成一与之形状相匹配或基本匹配的绝缘层， 其中所述 绝缘层对应所述底材高度落差区域亦配合形成有外凸尖角；
3) 通过光蚀刻工艺蚀刻所述绝缘层， 以露出所述各电极区；
4) 通过光蚀刻工艺蚀刻剩余绝缘层， 以平滑所述绝缘层的外凸尖角
Figure imgf000007_0001
[权利要求 2] 根据权利要求 1所述的制作方法， 其特征在于： 步骤 3) 与步骤 4) 中 ， 光蚀刻工艺采用相同的光罩， 其中步骤 3) 中采用正光阻， 步骤 4) 中采用负光阻， 步骤 4) 相对于步骤 3) 其蚀刻临界尺寸缩小 0.1-0.5
[权利要求 3] 根据权利要求 1或 2所述的制作方法， 其特征在于： 所述绝缘层的厚度 是 1.2-3 um， 步骤 4) 中， 所述光蚀刻工艺的蚀刻厚度是 0.1-0.3 um。
[权利要求 4] 根据权利要求 3所述的制作方法， 其特征在于： 步骤 4) 中， 所述外凸 尖角平滑后， 所述绝缘层对应所述底材的高度落差区域呈弧形过渡。
[权利要求 5] 根据权利要求 3所述的制作方法， 其特征在于： 步骤 4) 中， 所述外凸 尖角平滑后， 所述绝缘层对应所述底材的高度落差区域形成倒角结构 ， 外凸最小角度大于 135°。
[权利要求 6] 根据权利要求 1所述的制作方法， 其特征在于： 所述基极区、 发射极 区及集电极区形成一双极型三极管结构， 其中所述基极区位于所述发 射极和所述集电极之间， 所述晶片表面由所述集电极区向所述发射极 区其高度依次递增。
[权利要求 7] 根据权利要求 1所述的制作方法， 其特征在于： 所述底材还包括形成 于所述晶片各电极区上方的导电层； 步骤 3) 中， 所述绝缘层经蚀刻 后露出所述导电层。
[权利要求 8] 根据权利要求 5所述的制作方法， 其特征在于： 所述导电层是金属， 包括有 Ti、 Ni、 Cu、 Al、 Pt、 W、 Mo、 Cr、 Au中的一种或上述金属 的组合层， 是通过磁控溅镀、 离子蒸镀、 电弧离子蒸镀或化学气相沉 积的方式形成。
[权利要求 9] 根据权利要求 1或 8所述的制备方法， 其特征在于： 所述金属层包括有
Ti、 Ni、 Cu、 Al、 Pt、 W、 Mo、 Cr、 Au或上述金属的组合层， 是通 过磁控溅镀、 离子蒸镀、 电弧离子蒸镀或化学气相沉积的方式形成。
[权利要求 10] 根据权利要求 1所述的制作方法， 其特征在于： 所述绝缘层是聚亚酰 胺， 通过涂覆的方式形成。
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