WO2016172934A1 - 极化码的译码器和译码方法 - Google Patents

极化码的译码器和译码方法 Download PDF

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Publication number
WO2016172934A1
WO2016172934A1 PCT/CN2015/078011 CN2015078011W WO2016172934A1 WO 2016172934 A1 WO2016172934 A1 WO 2016172934A1 CN 2015078011 W CN2015078011 W CN 2015078011W WO 2016172934 A1 WO2016172934 A1 WO 2016172934A1
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Prior art keywords
decoding
code block
code
search
candidate
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PCT/CN2015/078011
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English (en)
French (fr)
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李斌
陈凯
金杰
沈晖
李微
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华为技术有限公司
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Priority to PCT/CN2015/078011 priority Critical patent/WO2016172934A1/zh
Priority to CN201580079174.4A priority patent/CN107534448B/zh
Publication of WO2016172934A1 publication Critical patent/WO2016172934A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes

Definitions

  • Embodiments of the present invention relate to the field of codecs and, more particularly, to a decoding method and decoder for a polarized Polar code.
  • the Polar code is the first error correction coding method that theoretically proves that the Shannon limit can be obtained and has low coding and decoding complexity.
  • the latest research shows that the serial cancellation list decoding (Successive Cancellation List decoding, SCL) based on serial cancellation decoding (English: Successive Cancellation decoding, SCL), serial cancellation stack decoding (English: Successful Cancellation Stack decoding, shorthand: SCS), Serial Cancellation Hybrid decoding (SCH) can significantly improve the frame error rate of the Polar code (English: Frame Error Rate, shorthand: FER) performance
  • SCL Successive Cancellation List decoding
  • SCS Serial cancellation stack decoding
  • SCH Serial Cancellation Hybrid decoding
  • Such algorithms are collectively referred to as enhanced SC decoding algorithms.
  • the Polar code can be better than the low-density parity check (English: Low-Density Parity-Check, abbreviated: FER performance of LDPC) code or Turbo code.
  • a code of code length N may correspond to a binary code tree composed of N layer edges, and SC coding can be described as a path search process on the code tree, and the decoding complexity is O ( Nlog 2 N).
  • SC decoding can achieve good performance when the code length N is long, and it is close to the Shannon limit.
  • the FER performance obtained by the SC code through SC decoding is not ideal.
  • Enhanced SC decoding allows multiple (SC decoding only one) candidate paths to be reserved on the binary decoding code tree. The number of candidate paths is the search width, thereby expanding the search range and reducing the search. The probability of leaving the correct path in the process to enhance the FER performance.
  • the CRC-assisted enhanced SC coding method can select a path with the highest probability and can pass the CRC check as the decoding from the plurality of candidate path sets. Output.
  • the search width of the enhanced SC decoding algorithm needs to be set to a larger value, resulting in higher decoding complexity and larger decoding delay.
  • DSL Digital Subscriber Line
  • CoMP Coordinated Multiple Points
  • the central station needs to decode data of multiple users at the same time. If each code block monopolizes a decoder, it needs to A code block implements a decoder with a large search width, so that the overall decoding complexity is very large, and the decoding delay is also large.
  • the invention provides a decoding method and a decoder for a polarization code, which can reduce the average decoding delay of the Polar decoding and reduce the average spatial complexity.
  • a first method provides a method for decoding a polarization code, comprising: performing parallel decoding on a code block by using L different search widths; and obtaining at least one candidate according to the completed decoding in the parallel decoding A path determining a decoding path of the code block.
  • the decoding path of the code block is determined according to the at least one candidate path obtained by performing decoding in the parallel coding
  • the method includes: performing, by using the completed decoding, at least one candidate path, a redundant cyclic CRC check; and determining, by the at least one candidate path, a candidate path that passes the CRC check as the code block The decoding path.
  • the method further includes: after determining the decoding path of the code block, stopping Unfinished decoding in the parallel decoding.
  • the performing, by using the different search width, the code block is decoded in parallel, including: Determining N candidate search widths, wherein any two of the N candidate search widths are different; according to the number of the N candidate search widths, the code rate of the code block, the signal to noise ratio of the code block, and The average decoding delay D a required by the code block, and the L different search widths are determined from the N candidate search widths.
  • the L different search widths are determined by: Where D a is the average decoding delay required by the code block, and d 1 , d 2 , . . . , d l-1 is a set of monotonically increasing integers greater than 0 and less than or equal to nj, where R is the code block Code rate, ⁇ is the signal to noise ratio of the code block, search width L n is monotonically increasing, and the function D( ⁇ , ⁇ , ⁇ ) is used to use the search width as The sum of the delays required for Ln to perform serial decoding.
  • the method further includes: if the L different search widths are used to the code block None of the candidate paths obtained by parallel decoding can pass the CRC check, and select M different search widths from the N candidate search widths to perform parallel decoding on the code blocks, where the M are different.
  • the minimum search width in the search width is greater than the largest search width among the L different search widths.
  • a decoder for a polarization code comprising: a decoding module, wherein the decoding module performs parallel decoding on the code block by using L different search widths; and a determining module, where the determining module is used for Decoding a decoding path of the code block according to at least one candidate path obtained by decoding performed by the decoding module.
  • the determining module further includes a check unit, where the check unit is used to obtain the decoded code block The at least one candidate path sequentially performs a redundant cyclic CRC check; the determining module is specifically configured to determine a candidate path that passes the CRC check in the at least one candidate path as a decoding path of the code block.
  • the determining module is specifically configured to: after determining a decoding path of the code block And stopping decoding of the uncompleted code blocks in the parallel one code.
  • the decoding module is specifically configured to: determine N candidate search widths And any two of the N candidate search widths are different; a sequence number configured according to the N candidate search widths, a code rate of the code block, a signal to noise ratio of the code block, and the code
  • the average decoding delay D a required by the block determines a minimum search width L i of the L different search widths from the N candidate search widths.
  • the decoding module is specifically configured to: determine to invoke the L different search width pairs according to the following function
  • the code block is decoded in parallel:
  • D a is the average decoding delay required by the code block
  • d 1 , d 2 , ..., d l-1 is a set of monotonically increasing integers greater than 0 and less than or equal to nj
  • R is the code block Code rate
  • ⁇ is the signal to noise ratio of the code block
  • search width L n is monotonically increasing
  • the function D( ⁇ , ⁇ , ⁇ ) is used to use the search width as The sum of delays required for Ln to perform serial decoding.
  • the decoding module is further configured to: if the L different search width pairs are used The candidate paths obtained by performing parallel decoding on the code block cannot pass the CRC check, and select M different search widths from the N candidate search widths to perform parallel decoding on the code blocks, where the The smallest search width among the M different search widths is larger than the largest search width among the L different search widths.
  • a third aspect provides a decoder for a polarization code, comprising: a decoding unit pool, the decoding unit pool comprising a plurality of decoding units, and a first decoding unit of the plurality of decoding units And the second decoding unit has a different search width; the control unit is configured to invoke L decoding units of the plurality of coding units to perform parallel decoding on the code blocks, and the L decodings Any two coding units in the unit have different search widths; a check unit, where the check unit is configured to determine the code according to at least one candidate path obtained by decoding performed by the decoding unit pool The decoding path of the block.
  • the checking unit is specifically configured to perform a redundancy loop check on the at least one candidate path obtained by the completed decoding in sequence;
  • the control unit is specifically configured to determine a candidate path that passes the CRC check in the at least one candidate path as a decoding path of the code block.
  • control unit is specifically configured to: after determining a decoding path of the code block And controlling the decoding unit pool to stop unfinished decoding in the parallel decoding.
  • control unit is specifically configured to: according to the multiple coding units The number. a code rate of the code block, a signal to noise ratio of the code block, and an average coding delay D a required by the code block, determining the L decoding units from the plurality of coding units.
  • the control unit is specifically configured to: determine the L decoding units according to the following function:
  • the jth decoding unit is a decoding unit having a minimum search width L i among the L decoding units, and D a is an average decoding delay required by the code block, d 1 , d 2 , d, l1 is a set of monotonically increasing integers greater than 0 and less than or equal to nj, R is the code rate of the code block, ⁇ is the signal to noise ratio of the code block, and the search width L n is monotonically increasing, and the function D( ⁇ , ⁇ , ⁇ ) is used to use the search width as The sum of delays required for Ln to perform serial decoding.
  • control unit is specifically configured to: if the L coding units are used The candidate path obtained by performing parallel decoding on the code block cannot pass the CRC check, and M decoding units are selected from the plurality of coding units to perform parallel decoding on the code block, where the M is The search widths of any two of the decoding units are different, and the smallest search width of the M different search widths is larger than the largest search width of the L different search widths.
  • the decoder further includes a cache unit, where the cache unit is used The code block is buffered according to control of the control unit.
  • the decoder further includes: a first multiplexing unit, Control of the control unit sends the code block into L decoding units in the decoding unit pool; a second multiplexing unit, the second multiplexing unit is configured to be used according to the control unit Controlling at least one candidate path of the code block obtained by the decoding pool into the check unit.
  • the method for decoding a polarization code decodes one or more code blocks in parallel by using L different search widths, and at least one candidate obtained according to the decoded in the parallel decoding.
  • the path determines the decoding path of the code block, so that the average decoding delay can be reduced while ensuring the same decoding error frame rate, and the average space complexity can be reduced when parallel decoding is performed on multiple code blocks. .
  • FIG. 1 illustrates a wireless communication system in accordance with various embodiments described herein.
  • FIG. 2 is a schematic flowchart of a method for decoding a polarization code according to an embodiment of the present invention.
  • FIG. 3 is a schematic block diagram of a decoder of a polarization code according to an embodiment of the present invention.
  • FIG. 4 is a schematic block diagram of a decoder of a polarization code according to another embodiment of the present invention.
  • FIG. 5 is a schematic block diagram of a decoder of a polarization code according to another embodiment of the present invention.
  • FIG. 6 is a schematic diagram showing a comparison between the decoding method of the embodiment of the present invention and the prior art decoding method in terms of FER performance.
  • FIG. 7 is a diagram showing that the decoding method of the embodiment of the present invention and the decoding method of the prior art are complicated in average calculation. A schematic diagram of the comparison on the degree.
  • Figure 8 is a schematic block diagram of a decoder of a polarization code according to another embodiment of the present invention.
  • GSM Global System of Mobile communication
  • CDMA Code Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access
  • GPRS General Packet Radio Service
  • LTE Long Term Evolution
  • FDD Frequency Division Duplex
  • TDD Time Division Duplex
  • UMTS Universal Mobile Telecommunication System
  • FIG. 1 illustrates a wireless communication system 100 in accordance with various embodiments described herein.
  • System 100 includes a base station 102 that can include multiple antenna groups.
  • one antenna group may include antennas 104 and 106
  • another antenna group may include antennas 108 and 110
  • additional groups may include antennas 112 and 114.
  • Two antennas are shown for each antenna group, however more or fewer antennas may be used for each group.
  • Base station 102 can additionally include a transmitter chain and a receiver chain, as will be understood by those of ordinary skill in the art, which can include multiple components associated with signal transmission and reception (e.g., processor, modulator, multiplexer, demodulation) , demultiplexer or antenna, etc.).
  • Base station 102 can communicate with one or more access terminals, such as access terminal 116 and access terminal 122. However, it will be appreciated that base station 102 can communicate with substantially any number of access terminals similar to access terminals 116 and 122. Access terminals 116 and 122 can be, for example, cellular telephones, smart phones, portable computers, handheld communication devices, handheld computing devices, satellite radios, global positioning systems, PDAs, and/or any other for communicating over wireless communication system 100. Suitable for equipment. As shown, access terminal 116 is in communication with antennas 112 and 114, with antennas 112 and 114 transmitting information to access terminal 116 over forward link 118 and receiving information from access terminal 116 over reverse link 120.
  • access terminal 116 is in communication with antennas 112 and 114, with antennas 112 and 114 transmitting information to access terminal 116 over forward link 118 and receiving information from access terminal 116 over reverse link 120.
  • access terminal 122 is in communication with antennas 104 and 106, wherein antennas 104 and 106 transmit information to access terminal 122 over forward link 124 and receive information from access terminal 122 over reverse link 126.
  • FDD Frequency Division Duplex
  • the forward link 118 can utilize different frequency bands than those used by the reverse link 120, and the forward link 124 can be utilized and reversed. Different frequency bands used by link 126.
  • TDD Time Division Duplex
  • the forward link 118 and the reverse link 120 can use a common frequency band, and the forward link 124 and the reverse link 126 can be used together. frequency band.
  • Each set of antennas and/or regions designed for communication is referred to as a sector of base station 102.
  • the antenna group can be designed to communicate with access terminals in sectors of the coverage area of base station 102.
  • the transmit antennas of base station 102 may utilize beamforming to improve the signal to noise ratio for forward links 118 and 124 of access terminals 116 and 122.
  • the base station 102 transmits to the randomly dispersed access terminals 116 and 122 in the relevant coverage area by the base station as compared to all of the access terminals transmitted by the base station, the mobile devices in the adjacent cells are subject to Less interference.
  • base station 102, access terminal 116, and/or access terminal 122 may be transmitting wireless communication devices and/or receiving wireless communication devices.
  • the transmitting wireless communication device can encode the data for transmission.
  • the transmitting wireless communication device can have (eg, generate, obtain, store in memory, etc.) a certain number of information bits to be transmitted over the channel to the receiving wireless communication device.
  • Such information bits may be included in a transport block (or multiple transport blocks) of data that may be segmented to produce a plurality of code blocks.
  • the transmitting wireless communication device can encode each code block using a polarization code encoder (not shown) to improve the reliability of data transmission, thereby ensuring communication quality.
  • SCS decoding uses an ordered stack instead of a list to save Reserve candidate paths.
  • each time only based on the candidate path with the highest reliability metric (on the top of the stack) is extended.
  • the decoding process is stopped, and the bit estimation sequence corresponding to the path is output as a decoding result.
  • SCL decoding can be seen as a breadth-first search on the code tree, while SCS decoding is the best priority search on the code tree.
  • SCL decoding allows for lower spatial complexity, while SCS decoding has lower computational complexity.
  • the two modes are mixed, that is, SCH decoding.
  • the implementation of SCH decoding is similar to SCS decoding, and an ordered stack is used to store candidate paths. The difference is that the stack depth of the SCH is much smaller than the SCS decoding, and by flexibly switching between the two modes, the number of candidate paths will never overflow the stack.
  • the computational complexity of SCH decoding is slightly higher than SCS decoding, much smaller than SCL decoding; the spatial complexity is slightly higher than SCL decoding is much smaller than SCS decoding.
  • the essence of enhanced SC decoding is to search for a set of candidate path sets with larger path metrics, and select the one with the largest path metric as the decoding output.
  • the CRC-assisted enhanced SC decoding algorithm can be used for decoding, that is, selecting from the finally obtained candidate path set.
  • a candidate path having the largest path metric and capable of passing the CRC check is used as the decoded output.
  • FIG. 2 is a schematic flowchart of a method for decoding a polarization code according to an embodiment of the present invention.
  • the method 200 is performed by a decoder. As shown in FIG. 2, the method 200 includes:
  • Step 210 Perform parallel decoding on the code block by using L different search widths
  • Step 220 Determine a decoding path of the code block according to at least one candidate path obtained by performing decoding in parallel decoding.
  • a code block having a code length S may correspond to a binary decoding code tree of an S layer.
  • SC coding can be described as a process of path search on the code tree.
  • the search path of SC decoding is one, that is, the search width of SC decoding is 1, and SCH decoding, SCL decoding, and SCS decoding are allowed to be reserved. Multiple candidate paths, that is, a larger search width can be selected to decode the code block, thereby expanding the search range and improving the decoding performance of the code block.
  • the code blocks in step 210 may adopt L different
  • the search width is parallel decoded.
  • the code block can refer to a certain code block or a certain number of code blocks, that is, several code blocks can be simultaneously decoded by different search widths.
  • step 220 specifically, when the code block is subjected to different search width parallel decoding, when the search width of the code block is small, the decoding candidate path is first obtained, so that the decoding path can be determined according to the candidate path that has been obtained. Output as a decoding result.
  • the method for decoding a polarization code decodes one or more code blocks in parallel by using L different search widths, and at least one candidate obtained according to the decoded in the parallel decoding.
  • the path determines the decoding path of the code block, so that the average decoding delay can be reduced while ensuring the same decoding error frame rate, and the average space complexity can be reduced when parallel decoding is performed on multiple code blocks. .
  • the code block may be serially decoded by selecting L different search widths; and the code block is determined according to at least one candidate path obtained by decoding in the serial decoding. Decoding path. Specifically, the code blocks sequentially call the L different search widths for serial decoding from small to large.
  • the method for decoding a polarization code decodes a code block serially by using L different search widths, and determines at least one candidate path obtained according to the completed decoding in the serial decoding.
  • the decoding path of the code block can reduce the average decoding delay while ensuring the same decoding error frame rate, and can also reduce the decoding complexity.
  • determining, according to at least one candidate path obtained by decoding in the parallel decoding, a decoding path of the code block including: at least one obtained by performing the decoding.
  • the candidate path sequentially performs a redundant cyclic CRC check; the candidate path that passes the CRC check in the at least one candidate path is determined as a decoding path of the code block.
  • a certain candidate path capable of passing the CRC check means that the CRC checksum of the candidate path sequence is all zeros.
  • the candidate path under the search width is obtained first, and the candidate path under the search width may be sequentially sorted according to the probability metric by the CRC check, first.
  • the path that can pass the CRC check is the decoding path of the code block.
  • the uncompleted decoding in the parallel decoding is stopped. That is to say, once the candidate path is successfully decoded by the CRC check, the decoder will stop all other decoding operations corresponding to the code block in progress, including the decoding operation and the CRC check operation, etc. And release the resource for the response, the resource includes The resources required to buffer the code block, the decoding unit being decoded in the decoder, and the CRC check circuit.
  • the decoder when the code blocks obtained by decoding the L search widths respectively fail to pass the CRC check, it indicates that the L search width fails to decode the code block, and the decoder will Release L search widths for decoding required decoding resources, so that other code blocks use the decoding resources for decoding; if the L search widths already include the maximum search width that the decoder can support , indicating that the decoding fails to decode the code block.
  • performing parallel decoding on the code block by using L different search widths includes: determining N candidate search widths, where any two of the N candidate search widths are different; The sequence number of the N candidate search widths, the code rate of the code block, the signal-to-noise ratio of the k-th code block, and the average decoding delay D a required by the code block, and L different from the N candidate search widths. Search width.
  • performing serial decoding on the code block by using L different search widths includes: determining N candidate search widths, where any two search widths of the N candidate search widths are different; The sequence number of the N candidate search widths, the code rate of the code block, the signal-to-noise ratio of the k-th code block, and the average decoding delay D a required by the code block, and L are determined from the N candidate search widths. The minimum search width L i among the different search widths.
  • the decoder can support the N types of search widths to decode the code blocks, and the N search widths can be referred to as N candidate search widths, and the N candidate search widths are all configured with sequence numbers, so the code is
  • the block decoding may be delayed according to the sequence number configured by the N candidate search widths, the code rate of the code block, the signal to noise ratio of the kth code block, and the average decoding delay of the code block requirement D a
  • the minimum search width L i of the L different search widths is determined from the N candidate search widths to ensure that the time decoded according to the L different search widths satisfies the average delay requirement of the code block.
  • L different search widths are determined by:
  • D a is the average decoding delay required by the code block
  • d 1 , d 2 , ..., d l-1 is a set of monotonically increasing integers greater than 0 and less than or equal to nj
  • R is the code rate of the code block
  • ⁇ For the signal to noise ratio of the code block, the search width L n is monotonically increasing, and the function D( ⁇ , ⁇ , ⁇ ) is the search width used. The sum of delays required for Ln to perform serial decoding.
  • the sequence number of the minimum search width L i is set to the jth, and the code block is serially decoded by using L different search widths, including: determining to invoke the jth according to the following function
  • the search width is decoded in parallel as the minimum search width L i of the L different search widths:
  • D a is the average decoding delay required by the code block
  • d 1 , d 2 , ..., d l-1 is a set of monotonically increasing integers greater than 0 and less than or equal to nj
  • R is the code rate of the code block
  • ⁇ For the signal to noise ratio of the code block, the search width L n is monotonically increasing, and the function D( ⁇ , ⁇ , ⁇ ) is the search width used. The sum of delays required for Ln to perform serial decoding.
  • M different from the N candidate search widths are selected.
  • the search width performs parallel decoding on the code block, wherein a minimum search width of the M different search widths is greater than a maximum search width of the L different search widths.
  • M different searches are selected from the N candidate search widths. Width Parallel decoding of code blocks, wherein a minimum search width among M different search widths is greater than a maximum search width among L different search widths.
  • the maximum search width of the L different search widths is used.
  • the large search width decodes the code block.
  • one or more search widths may be obtained from the one or more search widths.
  • the code block is decoded by selecting one or more search widths.
  • the method for decoding a polarization code decodes one or more code blocks in parallel by using L different search widths, and at least one candidate obtained according to the decoded in the parallel decoding.
  • the path determines the decoding path of the code block, so that the average decoding delay can be reduced while ensuring the same decoding error frame rate, and the average space complexity can be reduced when parallel decoding is performed on multiple code blocks. .
  • the decoding method of the polarization code is described in detail above with reference to the embodiment shown in FIG. 2.
  • the decoder for polarization code decoding will be described in detail below with reference to FIGS. 3 to 5.
  • the decoder includes:
  • the decoding module 310 is configured to perform parallel decoding on the code block by using L different search widths.
  • the determining module 320 is configured to determine a decoding path of the code block according to the at least one candidate path obtained by the decoding performed by the decoding module.
  • a code block having a code length S may correspond to a binary decoding code tree of an S layer.
  • SC coding can be described as a process of path search on the code tree.
  • the search path of SC decoding is one, that is, the search width of SC decoding is 1, and SCH decoding, SCL decoding, and SCS decoding are allowed to be reserved. Multiple candidate paths, that is, a larger search width can be selected to decode the code block, thereby expanding the search range and improving the decoding performance of the code block.
  • the code blocks in the decoding module 310 may be parallel coded by using L different search widths, and the code blocks may refer to a certain code block or some code blocks, that is, several code blocks may be used. At the same time, different search widths are used for parallel decoding.
  • the decoding candidate path is first obtained, so that the decoding path can be determined according to the candidate path that has been obtained. Output as a decoding result.
  • the method for decoding a polarization code decodes one or more code blocks in parallel by using L different search widths, and at least one candidate obtained according to the decoded in the parallel decoding.
  • the path determines the decoding path of the code block, so that the average decoding delay can be reduced while ensuring the same decoding error frame rate, and the average space complexity can be reduced when parallel decoding is performed on multiple code blocks. .
  • the decoding module 310 is configured to perform serial row decoding on the code block by using L different search widths; and the determining module 320 is configured to obtain, according to the decoding performed by the decoding module. At least one candidate path determines a decoding path of the code block.
  • the method for decoding a polarization code decodes a code block serially by using L different search widths, and determines at least one candidate path obtained according to the completed decoding in the serial decoding.
  • the decoding path of the code block can reduce the average decoding delay while ensuring the same decoding error frame rate, and can also reduce the decoding complexity.
  • the determining module further includes a check unit, where the check unit is configured to perform a redundant cyclic CRC check on the at least one candidate path obtained in the decoding of the code block.
  • the determining module 320 is specifically configured to determine a candidate path that passes the CRC check as a decoding path of the code block.
  • a certain candidate path can pass the CRC check to refer to the CRC of the candidate path sequence.
  • the checksum is all zeros.
  • the candidate path under the search width is obtained first, and the candidate path under the search width may be sequentially sorted according to the probability metric by the CRC check, first.
  • the path that can pass the CRC check is the decoding path of the code block.
  • the determining module 320 is specifically configured to: after determining the decoding path of the code block, stop decoding the uncompleted code block. That is to say, once the candidate path is successfully decoded by the CRC check, the decoder will stop all other decoding operations corresponding to the code block in progress, including the decoding operation and the CRC check operation, etc. And a resource for releasing the response, the resource including a resource required for buffering the code block, a decoding unit being decoded in the decoder, and a CRC check circuit.
  • the decoder when the code blocks obtained by decoding the L search widths respectively fail to pass the CRC check, it indicates that the L search width fails to decode the code block, and the decoder will Release L search widths for decoding required decoding resources, so that other code blocks use the decoding resources for decoding; if the L search widths already include the maximum search width that the decoder can support , indicating that the decoding fails to decode the code block.
  • the decoding module 310 is specifically configured to: determine N candidate search widths, where any two of the N candidate search widths are different; and the sequence configured according to the N candidate search widths The number, the code rate of the code block, the signal to noise ratio of the code block, and the average decoding delay D a required by the code block determine the minimum search width L i among the L different search widths from the N candidate search widths.
  • the decoder can support the N types of search widths to decode the code blocks, and the N search widths can be referred to as N candidate search widths, and the N candidate search widths are all configured with sequence numbers, so the code is
  • the block decoding may be delayed according to the sequence number configured by the N candidate search widths, the code rate of the code block, the signal to noise ratio of the kth code block, and the average decoding delay of the code block requirement D a
  • the minimum search width L i of the L different search widths is determined from the N candidate search widths to ensure that the time decoded according to the L different search widths satisfies the average delay requirement of the code block.
  • the sequence number of the decoding unit configuration having the minimum search width L i is the jth
  • the decoding module 310 is specifically configured to determine to call the jth search width as L according to the following function. Parallel decoding of code blocks by the minimum search width L i of different search widths:
  • D a is the average decoding delay required by the code block
  • d 1 , d 2 , . . . , d l-1 is a set of monotonically increasing integers greater than 0 and less than or equal to nj
  • R is the code rate of the code block
  • ⁇ is the signal to noise ratio of the code block
  • search width L n is monotonically increasing
  • D( ⁇ , ⁇ , ⁇ ) is the search width used. The sum of delays required for Ln to perform serial decoding.
  • the sequence number of the decoding unit configuration having the minimum search width L i is the jth
  • the decoding module 310 is specifically configured to determine to call the jth search width as L according to the following function.
  • the code block is serially decoded with a minimum search width L i of different search widths:
  • D a is the average decoding delay required by the code block
  • d 1 , d 2 , . . . , d l-1 is a set of monotonically increasing integers greater than 0 and less than or equal to nj
  • R is the code rate of the code block
  • ⁇ is the signal to noise ratio of the code block
  • search width L n is monotonically increasing
  • D( ⁇ , ⁇ , ⁇ ) is the search width used. The sum of delays required for Ln to perform serial decoding.
  • the decoding module 310 is further configured to: if the candidate path obtained by performing parallel decoding on the code block by using L different search widths, the candidate path cannot pass the CRC check, and the N candidate search is performed.
  • the code blocks are parallel decoded by selecting M different search widths in the width, wherein the minimum search width among the M different search widths is greater than the maximum search width among the L different search widths.
  • the decoding module 310 is further configured to: if the candidate path obtained by serially decoding the code block by using L different search widths, the candidate path cannot pass the CRC check, and the N candidate The code blocks are serially decoded by selecting M different search widths in the search width, wherein the minimum search width among the M different search widths is greater than the largest search width among the L different search widths.
  • the decoding module 310 is specifically configured to use the ratio L differently.
  • the search width with a large search width in the search width decodes the code block.
  • one or more search widths may be obtained from the one or more search widths.
  • the code block is decoded by selecting one or more search widths.
  • the method for decoding a polarization code decodes a code block in parallel by using L different search widths, and determines a code block according to at least one candidate path obtained by decoding in the parallel decoding. Decoding path, so it can be reduced while ensuring the same decoding frame error rate The small average decoding delay and the flat space complexity are reduced.
  • FIG. 4 is a block diagram showing the structure of a decoder for a polarization code of another embodiment, the decoder 400 comprising:
  • the decoding unit pool 410 includes a plurality of coding units, and the first coding unit and the second decoding unit of the plurality of coding units have different search widths.
  • the control unit 420 is configured to call the L coding units of the plurality of coding units to perform parallel coding on the code blocks, where any two of the L coding units have different search widths.
  • the verifying unit 430 is configured to determine a decoding path of the code block according to the at least one candidate path obtained by the decoding of the decoding unit pool.
  • a code block having a code length S may correspond to a binary decoding code tree of an S layer.
  • SC coding can be described as a process of path search on the code tree.
  • the search path of SC decoding is one, that is, the search width of SC decoding is 1, and SCH decoding, SCL decoding, and SCS decoding are allowed to be reserved.
  • Multiple candidate paths, that is, a larger search width can be selected to decode the code block, thereby expanding the search range and improving the decoding performance of the code block.
  • code blocks in the coding unit pool 410 may be parallel coded by using L different search widths, and the code blocks may refer to a certain code block or a certain code block, that is, several code blocks. Parallel decoding can be performed with different search widths at the same time.
  • decoding units having the same search width constitute one decoding group, that is, the decoding units in a certain decoding group have the same search width, and different decoding groups are decoded.
  • the search width of the unit is not the same.
  • the first coding unit may include one or more coding units
  • the second coding unit may include one or more coding units, and the meanings of the first coding unit and the second coding unit having different search widths are There are at least two decoding units in the decoding unit pool, and the search widths between the two decoding units are different.
  • control unit 420 is configured to schedule L coding units to perform parallel coding on the code blocks, that is, the working time of the two decoding units in the decoding unit pool partially or completely coincide.
  • the method for decoding a polarization code decodes a code block in parallel by using L different search widths, and determines a code block according to at least one candidate path obtained by decoding in the parallel decoding.
  • the decoding path can reduce the average decoding delay and reduce the average space complexity while ensuring the same decoding frame error rate.
  • a control unit 420 is configured to be used by the control unit 420.
  • the L coding units in the plurality of coding units are called to perform parallel decoding on the code blocks.
  • the control unit may call the decoding unit with the same search width in the decoding unit pool to perform parallel decoding on different code blocks. That is to say, the parallel decoding may mean that one code block is decoded by using a decoding unit having a different search width, or that a plurality of code blocks are decoded by using multiple decodings of the same search width.
  • the verification unit 430 is specifically configured to perform, in sequence, the redundancy loop check on the at least one candidate path obtained by the completed decoding; the control unit is specifically configured to use the at least one candidate path.
  • the candidate path through the CRC check is determined as the decoding path of the code block.
  • control unit 430 is specifically configured to: after determining the decoding path of the code block, control the decoding unit pool to stop decoding the incomplete block of the code block.
  • control unit 430 is specifically configured to: according to a sequence number configured by multiple coding units, a code rate of the code block, a signal to noise ratio of the code block, and the code The block requires an average coding delay D a from which the coding unit having the smallest search width L i among the L coding units is determined.
  • the sequence number configured by the coding unit having the minimum search width L i is the jth
  • the control unit 430 is specifically configured to determine the jth decoding unit according to the following function:
  • the jth decoding unit is a decoding unit having a minimum search width L i among the L decoding units, and D a is an average decoding delay required by the code block, d 1 , d 2 , . . . , d L-1 is a set of monotonically increasing integers greater than 0 and less than or equal to nj, R is the code rate of the code block, ⁇ is the signal to noise ratio of the code block, and the search width L n is monotonically increasing, and the function D( ⁇ , ⁇ , ⁇ ) is the search width used.
  • control unit 420 is specifically configured to: if the candidate path obtained by performing parallel decoding on the code block by using L coding units is unable to pass the CRC check, multiple translations are performed. Selecting M coding units in the code unit to perform parallel decoding on the code block, wherein a search width of any two of the M coding units is different, and a minimum search width among the M different search widths is greater than the L The maximum search width among different search widths.
  • the decoder 400 further includes a buffer unit 440, configured to cache the code block according to the control of the control unit 410.
  • a buffer unit 440 configured to cache the code block according to the control of the control unit 410.
  • different code block information can be cached in different logical units.
  • the decoder 400 further includes:
  • a first multiplexing unit 450 configured to send the code block into the L decoding units in the decoding unit pool according to the control of the control unit;
  • a second multiplexing unit 460 configured to send at least one candidate path of the code block obtained by the decoding pool into the verification unit according to control of the control unit.
  • the method for decoding a polarization code decodes a code block in parallel by using L different search widths, and determines a code block according to at least one candidate path obtained by decoding in the parallel decoding.
  • the decoding path can therefore reduce the average decoding delay while guaranteeing the same decoding frame error rate.
  • Fig. 5 is a schematic block diagram showing the structure of a decoder of another embodiment of the present invention.
  • the decoder includes a buffer 510, a decoding unit pool 520, a CRC check circuit 530, a control unit 540, and a multiplexing unit 550.
  • the decoding unit pool has n sets of decoding units, and the search width of the decoding units in each group is the same, and the search widths of the decoding units in different groups are different.
  • the search width of each group of decoding units is L 1 , L 2 , . . . , L n , respectively, without loss of generality, assuming that L 1 ⁇ L 2 ⁇ ... ⁇ L n , each group containing a decoding unit
  • the numbers are m 1 , m 2 , . . . , m n , and satisfy m 1 +m 2 +...+m n ⁇ M; the number of buffers, CRC check circuits, and multiplexing units in each group are not less than M.
  • each group of coding units in the coding unit pool may be composed of one or more of SC and enhanced SC coding units (including SCL, SCS or SCH decoding).
  • the search unit with a search width of 1 can be directly equivalent to SC decoding.
  • the received signals of the respective code blocks received from the channel are respectively stored in different logic units in one buffer; the control unit multiplexes the channel received signals of the kth code block for the code block pair decoding delay requirement
  • the unit is sent to one or more decoding units of different search widths for decoding, k ⁇ ⁇ 1, 2, ..., M ⁇ ; each coding unit having a search width of L i , i ⁇ ⁇ 1, 2,...,n ⁇ , according to their probability metrics, output L i candidate paths in order from large to small, and send them to a CRC check circuit through the multiplex unit to perform CRC in sequence under the scheduling of the control unit. check:
  • the sequence is output as the decoding of the kth code block. Sequence, decoding is successful and the message is fed back to the control unit;
  • the control unit After receiving the decoding success message, the control unit stops all other ongoing decoding operations (including decoding operations, CRC check operations, etc.) corresponding to the code block, and resets and releases the corresponding resources (cache, all) a scheduled decoding unit, a CRC check circuit, etc.); after receiving the decoding failure message, the control unit resets and releases the decoding resource that has declared the decoding failure (decoding unit and CRC check circuit that failed) And wait for a feedback message from other coding units that are decoding the code block.
  • the control unit After receiving the decoding success message, the control unit stops all other ongoing decoding operations (including decoding operations, CRC check operations, etc.) corresponding to the code block, and resets and releases the corresponding resources (cache, all) a scheduled decoding unit, a CRC check circuit, etc.); after receiving the decoding failure message, the control unit resets and releases the decoding resource that has declared the decoding failure (decoding unit and CRC check circuit that failed) And wait for a feedback message from
  • the decoding of the code block fails; otherwise
  • the control unit re-codes the code block according to scheduling one or more coding units, and satisfies: the smallest search width in the re-scheduled coding unit is greater than the maximum search width in the decoding unit that failed the previous announcement. .
  • the strategy for the control unit to schedule the decoding unit is as follows:
  • (1) Number of scheduling decoders: If a certain code block does not require a high decoding delay, the control unit attempts to schedule a decoding unit from the i 1th group, and each time one decoding unit is scheduled Attempting to decode; otherwise, the control unit selects one set of decoding units (2 ⁇ l ⁇ n) at a time, and each of the decoding units is scheduled to decode the code block at the same time;
  • the decoder simultaneously decodes m code blocks of length N, the m code blocks have no requirement for decoding delay, and there is no expected FER estimation.
  • the decoder shown in Table 1 supports M code blocks for simultaneous decoding, M ⁇ m, the decoding unit pool contains n groups of decoding units, and the decoder types in the decoder pool are all SCL, different searches Width and number
  • the quantity configuration is shown in Table 1.
  • the m code blocks are respectively sent to m decoding units with a search width of L 1 for decoding, and the decoding result is output if the CRC check is performed; otherwise, the code block that is not correctly decoded is switched to the search width.
  • the decoding unit of L 2 performs decoding, and so on, until a candidate sequence can pass the CRC check, then declares that the code block is successfully decoded and outputs the first candidate sequence that can pass the CRC check; if the search width If the decoding unit of L n cannot successfully decode it, it declares that the decoding of the code block fails.
  • the maximum decoding delay of the code block is The average delay is:
  • D l represents the decoding delay of the SCL decoder with a search width of L l ; and it is noted that for any 2 ⁇ l ⁇ n, Even if the smaller search width L l-1 can be correctly decoded, the larger L l can also be correctly decoded; conversely, when the larger L l decoding fails, the smaller L l-1 is used. The decoding will also fail.
  • the decoder configured as shown in Table 1 has a total space complexity of O(nmN).
  • the search width is L n for each of the m code blocks
  • the spatial complexity is O(L n mN).
  • the space complexity required by the inventive scheme is only 18.75% of the latter, but as shown in Fig. 6, the inventive scheme has no loss in FER performance.
  • the average computational complexity is much smaller than the traditional CASCL scheme, and it continues to decrease as the signal-to-noise ratio increases, as shown in Figure 7.
  • the configuration of the decoder is as shown in Table 2.
  • the decoder supports M code blocks to be simultaneously decoded, M ⁇ 1, and the decoding unit pool includes n groups of decoding units.
  • the decoder types in the decoder pool are all SCL, and the search width and number configuration of each group of decoders are shown in Table 2.
  • the steps for decoding a code block having a higher requirement for decoding delay by using the decoder are as follows:
  • the control unit calls one decoding unit from each of the n groups of decoding units, and a total of n decoding units having different search widths simultaneously decode the code block.
  • the average decoding delay of the code block is:
  • the decoder is configured as shown in Table 3.
  • the decoding structure is configured to include only two sets of decoding units, and the decoder types in the decoder pool are all SCL. The decoder simultaneously decodes m code blocks of length N, wherein m' code blocks have higher delay requirements, and the remaining mm' code blocks have no delay requirement;
  • the decoding unit (actually the SC decoding unit) performs decoding. If the candidate sequence obtained by the decoding fails the CRC check, it attempts to use the SCL with a search width of 32; if the search width is 32, the SCL translation If there is no sequence in the candidate sequence output by the code unit that can pass the CRC check, the decoding failure is declared;
  • one decoding unit is called from each of the two groups, and two decoding units having search widths of 1 and 32 are used at the same time (one The SC decoding unit and an SCL (32) decoding unit) decode the code block. If the SC decoding is successful (the result can pass the CRC check), the decoding is not required to wait for the end of the decoding of the SCL (32). The decoding sequence stops and releases the SCL (32) decoding unit.
  • the method for decoding a polarization code decodes a code block in parallel by using L different search widths, and determines a code block according to at least one candidate path obtained by decoding in the parallel decoding.
  • the decoding path can reduce the average decoding delay and reduce the average space complexity while ensuring the same decoding frame error rate.
  • Figure 7 is a schematic block diagram of an apparatus in accordance with another embodiment of the present invention.
  • the apparatus 20 of FIG. 6 can be used to implement the steps and methods of the above method embodiments.
  • the device 20 is applicable to base stations or terminals in various communication systems. In the embodiment of FIG.
  • the apparatus 20 includes a transmitting circuit 202, a receiving circuit 203, a decoding processor 204, a processing unit 205, a memory 206, and an antenna 201.
  • Processing unit 205 controls the operation of device 20 and is operable to process signals.
  • the processing unit 205 may also be referred to as a Central Processing Unit ("CPU").
  • Memory 206 can include read only memory and random access memory and provides instructions and data to processing unit 205. A portion of memory 206 may also include non-volatile line random access memory (NVRAM).
  • NVRAM non-volatile line random access memory
  • device 20 may be embedded or may itself be a wireless communication device such as a mobile telephone, and may also include a carrier that houses transmit circuitry 202 and receive circuitry 203 to allow for data transmission between device 20 and a remote location. receive. Transmit circuitry 202 and receive circuitry 203 may be coupled to antenna 201.
  • the various components of device 20 are coupled together by a bus system 209, which in addition to the data bus includes a power bus, a control bus, and a status signal bus. However, for clarity of description, various buses are labeled as bus system 209 in the figure.
  • Decoding processor 204 may be an integrated circuit chip with signal processing capabilities. In an implementation process, the steps of the above method may be completed by an integrated logic circuit of the hardware in the decoding processor 204 or an instruction in the form of software. These instructions can pass through the processing unit 205 to achieve and control.
  • the above decoding processor may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable Logic devices, discrete gates or transistor logic devices, discrete hardware components.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA off-the-shelf programmable gate array
  • the general purpose processor may be a microprocessor or the processor or any conventional processor, decoder or the like.
  • the steps of the method disclosed in the embodiments of the present invention may be directly implemented by the hardware decoding processor, or may be performed by a combination of hardware and software modules in the decoding processor.
  • the software module can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the storage medium is located in memory 206, and decoding processor 204 reads the information in memory 206 and, in conjunction with its hardware, performs the steps of the above method.
  • memory 206 may store instructions that cause decoding processor 204 or processing unit 205 to perform parallel decoding of code blocks using L different search widths; obtained from decoded in parallel decoding At least one candidate path determines a decoding path of the code block.
  • the method for decoding a polarization code decodes a code block in parallel by using L different search widths, and determines a code block according to at least one candidate path obtained by decoding in the parallel decoding.
  • the decoding path can reduce the average decoding delay and reduce the average space complexity while ensuring the same decoding frame error rate.
  • system and “network” are used interchangeably herein. It should be understood that the term “and/or” herein is merely an association relationship describing an associated object, indicating that there may be three relationships, for example, A and/or B, which may indicate that A exists separately, and A and B exist simultaneously. There are three cases of B alone. In addition, the character "/" in this article generally indicates that the contextual object is an "or" relationship.
  • B corresponding to A means that B is associated with A, and B can be determined from A.
  • determining B from A does not mean that B is only determined based on A, and that B can also be determined based on A and/or other information.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • An integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, can be stored in a computer readable storage medium.
  • the technical solution of the present invention or the part contributing to the prior art, or the part of the technical solution, may be embodied in the form of a software product stored in a storage medium.
  • a number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a USB flash drive, a mobile hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a disk or a CD.
  • ROM Read-Only Memory
  • RAM Random Access Memory

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Abstract

本发明实施例提供了一种极化码的译码方法和译码器，该译码方法包括：采用L个不同搜索宽度对码块进行并行译码；根据并行译码中已完成的译码所获得的至少一个候选路径，确定码块的译码路径。该译码器包括：译码模块，该译码模块采用L个不同搜索宽度对码块进行并行译码；确定模块，该确定模块用于根据译码模块已完成的译码所获得的至少一个候选路径，确定所述码块的译码路径。本发明实施提供的方法对码块进行不同的搜索宽度并行译码，能够使得码块的平均时延降低。

Description

极化码的译码器和译码方法 技术领域
本发明实施例涉及编解码领域，并且更具体地，涉及极化Polar码的译码方法和译码器。
背景技术
通信系统通常采用信道编码提高数据传输的可靠性，以保证通信的质量。Polar码是第一个理论上证明可以取得香农极限且具有低编译码复杂度的纠错编码方法。最新研究表明，基于串行抵消译码(英文：Successive Cancellation decoding，简写：SC)算法改进得到的串行抵消列表译码(英文：Successive Cancellation List decoding，简写：SCL)、串行抵消堆栈译码(英文：Successive Cancellation Stack decoding，简写：SCS)、串行抵消混合译码(Successive Cancellation Hybrid decoding，简写：SCH)能够显著提高Polar码的误帧率(英文：Frame Error Rate，简写：FER)性能，这类算法统称为增强SC译码算法。并且，在循环冗余校验(英文：Cyclic Redundancy Check，简写：CRC)辅助的增强SC译码算法下，Polar码能够优于低密度奇偶校验(英文：Low-Density Parity-Check，简写：LDPC)码或Turbo码的FER性能。
一个码长为N的码可以对应于一个由N层边构成的二叉译码码树，SC译码能够被描述为在该码树上的路径搜索过程，其译码的复杂度为O(Nlog2N)。SC译码在码长N很长的情况下能够取得好的性能，逼近香农极限，然而在有限码长配置下，Polar码通过SC译码获得的FER性能不理想。增强的SC译码允许在二叉译码码树上保留多条(SC译码仅仅保留一条)候选路径，该候选路径的数量即为搜索宽度，由此可以扩大搜索的范围，减小在搜索过程中离开正确路径的概率，以增强FER性能，进一步地，使用CRC辅助的增强SC译码方法能够从该多条候选路径集合中选择具有最大概率且能够通过CRC校验的一条路径作为译码输出。
由上所述，为了保证FER性能，增强SC译码算法的搜索宽度需要设定为一个较大的值，从而导致译码复杂度较高、译码时延较大。同时，在数字用户线路(英文：Digital Subscriber Line，简写：DSL)、多点协作传输(英 文：Coordinated Multiple Points，简写：CoMP)上行链路等通信系统中，中心站需要同时对接入多个用户的数据进行译码操作，若每一个码块独占一个译码器，则需要对每一码块都实现一个具有很大搜索宽度的译码器，使得整体译码复杂度非常大，译码时延也会较大。
发明内容
本发明提供了一种极化码的译码方法和译码器，能够减小Polar译码的平均译码时延并降低平均的空间复杂度。
第一方法，提供了一种极化码的译码方法，包括：采用L个不同搜索宽度对码块进行并行译码；根据所述并行译码中已完成的译码所获得的至少一个候选路径，确定所述码块的译码路径。
结合第一方面，在第一方面的第一种可能的实现方式中，所述根据所述并行译码中已经完成的译码所获得的至少一个候选路径，确定所述码块的译码路径，包括：将所述已完成的译码所获得的至少一个候选路径依次进行冗余循环CRC校验；将所述至少一个候选路径中通过所述CRC校验的候选路径确定为所述码块的译码路径。
结合第一方面或第一方面的第一种可能的实现方式，在第一方面的第二种可能的实现方式中，所述方法还包括：当确定所述码块的译码路径后，停止对所述并行译码中未完成的译码。
结合第一方面或第一方面的第一或第二种可能的实现方式，在第一方面的第三种可能的实现方式中，所述采用不同搜索宽度对码块进行并行译码，包括：确定N个候选搜索宽度，所述N个候选搜索宽度中任意两个搜索宽度不同；根据所述N个候选搜索宽度的编号、所述码块的码率、所述码块的信噪比和所述码块要求的平均译码时延Da，从所述N个候选搜索宽度中确定所述L个不同搜索宽度。
结合第一方面的第三种可能的实现方式，在第一方面的第四种可能的实现方式中，所述L个不同搜索宽度由下式确定：
Figure PCTCN2015078011-appb-000001
其中，Da为所述码块要求的平均译码时延，d1,d2,…,dl-1为一组大于0小于等于n-j的单调递增的整数，R为所述码块的码率，γ为所述码块的信噪比，搜索宽度
Figure PCTCN2015078011-appb-000002
Ln单调递增，函数D(·,·,·)为使用所述搜索宽度为
Figure PCTCN2015078011-appb-000003
Ln进行串行 译码所需要的时延总和。
结合第一方面的第三或第四种可能的实现方式，在第一方面的第五种可能的实现方式中，所述方法还包括：若采用所述L个不同搜索宽度对所述码块进行并行译码所得到的候选路径均不能通过所述CRC校验，从所述N个候选搜索宽度中选择M个不同搜索宽度对所述码块进行并行译码，其中，所述M个不同搜索宽度中的最小搜索宽度大于所述L个不同搜索宽度中的最大搜索宽度。
第二方面，提供了一种极化码的译码器，包括：译码模块，所述译码模块采用L个不同搜索宽度对码块进行并行译码；确定模块，所述确定模块用于根据所述译码模块已完成的译码所获得的至少一个候选路径，确定所述码块的译码路径。
结合第二方面，在第二方面的第一种可能的实现方式中，所述确定模块还包括校验单元，所述校验单元用于将所述码块已完成的译码中所获得的至少一个候选路径依次进行冗余循环CRC校验；所述确定模块具体用于将所述至少一个候选路径中通过所述CRC校验的候选路径确定为所述码块的译码路径。
结合第二方面或第二方面的第一种可能的实现方式，在第二方面的第二种可能的实现方式中，所述确定模块具体用于：当确定所述码块的译码路径后，停止对所述并行一码中码块未完成的译码。
结合第二方面或第二方面的第第一或第二种可能的实现方式，在第二方面的第三种可能的实现方式中，所述译码模块具体用于：确定N个候选搜索宽度，所述N个候选搜索宽度中任意两个搜索宽度不同；根据所述N个候选搜索宽度所配置的序列编号、所述码块的码率、所述码块的信噪比和所述码块要求的平均译码时延Da，从所述N个候选搜索宽度中确定所述L个不同搜索宽度中的最小搜索宽度Li。
结合第二方面的的第三种可能的实现方式，在第二方面的第四种可能的实现方式中，所述译码模块具体用于：根据以下函数确定调用所述L个不同搜索宽度对所述码块进行并行译码：
Figure PCTCN2015078011-appb-000004
其中，第Da为所述码块要求的平均译码时延，d1,d2,…,dl-1为一组大于0小于等于n-j的单调递增的整数，R为所述码块的码率，γ为所述码块的信噪比，搜索宽度
Figure PCTCN2015078011-appb-000005
Ln单调递增，函数D(·,·,·)为使用所述搜索宽度 为
Figure PCTCN2015078011-appb-000006
Ln进行串行译码所需要的时延总和。
结合第二方面的第三或第四种可能的实现方式，在第二方面的第五种可能的实现方式中，所述译码模块还用于：若采用所述L个不同搜索宽度对所述码块进行并行译码所得到的候选路径均不能通过所述CRC校验，从所述N个候选搜索宽度中选择M个不同搜索宽度对所述码块进行并行译码，其中，所述M个不同搜索宽度中的最小搜索宽度大于所述L个不同搜索宽度中的最大搜索宽度。
第三方面，提供了一种极化码的译码器，包括：译码单元池，所述译码单元池包括多个译码单元，所述多个译码单元中的第一译码单元和第二译码单元具有不同的搜索宽度；控制单元，所述控制单元用于调用所述多个译码单元中的L个译码单元对码块进行并行译码，所述L个译码单元中任意两个译码单元具有不同的搜索宽度；校验单元，所述校验单元用于根据所述译码单元池已完成的译码所获得到的至少一个候选路径，确定所述码块的译码路径。
结合第三方面，在第三方面的第一种可能的实现方式中，所述校验单元具体用于将所述已完成的译码所获得的至少一个候选路径依次进行冗余循环校验；所述控制单元具体用于将所述至少一个候选路径中通过所述CRC校验的候选路径确定为所述码块的译码路径。
结合第三方面或第三方面的第一种可能的实现方式，在第三方面的第二种可能的实现方式中，所述控制单元具体用于：当确定所述码块的译码路径后，控制所述译码单元池停止对所述并行译码中未完成的译码。
结合第三方面或第三方面的第一或第二种可能的实现方式，在第三方面的第三种可能的实现方式中，所述控制单元具体用于：根据所述多个译码单元的编号。所述码块的码率、所述码块的信噪比和所述码块要求的平均译码时延Da，从所述多个译码单元中确定所述L个译码单元。
结合第三方面的第三种可能的实现方式，在第三方面的第四种可能的实现方式中，所述控制单元具体用于：根据以下函数确定所述L个译码单元：
Figure PCTCN2015078011-appb-000007
其中，所述第j个译码单元为所述L个译码单元中具有最小搜索宽度Li的译码单元，Da为所述码块要求的平均译码时延，d1,d2,…,dl-1为一组大于0小于等于n-j的单调递增的整数，R为所述码块的码率，γ为所述码块的信噪比，搜索宽度
Figure PCTCN2015078011-appb-000008
Ln单 调递增，函数D(·,·,·)为使用所述搜索宽度为
Figure PCTCN2015078011-appb-000009
Ln进行串行译码所需要的时延总和。
结合第三方面的第三或第四种可能的实现方式，在第三方面的第五种可能的实现方式中，所述控制单元具体用于：若采用所述L个译码单元对所述码块进行并行译码所得到的候选路径均不能通过所述CRC校验，从所述多个译码单元中选择M个译码单元对所述码块进行并行译码，其中，所述M个译码单元中任意两个译码单元的搜索宽度不同，所述M个不同搜索宽度中的最小搜索宽度大于所述L个不同搜索宽度中的最大搜索宽度。
结合第三方面或第三方面的第一至第五种可能的实现方式，在第三方面的第六种可能的实现方式中，所述译码器还包括缓存单元，所述缓存单元用于根据所述控制单元的控制缓存所述码块。
结合第三方面或第三方面的第一至第六种可能的实现方式，所述译码器还包括：第一多路复用单元，所述第一多路复用单元用于根据所述控制单元的控制将所述码块送入所述译码单元池中的L个译码单元中；第二多路复用单元，所述第二多路复用单元用于根据所述控制单元的控制将所述译码池获得的所述码块的至少一个候选路径送入所述校验单元中。
因此，本发明实施例的极化码的译码方法通过采用L个不同搜索宽度对一个或多个码块并行译码，并根据该并行译码中已完成的译码所获得的至少一个候选路径确定码块的译码路径，因此可以在保证相同译码误帧率的情况下，能够减小平均译码时延，在对多个码块进行并行译码时，能够降低平均空间复杂度。
附图说明
图1示出了根据本文所述的各个实施例的无线通信系统。
图2是本发明实施例的极化码的译码方法的示意性流程图。
图3是本发明实施例的极化码的译码器的示意性框图。
图4是本发明另一实施例的极化码的译码器的示意性框图。
图5是本发明另一实施例的极化码的译码器的示意性框图。
图6是本发明实施例的译码方法与现有技术的译码方法在FER性能上的比较的示意图。
图7是本发明实施例的译码方法与现有技术的译码方法在平均计算复杂 度上的比较的示意图。
图8是本发明另一实施例的极化码的译码器的示意性框图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有付出创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例可应用于各种通信系统，因此，下面的描述不限制于特定通信系统。全球移动通讯(Global System of Mobile communication，简称“GSM”)系统、码分多址(Code Division Multiple Access，简称“CDMA”)系统、宽带码分多址(Wideband Code Division Multiple Access，简称“WCDMA”)系统、通用分组无线业务(General Packet Radio Service，简称“GPRS”)、长期演进(Long Term Evolution，简称“LTE”)系统、LTE频分双工(Frequency Division Duplex，简称“FDD”)系统、LTE时分双工(Time Division Duplex，简称“TDD”)、通用移动通信系统(Universal Mobile Telecommunication System，简称“UMTS”)等。在上述的系统中的基站或者终端使用传统Turbo码、LDPC码编码处理的信息或者数据都可以使用本实施例中的极化码编码。
图1示出了根据本文所述的各个实施例的无线通信系统100。系统100包括基站102，后者可包括多个天线组。例如，一个天线组可包括天线104和106，另一个天线组可包括天线108和110，附加组可包括天线112和114。对于每个天线组示出了2个天线，然而可对于每个组使用更多或更少的天线。基站102可附加地包括发射机链和接收机链，本领域普通技术人员可以理解，它们均可包括与信号发送和接收相关的多个部件(例如处理器、调制器、复用器、解调器、解复用器或天线等)。
基站102可以与一个或多个接入终端(例如接入终端116和接入终端122)通信。然而，可以理解，基站102可以与类似于接入终端116和122的基本上任意数目的接入终端通信。接入终端116和122可以是例如蜂窝电话、智能电话、便携式电脑、手持通信设备、手持计算设备、卫星无线电装置、全球定位系统、PDA和/或用于在无线通信系统100上通信的任意其它 适合设备。如图所示，接入终端116与天线112和114通信，其中天线112和114通过前向链路118向接入终端116发送信息，并通过反向链路120从接入终端116接收信息。此外，接入终端122与天线104和106通信，其中天线104和106通过前向链路124向接入终端122发送信息，并通过反向链路126从接入终端122接收信息。在频分双工(Frequency Division Duplex，简称为“FDD”)系统中，例如，前向链路118可利用与反向链路120所使用的不同频带，前向链路124可利用与反向链路126所使用的不同频带。此外，在时分双工(Time Division Duplex，简称为“TDD”)系统中，前向链路118和反向链路120可使用共同频带，前向链路124和反向链路126可使用共同频带。
被设计用于通信的每组天线和/或区域称为基站102的扇区。例如，可将天线组设计为与基站102覆盖区域的扇区中的接入终端通信。在通过前向链路118和124的通信中，基站102的发射天线可利用波束成形来改善针对接入终端116和122的前向链路118和124的信噪比。此外，与基站通过单个天线向它所有的接入终端发送相比，在基站102利用波束成形向相关覆盖区域中随机分散的接入终端116和122发送时，相邻小区中的移动设备会受到较少的干扰。
在给定时间，基站102、接入终端116和/或接入终端122可以是发送无线通信装置和/或接收无线通信装置。当发送数据时，发送无线通信装置可对数据进行编码以用于传输。具体地，发送无线通信装置可具有(例如生成、获得、在存储器中保存等)要通过信道发送至接收无线通信装置的一定数目的信息比特。这种信息比特可包含在数据的传输块(或多个传输块)中，其可被分段以产生多个码块。此外，发送无线通信装置可使用极化码编码器(未示出)来对每个码块编码，以提高数据传输的可靠性，进而保证通信质量。
对于串行抵消列表SCL译码，所有的候选路径与其对应的路径度量值都被存储在一个列表中。列表中所有的候选路径被同步地扩展，所以每次扩展之后，列表中候选路径数量就会翻倍。丢弃那可靠性度量值较小的部分候选路径，以保证候选路径数始终不大于列表大小的一半。在译码结束时，从列表中找出可靠性度量值最大的那条路径，其对应的比特估计序列即为译码结果。
对于串行抵消堆栈译码SCS译码使用一个有序堆栈，而不是列表，去存 储候选路径。SCS译码过程中，每次都只基于可靠性度量最大的那一条候选路径(位于堆栈的栈顶)进行扩展。当出现栈顶路径到达码树的某一个叶子节点时，停止译码过程，并且将该路径所对应的比特估计序列输出，作为译码结果。
SCL译码可以看作是在码树上做广度优先搜索，而SCS译码则是在码树上做最佳优先搜索。SCL译码允许较低的空间复杂度，而SCS译码的计算复杂度较低。将两种模式混合，即为SCH译码。SCH译码的实现机构类似SCS译码，也使用一个有序堆栈存储候选路径。所不同的是，SCH的堆栈深度远远小于SCS译码，并且通过灵活地在两种模式下切换，使得候选路径数始终不会使堆栈溢出。SCH译码的计算复杂度稍高于SCS译码、远小于SCL译码；空间复杂度稍高于SCL译码远小于SCS译码。
无论是何种实现方式，增强SC译码的本质就是搜索得到一组具有较大路径度量值的候选路径集合，并从中选择路径度量值最大的一条作为译码输出。
如果信息块包含了循环冗余校验信息，即信息块序列的CRC结果为全零序列，那么就可以使用CRC辅助的增强SC译码算法进行译码，即从最终得到的候选路径集合中选择具有最大路径度量值且能够通过CRC校验的一条候选路径作为译码输出。同样地，根据在码树上的搜索策略不同，有CASCL、CASCS以及CASCH三种实现方法。采用这类译码方法时，有限码长极化码的抗噪性能可以得到很大幅度的提高，并且能够显著优于现广泛应用于各通信系统的LDPC码与Turbo码。
图2是本发明实施例的一种极化码的译码方法的示意性流程图，该方法200有译码器执行。如图2，该方法200包括：
步骤210，采用L个不同搜索宽度对码块进行并行译码；
步骤220，根据并行译码中已完成的译码所获得的至少一个候选路径，确定码块的译码路径。
具体而言，一个码长为S的码块可以对应于一个S层的二叉译码码树。SC译码可以描述为在该码树上路径搜索的过程，SC译码的搜索路径为1条，即SC译码的搜索宽度为1，而SCH译码、SCL译码和SCS译码允许保留多条候选路径，即可以选择更大的搜索宽度对码块进行译码，以此扩大搜索范围，提高码块的译码性能。应理解，在步骤210中的码块可以采用L个不同 搜索宽度进行并行译码，该码块可以指某一码块也可以指某几个码块，也就是说几个码块可以同时采用不同的搜索宽度进行并行译码。
在步骤220中，具体地，对码块进行不同搜索宽度并行译码的时候，码块的搜索宽度较小时将首先获得译码候选路径，因此可以根据已经获得到的候选路径确定译码路径，作为译码结果输出。
因此，本发明实施例的极化码的译码方法通过采用L个不同搜索宽度对一个或多个码块并行译码，并根据该并行译码中已完成的译码所获得的至少一个候选路径确定码块的译码路径，因此可以在保证相同译码误帧率的情况下，能够减小平均译码时延，在对多个码块进行并行译码时，能够降低平均空间复杂度。
可选地，作为本发明一个实施例，可以选择L个不同搜索宽度对码块进行串行译码；根据串行译码中已完成的译码所获得的至少一个候选路径，确定码块的译码路径。具体地，码块依次从小到大调用这L个不同搜索宽度进行串行译码。
因此，本发明实施例的极化码的译码方法通过采用L个不同搜索宽度对码块串行译码，并根据该串行译码中已完成的译码所获得的至少一个候选路径确定码块的译码路径，因此可以在保证相同译码误帧率的情况下减小平均译码时延，还能够降低译码的复杂度。
可选地，作为本发明一个实施例，根据并行译码中已经完成的译码所获得的至少一个候选路径，确定码块的译码路径，包括：将已完成的译码所获得的至少一个候选路径依次进行冗余循环CRC校验；将所述至少一个候选路径中通过CRC校验的候选路径确定为码块的译码路径。
应理解，某个候选路径能够通过CRC校验是指该候选路径序列的CRC校验和为全零。
具体地，码块采用较小的搜索宽度时将较先获得该搜索宽度下的候选路径，可以将该搜索宽度下的候选路径按照概率度量从大到小排序依次通过上述CRC校验，第一个能够通过CRC校验的路径即为该码块的译码路径。
可选地，作为本发明一个实施例，当确定码块的译码路径后，停止对所述并行译码中未完成的译码。也就是说，一旦有候选路径通过CRC校验即译码成功，译码器将停止所有其它对应于该码块正在进行中的译码操作，包括译码操作和CRC校验操作等，并重置以及释放响应的资源，该资源包括 缓存码块所需要的资源、译码器中正在译码的译码单元以及CRC校验电路等。
具体地，当码块分别采用L个搜索宽度进行译码后所获得到的译码路径均不能通过CRC校验，则表明采用该L个搜索宽度对码块进行译码失败，译码器将释放L个搜索宽度进行译码所需的译码资源，以便于其它码块利用该些译码资源进行译码；如果该L个搜索宽度中已经包含该译码器所能支持的最大搜索宽度，则表明该译码对码块的译码失败。
可选地，作为本发明一个实施例，采用L个不同搜索宽度对码块进行并行译码，包括：确定N个候选搜索宽度，该N个候选搜索宽度中任意两个搜索宽度不同；根据该N个候选搜索宽度所配置的序列编号、码块的码率、第k个码块的信噪比和码块要求的平均译码时延Da，从N个候选搜索宽度中确定L个不同搜索宽度。
可选地，作为本发明一个实施例，采用L个不同搜索宽度对码块进行串行译码，包括：确定N个候选搜索宽度，该N个候选搜索宽度中任意两个搜索宽度不同；根据该N个候选搜索宽度所配置的序列编号、码块的码率、第k个码块的信噪比和码块要求的平均译码时延Da，从N个候选搜索宽度中确定L个不同搜索宽度中的最小搜索宽度Li。
具体地，该译码器能够支持N种搜索宽度对码块进行译码，这N种搜索宽度可以称之为N个候选搜索宽度，该N个候选搜索宽度都配置了序列编号，因此在码块对译码有时延要求的时候可以根据该N个候选搜索宽度所配置的序列编号、码块的码率、第k个码块的信噪比和码块要求的平均译码时延Da，从N个候选搜索宽度中确定L个不同搜索宽度中的最小搜索宽度Li，以保证根据该L个不同搜索宽度译码的时间满足该码块的平均时延需求。
可选地，作为本发明一个实施例，采用L个不同搜索宽度由下式确定：
Figure PCTCN2015078011-appb-000010
其中，Da为码块要求的平均译码时延，d1,d2,…,dl-1为一组大于0小于等于n-j的单调递增的整数，R为码块的码率，γ为码块的信噪比，搜索宽度
Figure PCTCN2015078011-appb-000011
Ln单调递增，函数D(·,·，·)为使用搜索宽度为
Figure PCTCN2015078011-appb-000012
Figure PCTCN2015078011-appb-000013
Ln进行串行译码所需要的时延总和。
可选地，作为本发明一个实施例，最小搜索宽度Li配置的序列编号为第j个，采用L个不同搜索宽度对码块进行串行译码，包括：根据以下函数确 定调用第j个搜索宽度作为L个不同搜索宽度中的最小搜索宽度Li对码块进行并行译码：
Figure PCTCN2015078011-appb-000014
其中，Da为码块要求的平均译码时延，d1,d2,…,dl-1为一组大于0小于等于n-j的单调递增的整数，R为码块的码率，γ为码块的信噪比，搜索宽度
Figure PCTCN2015078011-appb-000015
Ln单调递增，函数D(·,·,·)为使用搜索宽度为
Figure PCTCN2015078011-appb-000016
Figure PCTCN2015078011-appb-000017
Ln进行串行译码所需要的时延总和。
可选地，作为本发明一个实施例，若采用L个不同搜索宽度对码块进行并行译码所得到的候选路径均不能通过CRC校验，从所述N个候选搜索宽度中选择M个不同搜索宽度对所述码块进行并行译码，其中，所述M个不同搜索宽度中的最小搜索宽度大于所述L个不同搜索宽度中的最大搜索宽度。
可选地，作为本发明一个实施例，若采用L个不同搜索宽度对码块进行串行译码所得到的候选路径均不能通过CRC校验，从N个候选搜索宽度中选择M个不同搜索宽度对码块进行并行译码，其中，M个不同搜索宽度中的最小搜索宽度大于L个不同搜索宽度中的最大搜索宽度。
可选地，作为本发明一个实施例，若N个候选搜索宽度中比L个不同搜索宽度中的最大搜索宽度大的搜索宽度只有一个，则使用该比L个不同搜索宽度中的最大搜索宽度大的搜索宽度对码块进行译码。
具体地，当采用L个不同搜索宽度对码块进行译码失败后，若仍存在比该L个不同搜索宽度都大的一个或多个搜索宽度，那么可以从该一个或多个搜索宽度中选择一个或多个搜索宽度对码块进行译码。
因此，本发明实施例的极化码的译码方法通过采用L个不同搜索宽度对一个或多个码块并行译码，并根据该并行译码中已完成的译码所获得的至少一个候选路径确定码块的译码路径，因此可以在保证相同译码误帧率的情况下，能够减小平均译码时延，在对多个码块进行并行译码时，能够降低平均空间复杂度。
上面结合图2所示的实施例详细介绍了极化码的译码方法，下面结合图3至图5详细介绍用于极化码译码的译码器。
图3是本发明实施的一种极化码的译码器的结构框图。如图3所示，该译码器包括：
译码模块310，译码模块310用于采用L个不同搜索宽度对码块进行并行译码。
确定模块320，确定模块320用于根据译码模块已完成的译码所获得的至少一个候选路径，确定码块的译码路径。
具体而言，一个码长为S的码块可以对应于一个S层的二叉译码码树。SC译码可以描述为在该码树上路径搜索的过程，SC译码的搜索路径为1条，即SC译码的搜索宽度为1，而SCH译码、SCL译码和SCS译码允许保留多条候选路径，即可以选择更大的搜索宽度对码块进行译码，以此扩大搜索范围，提高码块的译码性能。应理解，在译码模块310中的码块可以采用L个不同搜索宽度进行并行译码，该码块可以指某一码块也可以指某几个码块，也就是说几个码块可以同时采用不同的搜索宽度进行并行译码。
具体地，在模块320中，对码块进行不同搜索宽度并行译码的时候，码块的搜索宽度较小时将首先获得译码候选路径，因此可以根据已经获得到的候选路径确定译码路径，作为译码结果输出。
因此，本发明实施例的极化码的译码方法通过采用L个不同搜索宽度对一个或多个码块并行译码，并根据该并行译码中已完成的译码所获得的至少一个候选路径确定码块的译码路径，因此可以在保证相同译码误帧率的情况下，能够减小平均译码时延，在对多个码块进行并行译码时，能够降低平均空间复杂度。
可选地，作为本发明一个实施例，译码模块310用于采用L个不同搜索宽度对码块进行串行行译码；确定模块320用于根据译码模块已完成的译码所获得的至少一个候选路径，确定码块的译码路径。
因此，本发明实施例的极化码的译码方法通过采用L个不同搜索宽度对码块串行译码，并根据该串行译码中已完成的译码所获得的至少一个候选路径确定码块的译码路径，因此可以在保证相同译码误帧率的情况下减小平均译码时延，还能够降低译码的复杂度。
可选地，作为本发明一个实施例，确定模块还包括校验单元，该校验单元用于将码块已完成的译码中所获得的至少一个候选路径依次进行冗余循环CRC校验；确定模块320具体用于将通过CRC校验的候选路径确定为码块的译码路径。
应理解，某个候选路径能够通过CRC校验是指该候选路径序列的CRC 校验和为全零。
具体地，码块采用较小的搜索宽度时将较先获得该搜索宽度下的候选路径，可以将该搜索宽度下的候选路径按照概率度量从大到小排序依次通过上述CRC校验，第一个能够通过CRC校验的路径即为该码块的译码路径。
可选地，作为本发明一个实施例，确定模块320具体用于：当确定码块的译码路径后，停止对码块未完成的译码。也就是说，一旦有候选路径通过CRC校验即译码成功，译码器将停止所有其它对应于该码块正在进行中的译码操作，包括译码操作和CRC校验操作等，并重置以及释放响应的资源，该资源包括缓存码块所需要的资源、译码器中正在译码的译码单元以及CRC校验电路等。
具体地，当码块分别采用L个搜索宽度进行译码后所获得到的译码路径均不能通过CRC校验，则表明采用该L个搜索宽度对码块进行译码失败，译码器将释放L个搜索宽度进行译码所需的译码资源，以便于其它码块利用该些译码资源进行译码；如果该L个搜索宽度中已经包含该译码器所能支持的最大搜索宽度，则表明该译码对码块的译码失败。
可选地，作为本发明一个实施例，译码模块310具体用于：确定N个候选搜索宽度，该N个候选搜索宽度中任意两个搜索宽度不同；根据N个候选搜索宽度所配置的序列编号、码块的码率、码块的信噪比和码块要求的平均译码时延Da，从N个候选搜索宽度中确定L个不同搜索宽度中的最小搜索宽度Li。
具体地，该译码器能够支持N种搜索宽度对码块进行译码，这N种搜索宽度可以称之为N个候选搜索宽度，该N个候选搜索宽度都配置了序列编号，因此在码块对译码有时延要求的时候可以根据该N个候选搜索宽度所配置的序列编号、码块的码率、第k个码块的信噪比和码块要求的平均译码时延Da，从N个候选搜索宽度中确定L个不同搜索宽度中的最小搜索宽度Li，以保证根据该L个不同搜索宽度译码的时间满足该码块的平均时延需求。
可选地，作为本发明一个实施例，具有最小搜索宽度Li的译码单元配置的序列编号为第j个，译码模块310具体用于根据以下函数确定调用第j个搜索宽度作为L个不同搜索宽度中的最小搜索宽度Li对码块进行并行译码：
Figure PCTCN2015078011-appb-000018
其中，第Da为码块要求的平均译码时延，d1,d2,…,dl-1为一组大于0小于 等于n-j的单调递增的整数，R为码块的码率，γ为码块的信噪比，搜索宽度
Figure PCTCN2015078011-appb-000019
Ln单调递增，函数D(·,·,·)为使用搜索宽度为
Figure PCTCN2015078011-appb-000020
Figure PCTCN2015078011-appb-000021
Ln进行串行译码所需要的时延总和。
可选地，作为本发明一个实施例，具有最小搜索宽度Li的译码单元配置的序列编号为第j个，译码模块310具体用于根据以下函数确定调用第j个搜索宽度作为L个不同搜索宽度中的最小搜索宽度Li对码块进行串行译码：
Figure PCTCN2015078011-appb-000022
其中，第Da为码块要求的平均译码时延，d1,d2,…,dl-1为一组大于0小于等于n-j的单调递增的整数，R为码块的码率，γ为码块的信噪比，搜索宽度
Figure PCTCN2015078011-appb-000023
Ln单调递增，函数D(·,·,·)为使用搜索宽度为
Figure PCTCN2015078011-appb-000024
Figure PCTCN2015078011-appb-000025
Ln进行串行译码所需要的时延总和。
可选地，作为本发明一个实施例，译码模块310还用于：若采用L个不同搜索宽度对码块进行并行译码所得到的候选路径均不能通过CRC校验，从N个候选搜索宽度中选择M个不同搜索宽度对码块进行并行译码，其中，M个不同搜索宽度中的最小搜索宽度大于L个不同搜索宽度中的最大搜索宽度。
可选地，作为本发明一个实施例，译码模块310还用于：若采用L个不同搜索宽度对码块进行串行译码所得到的候选路径均不能通过CRC校验，从N个候选搜索宽度中选择M个不同搜索宽度对码块进行串行译码，其中，M个不同搜索宽度中的最小搜索宽度大于L个不同搜索宽度中的最大搜索宽度。
可选地，作为本发明一个实施例，若N个候选搜索宽度中比L个不同搜索宽度中的最大搜索宽度大的搜索宽度只有一个，则译码模块310具体用于使用该比L个不同搜索宽度中的最大搜索宽度大的搜索宽度对码块进行译码。
具体地，当采用L个不同搜索宽度对码块进行译码失败后，若仍存在比该L个不同搜索宽度都大的一个或多个搜索宽度，那么可以从该一个或多个搜索宽度中选择一个或多个搜索宽度对码块进行译码。
因此，本发明实施例的极化码的译码方法通过采用L个不同搜索宽度对码块并行译码，并根据该并行译码中已完成的译码所获得的至少一个候选路径确定码块的译码路径，因此可以在保证相同译码误帧率的情况下，能够减 小平均译码时延和平降低均空间复杂度。
图4示出了另一实施例的一种极化码的译码器的结构框图，该译码器400包括：
译码单元池410，译码单元池410包括多个译码单元，多个译码单元中的第一译码单元和第二译码单元具有不同的搜索宽度。
控制单元420，该控制单元420用于调用多个译码单元中的L个译码单元对码块进行并行译码，该L个译码单元中任意两个译码单元具有不同的搜索宽度。
校验单元430，该校验单元430用于根据译码单元池已完成的译码所获得到的至少一个候选路径，确定码块的译码路径。
具体而言，一个码长为S的码块可以对应于一个S层的二叉译码码树。SC译码可以描述为在该码树上路径搜索的过程，SC译码的搜索路径为1条，即SC译码的搜索宽度为1，而SCH译码、SCL译码和SCS译码允许保留多条候选路径，即可以选择更大的搜索宽度对码块进行译码，以此扩大搜索范围，提高码块的译码性能。
应理解，在译码单元池410中的码块可以采用L个不同搜索宽度进行并行译码，该码块可以指某一码块也可以指某几个码块，也就是说几个码块可以同时采用不同的搜索宽度进行并行译码。
具体地，在译码单元池410中，具有相同搜索宽度的译码单元构成一个译码组，也就是说某一个译码组内的译码单元搜索宽度相同，不同的译码组内译码单元的搜索宽度不相同。其中第一译码单元可以包括一个或多个译码单元，第二译码单元可以包括一个或多个译码单元，第一译码单元和第二译码单元具有不同的搜索宽度的含义是：译码单元池中至少存在两个译码单元，这两个译码单元之间的搜索宽度不同。
应理解，控制单元420用于调度L个译码单元对码块进行并行译码，也就是说译码单元池中存在两个译码单元的工作时间部分或全部重合。
因此，本发明实施例的极化码的译码方法通过采用L个不同搜索宽度对码块并行译码，并根据该并行译码中已完成的译码所获得的至少一个候选路径确定码块的译码路径，因此可以在保证相同译码误帧率的情况下，能够减小平均译码时延和降低平均空间复杂度。
可选地，作为本发明一个实施例，控制单元420，该控制单元420用于 调用多个译码单元中的L个译码单元对码块进行并行译码。具体地，在控制单元420中，该控制单元可以调用译码单元池中搜索宽度相同的译码单元对不同的码块进行并行译码。也就是说并行译码可以是指一个码块利用具有不同搜索宽度的译码单元进行译码，也可是指多个码块采用相同搜索宽度的多个译码进行译码。
可选地，作为本发明一个实施例，校验单元430具体用于将已完成的译码所获得的至少一个候选路径依次进行冗余循环校验；控制单元具体用于将至少一个候选路径中通过CRC校验的候选路径确定为码块的译码路径。
可选地，作为本发明一个实施例，控制单元430具体用于当确定码块的译码路径后，控制译码单元池停止对码块未完成的译码。
可选地，作为本发明一个实施例，控制单元430具体用于：根据多个译码单元所配置的序列编号、所述码块的码率、所述码块的信噪比和所述码块要求的平均译码时延Da，从所述多个译码单元中确定所述L个译码单元中具有最小搜索宽度Li的译码单元。
可选地，作为本发明一个实施例，具有最小搜索宽度Li的译码单元所配置的序列编号为第j个，控制单元430具体用于根据以下函数确定第j个译码单元：
Figure PCTCN2015078011-appb-000026
其中，第j个译码单元为所述L个译码单元中具有最小搜索宽度Li的译码单元，Da为码块要求的平均译码时延，d1,d2,…,dl-1为一组大于0小于等于n-j的单调递增的整数，R为码块的码率，γ为码块的信噪比，搜索宽度
Figure PCTCN2015078011-appb-000027
Figure PCTCN2015078011-appb-000028
Ln单调递增，函数D(·,·,·)为使用搜索宽度为
Figure PCTCN2015078011-appb-000029
Figure PCTCN2015078011-appb-000030
Ln进行串行译码所需要的时延总和。
可选地，作为本发明一个实施例，控制单元420具体用于：若采用L个译码单元对所述码块进行并行译码所得到的候选路径均不能通过CRC校验，从多个译码单元中选择M个译码单元对码块进行并行译码，其中，M个译码单元中任意两个译码单元的搜索宽度不同，M个不同搜索宽度中的最小搜索宽度大于所述L个不同搜索宽度中的最大搜索宽度。
可选地，作为本发明一个实施例，译码器400还包括缓存单元440，该缓存单元440用于根据控制单元410的控制缓存码块。具体地，不同的码块信息可以缓存在不同的逻辑单元中。
可选地，作为本发明一个实施例，译码器400还包括：
第一多路复用单元450，第一多路复用单元450用于根据控制单元的控制将码块送入译码单元池中的L个译码单元中；
第二多路复用单元460，第二多路复用单元用于根据控制单元的控制将译码池获得的码块的至少一个候选路径送入所述校验单元中。
因此，本发明实施例的极化码的译码方法通过采用L个不同搜索宽度对码块并行译码，并根据该并行译码中已完成的译码所获得的至少一个候选路径确定码块的译码路径，因此可以在保证相同译码误帧率的情况下减小平均译码时延。
图5示出了本发明另一实施例的译码器的结构的示意性框图。如图5所示，译码器包括缓存510、译码单元池520、CRC校验电路530、控制单元540和多路复用单元550。译码单元池中具有n组译码单元，每个组内译码单元的搜索宽度一样，不同组内译码单元的搜索宽度不一样。
具体地，每一组译码单元的搜索宽度分别为L1,L2,…,Ln，不失一般性，假定L1<L2<…<Ln，每一组包含译码单元的数量分别为m1,m2,…,mn，并且满足m1+m2+…+mn≥M；每一组中缓存、CRC校验电路以及多路复用单元的数量均不小于M。
上述译码器中，译码单元池中的各组译码单元可以由SC和增强SC译码单元(包括SCL、SCS或者SCH译码)中的一种或者多种构成。并且搜索宽度为1的译码单元可以直接等价为SC译码。
从信道接收到的各个码块的接收信号被分别存储在一个缓存中的不同逻辑单元；控制单元针对码块对译码延时需求，将第k个码块的信道接收信号通过多路复用单元被送入1个或多个不同搜索宽度的译码单元中进行译码，k∈{1,2,…,M}；每一个搜索宽度为Li的译码单元，i∈{1,2,…,n}，都按照其概率度量从大到小依次输出Li个候选路径，并在控制单元的调度下通过多路复用单元送入到一个CRC校验电路中按顺序进行CRC校验：
(1)若第j个候选路径能够通过CRC校验，即序列的CRC校验和为全零，j＝1,2,…,Li，则输出该序列作为第k个码块的译码序列，译码成功并将此消息反馈给控制单元；
(2)若全部Li个候选路径均不能通过CRC校验，则译码失败并将此消息反馈给控制单元；
控制单元收到译码成功消息后，停止所有其它对应于该码块的正在进行中的译码操作(包括译码操作、CRC校验操作等)，并重置并释放相应资源(缓存、所有被调度的译码单元、CRC校验电路等)；控制单元收到译码失败消息后，重置并释放已经宣告译码失败的译码资源(宣告失败的译码单元和CRC校验电路)，并等待正在对该码块进行译码的其它译码单元的反馈消息。
若该码块所有对应的译码单元均反馈译码失败消息，且已调用的译码单元中已经包含了一个搜索宽度为Ln的译码单元，则宣告对该码块译码失败；否则控制单元重新根据调度1个或多个译码单元对该码块进行译码，并且满足：重新被调度的译码单元中最小的搜索宽度大于前一次宣告失败的译码单元中最大的搜索宽度。
控制单元调度译码单元的策略如下：
(1)调度译码器数量方面：若某个码块对译码时延要求不高，则控制单元从第i＝1组开始尝试调度译码单元，每次调度1个译码单元对其尝试译码；否则，控制单元每次选取l组译码单元(2≤l≤n)，从中各调度一个译码单元同时对该码块进行译码；
(2)起始调度译码器组序：若某个码块对译码时延要求不高，则在对某个码块进行首次译码尝试时，则控制单元尝试从(依时延需求，选取第1组1或包含第1组的l个译码单元组)；否则，直接从i＝j组开始调度译码单元(依时延需求，选取第j组或包含第j组的l个译码单元组)，j的选取满足：
Figure PCTCN2015078011-appb-000031
其中，Da为平均译码时延需求，d1,d2,…,dl-1为一组大于0小于等于n-j的单调递增的整数，函数D(·,·,·)根据搜索宽度配置序列、码率R和信噪比γ计算得到顺序调用所配置的搜索宽度时译码的时延估计值，该函数可以预先通过蒙特卡洛仿真的方法得到。
(3)当控制单元尝试从第i组中调用一个搜索宽度为Li的译码单元时，若该组中所有译码单元均已被占用，则直接判定接收到来自该组译码器的一个译码失败消息。
可选地，作为本发明一个实施例，译码器同时对m个长度均为N的码块进行译码，该m个码块对译码时延无需求，并且无预期的FER估计。
表1示出的译码器最大支持M个码块同时译码，M≥m，译码单元池中含有n组译码单元，译码器池中的译码器类型均为SCL，不同搜索宽度和数 量配置如表1所示。
表1译码单元池内各组译码单元的搜索宽度和数量配置
搜索宽度 L1＝1 L2＝2 … Ll＝2l-1 … Ln＝2n-1
数量 m1＝m m2＝m/2 … ml＝m/2l-1 … mn＝m/2n-1
将m个码块分别送入m个搜索宽度为L1的译码单元进行译码，译码结果若能通过CRC校验则输出；否则尝试将没有正确译码的码块切换至搜索宽度为L2的译码单元进行译码，依此类推，直到某个候选序列能够通过CRC校验，则宣告对该码块译码成功并输出首个能够通过CRC校验的候选序列；若搜索宽度为Ln的译码单元也无法对其进行成功译码，则宣告对该码块译码失败。
在对某个码块的译码过程中，若使用搜索宽度为Ll的译码单元译码失败后，发现搜索宽度为Ll+1的译码单元全部被占用，则尝试调用搜索宽度为Ll+2的译码器，依此类推，当所有搜索宽度大于Ll的译码器均被占用时，则直接宣告该码块译码失败。
在表1配置下，码块的最大译码时延为
Figure PCTCN2015078011-appb-000032
平均时延为：
Figure PCTCN2015078011-appb-000033
其中，Dl表示搜索宽度为Ll的SCL译码器的译码时延；同时注意到，对任意2≤l≤n有、
Figure PCTCN2015078011-appb-000034
即用较小的搜索宽度Ll-1能够正确译码时，用较大的Ll也能够正确译码；反之，用较大的Ll译码失败时，用较小的Ll-1译码也将失败。
如表1配置的译码器，其总的空间复杂度为O(nmN)。作为对比，若实现m个独立的译码器同时分别地对m个码块进行使用搜索宽度为Ln，则空间复杂度为O(LnmN)。例如，取n＝6，对BPSK调制通过AWGN信道传输的、码长N＝1024、码率R＝0.5的Polar码进行译码。相比搜索宽度为32的CASCL译码方案，本发明方案所需的空间复杂度仅为后者的18.75％，但如图6所示，本发明方案在FER性能上没有损失。同时，在平均计算复杂度远远小于传统的CASCL方案，并且随着信噪比升高而不断降低，如图7所示。
可选地，作为本发明一个实施例，译码器的配置如表2所示，译码器最大支持M个码块同时译码，M≥1，译码单元池中含有n组译码单元，译码器池中的译码器类型均为SCL，各组译码器搜索宽度和数量配置如表2所示。
表2译码单元池内各组译码单元的搜索宽度和数量配置
搜索宽度 L1＝1 L2＝2 … Ll＝2l-1 … Ln＝2n-1
数量 m1＝m m2≤m1 … ml≤ml-1 … mn≤mn-1
利用该译码器对1个对译码时延有较高要求的码块进行译码的步骤如下：
控制单元从n组译码单元中各调用1个译码单元，共n个具有不同搜索宽度的译码单元同时对该码块进行译码。一旦检测到成功译码(某一个译码单元输出的候选序列中的一个能够通过CRC校验)，则停止并释放其它未完成译码的译码单元，并输出该能够通过CRC校验的序列作为译码结果。
按以上方法译码时，码块平均译码时延为：
Figure PCTCN2015078011-appb-000035
其中，其中，Dl表示搜索宽度为Ll的SCL译码器的译码时延，因此码块的最大译码时延为Dmax＝Dn。
若采用表2的译码器配置及上述方法对某一对译码时延要求较高的码块进行译码，并且假设Dl+1＝1.5×Dl，则采用本发明译码方法平均译码时延为Davg＝1.132×D1；作为对比，直接采用CASCL译码的时延为7.594×D1；本发明所提方法的平均时延仅为直接采用CASCL译码的15％。可选地，作为本发明一个实施例，该译码器的配置如表3所示，译码结构配置为仅包含2组译码单元，译码器池中的译码器类型均为SCL。该译码器同时对m个长度均为N的码块进行译码，其中有m′个码块对时延要求较高，其余m-m′个码块无时延要求；
表3译码单元池内各组译码单元的搜索宽度和数量配置
搜索宽度 L1＝1 L2＝32
数量 m1＝m m2≤m，且m2≥m′
对其中m-m′个无时延要求的码块，首先尝试使用搜索宽度为1的SCL 译码单元(实际上就是SC译码单元)进行译码，若译码所得到的候选序列经CRC校验失败，则尝试使用搜索宽度为32的SCL译码；若搜索宽度为32的SCL译码单元输出的候选序列中没有能够通过CRC校验的序列，则宣告译码失败；
对其中m′个对时延要求较高的码块，在首次尝试译码时，就从两组中各调用一个译码单元，同时使用搜索宽度为1和32的两个译码单元(一个SC译码单元和一个SCL(32)译码单元)对该码块进行译码，若SC译码成功(结果能够通过CRC校验)，则无需等待SCL(32)的译码结束，直接输出译码序列，停止并释放SCL(32)译码单元。
因此，本发明实施例的极化码的译码方法通过采用L个不同搜索宽度对码块并行译码，并根据该并行译码中已完成的译码所获得的至少一个候选路径确定码块的译码路径，因此可以在保证相同译码误帧率的情况下，能够减小平均译码时延和降低平均空间复杂度。图7是本发明另一实施例的装置的示意框图。图6的装置20可用于实现上述方法实施例中各步骤及方法。装置20可应用于各种通信系统中的基站或者终端。图7的实施例中，装置20包括发射电路202、接收电路203、译码处理器204、处理单元205，存储器206及天线201。处理单元205控制装置20的操作，并且可用于处理信号。处理单元205还可以称为中央处理单元(Central Processing Unit，简称为“CPU”)。存储器206可以包括只读存储器和随机存取存储器，并向处理单元205提供指令和数据。存储器206的一部分还可以包括非易失行随机存取存储器(NVRAM)。具体的应用中，装置20可以嵌入或者本身可以就是例如移动电话之类的无线通信设备，还可以包括容纳发射电路202和接收电路203的载体，以允许装置20和远程位置之间进行数据发射和接收。发射电路202和接收电路203可以耦合到天线201。装置20的各个组件通过总线系统209耦合在一起，其中总线系统209除包括数据总线之外，还包括电源总线、控制总线和状态信号总线。但是为了清楚说明起见，在图中将各种总线都标为总线系统209。
上述本发明实施例揭示的方法可以应用于译码处理器204中，或者由译码处理器204实现。译码处理器204可能是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法的各步骤可以通过译码处理器204中的硬件的集成逻辑电路或者软件形式的指令完成。这些指令可以通过处理单元 205以配合实现及控制。用于执行本发明实施例揭示的方法，上述的译码处理器可以是通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现成可编程门阵列(FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本发明实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器，译码器等。结合本发明实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器206，译码处理器204读取存储器206中的信息，结合其硬件完成上述方法的步骤。
具体地，存储器206可存储使得译码处理器204或处理单元205执行以下过程的指令：采用L个不同搜索宽度对码块进行并行译码；根据并行译码中已完成的译码所获得的至少一个候选路径，确定码块的译码路径。
因此，本发明实施例的极化码的译码方法通过采用L个不同搜索宽度对码块并行译码，并根据该并行译码中已完成的译码所获得的至少一个候选路径确定码块的译码路径，因此可以在保证相同译码误帧率的情况下，能够减小平均译码时延和降低平均空间复杂度。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本发明的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。
在本发明的各种实施例中，应理解，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本发明实施例的实施过程构成任何限定。
另外，本文中术语“系统”和“网络”在本文中常可互换使用。应理解，本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
在本申请所提供的实施例中，应理解，“与A相应的B”表示B与A相关联，根据A可以确定B。但还应理解，根据A确定B并不意味着仅仅根据A确定B，还可以根据A和/或其它信息确定B。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介 质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，简称为“ROM”)、随机存取存储器(Random Access Memory，简称为“RAM”)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种极化码的译码方法，其特征在于，包括：
    采用L个不同搜索宽度对码块进行并行译码；
    根据所述并行译码中已完成的译码所获得的至少一个候选路径，确定所述码块的译码路径。
  2. 根据权利要求1所述的译码方法，其特征在于，所述根据所述并行译码中已经完成的译码所获得的至少一个候选路径，确定所述码块的译码路径，包括：
    将所述已完成的译码所获得的至少一个候选路径依次进行冗余循环CRC校验；
    将所述至少一个候选路径中通过所述CRC校验的候选路径确定为所述码块的译码路径。
  3. 根据权利要求1或2所的译码方法，其特征在于，所述方法还包括：
    当确定所述码块的译码路径后，停止所述并行译码中未完成的译码。
  4. 根据权利要求1至3中任一项所述的译码方法，其特征在于，所述采用L个不同搜索宽度对码块进行并行译码，包括：
    确定N个候选搜索宽度，所述N个候选搜索宽度中任意两个搜索宽度不同；
    根据所述N个候选搜索宽度的编号、所述码块的码率、所述码块的信噪比和所述码块要求的平均译码时延Da，从所述N个候选搜索宽度中确定所述L个不同搜索宽度。
  5. 根据权利要求4所述的译码方法，其特征在于，所述L个不同搜索宽度由下式确定：
    Figure PCTCN2015078011-appb-100001
    其中，Da为所述码块要求的平均译码时延，d1,d2,…,dl-1为一组大于0小于等于n-j的单调递增的整数，R为所述码块的码率，γ为所述码块的信噪比，搜索宽度
    Figure PCTCN2015078011-appb-100002
    单调递增，函数D(·,·,·)为使用所述搜索宽度为
    Figure PCTCN2015078011-appb-100003
    进行串行译码所需要的时延总和。
  6. 根据权利要求4或5中任一项所述的方法，其特征在于，所述方法还包括：
    若采用所述L个不同搜索宽度对所述码块进行并行译码所得到的候选路径均不能通过所述CRC校验，从所述N个候选搜索宽度中选择M个不同搜索宽度对所述码块进行并行译码，其中，所述M个不同搜索宽度中的最小搜索宽度大于所述L个不同搜索宽度中的最大搜索宽度。
  7. 一种极化码的译码器，其特征在于，包括：
    译码模块，所述译码模块采用L个不同搜索宽度对码块进行并行译码；
    确定模块，所述确定模块用于根据所述译码模块已完成的译码所获得的至少一个候选路径，确定所述码块的译码路径。
  8. 根据权利要求7所述的译码器，其特征在于，所述确定模块还包括校验单元，所述校验单元用于将所述码块已完成的译码中所获得的至少一个候选路径依次进行冗余循环CRC校验；
    所述确定模块具体用于将所述至少一个候选路径中通过所述CRC校验的候选路径确定为所述码块的译码路径。
  9. 根据权利要求7或8所述的译码器，其特征在于，所述确定模块具体用于：
    当确定所述码块的译码路径后，停止对所述并行译码中未完成的译码。
  10. 根据权利要求7至9中任一项所述的译码器，其特征在于，所述译码模块具体用于：
    确定N个候选搜索宽度，所述N个候选搜索宽度中任意两个搜索宽度不同；
    根据所述N个候选搜索宽度的编号、所述码块的码率、所述码块的信噪比和所述码块要求的平均译码时延Da，从所述N个候选搜索宽度中确定所述L个不同搜索宽度。
  11. 根据权利要求10所述的译码器，其特征在于，所述译码模块具体用于：
    根据以下函数确定调用所述L个不同搜索宽度所述码块进行并行译码：
    Figure PCTCN2015078011-appb-100004
    其中，第Da为所述码块要求的平均译码时延，d1,d2,…,dl-1为一组大于0小于等于n-j的单调递增的整数，R为所述码块的码率，γ为所述码块的信噪比，搜索宽度
    Figure PCTCN2015078011-appb-100005
    单调递增，函数D(·,·,·)为使用所述搜索宽度为
    Figure PCTCN2015078011-appb-100006
    进行串行译码所需要的时延总和。
  12. 根据权利要求10或11中任一项所述的译码器，其特征在于，所述译码模块还用于：
    若采用所述L个不同搜索宽度对所述码块进行并行译码所得到的候选路径均不能通过所述CRC校验，从所述N个候选搜索宽度中选择M个不同搜索宽度对所述码块进行并行译码，其中，所述M个不同搜索宽度中的最小搜索宽度大于所述L个不同搜索宽度中的最大搜索宽度。
  13. 一种极化码的译码器，其特征在于，包括：
    译码单元池，所述译码单元池包括多个译码单元，所述多个译码单元中的第一译码单元和第二译码单元具有不同的搜索宽度；
    控制单元，所述控制单元用于调用所述多个译码单元中的L个译码单元对码块进行并行译码，所述L个译码单元中任意两个译码单元具有不同的搜索宽度；
    校验单元，所述校验单元用于根据所述译码单元池已完成的译码所获得到的至少一个候选路径，确定所述码块的译码路径。
  14. 根据权利要求13所述的译码器，其特征在于，所述校验单元具体用于将所述已完成的译码所获得的至少一个候选路径依次进行冗余循环校验；
    所述控制单元具体用于将所述至少一个候选路径中通过所述CRC校验的候选路径确定为所述码块的译码路径。
  15. 根据权利要求13或14所述的译码器，其特征在于，所述控制单元具体用于：
    当确定所述码块的译码路径后，控制所述译码单元池停止对所述并行译码中未完成的译码。
  16. 根据权利要求13至15中任一项所述的译码器，其特征在于，所述控制单元具体用于：
    根据所述多个译码单元的编号、所述码块的码率、所述码块的信噪比和所述码块要求的平均译码时延Da，从所述多个译码单元中确定所述L个译码单元。
  17. 根据权利要求16所述的译码器，其特征在于，所述控制单元具体用于：
    根据以下函数确定所述L个译码单元：
    Figure PCTCN2015078011-appb-100007
    其中，所述第j个译码单元为所述L个译码单元中具有最小搜索宽度Li的译码单元，Da为所述码块要求的平均译码时延，d1,d2,…,dl-1为一组大于0小于等于n-j的单调递增的整数，R为所述码块的码率，γ为所述码块的信噪比，搜索宽度
    Figure PCTCN2015078011-appb-100008
    单调递增，函数D(·,·,·)为使用所述搜索宽度为
    Figure PCTCN2015078011-appb-100009
    进行串行译码所需要的时延总和。
  18. 根据权利要求15或16所述的译码器，其特征在于，所述控制单元具体用于：
    若采用所述L个译码单元对所述码块进行并行译码所得到的候选路径均不能通过所述CRC校验，从所述多个译码单元中选择M个译码单元对所述码块进行并行译码，其中，所述M个译码单元中任意两个译码单元的搜索宽度不同，所述M个不同搜索宽度中的最小搜索宽度大于所述L个不同搜索宽度中的最大搜索宽度。
  19. 根据权利要求13至18中任一项所述的方法，其特征在于，所述译码器还包括缓存单元，所述缓存单元用于根据所述控制单元的控制缓存所述码块。
  20. 根据权利要求13至19中任一项所述的方法，其特征在于，所述译码器还包括：
    第一多路复用单元，所述第一多路复用单元用于根据所述控制单元的控制将所述码块送入所述译码单元池中的L个译码单元中；
    第二多路复用单元，所述第二多路复用单元用于根据所述控制单元的控制将所述译码池获得的所述码块的至少一个候选路径送入所述校验单元中。
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