WO2017143870A1 - 极化码的编码方法、译码方法、编码设备和译码设备 - Google Patents

极化码的编码方法、译码方法、编码设备和译码设备 Download PDF

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Publication number
WO2017143870A1
WO2017143870A1 PCT/CN2017/000050 CN2017000050W WO2017143870A1 WO 2017143870 A1 WO2017143870 A1 WO 2017143870A1 CN 2017000050 W CN2017000050 W CN 2017000050W WO 2017143870 A1 WO2017143870 A1 WO 2017143870A1
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bit sequence
bit
sub
sequence
check
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PCT/CN2017/000050
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English (en)
French (fr)
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曾重阳
金杰
陈凯
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华为技术有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes

Definitions

  • Embodiments of the present invention relate to the field of communications, and more particularly, to a method, a decoding method, an encoding device, and a decoding device for a polarization code.
  • Communication systems usually use channel coding to improve the reliability of data transmission to ensure the quality of communication.
  • the Polar code is the first good code that theoretically proves that the Shannon capacity can be obtained and has low coding and decoding complexity.
  • an enhanced SC (Successive Cancellation) decoding algorithm is used, for example, a serial offset list (SCL, Successive Cancellation) based on the SC algorithm.
  • SCL Serial Offundancy Check
  • SCS Serial Cancellation Stack
  • SCH Serial Cancellation Hybrid
  • sequence X of length K- ⁇ (ie, for carrying information to be transmitted), add a CRC check code of length ⁇ to obtain a sequence Y of length K, that is, a CRC check code will be added.
  • Sequence Y as information bits;
  • the embodiment of the invention provides a coding method, a decoding method, an encoding device and a decoding device for a polarization code, which can reduce the delay of the decoding process and improve the user experience.
  • a method for encoding a polarization code comprising: encoding, by a coding device, target information transmitted to a decoding device, to generate a first bit sequence, the first bit sequence comprising information bits and fixed bits, the information The bit is used to carry the target information, and the fixed bit is used to carry the preset information; the encoding device determines the check bit according to the first bit sequence; the encoding device generates the first according to the first bit sequence and the check bit. a two-bit sequence; the encoding device generates a polarization code sequence according to the second bit sequence.
  • the parity bit is subsequent to the first bit sequence.
  • the encoding device determines the check bit according to the first bit sequence, including: the coding device is configured according to the length of the first bit sequence Determining the degree of parallelism M, M ⁇ 2; the encoding device performs a check process on the first bit sequence according to the degree of parallelism M to obtain the check bit.
  • the time of the check processing can be shortened, and the transmission delay can be reduced.
  • the degree of parallelism M is an integer power of two.
  • the length of the first bit sequence is an integer power of two.
  • the parallelism M can be easily obtained by making the degree of parallelism M and the length of the first bit sequence to an integer power of two.
  • the method further includes: the encoding device sends the first indication information to the decoding device, where the first indication information is used to indicate the The first bit sequence is located in the second bit sequence, or the first indication information is used to indicate the location of the check bit in the second bit sequence.
  • the decoding device can distinguish the first bit sequence and the check bit from the second bit sequence according to the first indication information, thereby improving the coding device to generate the second bit sequence. Flexibility, specifically, can improve the coding device to determine the first ratio Flexibility in the positional relationship between the special sequence and the check bits.
  • the encoding device determines the check bit according to the first bit sequence, including: the encoding device divides the first bit sequence Segment processing to generate P sub-bit sequences, each sub-bit sequence including information bits and fixed bits, P ⁇ 2; the encoding device determines parity bits according to the P sub-bit sequences, wherein the parity bits include P sub-schools
  • the P sub-bit sequence is in one-to-one correspondence with the P sub-check bits, and each sub-check bit is generated according to the corresponding sub-bit sequence.
  • the encoding device and the decoding device can perform the parity processing on the sub-bit sequences in the first bit sequence in parallel, which can shorten the time of the verification process and reduce the transmission delay.
  • each sub-bit sequence is adjacent to the corresponding sub-check bit.
  • each sub-bit sequence By arranging each sub-bit sequence adjacent to the corresponding sub-check bit, the sub-check bits corresponding to each sub-bit sequence can be easily determined.
  • each sub-bit sequence is located before the corresponding sub-check bit.
  • the encoding device determines the check bit according to the P sub-bit sequences, including: the length of the p-th sub-bit sequence of the encoding device Determining a degree of parallelism m corresponding to the p-th sub-bit sequence, where m ⁇ 2, p ⁇ [1, P]; the encoding device according to the degree of parallelism corresponding to the p-th sub-bit sequence, the p-th sub- The bit sequence performs a check process to obtain a sub-check bit corresponding to the p-th sub-bit sequence.
  • the time of the verification process can be shortened, and the transmission delay can be reduced.
  • the method further includes: the encoding end device sending, to the decoding device, second indication information, where the second indication information is used to indicate a position of each sub-bit sequence in the first bit sequence in the second bit sequence, and the second indication information is used to indicate that the sub-check sequence corresponding to each sub-bit sequence is in the second bit sequence position.
  • Decoding the device according to the second indication message by transmitting the second indication information to the decoding device
  • the information distinguishes each sub-bit sequence and the sub-check sequence corresponding to each sub-bit sequence from the second bit sequence, thereby improving the flexibility of the encoding device when generating the second bit sequence, and specifically, improving the encoding device determination. Flexibility in the positional relationship of each sub-bit sequence and the sub-check sequence corresponding to each sub-bit sequence.
  • the length of each sub-bit sequence is an integer power of two.
  • the degree of parallelism m is an integer power of two.
  • the parallelism m can be easily obtained by making the degree of parallelism m and the length of the first bit sequence to an integer power of two.
  • a method for decoding a polarization code comprising: decoding a device to obtain a polarization code sequence; and the decoding device decoding the polarization code sequence to obtain at least one second bit sequence
  • the second bit sequence includes a first bit sequence and a check bit, wherein the check bit is generated based on the first bit sequence, the first bit sequence includes information bits and fixed bits, and the information bits are used by the information bits And carrying the target information, the fixed bit is used to carry the preset information;
  • the decoding device acquires the verification bit corresponding to each second bit sequence according to the first bit sequence in each second bit sequence, and according to each a verification bit corresponding to the second bit sequence and a parity bit in each second bit sequence, determining a target second bit sequence from the at least one second bit sequence, wherein the verification corresponding to the target second bit sequence The bit is identical to the parity bit in the second bit sequence of the target; the decoding device determines the transmission by the encoding device according to the information bits in the target second
  • the parity bit is subsequent to the first bit sequence.
  • the decoding device acquires, according to the first bit sequence in each second bit sequence, the corresponding second bit sequence. Verifying the bit, comprising: the decoding device determining the degree of parallelism M, M ⁇ 2 according to the length of the first bit sequence; the decoding device performs a check process on the first bit sequence according to the parallelism M to obtain This check bit.
  • the time of the check processing can be shortened, and the transmission delay can be reduced.
  • the length of the first bit sequence is an integer power of 2.
  • the degree of parallelism M is an integer power of two.
  • the parallelism M can be easily obtained by making the degree of parallelism M and the length of the first bit sequence to an integer power of two.
  • the decoding device obtains, according to the first bit sequence in each second bit sequence, the corresponding second bit sequence.
  • the method further includes: the decoding device receiving the encoding device, sending the first indication information, where the first indication information is used to indicate the location of the first bit sequence in the second bit sequence, or the first The indication information is used to indicate the location of the parity bit in the second bit sequence; the decoding device determines the first bit sequence and the check bit in each second bit sequence according to the first indication information.
  • the decoding device can distinguish the first bit sequence and the check bit from the second bit sequence according to the first indication information, so that the encoding device can generate the second bit sequence
  • the flexibility in particular, can improve the flexibility of the encoding device when determining the positional relationship of the first bit sequence and the check bit.
  • the first bit sequence in each second bit sequence includes P sub-bit sequences, and each sub-bit sequence includes information bits and fixed waves.
  • the check bits in each second bit sequence include P sub-check bits
  • the P sub-bit sequences are in one-to-one correspondence with the P sub-check bits
  • each sub-check bit is according to the And generating, by the corresponding sub-bit sequence, the decoding device, according to the first bit sequence in each second bit sequence, the verification bit corresponding to each second bit sequence, and corresponding to each second bit sequence Determining bits and a parity bit in each second bit sequence, determining a target second bit sequence from the L second bit sequences, comprising: the decoding device determining P sub-bits in each second bit sequence a sequence and P sub-check bits; the decoding device acquires verification bits corresponding to each second bit sequence according to P sub-bit sequences in each second bit sequence, wherein each second The verification
  • the encoding device and the decoding device can perform the check processing on the sub bit sequences in the first bit sequence in parallel, which can shorten the time of the verification process. In between, reduce the transmission delay.
  • each sub-bit sequence is adjacent to the corresponding sub-check bit.
  • each sub-bit sequence By arranging each sub-bit sequence adjacent to the corresponding sub-check bit, the sub-check bits corresponding to each sub-bit sequence can be easily determined.
  • each sub-bit sequence is located before the corresponding sub-check bit.
  • the decoding device acquires, according to the P sub-bit sequences in each second bit sequence, the corresponding corresponding to the second bit sequence.
  • the verification bit includes: the decoding device determines, according to the length of the p-th sub-bit sequence in each second bit sequence, a parallel degree m corresponding to the p-th sub-bit sequence, where m ⁇ 2, p ⁇ [1 And the decoding device performs a check process on the p-th sub-bit sequence according to the parallelism m corresponding to the p-th sub-bit sequence to obtain a sub-verification bit corresponding to the p-th sub-bit sequence.
  • the time of the verification process can be shortened, and the transmission delay can be reduced.
  • the method further includes: the decoding end device receiving the second indication information sent by the encoding device, where the second indication information is used And indicating a position of each sub-bit sequence in the first bit sequence in the second bit sequence, and the second indication information is used to indicate that the sub-check sequence corresponding to each sub-bit sequence is in the second bit sequence s position.
  • the decoding device can distinguish the sub-bit sequence and the sub-check sequence corresponding to each sub-bit sequence from the second bit sequence according to the second indication information, thereby improving coding.
  • the flexibility of the device when generating the second bit sequence specifically, the flexibility of the encoding device to determine the positional relationship of each sub-bit sequence and the sub-check sequence corresponding to each sub-bit sequence.
  • the length of each sub-bit sequence is an integer power of two.
  • the degree of parallelism m is an integer power of two.
  • the parallelism m can be easily obtained by making the degree of parallelism m and the length of the first bit sequence to an integer power of two.
  • an apparatus for encoding a polarization code comprising: a generating unit, configured to generate a first bit sequence including information bits and fixed bits according to target information transmitted to a decoding device as needed The information bit is used to carry the target information, the fixed bit is used to carry the preset information, the check unit is configured to determine the check bit according to the first bit sequence, and the coding unit is configured to use, according to the first bit sequence And the check bit, generating a second bit sequence and for generating a polarization code sequence according to the second bit sequence.
  • the checking unit is specifically configured to determine, according to the length of the first bit sequence, a parallel degree M, M ⁇ 2, and according to the parallel degree M, The first bit sequence is subjected to a check process to obtain the check bit.
  • the encoding apparatus further includes: a sending unit, configured to send, to the decoding device, first indication information, where the first indication information is used The location of the first bit sequence in the second bit sequence is indicated, or the first indication information is used to indicate the location of the parity bit in the second bit sequence.
  • the checking unit is specifically configured to perform segmentation processing on the first bit sequence to generate P sub-bit sequences, each sub-bit
  • the sequence includes information bits and fixed bits, P ⁇ 2; for determining parity bits according to the P sub-bit sequences, wherein the parity bits include P sub-check bits, and the P sub-bit sequences and the P sub-checks
  • the bits correspond one-to-one, and each sub-check bit is generated according to the corresponding sub-bit sequence.
  • the checking unit is specifically configured to determine, according to a length of the pth sub-bit sequence, a parallel degree corresponding to the p-th sub-bit sequence m, where m ⁇ 2, p ⁇ [1, P]; for performing a check process on the p-th sub-bit sequence according to the degree of parallelism m corresponding to the p-th sub-bit sequence to obtain the p-th sub- The sub-check bits corresponding to the bit sequence.
  • the coding apparatus further includes: a sending unit, configured to send second indication information to the decoding device, where the second indication information is used And indicating the position of each sub-bit sequence in the first bit sequence in the second bit sequence, and the second indication information is used to indicate that the sub-check sequence corresponding to each sub-bit sequence is in the second bit sequence The location in .
  • a fourth aspect provides a decoding apparatus for a polarization code, comprising: an obtaining unit, configured to acquire a polarization code sequence; and a decoding unit, configured to perform decoding processing on the polarization code sequence to obtain at least one a second bit sequence, wherein the second bit sequence comprises a first bit sequence and a check bit, wherein the check bit is generated based on the first bit sequence, the first bit sequence comprising information bits and fixed bits
  • the information bit is used to carry the target information, and the fixed bit is used to carry the preset information.
  • the check unit is configured to acquire, according to the first bit sequence in each second bit sequence, the corresponding bit sequence.
  • Verifying a bit and determining a target second bit sequence from the at least one second bit sequence according to the verification bit corresponding to each second bit sequence and the parity bit in each second bit sequence, wherein the target The verification bit corresponding to the two-bit sequence is the same as the parity bit in the target second bit sequence; and the determining unit is configured to determine the target information transmitted by the encoding device according to the information bits in the target second bit sequence.
  • the checking unit is specifically configured to determine, according to the length of the first bit sequence, a parallel degree M, M ⁇ 2, and according to the parallel degree M, The first bit sequence is subjected to a check process to obtain the check bit.
  • the decoding apparatus further includes: a receiving unit, configured to receive, by the encoding device, first indication information, where the first indication information is used Instructing the first bit sequence to be in the second bit sequence, or the first indication information is used to indicate the location of the check bit in the second bit sequence; the check unit is further configured to use the first indication according to the first indication Information determines a first bit sequence and a check bit in each second bit sequence.
  • the first bit sequence in each second bit sequence includes P sub-bit sequences, and each sub-bit sequence includes information bits and fixed waves.
  • the check bits in each second bit sequence include P sub-check bits
  • the P sub-bit sequences are in one-to-one correspondence with the P sub-check bits
  • each sub-check bit is according to the Generating the corresponding sub-bit sequence
  • the decoding unit is specifically configured to determine P sub-bit sequences and P sub-check bits in each second bit sequence
  • the verification bit corresponding to each second bit sequence is obtained, wherein the verification bit corresponding to each second bit sequence includes P sub-verification bits, and the P sub-bit sequences are in one-to-one correspondence with the P sub-verification bits, each The sub-verification bits are generated according to the corresponding sub-bit sequence; for P sub-verification bits corresponding to each second bit sequence and
  • the checking unit is specifically configured to determine, according to the length of the p-th sub-bit sequence in each second bit sequence, a parallel degree m corresponding to the p-th sub-bit sequence, where m ⁇ 2, p ⁇ [1,P] And performing a check process on the p-th sub-bit sequence according to the parallelism m corresponding to the p-th sub-bit sequence to obtain a sub-verification bit corresponding to the p-th sub-bit sequence.
  • the decoding apparatus further includes: a receiving unit, configured to receive second indication information that is sent by the encoding device, the second indication information And indicating the position of each sub-bit sequence in the first bit sequence in the second bit sequence, and the second indication information is used to indicate that the sub-check sequence corresponding to each sub-bit sequence is in the second bit The position in the sequence.
  • a fifth aspect provides a coding apparatus for a polarization code, comprising: a bus; a processor connected to the bus; a memory connected to the bus; wherein the processor calls a program stored in the memory through the bus Generating a first bit sequence for the target information to be transmitted to the decoding device according to the need, the first bit sequence includes information bits and fixed bits, the information bits are used to carry the target information, and the fixed bits are used to carry the pre- Setting the information; the processor is configured to determine a check bit according to the first bit sequence; the processor is configured to generate a second bit sequence according to the first bit sequence and the check bit; the processor is configured to use the second bit according to the first bit sequence Sequence, generating a polarization code sequence.
  • the processor is specifically configured to determine, according to the length of the first bit sequence, a parallel degree M, M ⁇ 2; the processor is specifically configured to use the parallel Degree M, performing a check process on the first bit sequence to obtain the check bit.
  • the encoding device further includes a transmitter connected to the bus; and the processor is further configured to control the transmitter to decode the The device sends the first indication information, where the first indication information is used to indicate the location of the first bit sequence in the second bit sequence, or the first indication information is used to indicate the location of the parity bit in the second bit sequence.
  • the processor is specifically configured to perform segmentation processing on the first bit sequence to generate P sub-bit sequences, each sub-bit sequence Including information bits and fixed bits, P ⁇ 2; the processor is specifically configured to determine a check bit according to the P sub-bit sequences, where the check bits include P sub-check bits, and the P sub-bit sequences and the P The sub-check bits are in one-to-one correspondence, and each sub-check bit is generated according to the corresponding sub-bit sequence.
  • the processor is specifically configured to determine, according to the length of the p-th sub-bit sequence, a parallel degree m corresponding to the p-th sub-bit sequence, where m ⁇ 2, p ⁇ [1, P]; the processor is specifically configured according to the The parallel degree corresponding to the p-th sub-bit sequence is subjected to a check process on the p-th sub-bit sequence to obtain a sub-check bit corresponding to the p-th sub-bit sequence.
  • the encoding device further includes a transmitter connected to the bus; and the processor is further configured to control the transmitter to decode the The device sends a second indication information, where the second indication information is used to indicate a position of each sub-bit sequence in the first bit sequence in the second bit sequence, and the second indication information is used to indicate each sub-bit sequence. The position of the corresponding sub-check sequence in the second bit sequence.
  • a sixth aspect provides a decoding device for a polarization code, comprising: a bus; a processor connected to the bus; a memory connected to the bus; wherein the processor calls the memory stored in the memory through the bus a program for acquiring a polarization code sequence; the processor is configured to decode the polarization code sequence to obtain at least one second bit sequence, wherein the second bit sequence includes a first bit sequence and a checksum a bit, wherein the check bit is generated based on the first bit sequence, the first bit sequence includes information bits and fixed bits, the information bits are used to carry target information, and the fixed bits are used to carry preset information; The processor is configured to obtain, according to the first bit sequence in each second bit sequence, the verification bits corresponding to each second bit sequence, and according to the verification bits and each second bit sequence corresponding to each second bit sequence a check bit in which a target second bit sequence is determined from the at least one second bit sequence, wherein a verification ratio corresponding to the target second bit sequence Same as the second bit of the bit sequence of
  • the processor is specifically configured to determine, according to the length of the first bit sequence, a parallel degree M, M ⁇ 2; the processor is specifically configured to use the parallel Degree M, performing a check process on the first bit sequence to obtain the check bit.
  • the decoding device further includes a receiver connected to the bus; and the processor is further configured to control the receiver to receive the encoding The device sends the first indication information, where the first indication information is used to indicate the location of the first bit sequence in the second bit sequence, or the first indication information is used to indicate the location of the parity bit in the second bit sequence.
  • the first bit sequence in each second bit sequence includes P sub-bit sequences, and each sub-bit sequence packet Including information bits and fixed baud, P ⁇ 2, and the check bits in each second bit sequence include P sub-check bits, the P sub-bit sequences are in one-to-one correspondence with the P sub-check bits, each sub- The check bits are generated according to the corresponding sub-bit sequence, and the processor is specifically configured to determine P sub-bit sequences and P sub-check bits in each second bit sequence; the processor is specifically configured to use each The P sub-bit sequences in the second bit sequence acquire the verification bits corresponding to each second bit sequence, wherein the verification bits corresponding to each second bit sequence include P sub-verification bits, and the P sub-bit sequences and the P sub-verification bits are in one-to-one correspondence, and each sub-verification bit is generated according to the corresponding sub-bit sequence;
  • the processor is specifically configured to determine a target second bit sequence according to P sub-verification bits corresponding to each second bit sequence and P sub-check bits in each second bit sequence, where, for the target second bit sequence Any sub-bit sequence in which the sub-verification bit corresponding to the sub-bit sequence is the same as the sub-check bit corresponding to the sub-bit sequence.
  • the processor is specifically configured to determine the p-th sub-length according to a length of the p-th sub-bit sequence in each second bit sequence The degree of parallelism m corresponding to the bit sequence, where m ⁇ 2, p ⁇ [1, P]; the processor is specifically configured to: according to the degree of parallelism m corresponding to the p-th sub-bit sequence, the p-th sub-bit sequence A verification process is performed to obtain sub-verification bits corresponding to the p-th sub-bit sequence.
  • the decoding device further includes a receiver connected to the bus; and the processor is further configured to control the receiver to receive the encoding a second indication information sent by the device, where the second indication information is used to indicate a position of each sub-bit sequence in the first bit sequence in the second bit sequence, and the second indication information is used to indicate each sub-bit The position of the sub-check sequence corresponding to the sequence in the second bit sequence.
  • a computer program product comprising: computer program code, when the computer program code is run by a receiving unit, a processing unit, a sending unit or a receiver, a processor, a transmitter of a network device And causing the network device to perform the coding method of any one of the above first aspects, and various implementation manners thereof.
  • a computer program product comprising: computer program code, when the computer program code is run by a receiving unit, a processing unit, a sending unit or a receiver, a processor, and a transmitter of a network device
  • the network device is caused to perform the above-described second aspect, and a decoding method of any of the various implementations of the polarization code.
  • a computer readable storage medium storing a program causing a user equipment to perform the above-described first aspect, and any of the various implementations of the polarization code Coding method.
  • a computer readable storage medium storing a program causing a user equipment to perform the second aspect described above, and any one of the various implementations of the polarization code Decoding method.
  • the encoding method, the decoding method, the encoding device, and the decoding device of the polarization code determine the parity bit by causing the encoding device to perform a check processing on the first bit sequence including the information bits and the fixed bits. And combining the first bit sequence with the check bit to generate a second bit sequence, after which the encoding device may generate a polarization code sequence according to the second bit sequence, so that the decoding device may After the polarization code sequence is decoded to obtain the second bit sequence, the first bit sequence in the second bit sequence is verified based on the check bits in the second bit sequence, that is, The verification process is completed before the information bits are determined.
  • the estimation of the plurality of paths can be obtained.
  • the verification processing can be performed without acquiring the information bits in each path. Therefore, only the path through which the verification passes can be retained, and the information bits in the path through which the verification passes are used as the decoding output, which greatly shortens the delay of the decoding process and improves the user experience.
  • FIG. 1 is a diagram of a wireless communication system in accordance with various embodiments described herein.
  • FIG. 2 is a diagram of a system for performing a method of encoding a polarization code of an embodiment of the present invention in a wireless communication environment.
  • FIG. 3 is a diagram of a system for performing a method of decoding a polarization code of an embodiment of the present invention in a wireless communication environment.
  • FIG. 4 is a flow chart showing an example of a method of encoding a polarization code according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of the basic principle of a CRC according to an embodiment of the present invention.
  • Fig. 6 is a schematic diagram showing the basic principle of parallel processing of a CRC according to an embodiment of the invention.
  • FIG. 7 is a flow chart showing the parallel processing of the CRC of the embodiment of the invention.
  • FIG. 8 is another flow chart of parallel processing of a CRC according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram showing an example of an encoding process according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of another example of an encoding process according to an embodiment of the present invention.
  • FIG. 11 is a flowchart of a method for decoding a polarization code according to an embodiment of the present invention.
  • Figure 12 is a diagram showing an example of a decoding process in an embodiment of the present invention.
  • Figure 13 is a block diagram of an encoding apparatus for a polarization code according to an embodiment of the present invention.
  • Figure 14 is a block diagram of a decoding apparatus for a polarization code according to an embodiment of the present invention.
  • Fig. 15 is a schematic configuration diagram of an encoding apparatus to which a polarization code of an embodiment of the present invention is applied.
  • Figure 16 is a schematic configuration diagram of a decoding apparatus to which a polarization code of an embodiment of the present invention is applied.
  • 17 is a structural diagram of an access terminal to which a coding method or a decoding method of a polarization code according to an embodiment of the present invention is applied.
  • FIG. 18 is a structural diagram of a network device to which a coding method or a decoding method of a polarization code according to an embodiment of the present invention is applied.
  • a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer.
  • an application running on a computing device and a computing device can be a component.
  • One or more components can reside within a process and/or execution thread, and the components can be located on one computer and/or distributed between two or more computers.
  • these components can execute from various computer readable media having various data structures stored thereon.
  • a component may, for example, be based on signals having one or more data packets (eg, data from two components interacting with another component between the local system, the distributed system, and/or the network, such as the Internet interacting with other systems) Communicate through local and/or remote processes.
  • data packets eg, data from two components interacting with another component between the local system, the distributed system, and/or the network, such as the Internet interacting with other systems
  • the execution body of the encoding method or the decoding method of the polarization code in the embodiment of the present invention may be an access terminal.
  • An access terminal may also be called a system, a subscriber unit, a subscriber station, a mobile station, a mobile station, a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a wireless communication device, a user agent, a user device, or a user equipment (UE, User Equipment).
  • the access terminal may be a cellular phone, a cordless phone, a Session Initiation Protocol (SIP), a Wireless Local Loop (WLL) station, a personal digital processing (PDA), or a wireless communication.
  • SIP Session Initiation Protocol
  • WLL Wireless Local Loop
  • PDA personal digital processing
  • the execution body of the encoding method or the decoding method of the polarization code in the embodiment of the present invention may be Internet equipment.
  • the network device can be used for communicating with the mobile device, and the network device can be a Global System of Mobile communication (GSM) or a base station (BTS, Base Transceiver Station) in Code Division Multiple Access (CDMA). It may be a base station (NB, NodeB) in Wideband Code Division Multiple Access (WCDMA), or an evolved base station (eNB or eNodeB, Evolutional Node in Long Term Evolution (LTE)). B), or a relay station or access point, or a base station device in a future 5G network.
  • GSM Global System of Mobile communication
  • BTS Base Transceiver Station
  • CDMA Code Division Multiple Access
  • NB NodeB
  • WCDMA Wideband Code Division Multiple Access
  • eNB or eNodeB Evolutional Node in Long Term Evolution (LTE)
  • B or a relay station or access point, or a base
  • the term "article of manufacture” as used in this application encompasses a computer program accessible from any computer-readable device, carrier, or media.
  • the computer readable medium may include, but is not limited to, a magnetic storage device such as a hard disk, a floppy disk or a magnetic tape, etc.; an optical disk such as a compact disk (CD), a digital versatile disk (DVD), a digital versatile disk (DVD), and the like.
  • Smart cards and flash memory devices such as Erasable Programmable Read-Only Memory (EPROM).
  • various storage media described herein can represent one or more devices and/or other machine-readable media for storing information.
  • the term "machine-readable medium” may include, but is not limited to, a wireless channel and various other mediums capable of storing, containing, and/or carrying instructions and/or data.
  • the wireless communication system 100 includes a network device 102, which may include multiple antenna groups.
  • Each antenna group may include one or more antennas, for example, one antenna group may include antennas 104 and 106, another antenna group may include antennas 108 and 110, and an additional group may include antennas 112 and 114.
  • Two antennas are shown in Figure 1 for each antenna group, although more or fewer antennas may be used for each group.
  • Network device 102 may additionally include a transmitter chain and a receiver chain, as will be understood by those of ordinary skill in the art, which may include various components related to signal transmission and reception, such as processors, modulators, multiplexers, Demodulator, demultiplexer or antenna.
  • Network device 102 can communicate with one or more access terminals (e.g., access terminal 116 and access terminal 122). However, it will be appreciated that network device 102 can communicate with any number of access terminals similar to access terminal 116 or 122.
  • Access terminals 116 and 122 can be, for example, cellular telephones, smart phones, portable computers, handheld communication devices, handheld computing devices, satellite radios, global positioning systems, PDAs, and/or any other for communicating over wireless communication system 100. Suitable for equipment.
  • access terminal 116 is in communication with antennas 112 and 114, with antenna 112 And 114 transmits information to the access terminal 116 over the forward link 118 and receives information from the access terminal 116 over the reverse link 120.
  • access terminal 122 is in communication with antennas 104 and 106, wherein antennas 104 and 106 transmit information to access terminal 122 over forward link 124 and receive information from access terminal 122 over reverse link 126.
  • FDD Frequency Division Duplex
  • the forward link 118 can utilize a different frequency band than that used by the reverse link 120, and the forward link 124 can utilize the reverse link 126. Different frequency bands used.
  • TDD Time Division Duplex
  • the forward link 118 and the reverse link 120 can use a common frequency band
  • the forward link 124 and the reverse link 126 can use a common frequency band.
  • Each set of antennas and/or regions designed for communication is referred to as a sector of network device 102.
  • the antenna group can be designed to communicate with access terminals in sectors of the network device 102 coverage area.
  • the transmit antennas of network device 102 may utilize beamforming to improve the signal to noise ratio of forward links 118 and 124.
  • the neighboring cell is compared to the manner in which the network device transmits signals to all of its access terminals through a single antenna. Mobile devices in the middle are subject to less interference.
  • network device 102, access terminal 116, or access terminal 122 may be a wireless communication transmitting device and/or a wireless communication receiving device.
  • the wireless communication transmitting device can encode the data for transmission.
  • the wireless communication transmitting device may acquire (eg, generate, receive from other communication devices, or save in memory, etc.) a certain number of data bits to be transmitted over the channel to the wireless communication receiving device.
  • data bits may be included in one or more transport blocks of data, and the transport blocks may be segmented to produce a plurality of code blocks.
  • the wireless communication transmitting apparatus may encode each code block using a Polar code encoder (not shown) to generate a transmission signal.
  • the wireless communication receiving device may acquire a signal processed by the Polar code encoder transmitted by the channel receiving wireless communication transmitting device, and may decode the signal through a Polar decoder (not shown) to obtain the above data. Bit.
  • System 200 includes a wireless communication device 202 that is shown to transmit data via a channel. Although shown as transmitting data, the wireless communication device 202 can also receive data via a channel, for example, the wireless communication device 202 can transmit and receive data simultaneously, or the wireless communication device 202 can also transmit and receive data at different times, or Combination, etc.
  • the wireless communication device 202 can be, for example, a base station (e.g., base station 102 of FIG. 1, etc.), an access terminal (e.g., access terminal 116 of FIG. 1, access terminal 122 of FIG. 1, etc.), and the like.
  • the wireless communication device 202 can include a Polar code encoder 204 and a transmitter 206. Alternatively, the wireless communication device 202 can also include rate matching devices. Alternatively, when the wireless communication device 202 receives data via a channel, the wireless communication device 202 may also include a receiver that may be present separately or integrated with the transmitter 206 to form a transceiver.
  • the Polar code encoder 204 is configured to encode the data to be transmitted from the wireless communication device 202 to obtain a polarization code.
  • transmitter 206 can then transmit the output bits processed by Polar code encoder 204 (or Polar code encoder 204 and rate matching device) on the channel.
  • transmitter 206 can transmit relevant data to other different wireless communication devices (not shown).
  • FIG. 3 shows a schematic block diagram of a system 300 in which a method of decoding a polarization code of an embodiment of the present invention is applied in a wireless communication environment.
  • System 300 includes a wireless communication device 302 that is shown receiving data via a channel. Although shown as transmitting data, the wireless communication device 302 can also transmit data via a channel, for example, the wireless communication device 302 can transmit and receive data simultaneously, or the wireless communication device 302 can also transmit and receive data at different times, or Combination, etc.
  • the wireless communication device 302 can be, for example, a base station (e.g., base station 102 of FIG. 1, etc.), an access terminal (e.g., access terminal 116 of FIG. 1, access terminal 122 of FIG. 1, etc.), and the like.
  • Wireless communication device 302 can include a receiver 306 and a Polar code decoder 304. Alternatively, when wireless communication device 302 transmits data via a channel, the wireless communication device 302 may also include a transmitter that may be present separately or integrated with receiver 306 to form a transceiver.
  • the receiver 306 can receive the Polar code encoded signal transmitted by the other wireless communication device on the channel.
  • the Polar decoder 304 is configured to decode the signal received by the receiver 306 to acquire data transmitted by other wireless communication devices.
  • the Polar code is a linear block code whose generating matrix is G N and the encoding process is
  • Is the mother code of the Polar code is a binary line vector, the length is N, and its element is the mother code word;
  • I a binary line vector of length N (ie code length) and an integer power of 2;
  • G N is an N ⁇ N matrix
  • B N is an N ⁇ N transposed matrix, such as a bit reversal matrix.
  • the so-called bit reverse order permutation is to have a length of N sequence.
  • addition and multiplication operations mentioned above are addition and multiplication operations on a binary Galois field.
  • a part of the bits are used to carry information, called information bits, and the set of indices of these bits is denoted as A.
  • the other part of the bits is set to a fixed value pre-agreed by the transceiver, which is called a fixed bit, and the set of indexes is represented by the complement A c of A. Without loss of generality, these fixed bits are usually set to 0. This setting is also used in the description of the embodiment of the present invention; however, in practice, only the transmitting and receiving terminals need to be pre-agreed, and the fixed bit sequence can be arbitrarily set.
  • u A is In the information bit set, u A is a row vector of length K, ie
  • K, where
  • the most basic decoding method of the Polar code is SC decoding.
  • the SC decoding algorithm utilizes a sequence of signals received from the channel One by one Decoding each bit in the middle Estimated sequence
  • Ni represents the Cartesian product of Ni sets ⁇ 0,1 ⁇ .
  • SC decoding Serial Cancellation
  • LDPC Low-Density Parity-Check
  • CRC-assisted Successive Cancellation List CASCL
  • CRC-assisted SCS CRC-Aided Successive Cancellation Stack
  • CASCH CRC-assisted Successive Cancellation Hybrid
  • FIG. 4 is a schematic flowchart of a method 400 for encoding a polarization code according to an embodiment of the present invention.
  • the method 400 shown in FIG. 4 may be performed by an encoding device, for example, a Polar code encoder in a wireless communication device.
  • the method 400 includes:
  • the encoding device generates a first bit sequence according to the target information that needs to be transmitted to the decoding device, where the first bit sequence includes information bits and fixed bits, where the information bits are used to carry the target information, where the fixed bits are used to carry the pre- Set information.
  • the encoding device determines a parity bit according to the first bit sequence.
  • the encoding device generates a second bit sequence according to the first bit sequence and the check bit.
  • the encoding device generates a polarization code sequence according to the second bit sequence.
  • the encoding device may generate the information bit sequence X according to the information that needs to be transmitted to the decoding device (ie, an example of the target information) without loss of generality, and set the length of the information bit sequence X (or, The number of bits included in the information bit sequence X is K- ⁇ , where K- ⁇ ⁇ 1.
  • the process of generating the information bit sequence X by the encoding device may be similar to the prior art. Here, in order to avoid redundancy, detailed description thereof is omitted.
  • the encoding device may insert N-K fixed bits in the bit sequence X to obtain a bit sequence Y (i.e., an example of the first bit sequence) having a length (or a number of included bits) of N- ⁇ .
  • a bit sequence Y i.e., an example of the first bit sequence
  • the process of the coding device inserting the fixed bits in the information bits to generate the bit sequence Y may be similar to the prior art.
  • detailed description thereof is omitted.
  • the length of the first bit sequence is an integer power of two.
  • the length of the bit sequence Y (or the number of bits included in the bit sequence Y) is an integer power of 2, that is, if the length of the bit sequence Y is B, B satisfies the following formula 1.
  • the length of the first bit sequence listed above is only an exemplary description, and the embodiment of the present invention is not limited thereto.
  • the length of the bit sequence Y may be arbitrarily changed according to requirements.
  • the length of the bit sequence Y may be according to The code length (i.e., N) of the pre-set polarization code mother code and the length of the CRC check bit (i.e., ⁇ ) are determined.
  • the encoding device may perform a CRC check process for generating ⁇ check bits, or CRC check code, for the bit sequence Y generated as described above.
  • the encoding device may perform a CRC check process on the bit sequence Y as a whole to generate ⁇ parity bits (ie, mode 1) corresponding to the bit sequence Y as a whole.
  • the encoding device may perform segmentation processing on the bit sequence Y to obtain P (P ⁇ 2) sub-bit sequences, and perform CRC check processing on each sub-bit sequence separately to generate a calibration corresponding to each sub-bit sequence.
  • FIG. 5 is a schematic diagram showing the basic principle of a CRC according to an embodiment of the present invention.
  • the encoding device can serially process the bit sequence Y, processing 1 bit at a time.
  • g 0 to g ⁇ -1 are elements in the matrix G in the following formula 2, wherein the values of g 0 to g ⁇ -1 are 0 or 1, and the specific values may be based on The provisions in the prior art CRC processing are determined.
  • b 0 to b ⁇ -1 denote registers for storing intermediate values and outputting the stored values according to the instructions.
  • Y i represents the bit of the i-th processing (or, in the bit sequence Y of the i-th input), i ⁇ [0, N - ⁇ ].
  • N- ⁇ is the length of the sequence to be verified (ie, the bit sequence Y)
  • Means multiplication Indicates the modulo 2 addition operation.
  • the encoding device first adds Y i to the intermediate value stored in the register b ⁇ -1 (for ease of understanding and Explain, record the calculation results ), It is input to register b 0 . And, g 0 and The result of the multiplication operation is compared with the value output from the register b 0 (ie, ) after the addition operation is output to the registers b 1 , g 1 and Performs multiplication result is outputted after the arithmetic addition from the value of the register output to the register b 1 b 2, and so on, can be updated for intermediate values stored in the register ⁇ -1 b.
  • the final value stored in the register b ⁇ -1 can be used as the check sequence (ie, the sequence W).
  • Equation 2 the foregoing CRC check process may be represented by Equation 2 below.
  • S i is a vector of length ⁇ , representing the i-th intermediate state, i ⁇ [1, ⁇ ], and T represents transposition.
  • the method for the CRC processing shown in FIG. 5 is only exemplified in the above, and the embodiment of the present invention is not limited thereto.
  • the encoding device may also adopt a multi-bit parallel processing manner. Perform CRC processing.
  • the encoding device obtains the check sequence according to the first bit sequence, including: the encoding device determines the parallelism M, M ⁇ 2 according to the length of the first bit sequence;
  • the encoding device performs a check process on the first bit sequence according to the degree of parallelism M to obtain the check sequence.
  • the degree of parallelism M indicates the number of bits simultaneously processed when the code segment performs the check processing.
  • the encoding device may determine the parallelism M according to the length of the bit sequence (ie, the first bit sequence) to be verified, for example, if the length of the first bit sequence is large, the parallelism M may be made larger. To shorten the time for verification processing.
  • the specific parameters that can be determined for determining the degree of parallelism M are merely exemplary.
  • the embodiment of the present invention is not limited thereto.
  • the encoding device may also be based on a user setting or a system-defined check.
  • the processing time (or processing delay), the processing performance of the encoding device itself, and the like are used to determine the parallelism M. For example, if the user-set or system-specified verification processing time is short, the parallelism M can be made larger. To shorten the time for verification processing.
  • Fig. 6 is a diagram showing the basic principle of parallel processing of a CRC of an embodiment of the invention. As shown in FIG. 6, the encoding device can perform CRC check processing on the bit sequence Y in a parallel processing manner.
  • the encoding apparatus may perform a serial-to-parallel change processing on the bit sequence Y to obtain M bits processed by the i-th parity processing (ie, Y i to Y i+M-1 ), and thereafter, encoding
  • the device may multiply the Y i ⁇ Y i+M-1 by the matrix [R M-1 G R M-2 G ... G] to obtain ⁇ bits (ie, ).
  • the encoding device can make the matrix R M and the intermediate state of the last iteration Multiply the resulting ⁇ bits
  • the encoding device can make versus Modification 2 is performed to obtain ⁇ parity bits s 0 to s ⁇ -1 .
  • Equation 3 the degree of parallelism is M, that is, M bits are processed each time.
  • R M represents the multiplication of M R and T represents transposition.
  • Fig. 7 is a flow chart showing the parallel processing of the CRC of the embodiment of the invention in this case.
  • the encoding device may be based on the degree of parallelism of M 1 performs a verify process to give a bit string, and processing the bit sequence variation Y 7 And a bit that performs verification processing based on the degree of parallelism M 2 And based on the degree of parallelism M 1 pair of bits Perform check processing based on parallelism M 2 versus bit Perform verification processing.
  • the encoding apparatus may perform a serial-to-edge variation process on the bit sequence Y according to the determined degree of parallelism M 1 to obtain a bit and remaining bits based on the parallelism M 1 for the check processing, and determine according to the remaining bits.
  • the degree of parallelism of the remaining bits of the portion i.e., one of M 2--1 to M 2--q ) enables the remaining bits to be subjected to the check processing based on the determined degree of parallelism.
  • the length of the first bit sequence is an integer power of two.
  • the code length of the bit sequence Y (or the number of bits included) may be an integer power of 2, so that when determining the degree of parallelism, the selected degree of parallelism is The value is an integer power of 2, that is, it can ensure that the length of the bit sequence Y can be divisible by the parallelism M, and the parallel-based CRC check processing can be completed by using one parallelism, which greatly reduces the implementation complexity and saves The processing delay is therefore more suitable for practical system applications.
  • the object of the CRC check processing is information bits (ie, the bit sequence X in the embodiment of the present invention)
  • the coding block length specified by the LTE protocols 3GPP TS 36.212 and 3GPP TS 36.213 That is, the number of information bits of the input encoder is as long as the possible length after the rate is adapted.
  • the possible values of the number of information bits are 188, ranging from 40 to 6144. It is difficult to unify the parallelism of the CRC check processing. .
  • the manner of determining the degree of parallelism used in the foregoing embodiments of the present invention is merely exemplary, and the embodiment of the present invention is not limited thereto, if the length of the bit sequence Y (the first bit sequence) is the degree of parallelism M.
  • a maximum of two modules will be able to complete the verification process the verification process, wherein a degree of parallelism check processing module of M 1, the degree of parallelism is another check processing means M 2 .
  • check sequence W After the ⁇ check bits are generated as described above, the encoding device can use the ⁇ check bits as a check sequence (hereinafter, for ease of understanding and distinction, it is recorded as: check sequence W).
  • s 0 to s a in FIGS. 6 and 7 represent ⁇ parity bits in the above-described check sequence W.
  • the encoding device may determine the sequence Z of length N (ie, the second bit sequence according to the bit sequence Y (length N- ⁇ ) generated at S410 and the check sequence W (length ⁇ ) generated at S420. An example).
  • the bits in the bit sequence Y are located in the N- ⁇ first preset bits in the sequence Z, and the bits in the check sequence are located in the ⁇ of the sequence Z.
  • the second preset bit wherein the first preset bit and the second preset bit may be specified by the system, or may be determined by the encoding device and the decoding device.
  • the embodiment of the present invention is not particularly limited.
  • the second preset bit is after the first preset bit.
  • the encoding device may add the check sequence to the bit sequence Y to form the sequence Z. That is, in the embodiment of the present invention, the first preset bit may be in the bit sequence Y. The first N- ⁇ bits, the second predetermined bit may be the last ⁇ bits in the bit sequence Y.
  • the positional relationship between the bit sequence Y and the check sequence listed above is merely exemplary, and the embodiment of the present invention does not.
  • the positional relationship between the second preset bit and the first preset bit (or the bit relationship in the bit sequence Y and the positional relationship of the bit in the check sequence in the sequence Z) can be arbitrarily determined, as long as It is sufficient for the decoding device to determine the bit sequence Y and the check sequence from the bits Z in the sequence.
  • the encoding method further includes: the encoding device sends, to the decoding device, first indication information, where the first indication information is used to indicate a location of the first bit sequence in the second bit sequence, or the first The indication information is used to indicate the location of the parity bit in the second bit sequence.
  • the encoding device may further indicate the specific location of the first bit sequence (for example, the first preset bit) (ie, an example of the first indication information) and/or Or the indication information of the specific position of the check bit (for example, the second preset bit) (that is, another example of the first indication information) is sent to the decoding device, so that the decoding device can be based on the first indication information, A first bit sequence and a check sequence are determined from the second bit sequence.
  • the first bit sequence for example, the first preset bit
  • the indication information of the specific position of the check bit for example, the second preset bit
  • FIG. 9 is a diagram showing an example of an encoding process when the entire first bitcoin sequence is verified in the embodiment of the present invention.
  • the encoding device can insert a fixed bit in the information bit to acquire the bit sequence Y.
  • the encoding device can perform a check process on the sequence Y to obtain ⁇ check bits as the sub-check sequence W corresponding to the sequence Y.
  • the encoding device can add the check sequence W to the end of the sequence Y to obtain a sequence Z of length N, after which the encoding device can multiply the sequence Z by the kernel matrix to generate a polarization code.
  • the encoding device acquires a check sequence according to the first bit sequence, and includes:
  • the encoding device segments the first bit sequence to generate P sub-bit sequences, Each sub-bit sequence includes information bits and fixed bits, P ⁇ 2;
  • the encoding device obtains a check sequence according to the P sub-bit sequences, where the check sequence includes P sub-check sequences, and the P sub-bit sequences are in one-to-one correspondence with the P sub-check sequences, and each sub-check sequence is Generated from the corresponding sub-bit sequence.
  • the encoding device determines the check bit according to the P sub-bit sequences, including:
  • the encoding device determines the parallelism m corresponding to the p-th sub-bit sequence according to the length of the p-th sub-bit sequence, where m ⁇ 2, p ⁇ [1,P];
  • the encoding device performs a check process on the p-th sub-bit sequence according to the parallelism m corresponding to the p-th sub-bit sequence to obtain a sub-check bit corresponding to the p-th sub-bit sequence.
  • the encoding device may perform segmentation processing on the bit sequence Y to determine P sub-bit sequences.
  • the length of the sub-bit sequence may be specified by a system or a communication protocol, so that the decoding device can distinguish each of the received signals based on a system or a communication protocol. Bit sequence.
  • the encoding device may also determine the length of the sub-bit sequence autonomously.
  • the method further includes: the encoding device sends the second indication information to the decoding device, where the second indication information And indicating a position of each sub-bit sequence in the first bit sequence in the second bit sequence.
  • the decoding device can distinguish each sub-bit sequence from the received signal according to the second indication information.
  • the encoding device may separately perform CRC check processing on each sub-bit sequence to generate a sub-check sequence corresponding to each sub-bit sequence, that is, P sub-check sequences.
  • the check sequence W can be composed of the P sub-check sequences.
  • the method and the procedure for performing the CRC check processing on each sub-bit sequence by the encoding device may be similar to the above-described method and process for performing the CRC check processing on the entire bit sequence Y.
  • detailed description thereof will be omitted.
  • the length of the sub-check sequence may be specified by a system or a communication protocol, so that the decoding device can distinguish each of the received signals according to a system or a communication protocol. Sub-check sequence.
  • the encoding device may also determine the length of the sub-check sequence autonomously.
  • the length of the sub-check sequence may be the length of the corresponding sub-bit sequence
  • the decoding device can determine the length of the corresponding sub-check sequence according to the length of each sub-bit sequence.
  • the method further includes: the encoding end device sending the second indication information to the decoding device, where the second indication information is used to indicate that the sub-check sequence corresponding to each sub-bit sequence is in the second bit sequence. position.
  • the slave decoding device is capable of distinguishing each of the sub-check sequences from the received signals based on the second indication information.
  • sub-bit sequence Y p a sub-bit sequence corresponding to a sub-bit sequence (for ease of understanding and differentiation, recorded as: sub-bit sequence Y p ) (for ease of understanding and distinction, It is noted that the sub-bit sequence W p ) is used by the decoding device for the verification processing of the sub-bit sequence Y p (the specific process of the verification process will be described in detail later).
  • the lengths of the two sub-bit sequences may be the same or different, and the embodiment of the present invention is not particularly limited, as long as the length of the bit sequence Y is ensured to be N- ⁇ ;
  • the two sub-check sequences may be the same or different in length, and are not particularly limited in the embodiment of the present invention, as long as the length of the check sequence W formed by the P sub-check sequences is ⁇ .
  • each sub-bit sequence has a length that is an integer power of two.
  • the code length (or the number of bits included) of each sub-bit sequence may be an integer power of 2, so that the parallelism is selected when determining the degree of parallelism.
  • the value of the value is an integer power of 2, that is, it can ensure that the length of the sub-bit sequence can be divisible by the parallelism M, and only a parallel degree can be used to complete the CRC check processing based on the parallel mode, which greatly reduces the implementation complexity. Degree, saving processing delay, so it is more suitable for practical system applications.
  • the encoding device may determine the sequence Z of length N (ie, the second bit sequence according to the bit sequence Y (length N- ⁇ ) generated at S410 and the check sequence W (length ⁇ ) generated at S420. An example).
  • the bits in the bit sequence Y are located in the N- ⁇ first preset bits in the sequence Z, and the bits in the check sequence are located in the ⁇ second in the sequence Z.
  • the preset bit position, wherein the first preset bit bit and the second preset bit bit may be specified by the system, or may be determined by the encoding device and the decoding device.
  • the embodiment of the present invention is not particularly limited.
  • the second preset bit is after the first preset bit.
  • the encoding device may add the check sequence to the bit sequence.
  • the sequence Z is formed after the column Y, that is, in the embodiment of the present invention, the first preset bit may be the first N- ⁇ bits in the bit sequence Y, and the second preset bit may be in the bit sequence Y. The last ⁇ bits.
  • the positional relationship between the bit sequence Y and the check sequence listed above is merely exemplary, and the embodiment of the present invention does not.
  • the positional relationship between the second preset bit and the first preset bit (or the bit relationship in the bit sequence Y and the positional relationship of the bit in the check sequence in the sequence Z) can be arbitrarily determined, as long as It is sufficient for the decoding device to determine the bit sequence Y and the check sequence from the bits Z in the sequence.
  • each sub-bit sequence is adjacent to the corresponding sub-check sequence.
  • the encoding device may combine each sub-bit sequence with a sub-check sequence corresponding thereto, for example, a sub-check sequence corresponding thereto may be added at the end of each sub-bit sequence to form a sub-check sequence.
  • P bit sequences (referred to as sequence Z 1 to sequence Z P ), and the sequences Z 1 to Z P are combined to form a sequence Z.
  • the encoding apparatus 10 may be inserted in the fixed bit information bits to generate the sequence Y, thereafter, the encoding apparatus may be divided into a sequence Y of length ⁇ N- ⁇ promoter sequence Y 1 and a length of 1 (1 - ⁇ ) N- ⁇ 2 of the two sub-sequences Y 2.
  • the encoding device may be a sequence of length Y ⁇ N- ⁇ 1 1 performs a verify process to obtain [alpha] 1 parity bit, the sequence Y 1 corresponds to the sub-check sequence W 1. And, the encoding device can add the sub-check sequence W 1 to the end of the sequence Y 1 to obtain a sequence Z 1 of length ⁇ N.
  • the encoding apparatus may Y 2 N- ⁇ sequence of length 2 is (1- ⁇ ) check process, to give [alpha] 2 parity bits, the sequence Y 2 corresponding to the sub-check sequence W 2. And, the encoding device can add the sub-check sequence W 2 to the end of the sequence Y 2 to obtain a sequence Z 2 of length (1- ⁇ )N.
  • the encoding device can combine the sequence Z 1 and the sequence Z 2 to obtain a sequence Z of length N.
  • the sequence Z can be Y 1 W 1 Y 2 W 2 .
  • sequence Z listed above is merely exemplary, and the embodiment of the present invention is not limited thereto as long as the decoding device can accurately distinguish Y 1 , W 1 , Y 2 and W 2 from the sequence Z.
  • the sequence Z can also be Y 1 Y 2 W 1 W 2 .
  • the encoding device can multiply the sequence Z by the kernel matrix (ie, G N ), the final polarization codeword is obtained and transmitted to the decoding device.
  • G N the kernel matrix
  • the encoding device performs a check processing on the first bit sequence including the information bits and the fixed bits to determine a parity bit, and the first bit sequence is aligned with the school The bit is merged to generate a second bit sequence, and then the encoding device can generate a polarization code sequence according to the second bit sequence, so that the decoding device can decode the polarization code sequence to obtain the After the second bit sequence, the first bit sequence in the second bit sequence is subjected to a check process based on the check bits in the second bit sequence, that is, the verification process can be completed before the information bits are determined.
  • the estimation of the plurality of paths can be obtained.
  • the verification processing can be performed without acquiring the information bits in each path. Therefore, only the path through which the verification passes can be retained, and the information bits in the path through which the verification passes are used as the decoding output, which greatly shortens the delay of the decoding process and improves the user experience.
  • Method 500 includes:
  • the decoding device acquires a polarization code sequence.
  • the decoding device decodes the polarization code sequence to obtain at least one second bit sequence, where the second bit sequence includes a first bit sequence and a check sequence, where the check sequence is And generating, according to the first bit sequence, the first bit sequence, the information bit and the fixed bit, where the information bit is used to carry target information, where the fixed bit is used to carry preset information;
  • the decoding device acquires, according to the first bit sequence in each second bit sequence, a verification sequence corresponding to each second bit sequence, and according to the verification sequence and each of the second bit sequences.
  • a check sequence in the two-bit sequence, the target second bit sequence is determined from the at least one second bit sequence, wherein the verification sequence corresponding to the target second bit sequence and the check sequence in the target second bit sequence the same;
  • the decoding device determines, according to information bits in the target second bit sequence, target information transmitted by the encoding device.
  • the decoding device acquires the verification sequence corresponding to each second bit sequence according to the first bit sequence in each second bit sequence, including:
  • the decoding device determines the degree of parallelism M, M ⁇ 2 according to the length of the first bit sequence
  • the decoding device performs a check process on the first bit sequence according to the degree of parallelism M to obtain the check sequence.
  • the decoding device acquires the verification sequence corresponding to each second bit sequence according to the P sub-bit sequences in each second bit sequence, including:
  • the decoding device determines, according to the length of the p-th sub-bit sequence in each second bit sequence, a parallel degree m corresponding to the p-th sub-bit sequence, where m ⁇ 2, p ⁇ [1, P];
  • the decoding device performs a check process on the p-th sub-bit sequence according to the parallelism m corresponding to the p-th sub-bit sequence to obtain a sub-verification sequence corresponding to the p-th sub-bit sequence.
  • the decoding device receives the polarization code sequence transmitted by the encoding device.
  • the decoding device decodes the received polarization code sequence to obtain a decoding estimate of the polarization code sequence (ie, an example of a second bit sequence), wherein the decoding estimate A sequence corresponding to the bit sequence Y (that is, an example of the first bit sequence) and a sequence corresponding to the check sequence W (that is, an example of a check sequence) are included.
  • a decoding estimate of the polarization code sequence ie, an example of a second bit sequence
  • a decoding estimate (or a plurality of second bit sequences) of multiple paths can be acquired, and each path is The second bit sequence includes a first bit sequence and a verification sequence.
  • the second bit sequence #i includes N bits, wherein the first bit sequence in the second bit sequence #i (hereinafter, for ease of understanding and differentiation, is noted as: first bit The sequence #i) includes K- ⁇ information bits, and the first bit sequence #i includes NK fixed bits, and the check sequence in the second bit sequence #i (hereinafter, for ease of understanding and distinction, note : Check sequence #i) includes alpha check bits.
  • bit in the first bit sequence #i is located in a first preset bit in the second bit sequence #i
  • bit in the check sequence #i is located in the second preset in the second bit sequence #i Bit.
  • the specific location of the first preset bit and the second preset bit may be specified by a system or a communication protocol, so that the decoding device may determine from the second bit sequence according to the rule.
  • the first bit sequence and the check sequence may be specified by a system or a communication protocol, so that the decoding device may determine from the second bit sequence according to the rule.
  • the method further includes:
  • the decoding device Receiving, by the decoding device, the first indication information, where the first indication information is used to indicate the location of the first preset bit in the second bit sequence, or the first indication information is used to indicate the second a preset bit position in the second bit sequence;
  • the decoding device determines a first bit sequence and a check sequence in each second bit sequence according to the first indication information.
  • the encoding device may further indicate the specific location of the first preset bit (ie, an example of the first indication information) and/or the specific location of the second preset bit.
  • the indication information ie, another example of the first indication information
  • the indication information is sent to the decoding device, so that the decoding device can determine the first bit sequence #i and the second bit sequence #i according to the first indication information. Check sequence #i.
  • the check bit #i may be generated by the encoding device by the above manner 1.
  • the decoding device may perform CRC check processing on the entire first bit sequence #i to obtain a verification sequence #i for the entire first bit sequence #i, the verification sequence #i including ⁇
  • the process is similar to the process in which the encoding apparatus performs CRC check processing on the bit sequence Y as a whole to acquire a check sequence including ⁇ check bits.
  • the encoding apparatus performs CRC check processing on the bit sequence Y as a whole to acquire a check sequence including ⁇ check bits.
  • the decoding device may also perform the CRC check processing in a parallel manner.
  • the parallelism used by the decoding device may be the same as the parallelism used by the encoding device.
  • the embodiment of the present invention is not particularly limited.
  • the length of the first bit sequence is an integer power of two.
  • the degree of parallelism M is an integer power of two.
  • the parallel processing CRC check processing can be completed by using a parallel degree, which greatly reduces the implementation complexity and saves the processing delay, so it is more suitable for practical system applications.
  • the object of the CRC check processing is information bits (ie, the bit sequence X in the embodiment of the present invention)
  • the coding block length specified by the LTE protocols 3GPP TS 36.212 and 3GPP TS 36.213 That is, the number of information bits of the input encoder is as long as the possible length after the rate is adapted.
  • the possible values of the number of information bits are 188, ranging from 40 to 6144, it is difficult to unify the parallelism of the CRC check processing.
  • the decoding device can compare the verification sequence #i with the check sequence #i,
  • the decoding device may determine that the first bit sequence #i is verified, and at S540, the decoding device may extract the information bits from the first bit sequence #i, And acquiring target information carried in the information bits.
  • the decoding device may determine that the first bit sequence #i has not passed the verification, and may use the second bit sequence #i (or, the first bit sequence #i )give up.
  • the check bit may also be generated by the encoding device by the above manner 2.
  • the first bit sequence in each second bit sequence includes P sub-bit sequences, each sub-bit sequence includes information bits and fixed baud, P ⁇ 2, and each second bit sequence
  • the check sequence in the P test sequence includes P sub-check sequences, and the P sub-bit sequences are in one-to-one correspondence with the P sub-check sequences, and each sub-check sequence is generated according to the corresponding sub-bit sequence, and
  • the decoding device acquires a verification sequence corresponding to each second bit sequence according to a first bit sequence in each second bit sequence, and according to the verification sequence and each second bit corresponding to each second bit sequence a check sequence in the sequence, determining a target second bit sequence from the L second bit sequences, including:
  • the decoding device determines P sub-bit sequences and P sub-check sequences in each second bit sequence
  • the decoding device acquires a verification sequence corresponding to each second bit sequence according to P sub-bit sequences in each second bit sequence, where the verification sequence corresponding to each second bit sequence includes P sub-verification sequences.
  • the P sub-bit sequences are in one-to-one correspondence with the P sub-verification sequences, and each sub-verification sequence is generated according to the corresponding sub-bit sequence;
  • Decoding by the decoding device, a target second bit sequence according to P sub-verification sequences corresponding to each second bit sequence and P sub-check sequences in each second bit sequence, wherein, for the target second bit sequence Any sub-bit sequence, the sub-verification sequence corresponding to the sub-bit sequence is the same as the sub-check sequence corresponding to the sub-bit sequence.
  • the decoding device is configured according to the first bit sequence in each second bit sequence.
  • Obtaining a verification sequence corresponding to each second bit sequence including:
  • the decoding device determines the degree of parallelism M, M ⁇ 2 according to the length of the first bit sequence
  • the decoding device performs a check process on the first bit sequence according to the degree of parallelism M to obtain the check sequence.
  • the decoding device may determine each sub-bit sequence included in the first bit sequence #i, and check each sub-check sequence included in the sequence #i.
  • each sub-bit sequence and the length and position of each sub-check sequence may be specified by a system or a communication protocol, so that the decoding device can distinguish each sub-bit sequence according to the specification. And each sub-check sequence.
  • the method further includes:
  • the decoding end device receives the second indication information sent by the encoding device, the second indication information is used to indicate each sub-bit sequence in the first bit sequence, and the second indication information is used to indicate each sub-bit sequence The corresponding sub-check sequence.
  • the encoding device may further send, to the decoding device, indication information of a position of each sub-bit sequence in the second bit sequence #i, and each sub-check sequence is in the second bit.
  • the indication information of the position in the sequence #i that is, an example of the second indication information
  • the decoding device can distinguish each sub-bit sequence and each sub-check sequence according to the second indication information.
  • the decoding device may perform CRC check processing on each sub-bit sequence to obtain a verification sequence corresponding to each sub-bit sequence (represented as: a sub-verification sequence), wherein all sub-verification sequences include a total
  • the process is similar to the process in which the encoding device performs CRC check processing on each sub-bit sequence to obtain each sub-check sequence.
  • a detailed description thereof will be omitted.
  • each sub-bit sequence has a length that is an integer power of two.
  • the degree of parallelism M is an integer power of two.
  • the parallel used in determining the CRC check processing for each sub-bit sequence is determined.
  • degree as long as the value of the selected degree of parallelism is an integer power of 2, only a parallel degree can be used to complete the CRC check processing based on the parallel mode, which greatly reduces the implementation complexity and saves processing time. It is more suitable for practical system applications.
  • the object of the CRC check processing is information bits (ie, the bit sequence X in the embodiment of the present invention)
  • the LTE protocol 3GPP TS 36.212 and 3GPP TS The length of the coding block specified in 36.213 (that is, the number of information bits of the input encoder) and the possible length after the rate adaptation are taken as an example.
  • the possible values of the number of information bits are 188, ranging from 40 to 6144, which is difficult to unify.
  • the degree of parallelism of the CRC check processing is the degree of parallelism of the CRC check processing.
  • the decoding apparatus may determine that the sub-verification sequence corresponding to each sub-sequence in the first bit sequence #i is acquired without loss of generality, and the j-th sub-sequence in the first bit sequence #i is recorded.
  • the sub-verification sequence corresponding to the sub-sequence #j) is recorded as the sub-verification sequence #j
  • the sub-check sequence corresponding to the sub-sequence #j in the check sequence #i is recorded as: sub-check sequence #j.
  • the decoding device can compare the sub-verification sequence #j with the sub-check sequence #j,
  • the decoding device may determine that the sub-sequence #j passes the verification
  • the decoding device may determine that the sub-sequence #j has not passed the verification, and may, in the first bit sequence #i (or the second bit sequence #) i) Discard.
  • the decoding device can determine a second bit sequence (represented as a target second bit sequence) in which all subsequences in the multiplexed second sequence pass the verification, and at S440, the decoding device can obtain the second bit from the target.
  • the information bits are extracted from the first bit sequence included in the sequence, and the target information carried in the information bits is obtained.
  • a decoding apparatus may perform a decoding process based on an SCL decoding algorithm on a received plan to acquire a second bit sequence of L paths (including a first bit sequence and a check bit), after which the decoding device may perform a check process on the first bit sequence in the second bit sequence of each path to obtain a verification bit for each path, and further, the decoding device
  • the verification bit and the check bit of each path may be compared, so that the decoding device can determine a path in which the verification bit and the parity bit are the same as the path through which the verification passes, and from the second bit sequence of the path
  • the information bits are extracted and the information sent for the encoded segment is determined.
  • a method for decoding a polarization code performs a check process on a first bit sequence including information bits and fixed bits to determine a parity bit, and the first bit sequence is associated with the school
  • the bit is merged to generate a second bit sequence, and then the encoding device can generate a polarization code sequence according to the second bit sequence, so that the decoding device can decode the polarization code sequence to obtain the
  • the first bit sequence in the second bit sequence is subjected to a check process based on the check bits in the second bit sequence, ie, can be determined
  • the verification process is completed before the information bits.
  • the estimation of the plurality of paths can be obtained.
  • the verification processing can be performed without acquiring the information bits in each path. Therefore, only the path through which the verification passes can be retained, and the information bits in the path through which the verification passes are used as the decoding output, which greatly shortens the delay of the decoding process and improves the user experience.
  • FIG. 13 is a block diagram showing the structure of a coding apparatus 600 for a polarization code according to an embodiment of the present invention.
  • the encoding apparatus 600 of the polarization code shown in FIG. 13 includes a generating unit 610, a checking unit 620 connected to the generating unit 610, and an encoding unit 630 connected to the checking unit 620 and the generating unit 610.
  • the generating unit 610 is configured to generate a first bit sequence according to the target information that needs to be transmitted to the decoding device, where the first bit sequence includes information bits and fixed bits, where the information bits are used to carry the target information, the fixed bit Used to carry preset information.
  • the check unit 620 is configured to acquire the first bit sequence from the generating unit 610, and determine a check bit according to the first bit sequence. ;
  • the coding unit 630 is configured to acquire the first bit sequence from the generating unit 610, obtain the check bit from the check unit 620, and generate a second bit sequence according to the first bit sequence and the check bit, and further use A polarization code sequence is generated based on the second bit sequence.
  • the checking unit is specifically configured to determine, according to the length of the first bit sequence, a degree of parallelism M, M ⁇ 2;
  • the encoding device further includes:
  • a sending unit configured to send, to the decoding device, first indication information, where the first indication information is used to indicate that the first preset bit is in the second bit sequence, or
  • the first indication information is used to indicate the location of the second preset bit in the second bit sequence.
  • the check unit is specifically configured to perform segmentation processing on the first bit sequence to generate P sub-bit sequences, each sub-bit sequence including information bits and fixed bits, P ⁇ 2;
  • the checking unit is specifically configured to determine, according to the length of the pth sub-bit sequence, a degree of parallelism corresponding to the p-th sub-bit sequence, where p ⁇ [1, P];
  • the encoding device further includes:
  • a sending unit configured to send, to the decoding device, second indication information, where the second indication information is used to indicate each sub-bit sequence in the first bit sequence, and the second indication information is used to indicate each sub-bit sequence The corresponding sub-check sequence.
  • the encoding apparatus 600 of the polarization code according to the embodiment of the present invention may correspond to an implementation body of the encoding method 500 of the polarization code of the embodiment of the present invention, and each unit in the encoding apparatus 600 of the polarization code and the other operations described above For the sake of brevity, the detailed description of the encoding method 500 of the polarization code in FIG. 4 is omitted.
  • An encoding apparatus for a polarization code by performing a check processing on a first bit sequence including information bits and fixed bits, to determine a parity bit, and the first bit sequence and the school The bit is merged to generate a second bit sequence, and then the encoding device can generate a polarization code sequence according to the second bit sequence, so that the decoding device can decode the polarization code sequence to obtain the After the second bit sequence, the first bit sequence in the second bit sequence is subjected to a check process based on the check bits in the second bit sequence, that is, the verification process can be completed before the information bits are determined.
  • the estimation of the plurality of paths can be obtained.
  • the verification processing can be performed without acquiring the information bits in each path. Therefore, only the path through which the verification passes can be retained, and the information bits in the path through which the verification passes are used as the decoding output, which greatly shortens the delay of the decoding process and improves the user experience.
  • FIG. 14 is a block diagram showing the structure of a decoding apparatus 700 for a polarization code according to an embodiment of the present invention.
  • the decoding apparatus 700 of the polarization code shown in FIG. 14 includes: an obtaining unit 710, a decoding unit 720 connected to the obtaining unit 710, and a checking unit 730 connected to the decoding unit, connected to the checking unit 730 Determination unit 740.
  • the obtaining unit 710 is configured to acquire a polarization code sequence.
  • the decoding unit 720 is configured to perform decoding processing on the polarization code sequence acquired from the acquiring unit 710 to obtain at least one second bit sequence, where the second bit sequence includes the first a first bit sequence of the preset bit and a check bit located at the second preset bit, wherein the check bit is generated based on the first bit sequence, the first bit sequence includes information bits and fixed bits, The information bit is used to carry target information, and the fixed bit is used to carry preset information.
  • the verifying unit 730 is configured to acquire, according to the first bit sequence in each second bit sequence acquired from the decoding unit 720, the verification bit corresponding to each second bit sequence, and according to each second bit sequence Corresponding verification bits and check bits in each second bit sequence, determining a target second bit sequence from the at least one second bit sequence, wherein the verification bit corresponding to the target second bit sequence and the target
  • the parity bits in the two-bit sequence are the same;
  • the determining unit 740 is configured to determine target information transmitted by the encoding device according to the information bits in the target second bit sequence acquired from the checking unit 730.
  • the checking unit is specifically configured to determine, according to the length of the first bit sequence, a degree of parallelism M, M ⁇ 2;
  • the decoding device further includes:
  • a receiving unit configured to receive, by the encoding device, first indication information, where the first indication information is used to indicate a location of the first preset bit in the second bit sequence, or the first indication information is used to indicate the first Positioning two preset bits in the second bit sequence;
  • the checking unit is further configured to determine a first bit sequence and a check bit in each second bit sequence according to the first indication information.
  • the first bit sequence in each second bit sequence includes P sub-bit sequences, each sub-bit sequence includes information bits and fixed bits, P ⁇ 2, and check bits in each second bit sequence Include P sub-check bits, the P sub-bit sequences are in one-to-one correspondence with the P sub-check bits, and each sub-check bit is generated according to the corresponding sub-bit sequence, and
  • the decoding unit is specifically configured to determine P sub-bit sequences and P sub-check bits in each second bit sequence
  • each second bit sequence is obtained according to the P sub-bit sequences in each second bit sequence, where the verification bits corresponding to each second bit sequence include P sub-verification bits, and the P a sub-bit sequence is corresponding to the P sub-verification bits, and each sub-verification bit is generated according to the corresponding sub-bit sequence;
  • the target second bit sequence is determined, wherein, for any sub-bit sequence in the target second bit sequence, the sub-verification bit corresponding to the sub-bit sequence and the sub-bit sequence corresponding to the sub-bit sequence
  • the sub-check bits are the same.
  • the checking unit is specifically configured to determine, according to the length of the p-th sub-bit sequence in each second bit sequence, a parallel degree m corresponding to the p-th sub-bit sequence, where m ⁇ 2, p ⁇ [1,P];
  • the decoding device further includes:
  • a receiving unit configured to receive second indication information that is sent by the encoding device, where the second indication information is used to indicate each sub-bit sequence in the first bit sequence, and the second indication information is used to indicate each sub-bit sequence The corresponding sub-check sequence.
  • the decoding apparatus 700 of the polarization code according to the embodiment of the present invention may correspond to an implementation body of the decoding method 500 of the polarization code of the embodiment of the present invention, and each unit in the decoding apparatus 700 of the polarization code
  • the other operations and/or functions described above are respectively implemented in order to implement the corresponding process of the polarization code decoding method 500 in FIG. 11. For brevity, details are not described herein again.
  • a decoding apparatus for a polarization code by performing a check processing on a first bit sequence including information bits and fixed bits, to determine a parity bit, and the first bit sequence and the The parity bits are combined to generate a second bit sequence, and then the encoding device can generate a polarization code sequence according to the second bit sequence, so that the decoding device can obtain the polarization code sequence by performing decoding processing.
  • the first bit sequence in the second bit sequence is subjected to a check process based on the check bits in the second bit sequence, that is, the verification process can be completed before the information bits are determined.
  • the estimation of the plurality of paths can be obtained.
  • the verification processing can be performed without acquiring the information bits in each path. Therefore, only the path through which the verification passes can be retained, and the information bits in the path through which the verification passes are used as the decoding output, which greatly shortens the delay of the decoding process and improves the user experience.
  • Fig. 15 is a schematic configuration diagram of an encoding apparatus to which a polarization code of an embodiment of the present invention is applied.
  • the device 800 includes a processor 810 and a transmitter 820.
  • the processor 810 is connected to the transmitter 820.
  • the device 800 further includes a memory 830.
  • the memory 830 is connected to the processor 810, and further Optionally, the device 800 includes a bus system 840.
  • the processor 810, The memory 820 and the transmitter 830 may be connected by a bus system 840, which may be used to store instructions for executing instructions stored in the memory 830 to control the receiver 820 to receive information or signals;
  • the processor 810 is configured to generate a first bit sequence according to the target information that needs to be transmitted to the decoding device, where the first bit sequence includes information bits and fixed bits, where the information bits are used to carry the target information, and the fixed bits are used for carrying Default information;
  • the processor 810 is configured to determine a check bit according to the first bit sequence
  • the processor 810 is configured to generate a second bit sequence according to the first bit sequence and the check bit.
  • the processor 810 is configured to generate a polarization code sequence according to the second bit sequence.
  • the processor is specifically configured to determine, according to the length of the first bit sequence, a degree of parallelism M, M ⁇ 2;
  • the processor is specifically configured to perform a check process on the first bit sequence according to the degree of parallelism M to obtain the check bit.
  • the encoding device further includes a transmitter connected to the bus;
  • the processor is further configured to control the transmitter to send the first indication information to the decoding device, where the first indication information is used to indicate the location of the first bit sequence in the second bit sequence, or the first indication information is used by The location of the parity bit in the second bit sequence is indicated.
  • the processor is specifically configured to perform segmentation processing on the first bit sequence to generate P sub-bit sequences, each sub-bit sequence includes information bits and fixed bits, P ⁇ 2;
  • the processor is specifically configured to determine a check bit according to the P sub-bit sequences, where the check bit includes P sub-check bits, and the P sub-bit sequences are in one-to-one correspondence with the P sub-check bits, and each sub-school The check bits are generated based on the corresponding sub-bit sequence.
  • the processor is specifically configured to determine, according to the length of the p-th sub-bit sequence, a parallel degree m corresponding to the p-th sub-bit sequence, where m ⁇ 2, p ⁇ [1, P];
  • the processor is specifically configured to perform a check process on the p-th sub-bit sequence according to the degree of parallelism corresponding to the p-th sub-bit sequence to obtain a sub-check bit corresponding to the p-th sub-bit sequence.
  • the encoding device further includes a transmitter connected to the bus;
  • the processor is further configured to control the transmitter to send second indication information to the decoding device, where the second indication information is used to indicate that each sub-bit sequence in the first bit sequence is in the second bit sequence And the second indication information is used to indicate a position of the sub-check sequence corresponding to each sub-bit sequence in the second bit sequence.
  • the encoding device can be embedded or itself an access terminal or a network device.
  • the encoding apparatus 800 of the polarization code according to the embodiment of the present invention may correspond to an implementation body of the encoding method 500 of the polarization code of the embodiment of the present invention, and each unit in the encoding apparatus 800 of the polarization code and the other operations described above For the sake of brevity, the detailed description of the encoding method 500 of the polarization code in FIG. 4 is omitted.
  • An encoding apparatus for a polarization code by performing a check processing on a first bit sequence including information bits and fixed bits, to determine a parity bit, and the first bit sequence and the school The bit is merged to generate a second bit sequence, and then the encoding device can generate a polarization code sequence according to the second bit sequence, so that the decoding device can decode the polarization code sequence to obtain the After the second bit sequence, the first bit sequence in the second bit sequence is subjected to a check process based on the check bits in the second bit sequence, that is, the verification process can be completed before the information bits are determined.
  • the estimation of the plurality of paths can be obtained.
  • the verification processing can be performed without acquiring the information bits in each path. Therefore, only the path through which the verification passes can be retained, and the information bits in the path through which the verification passes are used as the decoding output, which greatly shortens the delay of the decoding process and improves the user experience.
  • Figure 16 is a schematic configuration diagram of a decoding apparatus to which a polarization code of an embodiment of the present invention is applied.
  • the device 900 includes a processor 910 and a receiver 920.
  • the processor 910 is connected to the receiver 920.
  • the device 900 further includes a memory 930.
  • the memory 930 is connected to the processor 910, and further Optionally, the device 900 includes a bus system 940.
  • the processor 910, the memory 920, and the transmitter 930 may be connected by a bus system 940, where the memory 930 may be used to store instructions for executing the instructions stored in the memory 930 to control the receiver 920 to receive information or signal;
  • the processor 910 is configured to acquire a polarization code sequence
  • the processor 910 is configured to perform decoding processing on the polarization code sequence to obtain at least one second bit sequence, where the second bit sequence includes a first bit sequence and a check bit, where the check bit is And generating, according to the first bit sequence, the first bit sequence, the information bit and the fixed bit, where the information bit is used to carry target information, where the fixed bit is used to carry preset information;
  • the processor 910 is configured to acquire each according to a first bit sequence in each second bit sequence. a verification bit corresponding to the second bit sequence, and determining a target second bit from the at least one second bit sequence according to the verification bit corresponding to each second bit sequence and the parity bit in each second bit sequence a sequence, wherein the verification bit corresponding to the second bit sequence of the target is the same as the parity bit in the target second bit sequence;
  • the processor 910 is configured to determine target information transmitted by the encoding device according to the information bits in the target second bit sequence.
  • the processor is specifically configured to determine, according to the length of the first bit sequence, a degree of parallelism M, M ⁇ 2;
  • the processor is specifically configured to perform a check process on the first bit sequence according to the degree of parallelism M to obtain the check bit.
  • the decoding device further includes a receiver connected to the bus;
  • the processor is further configured to control the receiver to receive the encoding device to send first indication information, where the first indication information is used to indicate a location of the first bit sequence in the second bit sequence, or the first indication information is used for Indicates the location of the parity bit in the second bit sequence.
  • the first bit sequence in each second bit sequence includes P sub-bit sequences, each sub-bit sequence includes information bits and fixed baud, P ⁇ 2, and the check in each second bit sequence
  • the bit includes P sub-check bits, the P sub-bit sequences are in one-to-one correspondence with the P sub-check bits, and each sub-check bit is generated according to the corresponding sub-bit sequence
  • the processor is specifically configured to determine P sub-bit sequences and P sub-check bits in each second bit sequence
  • the processor is specifically configured to obtain, according to P sub-bit sequences in each second bit sequence, verification bits corresponding to each second bit sequence, where the verification bits corresponding to each second bit sequence include P sub-verifications. a bit, the P sub-bit sequences are in one-to-one correspondence with the P sub-verification bits, and each sub-verification bit is generated according to the corresponding sub-bit sequence;
  • the processor is specifically configured to determine a target second bit sequence according to P sub-verification bits corresponding to each second bit sequence and P sub-check bits in each second bit sequence, where, for the target second bit sequence Any sub-bit sequence in which the sub-verification bit corresponding to the sub-bit sequence is the same as the sub-check bit corresponding to the sub-bit sequence.
  • the processor is specifically configured to determine, according to the length of the p-th sub-bit sequence in each second bit sequence, a parallel degree m corresponding to the p-th sub-bit sequence, where m ⁇ 2, p ⁇ [ 1,P];
  • the processor is specifically configured to perform a check process on the p-th sub-bit sequence according to the parallelism m corresponding to the p-th sub-bit sequence to obtain a sub-verification bit corresponding to the p-th sub-bit sequence.
  • the decoding device further includes a receiver connected to the bus;
  • the processor is further configured to control the receiver to receive the second indication information sent by the encoding device, where the second indication information is used to indicate a position of each sub-bit sequence in the first bit sequence in the second bit sequence, And, the second indication information is used to indicate a position of the sub-check sequence corresponding to each sub-bit sequence in the second bit sequence.
  • the decoding device can be embedded or itself an access terminal or a network device.
  • the decoding device 900 of the polarization code according to the embodiment of the present invention may correspond to an implementation body of the decoding method 500 of the polarization code of the embodiment of the present invention, and each unit in the decoding device 900 of the polarization code
  • the other operations and/or functions described above are respectively implemented in order to implement the corresponding process of the polarization code decoding method 500 in FIG. 11. For brevity, details are not described herein again.
  • a decoding apparatus for a polarization code by performing a check processing on a first bit sequence including information bits and fixed bits, to determine a parity bit, and the first bit sequence and the The parity bits are combined to generate a second bit sequence, and then the encoding device can generate a polarization code sequence according to the second bit sequence, so that the decoding device can obtain the polarization code sequence by performing decoding processing.
  • the first bit sequence in the second bit sequence is subjected to a check process based on the check bits in the second bit sequence, that is, the verification process can be completed before the information bits are determined.
  • the estimation of the plurality of paths can be obtained.
  • the verification processing can be performed without acquiring the information bits in each path. Therefore, only the path through which the verification passes can be retained, and the information bits in the path through which the verification passes are used as the decoding output, which greatly shortens the delay of the decoding process and improves the user experience.
  • Access terminal 1000 includes a receiver 1002 for receiving signals from, for example, a receiving antenna (not shown) and performing typical actions (e.g., filtering, amplifying, downconverting, etc.) on the received signals, and adjusting The resulting signal is digitized to obtain samples.
  • Receiver 1002 may be, for example, an MMSE (Minimum Mean-Squared Error) receiver.
  • Access terminal 1000 can also include a demodulator 1004 that can be used to demodulate received signals and provide them to processor 1006 for channel estimation.
  • MMSE Minimum Mean-Squared Error
  • Processor 1006 It may be a processor dedicated to analyzing information received by receiver 1002 and/or generating information transmitted by transmitter 1016, a processor for controlling one or more components of access terminal 1000, and/or for analysis A signal received by receiver 1002, a controller that generates information transmitted by transmitter 1016 and controls one or more components of access terminal 1000.
  • Access terminal 1000 can additionally include a memory 1008 operatively coupled to processor 1006 and storing the following data: data to be transmitted, received data, and any other related to performing various actions and functions described herein. Suitable for information.
  • the memory 1008 can additionally store associated protocols and/or algorithms for polarization code processing.
  • receiver 1002 can also be coupled to polarization code decoder 1012 and rate matching device (not shown).
  • the polarization code decoder 1012 may perform the specific process of the above method 500 under the control of the processor 1006.
  • access terminal 1000 can also include a modulator 1014 and a transmitter 1016 for transmitting signals to, for example, a base station, another access terminal, and the like.
  • the transmitter 1016 can also be coupled to a polarization code encoder 1018 and a rate matching device (not shown).
  • the polarization code encoder 1018 may perform the specific process of the above method 400 under the control of the processor 1006.
  • the polarization code decoder 1012 or the polarization code r encoder 1018 in FIG. 17 is separate from the processor 1006, it will be understood that the polarization code decoder 1012 or the polarization code r encoder 1018 may also be processed.
  • the receiver 1002 and the transmitter 1016 can also be integrated together in a practical application to form a transceiver.
  • Network device 1100 is a diagram of a network device 1100 that facilitates execution of an encoding method or a decoding method of the aforementioned polarization code in a wireless communication system.
  • Network device 1100 has a receiver 1110 that receives signals from one or more access terminals through a plurality of receive antennas 1106, and a transmitter 1124 that transmits signals to one or more access terminals through transmit antennas 11011.
  • the "receiver antenna” and the "transmit antenna” can be integrated to form a transceiver antenna.
  • Receiver 1110 can receive information from receive antenna 1106 and is operatively associated to a demodulator 1112 that demodulates received information.
  • the demodulated symbols are analyzed by a processor 1114 that is coupled to a memory 1120 for storing data to be transmitted to an access terminal (or a different base station) or from an access terminal (or different Base station) data received and/or associated with performing various actions and functions described herein Any other suitable information.
  • Receiver 1110 and processor 1114 can also be coupled to polarization code decoder 1116 and rate matching devices (not shown).
  • the polarization code decoder 1116 can perform the specific process of the above method 500 under the control of the processor 1114.
  • network device 1100 can also include a modulator 1122 and a transmitter 1124 for transmitting signals to, for example, a base station, another access terminal, and the like.
  • Transmitter 1124 and processor 1114 can also be coupled to polarization code encoder 1118 and rate matching device (not shown).
  • the polarization code encoder 1118 can perform the specific process of the above method 400 under the control of the processor 1114.
  • polarization code encoder 1116 or polarization code decoder 1116 is separate from processor 1114 in FIG. 18, it will be appreciated that polarization code encoder 1116 or polarization code decoder 1116 may be processor 614 or A portion of a plurality of processors (not shown).
  • the processor may be an integrated circuit chip with signal processing capabilities.
  • each step of the foregoing method embodiment may be completed by an integrated logic circuit of hardware in a processor or an instruction in a form of software.
  • the processor may be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a Field Programmable Gate Array (FPGA), or the like. Programming logic devices, discrete gates or transistor logic devices, discrete hardware components.
  • the methods, steps, and logical block diagrams disclosed in the embodiments of the present invention may be implemented or carried out.
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the steps of the method disclosed in the embodiments of the present invention may be directly implemented as a hardware decoding processor, or may be performed by a combination of hardware and software modules in the decoding processor.
  • the software module can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the storage medium is located in the memory, and the processor reads the information in the memory and combines the hardware to complete the steps of the above method.
  • the memory in the embodiments of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be a read-only memory (ROM), a programmable read only memory (PROM), an erasable programmable read only memory (Erasable PROM, EPROM), and a Erasable programmable read only memory (EEPROM) or flash memory.
  • the volatile memory can be a Random Access Memory (RAM) that acts as an external cache.
  • RAM Random Access Memory
  • many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (Synchronous DRAM).
  • SDRAM Double Data Rate SDRAM
  • DDR SDRAM Double Data Rate SDRAM
  • ESDRAM Enhanced Synchronous Dynamic Random Access Memory
  • SLDRAM Synchronous Connection Dynamic Random Access Memory
  • DR RAM direct memory bus random access memory
  • the embodiments described herein can be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof.
  • the processing unit may implement other electronics for performing the functions described herein in one or more ASICs, DSPs, DSPDs, PLDs, FPGAs, processors, controllers, microcontrollers, microprocessors, chips, and the like. Unit or combination thereof.
  • a code segment can represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software group, a class, or any combination of instructions, data structures, or program statements.
  • a code segment can be combined into another code segment or hardware circuit by transmitting and/or receiving information, data, arguments, parameters or memory contents. Information, arguments, parameters, data, etc. can be communicated, forwarded, or transmitted using any suitable means including memory sharing, messaging, token passing, network transmission, and the like.
  • the techniques described herein can be implemented by modules (eg, procedures, functions, and so on) that perform the functions described herein.
  • the software code can be stored in memory and executed by the processor.
  • the memory unit can be implemented in the processor or external to the processor, in the latter case the memory unit can be communicatively coupled to the processor via various means known in the art.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in the embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the functions may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a standalone product. Based on such understanding, the technical solution of the embodiments of the present invention, or the part contributing to the prior art or the part of the technical solution, may be embodied in the form of a software product stored in a storage medium.
  • the instructions include a plurality of instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method of the embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read only memory (ROM, Read-Only) Memory, random access memory (RAM), disk or optical disk, and other media that can store program code.

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Abstract

一种极化码的编码方法、译码方法、编码装置和译码装置，该编码方法，包括：编码设备根据需要传输至译码设备的目标信息，生成第一比特序列，该第一比特序列包括信息比特和固定比特，该信息比特用于承载该目标信息，该固定比特用于承载预设信息（S410）；该编码设备根据该第一比特序列，确定校验比特（S420）；该编码设备根据该第一比特序列和该校验比特，生成第二比特序列（S430）；该编码设备根据该第二比特序列，生成极化码序列（S440）。能够减小译码处理的延时，改善用户体验。

Description

极化码的编码方法、译码方法、编码设备和译码设备
本申请要求于2016年2月24日提交中国专利局、申请号为201610102402.1、发明名称为“极化码的编码方法、译码方法、编码设备和译码设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明实施例涉及通信领域，并且更具体地，涉及极化码的编码方法、译码方法、编码设备和译码设备。
背景技术
通信系统通常采用信道编码提高数据传输的可靠性，以保证通信的质量。其中，极化(Polar)码是第一个从理论上证明可以取得香农容量且具有低编译码复杂度的好码。
在循环冗余校验(CRC，Cyclic Redundancy Check)辅助下，采用增强传统的串行抵消(SC，Successive Cancellation)译码算法，例如，基于SC算法改进得到的串行抵消列表(SCL，Successive Cancellation List)译码算法、串行抵消堆栈(SCS，Successive Cancellation Stack)译码算法和串行抵消混合(SCH，Successive Cancellation Hybrid)译码算法等，能够显著提高Polar码的误帧率(Frame Error Rate，FER)性能。
在编码端，在现有的Polar码和CRC校验级联过程时，通过以下步骤进行：
1.对长度为K－α的序列X(即，用于承载待发送的信息)，添加长度为α的CRC校验码，得到长度为K的序列Y，即，将添加了CRC校验码的序列Y作为信息比特；
2.对上述序列Y进行码率为K/N的Polar码编码。即，首先，对序列Y插入N－K个固定比特(通常为0)，得到长度为N的序列Z，并使Z序列乘以核矩阵，得到最终的Polar码序列。
此情况下，在译码端，需要获取所接收到的Polar码序列中的信息比特的估值后，才能够进行CRC校验，特别是在基于SCL译码算法等的译码过程中，能够获得多个路径的估值，即，需要获取每个路径中的信息比特之后， 才能够进行CRC校验，大大增加了译码处理的延时，影响用户体验。
发明内容
本发明实施例提供一种极化码的编码方法、译码方法、编码装置和译码装置，能够减小译码处理的延时，改善用户体验。
第一方面，提供了一种极化码的编码方法，包括：编码设备根据需要传输至译码设备的目标信息，生成第一比特序列，该第一比特序列包括信息比特和固定比特，该信息比特用于承载该目标信息，该固定比特用于承载预设信息；该编码设备根据该第一比特序列，确定校验比特；该编码设备根据该第一比特序列和该校验比特，生成第二比特序列；该编码设备根据该第二比特序列，生成极化码序列。
结合第一方面及其上述实现方式，在第一方面的第一种实现方式中，在该第二比特序列中，该校验比特在该第一比特序列之后。从而能够满足现有通信标准中对待校验比特和校验比特的位置关系的要求。
结合第一方面及其上述实现方式，在第一方面的第二种实现方式中，该编码设备根据该第一比特序列，确定校验比特，包括：该编码设备根据该第一比特序列的长度，确定并行度M，M≥2；该编码设备根据该并行度M，对该第一比特序列进行校验处理，以获取该校验比特。
通过基于并行度M，同时进行针对该第一比特序列中的M个比特的校验处理，能够缩短校验处理的时间，减小传输时延。
结合第一方面及其上述实现方式，在第一方面的第三种实现方式中，并行度M为2的整数次幂。并且，该第一比特序列的长度为2的整数次幂。
通过使并行度M和第一比特序列的长度为2的整数次幂，能够容易地获得并行度M。
结合第一方面及其上述实现方式，在第一方面的第四种实现方式中，该方法还包括：该编码设备向该译码设备发送第一指示信息，该第一指示信息用于指示该第一比特序列在该第二比特序列中位置，或该第一指示信息用于指示该校验比特在该第二比特序列中位置。
通过向译码设备发送第一指示信息，能够使译码设备根据该第一指示信息从第二比特序列中区分第一比特序列和校验比特，从而能够提高编码设备生成该第二比特序列时的灵活度，具体地说，能够提高编码设备确定第一比 特序列和校验比特的位置关系时的灵活度。
结合第一方面及其上述实现方式，在第一方面的第五种实现方式中，该编码设备根据该第一比特序列，确定校验比特，包括：该编码设备对该第一比特序列进行分段处理，以生成P个子比特序列，每个子比特序列包括信息比特和固定比特，P≥2；该编码设备根据该P个子比特序列，确定校验比特，其中，该校验比特包括P个子校验比特，该P个子比特序列与该P个子校验比特一一对应，每个子校验比特是根据该对应的子比特序列生成的。
通过对第一比特序列进行分段处理，能够使编码设备和译码设备并行地对第一比特序列中的个子比特序列进行校验处理，能够缩短校验处理的时间，减小传输时延。
结合第一方面及其上述实现方式，在第一方面的第六种实现方式中，在第二比特序列中，每个子比特序列与所对应的子校验比特相邻。
通过使每个子比特序列与所对应的子校验比特相邻配置，能够容易地确定各子比特序列所对应的子校验比特。
结合第一方面及其上述实现方式，在第一方面的第七种实现方式中，在第二比特序列中，每个子比特序列位于所对应的子校验比特之前。从而能够满足现有通信标准中对待校验比特和校验比特的位置关系的要求。
结合第一方面及其上述实现方式，在第一方面的第八种实现方式中，该编码设备根据该P个子比特序列，确定校验比特，包括：该编码设备根据第p个子比特序列的长度，确定该第p个子比特序列所对应的并行度m，其中，m≥2，p∈[1，P]；该编码设备根据该第p个子比特序列所对应的并行度，对该第p个子比特序列进行校验处理，以获取该第p个子比特序列所对应的子校验比特。
通过基于并行度m，同时进行针对一个子比特序列的m个比特的校验处理，能够缩短校验处理的时间，减小传输时延。
结合第一方面及其上述实现方式，在第一方面的第九种实现方式中，该方法还包括：该编码端设备向该译码设备发送第二指示信息，该第二指示信息用于指示该第一比特序列中的每个子比特序列在该第二比特序列中的位置，并且，该第二指示信息用于指示每个子比特序列所对应的子校验序列在该第二比特序列中的位置。
通过向译码设备发送第二指示信息，能够使译码设备根据该第二指示信 息从第二比特序列中区分每个子比特序列以及每个子比特序列所对应的子校验序列，从而能够提高编码设备生成该第二比特序列时的灵活度，具体地说，能够提高编码设备确定每个子比特序列以及每个子比特序列所对应的子校验序列的位置关系时的灵活度。
结合第一方面及其上述实现方式，在第一方面的第十种实现方式中，每个子比特序列的长度为2的整数次幂。并且，并行度m为2的整数次幂。
通过使并行度m和第一比特序列的长度为2的整数次幂，能够容易地获得并行度m。
第二方面，提供了一种极化码的译码方法，包括：译码设备获取极化码序列；该译码设备对该极化码序列进行译码处理，以获取至少一个第二比特序列，其中，该第二比特序列包括第一比特序列和校验比特，其中，该校验比特是基于该第一比特序列生成的，该第一比特序列包括信息比特和固定比特，该信息比特用于承载目标信息，该固定比特用于承载预设信息；该译码设备根据每个第二比特序列中的第一比特序列，获取每个第二比特序列所对应的验证比特，并根据每个第二比特序列所对应的验证比特和每个第二比特序列中的校验比特，从该至少一个第二比特序列中确定目标第二比特序列，其中，该目标第二比特序列所对应的验证比特与该目标第二比特序列中的校验比特相同；该译码设备根据该目标第二比特序列中的信息比特，确定编码设备所传输的目标信息。
结合第二方面，在第二方面的第一种实现方式中，在该第二比特序列中，该校验比特在该第一比特序列之后。从而能够满足现有通信标准中对待校验比特和校验比特的位置关系的要求。
结合第二方面及其上述实现方式，在第二方面的第二种实现方式中，该译码设备根据每个第二比特序列中的第一比特序列，获取每个第二比特序列所对应的验证比特，包括：该译码设备根据该第一比特序列的长度，确定并行度M，M≥2；该译码设备根据该并行度M，对该第一比特序列进行校验处理，以获取该校验比特。
通过基于并行度M，同时进行针对该第一比特序列中的M个比特的校验处理，能够缩短校验处理的时间，减小传输时延。
结合第二方面及其上述实现方式，在第二方面的第三种实现方式中，该第一比特序列的长度为2的整数次幂。并且，并行度M为2的整数次幂。
通过使并行度M和第一比特序列的长度为2的整数次幂，能够容易地获得并行度M。
结合第二方面及其上述实现方式，在第二方面的第四种实现方式中，在该译码设备根据每个第二比特序列中的第一比特序列，获取每个第二比特序列所对应的验证比特之前，该方法还包括：该译码设备接收该编码设备发送第一指示信息，该第一指示信息用于指示该第一比特序列在该第二比特序列中位置，或该第一指示信息用于指示该校验比特在该第二比特序列中位置；该译码设备根据该第一指示信息，确定每个第二比特序列中的第一比特序列和校验比特。
通过接收编码设备发送的第一指示信息，能够使译码设备根据该第一指示信息从第二比特序列中区分第一比特序列和校验比特，从而能够提高编码设备生成该第二比特序列时的灵活度，具体地说，能够提高编码设备确定第一比特序列和校验比特的位置关系时的灵活度。
结合第二方面及其上述实现方式，在第二方面的第五种实现方式中，每个第二比特序列中的第一比特序列包括P个子比特序列，每个子比特序列包括信息比特和固定波特，P≥2，并且，每个第二比特序列中的校验比特包括P个子校验比特，该P个子比特序列与该P个子校验比特一一对应，每个子校验比特是根据该对应的子比特序列生成的，以及该译码设备根据每个第二比特序列中的第一比特序列，获取每个第二比特序列所对应的验证比特，并根据每个第二比特序列所对应的验证比特和每个第二比特序列中的校验比特，从该L个第二比特序列中确定目标第二比特序列，包括：该译码设备确定每个第二比特序列中的P个子比特序列和P个子校验比特；该译码设备根据每个第二比特序列中的P个子比特序列，获取每个第二比特序列所对应的验证比特，其中，每个第二比特序列所对应的验证比特包括P个子验证比特，该P个子比特序列与该P个子验证比特一一对应，每个子验证比特是根据该对应的子比特序列生成的；该译码设备根据每个第二比特序列所对应的P个子验证比特和每个第二比特序列中的P个子校验比特，确定目标第二比特序列，其中，对于目标第二比特序列中的任一子比特序列，该子比特序列所对应的子验证比特和该子比特序列所对应的子校验比特相同。
通过对第一比特序列进行分段处理，能够使编码设备和译码设备并行地对第一比特序列中的个子比特序列进行校验处理，能够缩短校验处理的时 间，减小传输时延。
结合第二方面及其上述实现方式，在第二方面的第六种实现方式中，在第二比特序列中，每个子比特序列与所对应的子校验比特相邻。
通过使每个子比特序列与所对应的子校验比特相邻配置，能够容易地确定各子比特序列所对应的子校验比特。
结合第二方面及其上述实现方式，在第二方面的第七种实现方式中，在第二比特序列中，每个子比特序列位于所对应的子校验比特之前。从而能够满足现有通信标准中对待校验比特和校验比特的位置关系的要求。
结合第二方面及其上述实现方式，在第二方面的第八种实现方式中，该译码设备根据每个第二比特序列中的P个子比特序列，获取每个第二比特序列所对应的验证比特，包括：该译码设备根据每个第二比特序列中的第p个子比特序列的长度，确定该第p个子比特序列所对应的并行度m，其中，m≥2，p∈[1，P]；该译码设备根据该第p个子比特序列所对应的并行度m，对该第p个子比特序列进行校验处理，以获取该第p个子比特序列所对应的子验证比特。
通过基于并行度m，同时进行针对一个子比特序列的m个比特的校验处理，能够缩短校验处理的时间，减小传输时延。
结合第二方面及其上述实现方式，在第二方面的第九种实现方式中，该方法还包括：该译码端设备接收该编码设备发送的第二指示信息，该第二指示信息用于指示该第一比特序列中的每个子比特序列在该第二比特序列中的位置，并且，该第二指示信息用于指示每个子比特序列所对应的子校验序列在该第二比特序列中的位置。
通过接收编码设备发送的第二指示信息，能够使译码设备根据该第二指示信息从第二比特序列中区分每个子比特序列以及每个子比特序列所对应的子校验序列，从而能够提高编码设备生成该第二比特序列时的灵活度，具体地说，能够提高编码设备确定每个子比特序列以及每个子比特序列所对应的子校验序列的位置关系时的灵活度。
结合第二方面及其上述实现方式，在第二方面的第十种实现方式中，每个子比特序列的长度为2的整数次幂。并且，并行度m为2的整数次幂。
通过使并行度m和第一比特序列的长度为2的整数次幂，能够容易地获得并行度m。
第三方面，提供了一种极化码的编码装置，包括：生成单元，用于根据需要传输至译码设备的目标信息，生成第一比特序列，该第一比特序列包括信息比特和固定比特，该信息比特用于承载该目标信息，该固定比特用于承载预设信息；校验单元，用于根据该第一比特序列，确定校验比特；编码单元，用于根据该第一比特序列和该校验比特，生成第二比特序列，并用于根据该第二比特序列，生成极化码序列。
结合第三方面，在第三方面的第一种实现方式中，该校验单元具体用于根据该第一比特序列的长度，确定并行度M，M≥2；用于根据该并行度M，对该第一比特序列进行校验处理，以获取该校验比特。
结合第三方面及其上述实现方式，在第三方面的第二种实现方式中，该编码装置还包括：发送单元，用于向该译码设备发送第一指示信息，该第一指示信息用于指示该第一比特序列在该第二比特序列中位置，或该第一指示信息用于指示该校验比特在该第二比特序列中位置。
结合第三方面及其上述实现方式，在第三方面的第三种实现方式中，该校验单元具体用于对该第一比特序列进行分段处理，以生成P个子比特序列，每个子比特序列包括信息比特和固定比特，P≥2；用于根据该P个子比特序列，确定校验比特，其中，该校验比特包括P个子校验比特，该P个子比特序列与该P个子校验比特一一对应，每个子校验比特是根据该对应的子比特序列生成的。
结合第三方面及其上述实现方式，在第三方面的第四种实现方式中，该校验单元具体用于根据第p个子比特序列的长度，确定该第p个子比特序列所对应的并行度m，其中，m≥2，p∈[1，P]；用于根据该第p个子比特序列所对应的并行度m，对该第p个子比特序列进行校验处理，以获取该第p个子比特序列所对应的子校验比特。
结合第三方面及其上述实现方式，在第三方面的第五种实现方式中，该编码装置还包括：发送单元，用于向该译码设备发送第二指示信息，该第二指示信息用于指示该第一比特序列中的每个子比特序列在该第二比特序列中的位置，并且，该第二指示信息用于指示每个子比特序列所对应的子校验序列在该第二比特序列中的位置。
第四方面，提供了一种极化码的译码装置，包括：获取单元，用于获取极化码序列；译码单元，用于对该极化码序列进行译码处理，以获取至少一 个第二比特序列，其中，该第二比特序列包括第一比特序列和校验比特，其中，该校验比特是基于该第一比特序列生成的，该第一比特序列包括信息比特和固定比特，该信息比特用于承载目标信息，该固定比特用于承载预设信息；校验单元，用于根据每个第二比特序列中的第一比特序列，获取每个第二比特序列所对应的验证比特，并根据每个第二比特序列所对应的验证比特和每个第二比特序列中的校验比特，从该至少一个第二比特序列中确定目标第二比特序列，其中，该目标第二比特序列所对应的验证比特与该目标第二比特序列中的校验比特相同；确定单元，用于根据该目标第二比特序列中的信息比特，确定编码设备所传输的目标信息。
结合第四方面，在第四方面的第一种实现方式中，该校验单元具体用于根据该第一比特序列的长度，确定并行度M，M≥2；用于根据该并行度M，对该第一比特序列进行校验处理，以获取该校验比特。
结合第四方面及其上述实现方式，在第四方面的第二种实现方式中，该译码装置还包括：接收单元，用于接收该编码设备发送第一指示信息，该第一指示信息用于指示该第一比特序列在该第二比特序列中位置，或该第一指示信息用于指示该校验比特在该第二比特序列中位置；该校验单元还用于根据该第一指示信息，确定每个第二比特序列中的第一比特序列和校验比特。
结合第四方面及其上述实现方式，在第四方面的第三种实现方式中，每个第二比特序列中的第一比特序列包括P个子比特序列，每个子比特序列包括信息比特和固定波特，P≥2，并且，每个第二比特序列中的校验比特包括P个子校验比特，该P个子比特序列与该P个子校验比特一一对应，每个子校验比特是根据该对应的子比特序列生成的，以及该译码单元具体用于确定每个第二比特序列中的P个子比特序列和P个子校验比特；用于根据每个第二比特序列中的P个子比特序列，获取每个第二比特序列所对应的验证比特，其中，每个第二比特序列所对应的验证比特包括P个子验证比特，该P个子比特序列与该P个子验证比特一一对应，每个子验证比特是根据该对应的子比特序列生成的；用于根据每个第二比特序列所对应的P个子验证比特和每个第二比特序列中的P个子校验比特，确定目标第二比特序列，其中，对于目标第二比特序列中的任一子比特序列，该子比特序列所对应的子验证比特和该子比特序列所对应的子校验比特相同。
结合第四方面及其上述实现方式，在第四方面的第四种实现方式中，该 校验单元具体用于根据每个第二比特序列中的第p个子比特序列的长度，确定该第p个子比特序列所对应的并行度m，其中，m≥2，p∈[1，P]；用于根据该第p个子比特序列所对应的并行度m，对该第p个子比特序列进行校验处理，以获取该第p个子比特序列所对应的子验证比特。
结合第四方面及其上述实现方式，在第四方面的第五种实现方式中，该译码装置还包括：接收单元，用于接收该编码设备发送的第二指示信息，该第二指示信息用于指示该第一比特序列中的每个子比特序列在该第二比特序列中的位置，并且，该第二指示信息用于指示每个子比特序列所对应的子校验序列在该第二比特序列中的位置。
第五方面，提供了一种极化码的编码设备，包括：总线；与该总线相连的处理器；与该总线相连的存储器；其中，该处理器通过该总线，调用该存储器中存储的程序，以用于根据需要传输至译码设备的目标信息，生成第一比特序列，该第一比特序列包括信息比特和固定比特，该信息比特用于承载该目标信息，该固定比特用于承载预设信息；该处理器用于根据该第一比特序列，确定校验比特；该处理器用于根据该第一比特序列和该校验比特，生成第二比特序列；该处理器用于根据该第二比特序列，生成极化码序列。
结合第五方面，在第五方面的第一种实现方式中，该处理器具体用于根据该第一比特序列的长度，确定并行度M，M≥2；该处理器具体用于根据该并行度M，对该第一比特序列进行校验处理，以获取该校验比特。
结合第五方面及其上述实现方式，在第五方面的第二种实现方式中，该编码设备还包括与该总线相连的发射器；以及该处理器还用于控制该发射机向该译码设备发送第一指示信息，该第一指示信息用于指示该第一比特序列在该第二比特序列中位置，或该第一指示信息用于指示该校验比特在该第二比特序列中位置。
结合第五方面及其上述实现方式，在第五方面的第三种实现方式中，该处理器具体用于对该第一比特序列进行分段处理，以生成P个子比特序列，每个子比特序列包括信息比特和固定比特，P≥2；该处理器具体用于根据该P个子比特序列，确定校验比特，其中，该校验比特包括P个子校验比特，该P个子比特序列与该P个子校验比特一一对应，每个子校验比特是根据该对应的子比特序列生成的。
结合第五方面及其上述实现方式，在第五方面的第四种实现方式中，该 处理器具体用于根据第p个子比特序列的长度，确定该第p个子比特序列所对应的并行度m，其中，m≥2，p∈[1，P]；该处理器具体用于根据该第p个子比特序列所对应的并行度，对该第p个子比特序列进行校验处理，以获取该第p个子比特序列所对应的子校验比特。
结合第五方面及其上述实现方式，在第五方面的第五种实现方式中，该编码设备还包括与该总线相连的发射器；以及该处理器还用于控制该发射机向该译码设备发送第二指示信息，该第二指示信息用于指示该第一比特序列中的每个子比特序列在该第二比特序列中的位置，并且，该第二指示信息用于指示每个子比特序列所对应的子校验序列在该第二比特序列中的位置。
第六方面，提供了一种极化码的译码设备，包括：总线；与该总线相连的处理器；与该总线相连的存储器；其中，该处理器通过该总线，调用该存储器中存储的程序，以用于获取极化码序列；该处理器用于对该极化码序列进行译码处理，以获取至少一个第二比特序列，其中，该第二比特序列包括第一比特序列和校验比特，其中，该校验比特是基于该第一比特序列生成的，该第一比特序列包括信息比特和固定比特，该信息比特用于承载目标信息，该固定比特用于承载预设信息；该处理器用于根据每个第二比特序列中的第一比特序列，获取每个第二比特序列所对应的验证比特，并根据每个第二比特序列所对应的验证比特和每个第二比特序列中的校验比特，从该至少一个第二比特序列中确定目标第二比特序列，其中，该目标第二比特序列所对应的验证比特与该目标第二比特序列中的校验比特相同；该处理器用于根据该目标第二比特序列中的信息比特，确定编码设备所传输的目标信息。
结合第六方面，在第六方面的第一种实现方式中，该处理器具体用于根据该第一比特序列的长度，确定并行度M，M≥2；该处理器具体用于根据该并行度M，对该第一比特序列进行校验处理，以获取该校验比特。
结合第六方面及其上述实现方式，在第六方面的第二种实现方式中，该译码设备还包括与该总线相连的接收器；以及该处理器还用于控制该接收机接收该编码设备发送第一指示信息，该第一指示信息用于指示该第一比特序列在该第二比特序列中位置，或该第一指示信息用于指示该校验比特在该第二比特序列中位置。
结合第六方面及其上述实现方式，在第六方面的第三种实现方式中，每个第二比特序列中的第一比特序列包括P个子比特序列，每个子比特序列包 括信息比特和固定波特，P≥2，并且，每个第二比特序列中的校验比特包括P个子校验比特，该P个子比特序列与该P个子校验比特一一对应，每个子校验比特是根据该对应的子比特序列生成的，以及该处理器具体用于确定每个第二比特序列中的P个子比特序列和P个子校验比特；该处理器具体用于根据每个第二比特序列中的P个子比特序列，获取每个第二比特序列所对应的验证比特，其中，每个第二比特序列所对应的验证比特包括P个子验证比特，该P个子比特序列与该P个子验证比特一一对应，每个子验证比特是根据该对应的子比特序列生成的；
该处理器具体用于根据每个第二比特序列所对应的P个子验证比特和每个第二比特序列中的P个子校验比特，确定目标第二比特序列，其中，对于目标第二比特序列中的任一子比特序列，该子比特序列所对应的子验证比特和该子比特序列所对应的子校验比特相同。
结合第六方面及其上述实现方式，在第六方面的第四种实现方式中，该处理器具体用于根据每个第二比特序列中的第p个子比特序列的长度，确定该第p个子比特序列所对应的并行度m，其中，m≥2，p∈[1，P]；该处理器具体用于根据该第p个子比特序列所对应的并行度m，对该第p个子比特序列进行校验处理，以获取该第p个子比特序列所对应的子验证比特。
结合第六方面及其上述实现方式，在第六方面的第五种实现方式中，该译码设备还包括与该总线相连的接收器；以及该处理器还用于控制该接收机接收该编码设备发送的第二指示信息，该第二指示信息用于指示该第一比特序列中的每个子比特序列在该第二比特序列中的位置，并且，该第二指示信息用于指示每个子比特序列所对应的子校验序列在该第二比特序列中的位置。
第七方面，提供了一种计算机程序产品，该计算机程序产品包括：计算机程序代码，当该计算机程序代码被网络设备的接收单元、处理单元、发送单元或接收器、处理器、发送器运行时，使得该网络设备执行上述第一方面，及其各种实现方式中的任一种极化码的编码方法。
第八方面，提供了一种计算机程序产品，该计算机程序产品包括：计算机程序代码，当该计算机程序代码被网络设备的接收单元、处理单元、发送单元或接收器、处理器、发送器运行时，使得该网络设备执行上述第二方面，及其各种实现方式中的任一种极化码的译码方法。
第九方面，提供了一种计算机可读存储介质，该计算机可读存储介质存储有程序，该程序使得用户设备执行上述第一方面，及其各种实现方式中的任一种极化码的编码方法。
第十方面，提供了一种计算机可读存储介质，该计算机可读存储介质存储有程序，该程序使得用户设备执行上述第二方面，及其各种实现方式中的任一种极化码的译码方法。
根据本发明实施例的极化码的编码方法、译码方法、编码设备和译码设备，通过使编码设备对包括信息比特和固定比特的第一比特序列进行校验处理，以确定校验比特，并将该第一比特序列与该校验比特进行合并，生成第二比特序列，其后，编码设备可以根据该第二比特序列，生成极化码序列，从而，译码设备可以在对该极化码序列进行译码处理而获取该第二比特序列后，基于该第二比特序列中的校验比特，对该第二比特序列中的第一比特序列进行校验处理，即，能够在确定信息比特之前，完成校验过程。特别是在基于SCL译码算法等的译码过程中，能够获得多个路径的估值，在本发明实施例中，能够在无需获取每个路径中的信息比特的情况下进行校验处理，从而可以仅保留校验通过的路径，并将该校验通过的路径中的信息比特作为译码输出，大大缩短了译码处理的延时，改善了用户体验。
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图1是根据本文所述的各个实施例的无线通信系统的示图。
图2是在无线通信环境中执行本发明实施例的极化码的编码方法的系统的示图。
图3是在无线通信环境中执行本发明实施例的极化码的译码方法的系统的示图。
图4是本发明实施例的极化码的编码方法的一例的流程图。
图5是本发明实施例的CRC的基本原理的示意图。
图6是发明实施例的CRC的并行处理的基本原理的示意图。
图7是发明实施例的CRC的并行处理的一个流程示意图。
图8是发明实施例的CRC的并行处理的另一个流程示意图。
图9是本发明实施例的编码过程的一例的示意图。
图10是本发明实施例的编码过程的另一例的示意图。
图11是本发明实施例的极化码的译码方法的流程图。
图12是本发明实施例的译码过程的一例的示意图。
图13是本发明实施例的极化码的编码装置的框图。
图14是本发明实施例的极化码的译码装置的框图。
图15是适用本发明实施例的极化码的编码设备的示意性结构图。
图16是适用本发明实施例的极化码的译码设备的示意性结构图。
图17是适用本发明实施例的极化码的编码方法或译码方法的接入终端的结构图。
图18是适用本发明实施例的极化码的编码方法或译码方法的网络设备的结构图。
具体实施方式
在本说明书中使用的术语"部件"、"模块"、"系统"等用于表示计算机相关的实体、硬件、固件、硬件和软件的组合、软件、或执行中的软件。例如，部件可以是但不限于，在处理器上运行的进程、处理器、对象、可执行文件、执行线程、程序和/或计算机。通过图示，在计算设备上运行的应用和计算设备都可以是部件。一个或多个部件可驻留在进程和/或执行线程中，部件可位于一个计算机上和/或分布在2个或更多个计算机之间。此外，这些部件可从在上面存储有各种数据结构的各种计算机可读介质执行。部件可例如根据具有一个或多个数据分组(例如来自与本地系统、分布式系统和/或网络间的另一部件交互的二个部件的数据，例如通过信号与其它系统交互的互联网)的信号通过本地和/或远程进程来通信。
本发明实施例的极化码的编码方法或译码方法的执行主体可以是接入终端。接入终端也可以称为系统、用户单元、用户站、移动站、移动台、远方站、远程终端、移动设备、用户终端、终端、无线通信设备、用户代理、用户装置或用户设备(UE，User Equipment)。接入终端可以是蜂窝电话、无绳电话、会话启动协议(SIP，Session Initiation Protocol)电话、无线本地环路(WLL，Wireless Local Loop)站、个人数字处理(PDA，Personal Digital Assistant)、具有无线通信功能的手持设备、计算设备或连接到无线调制解调器的其它处理设备。
或者，本发明实施例的极化码的编码方法或译码方法的执行主体可以是 网络设备。网络设备可用于与移动设备通信，网络设备可以是全球移动通讯(GSM，Global System of Mobile communication)或码分多址(CDMA，Code Division Multiple Access)中的基站(BTS，Base Transceiver Station)，也可以是宽带码分多址(WCDMA，Wideband Code Division Multiple Access)中的基站(NB，NodeB)，还可以是长期演进(LTE，Long Term Evolution，)中的演进型基站(eNB或eNodeB，Evolutional Node B)，或者中继站或接入点，或者未来5G网络中的基站设备等。
此外，本发明实施例的各个方面或特征可以实现成方法、装置或使用标准编程和/或工程技术的制品。本申请中使用的术语"制品"涵盖可从任何计算机可读器件、载体或介质访问的计算机程序。例如，计算机可读介质可以包括，但不限于:磁存储器件，例如，硬盘、软盘或磁带等；光盘，例如，压缩盘(CD，Compact Disk)、数字通用盘(DVD，Digital Versatile Disk)等；智能卡和闪存器件，例如，可擦写可编程只读存储器(EPROM，Erasable Programmable Read-Only Memory)等。
另外，本文描述的各种存储介质可代表用于存储信息的一个或多个设备和/或其它机器可读介质。术语"机器可读介质"可包括但不限于，无线信道和能够存储、包含和/或承载指令和/或数据的各种其它介质。
现在，参照图1，示出根据本文所述的各个实施例的无线通信系统100。无线通信系统100包括网络设备102，网络设备102可包括多个天线组。每个天线组可以包括一个或多个天线，例如，一个天线组可包括天线104和106，另一个天线组可包括天线108和110，附加组可包括天线112和114。图1中对于每个天线组示出了2个天线，然而可对于每个组使用更多或更少的天线。网络设备102可附加地包括发射机链和接收机链，本领域普通技术人员可以理解，它们均可包括与信号发送和接收相关的多个部件，例如，处理器、调制器、复用器、解调器、解复用器或天线等。
网络设备102可以与一个或多个接入终端(例如，接入终端116和接入终端122)通信。然而，可以理解，网络设备102可以与类似于接入终端116或122的任意数目的接入终端通信。接入终端116和122可以是例如蜂窝电话、智能电话、便携式电脑、手持通信设备、手持计算设备、卫星无线电装置、全球定位系统、PDA和/或用于在无线通信系统100上通信的任意其它适合设备。如图所示，接入终端116与天线112和114通信，其中天线112 和114通过前向链路118向接入终端116发送信息，并通过反向链路120从接入终端116接收信息。此外，接入终端122与天线104和106通信，其中天线104和106通过前向链路124向接入终端122发送信息，并通过反向链路126从接入终端122接收信息。在频分双工(FDD，Frequency Division Duplex)系统中，例如，前向链路118可利用与反向链路120所使用的不同频带，前向链路124可利用与反向链路126所使用的不同频带。此外，在时分双工(TDD，Time Division Duplex)系统中，前向链路118和反向链路120可使用共同频带，前向链路124和反向链路126可使用共同频带。
被设计用于通信的每组天线和/或区域称为网络设备102的扇区。例如，可将天线组设计为与网络设备102覆盖区域的扇区中的接入终端通信。在网络设备102通过前向链路118和124分别与接入终端116和122进行通信的过程中，网络设备102的发射天线可利用波束成形来改善前向链路118和124的信噪比。此外，与网络设备通过单个天线向它所有的接入终端发送信号的方式相比，在网络设备102利用波束成形向相关覆盖区域中随机分散的接入终端116和122发送信号时，相邻小区中的移动设备会受到较少的干扰。
在给定时间，网络设备102、接入终端116或接入终端122可以是无线通信发送装置和/或无线通信接收装置。当发送数据时，无线通信发送装置可对数据进行编码以用于传输。
具体地，无线通信发送装置可获取(例如，生成、从其它通信装置接收、或在存储器中保存等)要通过信道发送至无线通信接收装置的一定数目的数据比特。这种数据比特可包含在数据的一个或多个传输块中，传输块可被分段以产生多个码块。此外，无线通信发送装置可使用Polar码编码器(图中未示出)来对每个码块编码，生成发射信号。
无线通信接收装置可获取通过信道接收无线通信发送装置发送的经过Polar码编码器进行编码处理后的信号，并且，可以通过Polar译码器(未示出)对该信号进行解码，以获取上述数据比特。
图2示出了在无线通信环境中适用本发明实施例的极化码的编码方法的系统200的示意性框图。系统200包括无线通信设备202，该无线通信设备202被显示为经由信道发送数据。尽管示出为发送数据，但无线通信设备202还可经由信道接收数据，例如，无线通信设备202可同时发送和接收数据，或者，无线通信设备202也可以在不同时刻发送和接收数据，或其组合等。 无线通信设备202例如可以是基站(例如，图1的基站102等)、接入终端(例如，图1的接入终端116、图1的接入终端122等)等。
无线通信设备202可以包括Polar码编码器204和发射机206。可选地，无线通信设备202还可以包括速率匹配装置。可选地，当无线通信设备202经由信道接收数据时，该无线通信设备202还可以包括一个接收机，该接收机可以单独存在，也可以与发射机206集成在一起形成一个收发机。
其中，Polar码编码器204用于对要从无线通信装置202传送的数据进行编码得到极化码。
此外，发射机206可随后在信道上传送经过Polar码编码器204(或者，Polar码编码器204和速率匹配装置)处理后的输出比特。例如，发射机206可以将相关数据发送到其它不同的无线通信装置(图中未示出)。
图3示出了在无线通信环境中适用本发明实施例的极化码的译码方法的系统300的示意性框图。系统300包括无线通信设备302，该无线通信设备302被显示为经由信道接收数据。尽管示出为发送数据，但无线通信设备302还可经由信道发送数据，例如，无线通信设备302可同时发送和接收数据，或者，无线通信设备302也可以在不同时刻发送和接收数据，或其组合等。无线通信设备302例如可以是基站(例如，图1的基站102等)、接入终端(例如，图1的接入终端116、图1的接入终端122等)等。
无线通信设备302可以包括接收机306和Polar码译码器304。可选地，当无线通信设备302经由信道发送数据时，该无线通信设备302还可以包括一个发射机，该发射机可以单独存在，也可以与接收机306集成在一起形成一个收发机。
其中，接收机306可在信道接收来自其他无线通信装置发射的经过Polar码编码处理后的信号。
并且，Polar译码器304用于对该接收机306接收到的信号进行译码，获取其他无线通信装置所发送的数据。
在对具体的实施例展开描述之前，首先介绍本发明实施例所涉及的Polar码的编译码过程：
通信系统通常采用信道编码提高数据传输的可靠性，以保证通信的质量。Arikan提出的极化(Polar)码是第一个从理论上证明可以取得香农容量且具有低编译码复杂度的好码。
Polar码是一种线性块码，其生成矩阵为GN，编码过程为
Figure PCTCN2017000050-appb-000001
其中，
Figure PCTCN2017000050-appb-000002
是Polar码的母码，是一个二进制的行矢量，长度为N，其元素为母码码字；
Figure PCTCN2017000050-appb-000003
是一个二进制的行矢量，长度为N(即码长)并且值为2的整数次幂；
GN是一个N×N的矩阵，且
Figure PCTCN2017000050-appb-000004
这里
Figure PCTCN2017000050-appb-000005
BN是一个N×N的转置矩阵，例如比特反序排列置换(Bit Reversal)矩阵，所谓比特反序置换即是将一个长度为N序列
Figure PCTCN2017000050-appb-000006
经过排列后得到
Figure PCTCN2017000050-appb-000007
其中ya＝xb，序号a和b的二进制表示展开互为反序序列。如序列(1,2,3,4,5,6,7,8)经比特反序排列后为(1,5,3,7,2,6,4,8)；
Figure PCTCN2017000050-appb-000008
定义为log2N个矩阵F2的克罗内克(Kronecker)乘积；
以上涉及的加法、乘法操作均为二进制伽罗华域(Galois Field)上的加法、乘法操作。
Polar码的编码过程中，
Figure PCTCN2017000050-appb-000009
中的一部分比特用来携带信息，称为信息比特，这些比特的索引的集合记作A。另外的一部分比特置为收发端预先约定的固定值，称之为固定比特，其索引的集合用A的补集Ac表示。不失一般性，这些固定比特通常被设为0，本发明实施例的叙述中也采用这一设置；但实际上，只需要收发端预先约定，固定比特序列可以被任意设置。
当固定比特被设为0时，Polar码的编码输出可简化为：
Figure PCTCN2017000050-appb-000010
这里uA为
Figure PCTCN2017000050-appb-000011
中的信息比特集合，uA为长度为K比特的行矢量，即|A|＝K，其中，|·|表示集合中元素的个数，K为信息块的大小，
Figure PCTCN2017000050-appb-000012
是矩阵GN中由集合A中的索引对应的那些行得到的子矩阵，
Figure PCTCN2017000050-appb-000013
是一个K×N的矩阵。集合A的选取决定了Polar码的性能。
Polar码最基本的译码方法是SC译码。SC译码算法利用从信道中接收 到的信号序列
Figure PCTCN2017000050-appb-000014
逐个对
Figure PCTCN2017000050-appb-000015
中的各个比特进行译码、得到
Figure PCTCN2017000050-appb-000016
的估计序列
Figure PCTCN2017000050-appb-000017
对索引i从1到N，逐个进行以下译码判决：
Figure PCTCN2017000050-appb-000018
其中，
Figure PCTCN2017000050-appb-000019
上式中，
Figure PCTCN2017000050-appb-000020
为比特ui所对应的极化信道的信道转移概率函数。极化信道的转移概率函数
Figure PCTCN2017000050-appb-000021
根据用以传输编码比特的原始信道的转移概率函数W(y|x)按下式得到：
Figure PCTCN2017000050-appb-000022
其中，如前所述，
Figure PCTCN2017000050-appb-000023
和
Figure PCTCN2017000050-appb-000024
的对应关系
Figure PCTCN2017000050-appb-000025
{0,1}N-i表示N-i个集合{0,1}的笛卡尔(Cartesian)乘积。
SC译码的优点是：1)在码长足够大时，理论上证明了Polar码在SC译码下能够达到信道容量；2)译码复杂度很低，与码长N与码长的对数log2N的乘积呈线性关系，为O(Nlog2N)。
当码长较短的时候，传统的串行抵消(Successive Cancellation，SC)译码的性能并不理想，其性能不如目前已广泛使用的低密度奇偶校验(Low-Density Parity-Check，LDPC)码或Turbo码。陆续提出了以SCL译码算法为代表的增强SC译码算法(还包括SCS译码、SCH译码等)。在信息序列中包含CRC信息的情况(HARQ传输即属于这种场景)下，通过CRC辅助的增强SC译码，如CRC辅助的SCL(CRC-Aided Successive Cancellation List，CASCL)译码、CRC辅助的SCS(CRC-Aided Successive Cancellation Stack，CASCS)译码和CRC辅助的SCH(CRC-Aided Successive Cancellation Hybrid，CASCH)译码等，Polar码能够在译码复杂度相当的情况下获得与Turbo码或LDPC码相当，甚至更优的FER性能。因此，Polar码在未来通信系统中具有非常好的应用前景。
下面，结合图4对上述Polar码编码器204的具体处理过程，进行详细说明。结合图5对上述Polar码译码器304的具体处理过程，进行详细说明。
图4是本发明实施例的极化码的编码方法400的示意性流程图，图4所示的方法400可以由编码设备，例如，无线通信设备中的Polar码编码器执行。该方法400包括：
S410，编码设备根据需要传输至译码设备的目标信息，生成第一比特序列，该第一比特序列包括信息比特和固定比特，该信息比特用于承载该目标信息，该固定比特用于承载预设信息。
S420，该编码设备根据该第一比特序列，确定校验比特。
S430，该编码设备根据该第一比特序列和该校验比特，生成第二比特序列；
S440，该编码设备根据该第二比特序列，生成极化码序列。
具体地说，在S410，编码设备可以根据需要传输至译码设备的信息(即，目标信息的一例)生成信息比特序列X，不失一般性，设该信息比特序列X的长度(或者说，该信息比特序列X包括的比特的数量)为K-α，其中，K-α≥1。在本发明实施例中，编码设备生成信息比特序列X的过程可以与现有技术相似，这里，为了避免赘述，省略其详细说明。
其后，编码设备可以在该比特序列X中插入N-K个固定比特，从而得到长度(或者说，所包括的比特数量)为N-α的比特序列Y(即，第一比特序列的一例)。在本发明实施例中，编码设备在信息比特中插入固定比特从而生成上述比特序列Y的过程可以与现有技术相似，这里，为了避免赘述，省略其详细说明。
可选地，该第一比特序列的长度为2的整数次幂。
具体地说，在本发明实施例中，该比特序列Y的长度(或者说，比特序列Y所包括的比特数量)为2的整数次幂，即，设该比特序列Y的长度为B，则B满足以下式1。
B＝2j,j≥1         式1
应理解，以上列举的第一比特序列的长度仅为示例性说明，本发明实施例并未限定于此，该比特序列Y的长度可以根据需要任意变更，例如，该比特序列Y的长度可以根据预先设定的极化码母码的码长(即，N)和CRC校验比特的长度(即，α)确定。
在S420，编码设备可以对如上所述生成的比特序列Y进行用于生成α个校验比特的CRC校验处理，或者说，CRC校验编码。
在本发明实施例中，编码设备可以对比特序列Y整体进行CRC校验处理，以生成与该比特序列Y整体相对应的α个校验比特(即，方式1)。或者，编码设备也可以对比特序列Y进行分段处理，以获取P(P≥2)个子比特序列，并分别对每个子比特序列进行CRC校验处理，以生成每个子比特序列所对应的校验比特(即，方式2)。
下面，分别对以上两种方式下的处理过程进行详细说明。
方式1
图5示出了本发明实施例的CRC的基本原理的示意图。如图5所示，在本发明实施例中，编码设备可以对比特序列Y进行串行处理，每次处理1比特。在图5所示处理方式中，g0～gα-1为以下式2中矩阵G中的元素，其中，g0～gα-1的取值为0或1，具体的取值可以根据现有技术中CRC处理过程中的规定来确定。b0～bα-1表示寄存器，用于存储中间值，并根据指示将所存储的数值进行输出。Yi表示第i次处理(或者说，第i次输入的比特序列Y中)的比特，i∈[0，N-α]。其中，N-α为待校验的序列(即，比特序列Y)的长度，另外图5和图6中的
Figure PCTCN2017000050-appb-000026
表示乘运算，
Figure PCTCN2017000050-appb-000027
表示模2加运算。
如图5所示，以对比特序列Y中的第i个比特Yi的处理为例，编码设备首先将Yi于存储在寄存器bα-1中的中间值进行加运算(为了便于理解和说明，将计算结果记做
Figure PCTCN2017000050-appb-000028
)，
Figure PCTCN2017000050-appb-000029
被输入至寄存器b0。并且，g0与
Figure PCTCN2017000050-appb-000030
进行乘运算后的结果被与从寄存器b0输出的值(即，
Figure PCTCN2017000050-appb-000031
)进行加运算后输出至寄存器b1，g1与
Figure PCTCN2017000050-appb-000032
进行乘运算后的结果被与从寄存器b1输出的值进行加运算后输出至寄存器b2，以此类推，能够对寄存器bα-1中存储的中间值进行更新。从而，比特序列Y中的各比特均处理完成后，可以将寄存器bα-1存储的最终值作为校验序列(即，序列W)。
在本发明实施例中，可以将上述CRC校验过程可以通过以下式2表示。
Si＝R·Si-1+G·Yi       式2
其中，
Figure PCTCN2017000050-appb-000033
其中，Si是一个长度为α的向量，表示第i个中间状态，i∈[1，α]，T表示转置。
应理解，以上列举的图5所示CRC处理的方法仅为示例性说明，本发明实施例并未限定于此，例如，在本发明实施例中，编码设备还可以采用多比特并行处理的方式进行CRC处理。
即，可选地，该编码设备根据该第一比特序列，获取校验序列，包括：该编码设备根据该第一比特序列的长度，确定并行度M，M≥2；
该编码设备根据该并行度M，对该第一比特序列进行校验处理，以获取该校验序列。
具体地说，在本发明实施例中，并行度M表示编码段进行校验处理时同时处理的比特的数量。
例如，编码设备可以根据需要校验的比特序列(即，第一比特序列)的长度来确定该并行度M，例如，如果该第一比特序列的长度较大，则可以使并行度M较大，以缩短校验处理的时间。
应理解，以上列举的用于确定并行度M的具体参数可确定方式仅为示例性说明，本发明实施例并未限定于此，例如，编码设备还可以基于用户设定或系统规定的校验处理时间(或者说，处理时延)、编码设备自身的处理性能等来确定该并行度M，例如，如果用户设定或系统规定的校验处理时间较短，则可以使并行度M较大，以缩短校验处理的时间。
图6示出了发明实施例的CRC的并行处理的基本原理的示意图。如图6所示，编码设备可以采用并行处理方式，对比特序列Y进行CRC校验处理。
如图6所示，编码设备可以对比特序列Y进行串并变化处理，得到第i次校验处理所处理的M个比特(即，Yi～Yi+M－1)，其后，编码设备可以使该Yi～Yi+M－1与矩阵[RM-1G RM-2G … G]相乘，得到的α个比特(即，
Figure PCTCN2017000050-appb-000034
)。并且，编码设备可以使矩阵RM与上一次迭代的中间状态
Figure PCTCN2017000050-appb-000035
相乘得到的 α个比特
Figure PCTCN2017000050-appb-000036
最后，编码设备可以使
Figure PCTCN2017000050-appb-000037
与
Figure PCTCN2017000050-appb-000038
进行模2加，得到α个校验比特s0～sα-1。
假设并行度为M，即每次处理M个比特，则CRC校验过程可以通过以下式3表示。
Figure PCTCN2017000050-appb-000039
其中，RM表示M个R相乘，T表示转置。
当比特序列Y的长度不能被并行度M整除时，不能简单地由上述图6或式3所示方式实现，需要通过两步进行计算：
(1)计算前
Figure PCTCN2017000050-appb-000040
个比特，并行度为M1＝M；
(2)计算最后
Figure PCTCN2017000050-appb-000041
个比特，并行度为
Figure PCTCN2017000050-appb-000042
图7示出了此情况下，发明实施例的CRC的并行处理的流程示意图。如图7所示，编码设备可以对比特序列Y进行串并变化处理得到基于并行度M1进行校验处理的比特
Figure PCTCN2017000050-appb-000043
以及基于并行度M2进行校验处理的比特
Figure PCTCN2017000050-appb-000044
并基于并行度M1对比特
Figure PCTCN2017000050-appb-000045
进行校验处理，基于并行度M2对比特
Figure PCTCN2017000050-appb-000046
进行校验处理。
在实际应用中，需要支持多种不同的比特序列Y(即，在信息比特中插入固定比特之后形成的序列)的长度，如果针对所有的长度N-α，M1的取值相同，则M2的值有可能不同。设M2有q种可能的情况下，在共用一个CRC模块时，可以采用图8所示的CRC的并行处理的流程。如图8所示，编码设备可以根据所确定的并行度M1，对比特序列Y进行串并变化处理得到基于并行度M1进行校验处理的比特和剩余的比特，并根据剩余的比特确定该部分剩余比特的并行度(即，M2--1～M2--q中的一种)，从而能够基于所确定 的并行度，对该剩余的比特进行校验处理。
可选地，该第一比特序列的长度为2的整数次幂。
具体地说，在本发明实施例中，可以使比特序列Y的码长(或者说，包括的比特数)为2的整数次幂，从而在确定并行度时，只要使所选取的并行度的值为2的整数次幂即可，即，能够确保比特序列Y的长度能够被并行度M整除，采用一个并行度便能够完成基于并行方式的CRC校验处理，大大降低了实现复杂度，节省了处理时延，因此更适合实际系统应用。
与此相对，在现有技术中，由于CRC校验处理的对象为信息比特(即，本发明实施例中的比特序列X)，以LTE协议3GPP TS 36.212与3GPP TS 36.213规定的编码块长度(即输入编码器的信息比特数量)与速率适配后可能的长度为例，信息比特数量的可能的取值共有188种，取值范围从40到6144，很难统一CRC校验处理的并行度。
应理解，以上列举的本发明实施例所使用的并行度的确定方式仅为示例性说明，本发明实施例并未限定于此，如果比特序列Y(第一比特序列)的长度是并行度M1的整数倍，即，N＝k·M1，则可以分k次处理，每次处理M1个比特；
如果比特序列Y的长度不是M1的整数倍，例如，N＝k·M1+M2，其中，1≤M2＜M1，M1≥2，则例如，可以分k+1次处理，前k次每次处理M1个比特(并行度为M1)，最后一次处理M2个比特(并行度为M2)。
即，在本发明实施例中，最多需要两个校验处理模块便能够完成校验处理，其中，一个校验处理模块的并行度为M1，另一个校验处理模块的并行度为M2。
在如上所述，生成了α个校验比特之后，编码设备可以将该α个校验比特作为校验序列(以下，为了便于理解和区分，记做：校验序列W)。
需要说明的是，图6和图7中的s0～sa表示上述校验序列W中的α个校验比特。
在S430，编码设备可以根据在S410生成的比特序列Y(长度为N-α)和在S420生成的校验序列W(长度为α)，确定长度为N的序列Z(即，第二比特序列的一例)。
作为示例而非限定，在本发明实施例中，比特序列Y中的比特位于序列Z中的N-α个第一预设比特位，校验序列中的比特位于序列Z中的α个第 二预设比特位，其中，该第一预设比特位和第二预设比特位可以由系统规定，也可以由编码设备和译码设备协商确定，本发明实施例并未特别限定。
可选地，在该第二比特序列中，该第二预设比特位在该第一预设比特位之后。
具体地说，在本发明实施例中，编码设备可以将校验序列添加在比特序列Y之后形成序列Z，即，在本发明实施例中，第一预设比特位可以是比特序列Y中的前N-α个比特位，第二预设比特位可以是比特序列Y中的末尾的α个比特位。
应理解，以上列举的比特序列Y与校验序列之间的位置关系(或者说，该第二预设比特位在该第一预设比特位)仅为示例性说明，本发明实施例并未限定于此，第二预设比特位与第一预设比特位的位置关系(或者说，比特序列Y中的比特与校验序列中的比特在序列Z中的位置关系)可以任意确定，只要使译码设备能够从比特在序列Z中确定比特序列Y和校验序列即可。
可选的，该编码方法还包括：该编码设备向该译码设备发送第一指示信息，该第一指示信息用于指示该第一比特序列在该第二比特序列中位置，或该第一指示信息用于指示该校验比特在该第二比特序列中位置。
具体地说，在本发明实施例中，编码设备还可以将该第一比特序列(例如，上述第一预设比特位)的具体位置的指示信息(即，第一指示信息的一例)和/或校验比特(例如，第二预设比特位)的具体位置的指示信息(即，第一指示信息的另一例)发送给译码设备，从而，译码设备可以根据该第一指示信息，从该第二比特序列中确定第一比特序列和校验序列。
图9是本发明实施例的对第一比特币序列整体进行校验时的编码过程的一例的示意图。如图9所示，首先，编码设备可以在信息比特中插入固定比特，以获取比特序列Y。其后，编码设备可以对序列Y进行校验处理，得到α个校验比特，作为序列Y所对应的子校验序列W。并且，编码设备可以将校验序列W添加至序列Y的末尾，得到长度为N的序列Z，其后，编码设备可以将该序列Z与核矩阵相乘，生成极化码。
方式2
该编码设备根据该第一比特序列，获取校验序列，包括：
该编码设备对该第一比特序列进行分段处理，以生成P个子比特序列， 每个子比特序列包括信息比特和固定比特，P≥2；
该编码设备根据该P个子比特序列，获取校验序列，其中，该校验序列包括P个子校验序列，该P个子比特序列与该P个子校验序列一一对应，每个子校验序列是根据该对应的子比特序列生成的。
其中，该编码设备根据该P个子比特序列，确定校验比特，包括：
该编码设备根据第p个子比特序列的长度，确定该第p个子比特序列所对应的并行度m，其中，m≥2，p∈[1，P]；
该编码设备根据该第p个子比特序列所对应的并行度m，对该第p个子比特序列进行校验处理，以获取该第p个子比特序列所对应的子校验比特。
具体地说，在本发明实施例中，编码设备在生成的比特序列Y之后，可以对该比特序列Y进行分段处理，以确定P个子比特序列。
需要说明的是，在本发明实施例中，子比特序列的长度可以是系统或通信协议规定的，从而，译码设备能够基于系统或通信协议规定，从所接收到的信号中的区分各子比特序列。
或者，在本发明实施例中，编码设备也可以自主确定子比特序列的长度，此情况下，该方法还包括：该编码端设备向该译码设备发送第二指示信息，该第二指示信息用于指示该第一比特序列中的每个子比特序列在该第二比特序列中的位置。
即，译码设备能够根据该第二指示信息，从所接收到的信号中的区分各子比特序列。
在S420，编码设备可以对每个子比特序列分别进行CRC校验处理，以生成每个子比特序列所对应的子校验序列，即，P个子校验序列。
从而，在本发明实施例中，校验序列W可以由该P个子校验序列构成。
这里，编码设备对每个子比特序列进行CRC校验处理的方法和过程可以与上述对比特序列Y整体进行CRC校验处理的方法和过程相似，这里，为了避免赘述，省略其详细说明。
需要说明的是，在本发明实施例中，子校验序列的长度可以是系统或通信协议规定的，从而，译码设备能够基于系统或通信协议规定，从所接收到的信号中的区分各子校验序列。
或者，在本发明实施例中，编码设备也可以自主确定子校验序列的长度。
此情况下，例如，子校验序列的长度可以与所对应的子比特序列的长度 之间具有映射关系，即，译码设备可以根据每个子比特序列的长度，确定其所对应的子校验序列的长度。
再例如，该方法还包括：该编码端设备向该译码设备发送第二指示信息，该第二指示信息用于指示每个子比特序列所对应的子校验序列在该第二比特序列中的位置。从译码设备能够基于该第二指示信息，从所接收到的信号中的区分各子校验序列。
并且，在本发明实施例中，在本发明实施例中，一个子比特序列(为了便于理解和区分，记做：子比特序列Yp)所对应的子校验序列(为了便于理解和区分，记做：子比特序列Wp)用于译码设备对该子比特序列Yp的验证处理(随后，对该验证处理的具体过程进行详细说明)。
另外，在本发明实施例中，对于任意两个子比特序列，其长度可以相同也可以相异，本发明实施例并未特别限定，只要确保比特序列Y的长度为N-α；并且，对于任意两个子校验序列，其长度可以相同也可以相异，本发明实施例并未特别限定，只要确保有该P个子校验序列构成的校验序列W的长度为α即可。
可选地，每个子比特序列的长度为2的整数次幂。
具体地说，在本发明实施例中，可以使每个子比特序列的码长(或者说，包括的比特数)为2的整数次幂，从而在确定并行度时，只要使所选取的并行度的值为2的整数次幂即可，即，能够确保子比特序列的长度能够被并行度M整除，仅需要采用一个并行度便能够完成基于并行方式的CRC校验处理，大大降低了实现复杂度，节省了处理时延，因此更适合实际系统应用。
在S430，编码设备可以根据在S410生成的比特序列Y(长度为N-α)和在S420生成的校验序列W(长度为α)，确定长度为N的序列Z(即，第二比特序列的一例)。
作为示例而非限定，在本发明实施例中，比特序列Y中的比特位于序列Z中的N-α个第一预设比特位，校验序列中的比特位于序列Z中的α个第二预设比特位，其中，该第一预设比特位和第二预设比特位可以由系统规定，也可以由编码设备和译码设备协商确定，本发明实施例并未特别限定。
可选地，在该第二比特序列中，该第二预设比特位在该第一预设比特位之后。
具体地说，在本发明实施例中，编码设备可以将校验序列添加在比特序 列Y之后形成序列Z，即，在本发明实施例中，第一预设比特位可以是比特序列Y中的前N-α个比特位，第二预设比特位可以是比特序列Y中的末尾的α个比特位。
应理解，以上列举的比特序列Y与校验序列之间的位置关系(或者说，该第二预设比特位在该第一预设比特位)仅为示例性说明，本发明实施例并未限定于此，第二预设比特位与第一预设比特位的位置关系(或者说，比特序列Y中的比特与校验序列中的比特在序列Z中的位置关系)可以任意确定，只要使译码设备能够从比特在序列Z中确定比特序列Y和校验序列即可。
例如，可选地，在第二比特序列中，每个子比特序列与所对应的子校验序列相邻。
具体地说，在本发明实施例中，编码设备可以将每个子比特序列和与其相对应的子校验序列合并，例如，可以在每个子比特序列末尾添加与其相对应的子校验序列，形成P个比特序列(记做：序列Z1～序列ZP)，并将该序列Z1～序列ZP合并，形成序列Z。
图10是分段处理时编码过程的另一例的示意图。不失一般性，以将比特序列Y分为2个(P＝2)子比特序列时的处理为例：
如图10所示，首先，编码设备可以在信息比特中插入固定比特，以生成序列Y，其后，编码设备可以将序列Y分成长度为λN-α1的子序列Y1和长度为(1-λ)N-α2的两个子序列Y2。
其后，编码设备可以对长度为λN-α1的序列Y1进行校验处理，得到α1个校验比特，作为序列Y1所对应的子校验序列W1。并且，编码设备可以将子校验序列W1添加至序列Y1的末尾，得到长度为λN的序列Z1。
类似地，编码设备可以对长度为(1-λ)N-α2的序列Y2进行校验处理，得到α2个校验比特，作为序列Y2所对应的子校验序列W2。并且，编码设备可以将子校验序列W2添加至序列Y2的末尾，得到长度为(1-λ)N的序列Z2。
从而，编码设备可以将序列Z1和序列Z2合并，得到长度为N的序列Z。
此情况下，序列Z可以为Y1W1Y2W2。
应理解，以上列举的序列Z的形式仅为示例性说明，本发明实施例并未限定于此，只要能够使译码设备准确地从序列Z中区分Y1、W1、Y2和W2即可，例如，该序列Z还可以为Y1Y2W1W2。
在通过上述方式1或方式2获得长度为N的序列Z之后。
在S440，编码设备可以使序列Z乘以核矩阵
Figure PCTCN2017000050-appb-000047
(即，GN)，得到最终的极化码码字，并将其传输至译码设备。
根据本发明实施例的极化码的编码方法，通过使编码设备对包括信息比特和固定比特的第一比特序列进行校验处理，以确定校验比特，并将该第一比特序列与该校验比特进行合并，生成第二比特序列，其后，编码设备可以根据该第二比特序列，生成极化码序列，从而，译码设备可以在对该极化码序列进行译码处理而获取该第二比特序列后，基于该第二比特序列中的校验比特，对该第二比特序列中的第一比特序列进行校验处理，即，能够在确定信息比特之前，完成校验过程。特别是在基于SCL译码算法等的译码过程中，能够获得多个路径的估值，在本发明实施例中，能够在无需获取每个路径中的信息比特的情况下进行校验处理，从而可以仅保留校验通过的路径，并将该校验通过的路径中的信息比特作为译码输出，大大缩短了译码处理的延时，改善了用户体验。
图11是本发明实施例的极化码的译码方法500的示意性流程图，图9所示的方法500可以由译码设备，例如，无线通信设备中的Polar码译码器执行，该方法500包括：
S510，译码设备获取极化码序列；
S520，该译码设备对该极化码序列进行译码处理，以获取至少一个第二比特序列，其中，该第二比特序列包括第一比特序列和校验序列，其中，该校验序列是基于该第一比特序列生成的，该第一比特序列包括信息比特和固定比特，该信息比特用于承载目标信息，该固定比特用于承载预设信息；
S530，该译码设备根据每个第二比特序列中的第一比特序列，获取每个第二比特序列所对应的验证序列，并根据每个第二比特序列所对应的验证序列和每个第二比特序列中的校验序列，从该至少一个第二比特序列中确定目标第二比特序列，其中，该目标第二比特序列所对应的验证序列与该目标第二比特序列中的校验序列相同；
S540，该译码设备根据该目标第二比特序列中的信息比特，确定编码设备所传输的目标信息。
其中，可选地，该译码设备根据每个第二比特序列中的第一比特序列，获取每个第二比特序列所对应的验证序列，包括：
该译码设备根据该第一比特序列的长度，确定并行度M，M≥2；
该译码设备根据该并行度M，对该第一比特序列进行校验处理，以获取该校验序列。
或者，可选地，该译码设备根据每个第二比特序列中的P个子比特序列，获取每个第二比特序列所对应的验证序列，包括：
该译码设备根据每个第二比特序列中的第p个子比特序列的长度，确定该第p个子比特序列所对应的并行度m，其中，m≥2，p∈[1，P]；
该译码设备根据该第p个子比特序列所对应的并行度m，对该第p个子比特序列进行校验处理，以获取该第p个子比特序列所对应的子验证序列。
具体地说，在S510，译码设备接收编码设备发送的极化码序列。
在S520，译码设备对所接收到的该极化码序列进行译码处理，获得该极化码序列的译码估值(即，第二比特序列的一例)，其中，该译码估值包括与上述比特序列Y相对应的序列(即，第一比特序列的一例)以及与上述校验序列W相对应的序列(即，校验序列的一例)。
需要说明的是，如图在译码设备使用例如SCL译码算法进行译码处理时，能够获取多个路径的译码估值(或者说，多个第二比特序列)，并且，每个路径的第二比特序列均包含第一比特序列和验证序列。
以下，为了便于理解和区分，不失一般性，以译码设备对第i个路径的第二比特序列(记做，第二比特序列#i)的处理为例，对后续译码过程进行详细说明。
根据上述针对编码过程的描述，该第二比特序列#i包括N个比特，其中，该第二比特序列#i中的第一比特序列(以下，为了便于理解和区分，记做：第一比特序列#i)包括K-α个信息比特，并且，该第一比特序列#i包括N-K个固定比特，该第二比特序列#i中的校验序列(以下，为了便于理解和区分，记做：校验序列#i)包括α个校验比特。
这里，该第一比特序列#i中的比特位于第二比特序列#i中的第一预设比特位，该校验序列#i中的比特位于第二比特序列#i中的第二预设比特位。
在本发明实施例中，该第一预设比特位与第二预设比特位的具体位置可以由系统或通信协议规定，从而，译码设备可以根据该规定，从该第二比特序列中确定第一比特序列和校验序列。
或者，可选地，在该译码设备根据每个第二比特序列中的第一比特序列， 获取每个第二比特序列所对应的验证序列之前，该方法还包括：
该译码设备接收该编码设备发送第一指示信息，该第一指示信息用于指示该第一预设比特位在该第二比特序列中位置，或该第一指示信息用于指示该第二预设比特位在该第二比特序列中位置；
该译码设备根据该第一指示信息，确定每个第二比特序列中的第一比特序列和校验序列。
具体地说，在本发明实施例中，编码设备还可以将第一预设比特位的具体位置的指示信息(即，第一指示信息的一例)和/或第二预设比特位的具体位置的指示信息(即，第一指示信息的另一例)发送给译码设备，从而，译码设备可以根据该第一指示信息，从该第二比特序列#i中确定第一比特序列#i和校验序列#i。
在本发明实施例中，该校验比特#i可能是编码设备通过上述方式1生成的。
此情况下，在S530，译码设备可以对第一比特序列#i整体进行CRC校验处理，以获取针对该第一比特序列#i整体的验证序列#i，该验证序列#i包括α个验证比特，另外，该过程与编码设备对比特序列Y整体进行CRC校验处理，以获取针对包括α个校验比特的校验序列的过程相似，这里，为了避免赘述，省略其详细说明。
需要说明的是，在本发明实施例中，译码设备也可以采用并行方式进行CRC校验处理，此情况下，译码设备所使用的并行度与编码设备所使用的并行度可以相同也可以不同，本发明实施例并未特别限定。
可选地，该第一比特序列的长度为2的整数次幂。
可选地，该并行度M为2的整数次幂。
具体地说，在本发明实施例中，由于第一比特序列#i的长度为2的整数次幂，因此在确定并行度时，只要使所选取的并行度的值为2的整数次幂即可，采用一个并行度便能够完成基于并行方式的CRC校验处理，大大降低了实现复杂度，节省了处理时延，因此更适合实际系统应用。
与此相对，在现有技术中，由于CRC校验处理的对象为信息比特(即，本发明实施例中的比特序列X)，以LTE协议3GPP TS 36.212与3GPP TS 36.213规定的编码块长度(即输入编码器的信息比特数量)与速率适配后可能的长度为例，信息比特数量的可能的取值共有188种，取值范围从40到 6144，很难统一CRC校验处理的并行度。
在获取验证序列#i之后，译码设备可以将该验证序列#i和校验序列#i进行对比，
如果验证序列#i与校验序列#i相同，则译码设备可以确定该第一比特序列#i通过验证，并在S540，译码设备可以从该第一比特序列#i中提取信息比特，并获取承载于该信息比特中的目标信息。
如果验证序列#i与校验序列#i不相同，则译码设备可以确定该第一比特序列#i未通过验证，并可以将第二比特序列#i(或者说，第一比特序列#i)舍弃。
在本发明实施例中，该校验比特也可能是编码设备通过上述方式2生成的。
此情况下，可选地，每个第二比特序列中的第一比特序列包括P个子比特序列，每个子比特序列包括信息比特和固定波特，P≥2，并且，每个第二比特序列中的校验序列包括P个子校验序列，该P个子比特序列与该P个子校验序列一一对应，每个子校验序列是根据该对应的子比特序列生成的，以及
该译码设备根据每个第二比特序列中的第一比特序列，获取每个第二比特序列所对应的验证序列，并根据每个第二比特序列所对应的验证序列和每个第二比特序列中的校验序列，从该L个第二比特序列中确定目标第二比特序列，包括：
该译码设备确定每个第二比特序列中的P个子比特序列和P个子校验序列；
该译码设备根据每个第二比特序列中的P个子比特序列，获取每个第二比特序列所对应的验证序列，其中，每个第二比特序列所对应的验证序列包括P个子验证序列，该P个子比特序列与该P个子验证序列一一对应，每个子验证序列是根据该对应的子比特序列生成的；
该译码设备根据每个第二比特序列所对应的P个子验证序列和每个第二比特序列中的P个子校验序列，确定目标第二比特序列，其中，对于目标第二比特序列中的任一子比特序列，该子比特序列所对应的子验证序列和该子比特序列所对应的子校验序列相同。
其中，可选地，该译码设备根据每个第二比特序列中的第一比特序列， 获取每个第二比特序列所对应的验证序列，包括：
该译码设备根据该第一比特序列的长度，确定并行度M，M≥2；
该译码设备根据该并行度M，对该第一比特序列进行校验处理，以获取该校验序列。
具体地说，在本发明实施例中，译码设备可以确定第一比特序列#i所包括的各子比特序列，以及，校验序列#i所包括的各子校验序列。
在本发明实施例中，各子比特序列的长度和位置以及各子校验序列的长度和位置可以是有系统或者通信协议规定的，从而，译码设备可以根据该规定，区分各子比特序列和各子校验序列。
或者，该方法还包括：
该译码端设备接收该编码设备发送的第二指示信息，该第二指示信息用于指示该第一比特序列中的每个子比特序列，并且，该第二指示信息用于指示每个子比特序列所对应的子校验序列。
具体地说，在本发明实施例中，编码设备还可以向译码设备发送每个子比特序列在该第二比特序列#i中的位置的指示信息，以及每个子校验序列在该第二比特序列#i中的位置的指示信息(即，第二指示信息的一例)，从而，译码设备可以根据该第二指示信息，区分各子比特序列和各子校验序列。
从而，在S530，译码设备可以对各子比特序列分别进行CRC校验处理，以获取每个子比特序列所对应的验证序列(记做：子验证序列)，其中，所有子验证序列共包括α个验证比特，另外，该过程与编码设备对每个子比特序列进行CRC校验处理，以获取各子校验序列的过程相似，这里，为了避免赘述，省略其详细说明。
可选地，每个子比特序列的长度为2的整数次幂。
可选地，该并行度M为2的整数次幂。
具体地说，在本发明实施例中，由于第一比特序列#i中的每个子比特序列的长度为2的整数次幂，因此在确定对每个子比特序列进行CRC校验处理所使用的并行度时，只要使所选取的并行度的值为2的整数次幂即可，仅需要采用一个并行度便能够完成基于并行方式的CRC校验处理，大大降低了实现复杂度，节省了处理时延，因此更适合实际系统应用。
与此相对，在现有技术中，由于CRC校验处理的对象为信息比特(即，本发明实施例中的比特序列X)，以LTE协议3GPP TS 36.212与3GPP TS  36.213规定的编码块长度(即输入编码器的信息比特数量)与速率适配后可能的长度为例，信息比特数量的可能的取值共有188种，取值范围从40到6144，很难统一CRC校验处理的并行度。
如上所述，译码设备可以确定在获取第一比特序列#i中的每个子序列所对应的子验证序列，不失一般性，将第一比特序列#i中的第j个子序列(记做：子序列#j)所对应的子验证序列记做子验证序列#j，将校验序列#i中与该子序列#j相对应的子校验序列记做：子校验序列#j。
之后，译码设备可以将该子验证序列#j和子校验序列#j进行对比，
如果子验证序列#j与子校验序列#j相同，则译码设备可以确定该子序列#j通过验证；
如果子验证序列#j与子校验序列#j不相同，则译码设备可以确定该子序列#j未通过验证，并且，可以将第一比特序列#i(或者说，第二比特序列#i)舍弃。
从而，译码设备可以确定该多路第二序列中所有子序列均通过验证的一路第二比特序列(记做：目标第二比特序列)，在S440，译码设备可以从该目标第二比特序列所包括的第一比特序列中提取信息比特，并获取承载于该信息比特中的目标信息。
图12是译码过程的一例的示意图，如图12所示，译码设备可以对所接收到的计划进行基于SCL译码算法的译码处理，以获取L个路径的第二比特序列(包括第一比特序列和校验比特)，其后，译码设备可以对每个路径的第二比特序列中的第一比特序列进行校验处理，得到每个路径的验证比特，进而，译码设备可以对每个路径的验证比特和校验比特进行对比处理，从而，译码设备能够确定验证比特和校验比特相同的一个路径，作为验证通过的路径，并从该路径的第二比特序列中提取信息比特，确定为编码段发送的信息。
根据本发明实施例的极化码的译码方法通过使编码设备对包括信息比特和固定比特的第一比特序列进行校验处理，以确定校验比特，并将该第一比特序列与该校验比特进行合并，生成第二比特序列，其后，编码设备可以根据该第二比特序列，生成极化码序列，从而，译码设备可以在对该极化码序列进行译码处理而获取该第二比特序列后，基于该第二比特序列中的校验比特，对该第二比特序列中的第一比特序列进行校验处理，即，能够在确定 信息比特之前，完成校验过程。特别是在基于SCL译码算法等的译码过程中，能够获得多个路径的估值，在本发明实施例中，能够在无需获取每个路径中的信息比特的情况下进行校验处理，从而可以仅保留校验通过的路径，并将该校验通过的路径中的信息比特作为译码输出，大大缩短了译码处理的延时，改善了用户体验。
上文中，结合图1至图12，详细描述了根据本发明实施例的极化码的编码方法和译码方法，下面，将结合图13和图14，详细描述根据本发明实施例的极化码的编码装置和译码装置。
图13是本发明一个实施例的极化码的编码装置600的结构框图。图13所示的极化码的编码装置600包括：生成单元610，与该生成单元610相连的校验单元620，与该校验单元620和生成单元610相连的编码单元630。
其中，该生成单元610用于根据需要传输至译码设备的目标信息，生成第一比特序列，该第一比特序列包括信息比特和固定比特，该信息比特用于承载该目标信息，该固定比特用于承载预设信息。
该校验单元620用于从生成单元610获取该第一比特序列，并根据该第一比特序列，确定校验比特。；
该编码单元630，用于从生成单元610获取该第一比特序列，从校验单元620获取该校验比特，并根据该第一比特序列和该校验比特，生成第二比特序列，进而用于根据该第二比特序列，生成极化码序列。
可选地，该校验单元具体用于根据该第一比特序列的长度，确定并行度M，M≥2；
用于根据该并行度M，对该第一比特序列进行校验处理，以获取该校验比特。
可选地，该编码装置还包括：
发送单元，用于向该译码设备发送第一指示信息，该第一指示信息用于指示该第一预设比特位在该第二比特序列中位置，或
该第一指示信息用于指示该第二预设比特位在该第二比特序列中位置。
可选地，该校验单元具体用于对该第一比特序列进行分段处理，以生成P个子比特序列，每个子比特序列包括信息比特和固定比特，P≥2；
用于根据该P个子比特序列，确定校验比特，其中，该校验比特包括P个子校验比特，该P个子比特序列与该P个子校验比特一一对应，每个子校 验比特是根据该对应的子比特序列生成的。
可选地，该校验单元具体用于根据第p个子比特序列的长度，确定该第p个子比特序列所对应的并行度，其中，p∈[1，P]；
用于根据该第p个子比特序列所对应的并行度，对该第p个子比特序列进行校验处理，以获取该第p个子比特序列所对应的子校验比特。
可选地，该编码装置还包括：
发送单元，用于向该译码设备发送第二指示信息，该第二指示信息用于指示该第一比特序列中的每个子比特序列，并且，该第二指示信息用于指示每个子比特序列所对应的子校验序列。
根据本发明实施例的极化码的编码装置600可对应于本发明实施例的极化码的编码方法500的实施主体，并且，该极化码的编码装置600中的各单元和上述其他操作和/或功能分别为了实现图4中的极化码的编码方法500的相应流程，为了简洁，在此不再赘述。
根据本发明实施例的极化码的编码装置，通过使编码设备对包括信息比特和固定比特的第一比特序列进行校验处理，以确定校验比特，并将该第一比特序列与该校验比特进行合并，生成第二比特序列，其后，编码设备可以根据该第二比特序列，生成极化码序列，从而，译码设备可以在对该极化码序列进行译码处理而获取该第二比特序列后，基于该第二比特序列中的校验比特，对该第二比特序列中的第一比特序列进行校验处理，即，能够在确定信息比特之前，完成校验过程。特别是在基于SCL译码算法等的译码过程中，能够获得多个路径的估值，在本发明实施例中，能够在无需获取每个路径中的信息比特的情况下进行校验处理，从而可以仅保留校验通过的路径，并将该校验通过的路径中的信息比特作为译码输出，大大缩短了译码处理的延时，改善了用户体验。
图14是本发明一个实施例的极化码的译码装置700的结构框图。图14所示的极化码的译码装置700包括：获取单元710，与该获取单元710相连的译码单元720，与该译码单元相连的校验单元730，与该校验单元730相连的确定单元740。
其中，该获取单元710用于获取极化码序列。
该译码单元720用于对从该获取单元710获取的该极化码序列进行译码处理，以获取至少一个第二比特序列，其中，该第二比特序列包括位于第一 预设比特位的第一比特序列和位于第二预设比特位的校验比特，其中，该校验比特是基于该第一比特序列生成的，该第一比特序列包括信息比特和固定比特，该信息比特用于承载目标信息，该固定比特用于承载预设信息；
校验单元730用于根据从该译码单元720获取的每个第二比特序列中的第一比特序列，获取每个第二比特序列所对应的验证比特，并根据每个第二比特序列所对应的验证比特和每个第二比特序列中的校验比特，从该至少一个第二比特序列中确定目标第二比特序列，其中，该目标第二比特序列所对应的验证比特与该目标第二比特序列中的校验比特相同；
确定单元740用于根据从该校验单元730获取的该目标第二比特序列中的信息比特，确定编码设备所传输的目标信息。
可选地，该校验单元具体用于根据该第一比特序列的长度，确定并行度M，M≥2；
用于根据该并行度M，对该第一比特序列进行校验处理，以获取该校验比特。
可选地，该译码装置还包括：
接收单元，用于接收该编码设备发送第一指示信息，该第一指示信息用于指示该第一预设比特位在该第二比特序列中位置，或该第一指示信息用于指示该第二预设比特位在该第二比特序列中位置；
该校验单元还用于根据该第一指示信息，确定每个第二比特序列中的第一比特序列和校验比特。
可选地，每个第二比特序列中的第一比特序列包括P个子比特序列，每个子比特序列包括信息比特和固定比特，P≥2，并且，每个第二比特序列中的校验比特包括P个子校验比特，该P个子比特序列与该P个子校验比特一一对应，每个子校验比特是根据该对应的子比特序列生成的，以及
该译码单元具体用于确定每个第二比特序列中的P个子比特序列和P个子校验比特；
用于根据每个第二比特序列中的P个子比特序列，获取每个第二比特序列所对应的验证比特，其中，每个第二比特序列所对应的验证比特包括P个子验证比特，该P个子比特序列与该P个子验证比特一一对应，每个子验证比特是根据该对应的子比特序列生成的；
用于根据每个第二比特序列所对应的P个子验证比特和每个第二比特 序列中的P个子校验比特，确定目标第二比特序列，其中，对于目标第二比特序列中的任一子比特序列，该子比特序列所对应的子验证比特和该子比特序列所对应的子校验比特相同。
可选地，该校验单元具体用于根据每个第二比特序列中的第p个子比特序列的长度，确定该第p个子比特序列所对应的并行度m，其中，m≥2，p∈[1，P]；
用于根据该第p个子比特序列所对应的并行度m，对该第p个子比特序列进行校验处理，以获取该第p个子比特序列所对应的子验证比特。
可选地，该译码装置还包括：
接收单元，用于接收该编码设备发送的第二指示信息，该第二指示信息用于指示该第一比特序列中的每个子比特序列，并且，该第二指示信息用于指示每个子比特序列所对应的子校验序列。
根据本发明实施例的极化码的译码装置700可对应于本发明实施例的极化码的译码方法500的实施主体，并且，该极化码的译码装置700中的各单元和上述其他操作和/或功能分别为了实现图11中的极化码的译码方法500的相应流程，为了简洁，在此不再赘述。
根据本发明实施例的极化码的译码装置，通过使编码设备对包括信息比特和固定比特的第一比特序列进行校验处理，以确定校验比特，并将该第一比特序列与该校验比特进行合并，生成第二比特序列，其后，编码设备可以根据该第二比特序列，生成极化码序列，从而，译码设备可以在对该极化码序列进行译码处理而获取该第二比特序列后，基于该第二比特序列中的校验比特，对该第二比特序列中的第一比特序列进行校验处理，即，能够在确定信息比特之前，完成校验过程。特别是在基于SCL译码算法等的译码过程中，能够获得多个路径的估值，在本发明实施例中，能够在无需获取每个路径中的信息比特的情况下进行校验处理，从而可以仅保留校验通过的路径，并将该校验通过的路径中的信息比特作为译码输出，大大缩短了译码处理的延时，改善了用户体验。
图15是适用本发明实施例的极化码的编码设备的示意性结构图。如图15所示，该设备800包括：处理器810和发射器820，处理器810和发射器820相连，可选地，该设备800还包括存储器830，存储器830与处理器810相连，进一步可选地，该设备800包括总线系统840。其中，处理器810、 存储器820和发送器830可以通过总线系统840相连，该存储器830可以用于存储指令，该处理器810用于执行该存储器830存储的指令，以控制接收器820接收信息或信号；
处理器810用于根据需要传输至译码设备的目标信息，生成第一比特序列，该第一比特序列包括信息比特和固定比特，该信息比特用于承载该目标信息，该固定比特用于承载预设信息；
该处理器810用于根据该第一比特序列，确定校验比特；
该处理器810用于根据该第一比特序列和该校验比特，生成第二比特序列；
该处理器810用于根据该第二比特序列，生成极化码序列。
可选地，该处理器具体用于根据该第一比特序列的长度，确定并行度M，M≥2；
该处理器具体用于根据该并行度M，对该第一比特序列进行校验处理，以获取该校验比特。
可选地，该编码设备还包括与该总线相连的发射器；以及
该处理器还用于控制该发射机向该译码设备发送第一指示信息，该第一指示信息用于指示该第一比特序列在该第二比特序列中位置，或该第一指示信息用于指示该校验比特在该第二比特序列中位置。
可选地，该处理器具体用于对该第一比特序列进行分段处理，以生成P个子比特序列，每个子比特序列包括信息比特和固定比特，P≥2；
该处理器具体用于根据该P个子比特序列，确定校验比特，其中，该校验比特包括P个子校验比特，该P个子比特序列与该P个子校验比特一一对应，每个子校验比特是根据该对应的子比特序列生成的。
可选地，该处理器具体用于根据第p个子比特序列的长度，确定该第p个子比特序列所对应的并行度m，其中，m≥2，p∈[1，P]；
该处理器具体用于根据该第p个子比特序列所对应的并行度，对该第p个子比特序列进行校验处理，以获取该第p个子比特序列所对应的子校验比特。
可选地，该编码设备还包括与该总线相连的发射器；以及
该处理器还用于控制该发射机向该译码设备发送第二指示信息，该第二指示信息用于指示该第一比特序列中的每个子比特序列在该第二比特序列 中的位置，并且，该第二指示信息用于指示每个子比特序列所对应的子校验序列在该第二比特序列中的位置。
该编码设备可以嵌入或本身即为接入终端或网络设备。
根据本发明实施例的极化码的编码设备800可对应于本发明实施例的极化码的编码方法500的实施主体，并且，该极化码的编码设备800中的各单元和上述其他操作和/或功能分别为了实现图4中的极化码的编码方法500的相应流程，为了简洁，在此不再赘述。
根据本发明实施例的极化码的编码设备，通过使编码设备对包括信息比特和固定比特的第一比特序列进行校验处理，以确定校验比特，并将该第一比特序列与该校验比特进行合并，生成第二比特序列，其后，编码设备可以根据该第二比特序列，生成极化码序列，从而，译码设备可以在对该极化码序列进行译码处理而获取该第二比特序列后，基于该第二比特序列中的校验比特，对该第二比特序列中的第一比特序列进行校验处理，即，能够在确定信息比特之前，完成校验过程。特别是在基于SCL译码算法等的译码过程中，能够获得多个路径的估值，在本发明实施例中，能够在无需获取每个路径中的信息比特的情况下进行校验处理，从而可以仅保留校验通过的路径，并将该校验通过的路径中的信息比特作为译码输出，大大缩短了译码处理的延时，改善了用户体验。
图16是适用本发明实施例的极化码的译码设备的示意性结构图。如图16所示，该设备900包括：处理器910和接收器920，处理器910和接收器920相连，可选地，该设备900还包括存储器930，存储器930与处理器910相连，进一步可选地，该设备900包括总线系统940。其中，处理器910、存储器920和发送器930可以通过总线系统940相连，该存储器930可以用于存储指令，该处理器910用于执行该存储器930存储的指令，以控制接收器920接收信息或信号；
该处理器910用于获取极化码序列；
该处理器910用于对该极化码序列进行译码处理，以获取至少一个第二比特序列，其中，该第二比特序列包括第一比特序列和校验比特，其中，该校验比特是基于该第一比特序列生成的，该第一比特序列包括信息比特和固定比特，该信息比特用于承载目标信息，该固定比特用于承载预设信息；
该处理器910用于根据每个第二比特序列中的第一比特序列，获取每个 第二比特序列所对应的验证比特，并根据每个第二比特序列所对应的验证比特和每个第二比特序列中的校验比特，从该至少一个第二比特序列中确定目标第二比特序列，其中，该目标第二比特序列所对应的验证比特与该目标第二比特序列中的校验比特相同；
该处理器910用于根据该目标第二比特序列中的信息比特，确定编码设备所传输的目标信息。
可选地，该处理器具体用于根据该第一比特序列的长度，确定并行度M，M≥2；
该处理器具体用于根据该并行度M，对该第一比特序列进行校验处理，以获取该校验比特。
可选地，该译码设备还包括与该总线相连的接收机；以及
该处理器还用于控制该接收机接收该编码设备发送第一指示信息，该第一指示信息用于指示该第一比特序列在该第二比特序列中位置，或该第一指示信息用于指示该校验比特在该第二比特序列中位置。
可选地，每个第二比特序列中的第一比特序列包括P个子比特序列，每个子比特序列包括信息比特和固定波特，P≥2，并且，每个第二比特序列中的校验比特包括P个子校验比特，该P个子比特序列与该P个子校验比特一一对应，每个子校验比特是根据该对应的子比特序列生成的，以及
该处理器具体用于确定每个第二比特序列中的P个子比特序列和P个子校验比特；
该处理器具体用于根据每个第二比特序列中的P个子比特序列，获取每个第二比特序列所对应的验证比特，其中，每个第二比特序列所对应的验证比特包括P个子验证比特，该P个子比特序列与该P个子验证比特一一对应，每个子验证比特是根据该对应的子比特序列生成的；
该处理器具体用于根据每个第二比特序列所对应的P个子验证比特和每个第二比特序列中的P个子校验比特，确定目标第二比特序列，其中，对于目标第二比特序列中的任一子比特序列，该子比特序列所对应的子验证比特和该子比特序列所对应的子校验比特相同。
可选地，该处理器具体用于根据每个第二比特序列中的第p个子比特序列的长度，确定该第p个子比特序列所对应的并行度m，其中，m≥2，p∈[1，P]；
该处理器具体用于根据该第p个子比特序列所对应的并行度m，对该第p个子比特序列进行校验处理，以获取该第p个子比特序列所对应的子验证比特。
可选地，该译码设备还包括与该总线相连的接收机；以及
该处理器还用于控制该接收机接收该编码设备发送的第二指示信息，该第二指示信息用于指示该第一比特序列中的每个子比特序列在该第二比特序列中的位置，并且，该第二指示信息用于指示每个子比特序列所对应的子校验序列在该第二比特序列中的位置。
该译码设备可以嵌入或本身即为接入终端或网络设备。
根据本发明实施例的极化码的译码设备900可对应于本发明实施例的极化码的译码方法500的实施主体，并且，该极化码的译码设备900中的各单元和上述其他操作和/或功能分别为了实现图11中的极化码的译码方法500的相应流程，为了简洁，在此不再赘述。
根据本发明实施例的极化码的译码设备，通过使编码设备对包括信息比特和固定比特的第一比特序列进行校验处理，以确定校验比特，并将该第一比特序列与该校验比特进行合并，生成第二比特序列，其后，编码设备可以根据该第二比特序列，生成极化码序列，从而，译码设备可以在对该极化码序列进行译码处理而获取该第二比特序列后，基于该第二比特序列中的校验比特，对该第二比特序列中的第一比特序列进行校验处理，即，能够在确定信息比特之前，完成校验过程。特别是在基于SCL译码算法等的译码过程中，能够获得多个路径的估值，在本发明实施例中，能够在无需获取每个路径中的信息比特的情况下进行校验处理，从而可以仅保留校验通过的路径，并将该校验通过的路径中的信息比特作为译码输出，大大缩短了译码处理的延时，改善了用户体验。
图17是在无线通信系统中有助于执行前述极化码的编码方法或译码方法的接入终端1000的示图。接入终端1000包括接收机1002，接收机1002用于从例如接收天线(未示出)接收信号，并对所接收的信号执行典型的动作(例如过滤、放大、下变频等)，并对调节后的信号进行数字化以获得采样。接收机1002可以是例如MMSE(最小均方误差，Minimum Mean-Squared Error)接收机。接入终端1000还可包括解调器1004，解调器1004可用于解调所接收的信号并将它们提供至处理器1006用于信道估计。处理器1006 可以是专用于分析由接收机1002接收的信息和/或生成由发射机1016发送的信息的处理器、用于控制接入终端1000的一个或多个部件的处理器、和/或用于分析由接收机1002接收的信号、生成由发射机1016发送的信息并控制接入终端1000的一个或多个部件的控制器。
接入终端1000可以另外包括存储器1008，后者可操作地耦合至处理器1006，并存储以下数据：要发送的数据、接收的数据以及与执行本文所述的各种动作和功能相关的任意其它适合信息。存储器1008可附加地存储极化码处理的相关的协议和/或算法。
实际的应用中，接收机1002还可以耦合至极化码译码器1012和速率匹配设备(图中未示出)。
在本发明实施例中，极化码译码器1012可以在处理器1006的控制下执行上述方法500的具体过程。
此外，接入终端1000还可以包括调制器1014和发射机1016，该发射机1016用于向例如基站、另一接入终端等发送信号。
实际的应用中，发射机1016还可以耦合至极化码编码器1018和速率匹配设备(图中未示出)。
在本发明实施例中，极化码编码器1018可以在处理器1006的控制下执行上述方法400的具体过程。
尽管图17中极化码译码器1012或极化码r编码器1018是与处理器1006分离的，但是可以理解，极化码译码器1012或极化码r编码器1018也可以是处理器1006或多个处理器(未示出)的一部分。另外，接收机1002和发射机1016在实际应用时也可以集成在一起，形成一个收发机。
图18是在无线通信系统中有助于执行前述极化码的编码方法或译码方法的网络设备1100的示图。网络设备1100具有通过多个接收天线1106从一个或多个接入终端接收信号的接收机1110，以及通过发射天线11011向一个或多个接入终端发射信号的发射机1124。一般的，“接收天线”和“发射天线”可以集成在一起形成一个收发天线。接收机1110可以从接收天线1106接收信息，并且可操作地关联至对接收信息进行解调的解调器1112。通过处理器1114来分析所解调的符号，该处理器1114连接至存储器1120，该存储器1120用于存储要发送至接入终端(或不同的基站)的数据或从接入终端(或不同的基站)接收的数据和/或与执行本文所述的各个动作和功能相关的 任意其它适合信息。
接收机1110和处理器1114还可耦合至极化码译码器1116和速率匹配装置(未图示)。
该极化码译码器1116可以在处理器1114的控制下执行上述方法500的具体过程。
此外，网络设备1100还可以包括调制器1122和发射机1124，该发射机1124用于向例如基站、另一接入终端等发送信号。
发射机1124和处理器1114还可耦合至极化码编码器1118和速率匹配装置(未图示)。
在本发明实施例中，极化码编码器1118可以在处理器1114的控制下执行上述方法400的具体过程。
尽管图18中极化码编码器1116或极化码译码器1116是与处理器1114分离的，但是可以理解，极化码编码器1116或极化码译码器1116可以是处理器614或多个处理器(未示出)的一部分。
在本发明实施例中，处理器可能是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法实施例的各步骤可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器可以是通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现成可编程门阵列(Field Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本发明实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本发明实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤。
可以理解，本发明实施例中的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电 可擦除可编程只读存储器(Electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(Static RAM，SRAM)、动态随机存取存储器(Dynamic RAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(Synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(Direct Rambus RAM，DR RAM)。应注意，本文描述的系统和方法的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
可以理解的是，本文描述的这些实施例可以用硬件、软件、固件、中间件、微码或其组合来实现。对于硬件实现，处理单元可以实现在一个或多个ASIC、DSP、DSPD、PLD、FPGA、处理器、控制器、微控制器、微处理器、芯片等用于执行本申请所述功能的其它电子单元或其组合中。
当在软件、固件、中间件或微码、程序代码或代码段中实现实施例时，它们可存储在例如存储部件的机器可读介质中。代码段可表示过程、函数、子程序、程序、例程、子例程、模块、软件分组、类、或指令、数据结构或程序语句的任意组合。代码段可通过传送和/或接收信息、数据、自变量、参数或存储器内容来稿合至另一代码段或硬件电路。可使用包括存储器共享、消息传递、令牌传递、网络传输等任意适合方式来传递、转发或发送信息、自变量、参数、数据等。
对于软件实现，可通过执行本文所述功能的模块(例如过程、函数等)来实现本文所述的技术。软件代码可存储在存储器中并通过处理器执行。存储器单元可以在处理器中或在处理器外部实现，在后一种情况下存储器单元可经由本领域己知的各种手段以通信方式耦合至处理器。
应理解，本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
应理解，在本发明实施例中，上述各过程的序号的大小并不意味着执行 顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本发明实施例的实施过程构成任何限定。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明实施例的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明实施例的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only  Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本发明实施例的具体实施方式，但本发明实施例的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明实施例揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明实施例的保护范围之内。

Claims (24)

  1. 一种极化码的编码方法，其特征在于，包括：
    编码设备根据需要传输至译码设备的目标信息，生成第一比特序列，所述第一比特序列包括信息比特和固定比特，所述信息比特用于承载所述目标信息，所述固定比特用于承载预设信息；
    所述编码设备根据所述第一比特序列，确定校验比特；
    所述编码设备根据所述第一比特序列和所述校验比特，生成第二比特序列；
    所述编码设备根据所述第二比特序列，生成极化码序列。
  2. 根据权利要求1所述的编码方法，其特征在于，所述编码设备根据所述第一比特序列，确定校验比特，包括：
    所述编码设备根据所述第一比特序列的长度，确定并行度M，M≥2；
    所述编码设备根据所述并行度M，对所述第一比特序列进行校验处理，以获取所述校验比特。
  3. 根据权利要求1或2所述的编码方法，其特征在于，所述编码方法还包括：
    所述编码设备向所述译码设备发送第一指示信息，所述第一指示信息用于指示所述第一比特序列在所述第二比特序列中位置，或所述第一指示信息用于指示所述校验比特在所述第二比特序列中位置。
  4. 根据权利要求1所述的编码方法，其特征在于，所述编码设备根据所述第一比特序列，确定校验比特，包括：
    所述编码设备对所述第一比特序列进行分段处理，以生成P个子比特序列，每个子比特序列包括信息比特和固定比特，P≥2；
    所述编码设备根据所述P个子比特序列，确定校验比特，其中，所述校验比特包括P个子校验比特，所述P个子比特序列与所述P个子校验比特一一对应，每个子校验比特是根据所述对应的子比特序列生成的。
  5. 根据权利要求4所述的编码方法，其特征在于，所述编码设备根据所述P个子比特序列，确定校验比特，包括：
    所述编码设备根据第p个子比特序列的长度，确定所述第p个子比特序列所对应的并行度m，其中，m≥2，p∈[1，P]；
    所述编码设备根据所述第p个子比特序列所对应的并行度m，对所述第 p个子比特序列进行校验处理，以获取所述第p个子比特序列所对应的子校验比特。
  6. 根据权利要求4或5所述的编码方法，其特征在于，所述编码方法还包括：
    所述编码端设备向所述译码设备发送第二指示信息，所述第二指示信息用于指示所述第一比特序列中的每个子比特序列在所述第二比特序列中的位置，并且，所述第二指示信息用于指示每个子比特序列所对应的子校验序列在所述第二比特序列中的位置。
  7. 一种极化码的译码方法，其特征在于，包括：
    译码设备获取极化码序列；
    所述译码设备对所述极化码序列进行译码处理，以获取至少一个第二比特序列，其中，所述第二比特序列包括第一比特序列和校验比特，所述校验比特是基于所述第一比特序列生成的，所述第一比特序列包括信息比特和固定比特，所述信息比特用于承载目标信息，所述固定比特用于承载预设信息；
    所述译码设备根据每个第二比特序列中的第一比特序列，获取每个第二比特序列所对应的验证比特，并根据每个第二比特序列所对应的验证比特和每个第二比特序列中的校验比特，从所述至少一个第二比特序列中确定目标第二比特序列，其中，所述目标第二比特序列所对应的验证比特与所述目标第二比特序列中的校验比特相同；
    所述译码设备根据所述目标第二比特序列中的信息比特，确定编码设备所传输的目标信息。
  8. 根据权利要求7所述的译码方法，其特征在于，所述译码设备根据每个第二比特序列中的第一比特序列，获取每个第二比特序列所对应的验证比特，包括：
    所述译码设备根据所述第一比特序列的长度，确定并行度M，M≥2；
    所述译码设备根据所述并行度M，对所述第一比特序列进行校验处理，以获取所述校验比特。
  9. 根据权利要求7或8所述的译码方法，其特征在于，在所述译码设备根据每个第二比特序列中的第一比特序列，获取每个第二比特序列所对应的验证比特之前，所述译码方法还包括：
    所述译码设备接收所述编码设备发送第一指示信息，所述第一指示信息 用于指示所述第一比特序列在所述第二比特序列中位置，或所述第一指示信息用于指示所述校验比特在所述第二比特序列中位置；
    所述译码设备根据所述第一指示信息，确定每个第二比特序列中的第一比特序列和校验比特。
  10. 根据权利要求7所述的译码方法，其特征在于，每个第二比特序列中的第一比特序列包括P个子比特序列，每个子比特序列包括信息比特和固定波特，P≥2，并且，每个第二比特序列中的校验比特包括P个子校验比特，所述P个子比特序列与所述P个子校验比特一一对应，每个子校验比特是根据所述对应的子比特序列生成的，以及
    所述译码设备根据每个第二比特序列中的第一比特序列，获取每个第二比特序列所对应的验证比特，并根据每个第二比特序列所对应的验证比特和每个第二比特序列中的校验比特，从所述L个第二比特序列中确定目标第二比特序列，包括：
    所述译码设备确定每个第二比特序列中的P个子比特序列和P个子校验比特；
    所述译码设备根据每个第二比特序列中的P个子比特序列，获取每个第二比特序列所对应的验证比特，其中，每个第二比特序列所对应的验证比特包括P个子验证比特，所述P个子比特序列与所述P个子验证比特一一对应，每个子验证比特是根据所述对应的子比特序列生成的；
    所述译码设备根据每个第二比特序列所对应的P个子验证比特和每个第二比特序列中的P个子校验比特，确定目标第二比特序列，其中，对于目标第二比特序列中的任一子比特序列，所述子比特序列所对应的子验证比特和所述子比特序列所对应的子校验比特相同。
  11. 根据权利要求10所述的译码方法，其特征在于，所述译码设备根据每个第二比特序列中的P个子比特序列，获取每个第二比特序列所对应的验证比特，包括：
    所述译码设备根据每个第二比特序列中的第p个子比特序列的长度，确定所述第p个子比特序列所对应的并行度m，其中，m≥2，p∈[1，P]；
    所述译码设备根据所述第p个子比特序列所对应的并行度m，对所述第p个子比特序列进行校验处理，以获取所述第p个子比特序列所对应的子验证比特。
  12. 根据权利要求10或11所述的译码方法，其特征在于，所述译码方法还包括：
    所述译码端设备接收所述编码设备发送的第二指示信息，所述第二指示信息用于指示所述第一比特序列中的每个子比特序列在所述第二比特序列中的位置，并且，所述第二指示信息用于指示每个子比特序列所对应的子校验序列在所述第二比特序列中的位置。
  13. 一种极化码的编码设备，其特征在于，包括：
    总线；
    与所述总线相连的处理器；
    与所述总线相连的存储器；
    其中，所述处理器通过所述总线，调用所述存储器中存储的程序，以用于根据需要传输至译码设备的目标信息，生成第一比特序列，所述第一比特序列包括信息比特和固定比特，所述信息比特用于承载所述目标信息，所述固定比特用于承载预设信息；
    所述处理器用于根据所述第一比特序列，确定校验比特；
    所述处理器用于根据所述第一比特序列和所述校验比特，生成第二比特序列；
    所述处理器用于根据所述第二比特序列，生成极化码序列。
  14. 根据权利要求13所述的编码设备，其特征在于，所述处理器具体用于根据所述第一比特序列的长度，确定并行度M，M≥2；
    所述处理器具体用于根据所述并行度M，对所述第一比特序列进行校验处理，以获取所述校验比特。
  15. 根据权利要求13或14所述的编码设备，其特征在于，所述编码设备还包括与所述总线相连的发射机；以及
    所述处理器还用于控制所述发射机向所述译码设备发送第一指示信息，所述第一指示信息用于指示所述第一比特序列在所述第二比特序列中位置，或所述第一指示信息用于指示所述校验比特在所述第二比特序列中位置。
  16. 根据权利要求13所述的编码设备，其特征在于，所述处理器具体用于对所述第一比特序列进行分段处理，以生成P个子比特序列，每个子比特序列包括信息比特和固定比特，P≥2；
    所述处理器具体用于根据所述P个子比特序列，确定校验比特，其中， 所述校验比特包括P个子校验比特，所述P个子比特序列与所述P个子校验比特一一对应，每个子校验比特是根据所述对应的子比特序列生成的。
  17. 根据权利要求16所述的编码设备，其特征在于，所述处理器具体用于根据第p个子比特序列的长度，确定所述第p个子比特序列所对应的并行度m，其中，m≥2，p∈[1，P]；
    所述处理器具体用于根据所述第p个子比特序列所对应的并行度，对所述第p个子比特序列进行校验处理，以获取所述第p个子比特序列所对应的子校验比特。
  18. 根据权利要求16或17所述的编码设备，其特征在于，所述编码设备还包括与所述总线相连的发射机；以及
    所述处理器还用于控制所述发射机向所述译码设备发送第二指示信息，所述第二指示信息用于指示所述第一比特序列中的每个子比特序列在所述第二比特序列中的位置，并且，所述第二指示信息用于指示每个子比特序列所对应的子校验序列在所述第二比特序列中的位置。
  19. 一种极化码的译码设备，其特征在于，包括：
    总线；
    与所述总线相连的处理器；
    与所述总线相连的存储器；
    其中，所述处理器通过所述总线，调用所述存储器中存储的程序，以用于获取极化码序列；
    所述处理器用于对所述极化码序列进行译码处理，以获取至少一个第二比特序列，其中，所述第二比特序列包括第一比特序列和校验比特，其中，所述校验比特是基于所述第一比特序列生成的，所述第一比特序列包括信息比特和固定比特，所述信息比特用于承载目标信息，所述固定比特用于承载预设信息；
    所述处理器用于根据每个第二比特序列中的第一比特序列，获取每个第二比特序列所对应的验证比特，并根据每个第二比特序列所对应的验证比特和每个第二比特序列中的校验比特，从所述至少一个第二比特序列中确定目标第二比特序列，其中，所述目标第二比特序列所对应的验证比特与所述目标第二比特序列中的校验比特相同；
    所述处理器用于根据所述目标第二比特序列中的信息比特，确定编码设 备所传输的目标信息。
  20. 根据权利要求19所述的译码设备，其特征在于，所述处理器具体用于根据所述第一比特序列的长度，确定并行度M，M≥2；
    所述处理器具体用于根据所述并行度M，对所述第一比特序列进行校验处理，以获取所述校验比特。
  21. 根据权利要求19或20所述的译码设备，其特征在于，所述译码设备还包括与所述总线相连的接收机；以及
    所述处理器还用于控制所述接收机接收所述编码设备发送第一指示信息，所述第一指示信息用于指示所述第一比特序列在所述第二比特序列中位置，或所述第一指示信息用于指示所述校验比特在所述第二比特序列中位置。
  22. 根据权利要求19所述的译码设备，其特征在于，每个第二比特序列中的第一比特序列包括P个子比特序列，每个子比特序列包括信息比特和固定波特，P≥2，并且，每个第二比特序列中的校验比特包括P个子校验比特，所述P个子比特序列与所述P个子校验比特一一对应，每个子校验比特是根据所述对应的子比特序列生成的，以及
    所述处理器具体用于确定每个第二比特序列中的P个子比特序列和P个子校验比特；
    所述处理器具体用于根据每个第二比特序列中的P个子比特序列，获取每个第二比特序列所对应的验证比特，其中，每个第二比特序列所对应的验证比特包括P个子验证比特，所述P个子比特序列与所述P个子验证比特一一对应，每个子验证比特是根据所述对应的子比特序列生成的；
    所述处理器具体用于根据每个第二比特序列所对应的P个子验证比特和每个第二比特序列中的P个子校验比特，确定目标第二比特序列，其中，对于目标第二比特序列中的任一子比特序列，所述子比特序列所对应的子验证比特和所述子比特序列所对应的子校验比特相同。
  23. 根据权利要求22所述的译码设备，其特征在于，所述处理器具体用于根据每个第二比特序列中的第p个子比特序列的长度，确定所述第p个子比特序列所对应的并行度m，其中，m≥2，p∈[1，P]；
    所述处理器具体用于根据所述第p个子比特序列所对应的并行度m，对所述第p个子比特序列进行校验处理，以获取所述第p个子比特序列所对应 的子验证比特。
  24. 根据权利要求10或11所述的译码设备，其特征在于，所述译码设备还包括与所述总线相连的接收机；以及
    所述处理器还用于控制所述接收机接收所述编码设备发送的第二指示信息，所述第二指示信息用于指示所述第一比特序列中的每个子比特序列在所述第二比特序列中的位置，并且，所述第二指示信息用于指示每个子比特序列所对应的子校验序列在所述第二比特序列中的位置。
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