WO2019242022A1 - 一种极化码译码方法及译码装置 - Google Patents

一种极化码译码方法及译码装置 Download PDF

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Publication number
WO2019242022A1
WO2019242022A1 PCT/CN2018/092500 CN2018092500W WO2019242022A1 WO 2019242022 A1 WO2019242022 A1 WO 2019242022A1 CN 2018092500 W CN2018092500 W CN 2018092500W WO 2019242022 A1 WO2019242022 A1 WO 2019242022A1
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decoding
decoded
check
bit sequence
target output
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PCT/CN2018/092500
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English (en)
French (fr)
Inventor
葛华楠
游治
张玉伦
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华为技术有限公司
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Priority to PCT/CN2018/092500 priority Critical patent/WO2019242022A1/zh
Priority to CN201880089146.4A priority patent/CN111713023B/zh
Publication of WO2019242022A1 publication Critical patent/WO2019242022A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes

Definitions

  • the present application relates to the field of communication technologies, and in particular, to a polar code decoding method and a decoding device.
  • the rapid evolution of wireless communication indicates that the fifth generation (5G) communication system will present some new features.
  • the three most typical communication scenarios include enhanced mobile Internet (eMBB) and massive machine connections.
  • Communication massive machine type communication, mMTC) and high-reliability low-latency communication (URLLC).
  • mMTC massive machine type communication
  • URLLC high-reliability low-latency communication
  • LTE long-term evolution
  • channel coding is one of the important research objects to meet the needs of 5G communication.
  • Polar codes are selected as the control channel coding method in the 5G standard.
  • Polar code can also be called Polar code, and it is the first and the only known channel coding method that can be strictly proved to reach the channel capacity.
  • the performance of polarized codes is far superior to that of Turbo codes and low density parity check (LDPC) codes.
  • the embodiments of the present application provide a method for decoding a polar code, which is used to simplify the complexity of the polar code in decoding and reduce the decoding delay.
  • an embodiment of the present application provides a method for decoding a polar code.
  • the method includes:
  • the to-be-decoded bit sequence includes information bits and calibration Check bits, the check bits are interspersed between the information bits; where 1 ⁇ i ⁇ N, N is the total number of decoded blocks in the bit sequence to be decoded, and L is an integer;
  • the decoded bit sequence corresponding to any target output path of the L target output paths are information bits, for the decoded bit sequence corresponding to any one of the target output paths, perform the following operations:
  • Test sequence; m is an integer greater than or equal to 1.
  • the embodiments of the present application can directly read m row vectors corresponding to m information bits from the first check matrix without using the D-CRC interleaving table and the D-CRC check matrix alternately, thereby saving chip power consumption. And can effectively simplify the complexity of Polar code decoding, reduce decoding delay; and no longer need to store D-CRC interleaving table, effectively saving chip area.
  • the method further includes: if it is determined that the check results of the decoding bit sequences corresponding to the L target output paths are all verification failures, stopping the first bit in the to-be-decoded sequence; i + 1 decoding block for decoding; if it is determined that the check result of the decoding bit sequence corresponding to at least one of the L target output paths is a verification success, based on the i-th decoding block's
  • the L target output paths decode the i + 1th decoding block in the bit sequence to be decoded.
  • the i + th output path of the i-th decoding block can be used to pair the i + th 1 decoding block for decoding, that is, at this time, the check results of the decoding bit sequences corresponding to the L target output paths respectively do not affect the L on which the i + 1th decoding block is decoded Target output paths to avoid raising false alarm rates.
  • the method further includes: based on the L target output path pairs of the i-th decoding block The i + 1th decoding block in the bit sequence to be decoded is decoded.
  • reading m consecutive information bits in the decoded bit sequence, and reading m row vectors corresponding to the m information bits from a first check matrix including: a string Read consecutive m information bits in the decoded bit sequence, and read m row vectors corresponding to the m information bits in series from the first check matrix; or, read the translations in parallel M consecutive information bits in the code bit sequence, and m row vectors corresponding to the m information bits are read in parallel from the first check matrix, thereby effectively improving decoding efficiency.
  • the first p bits in the decoded bit sequence corresponding to any target output path of the L target output paths are check bits, and only p in the decoded bit sequence Check bits, perform the following operation on the decoded bit sequence corresponding to any target output path: use p check bits in the decoded bit sequence to check the most recently obtained CRC check sequence;
  • the method further includes: if it is determined that the check results of the decoding bit sequences corresponding to the L target output paths are all verification failures, stopping the i + 1th decoding block in the to-be-decoded sequence; Perform decoding to save processing resources; if it is determined that the check result of the decoded bit sequence corresponding to at least one of the L target output paths is a successful check, based on the i-th decoding block ’s
  • the L target output paths decode the i + 1th decoding block in the bit sequence to be decoded.
  • an embodiment of the present application provides a decoding device, where the decoding device includes:
  • a decoding unit configured to decode an i-th decoding block in a bit sequence to be decoded, and select L target output paths from a plurality of output paths of the i-th decoding block; the bit to be decoded
  • the sequence includes information bits and parity bits, and the parity bits are interspersed between the information bits; where 1 ⁇ i ⁇ N, where N is the total number of decoded blocks in the bit sequence to be decoded, L is an integer;
  • a checking unit configured to: if the first m bits in the decoded bit sequence corresponding to any one of the L target output paths are information bits, the decoded bit corresponding to any one of the target output paths Sequence, do the following:
  • Test sequence; m is an integer greater than or equal to 1.
  • the check unit is further configured to: if a check bit is read after reading the m information bits, use the check bit to check the CRC check sequence Check; m is an integer greater than or equal to 1;
  • the decoding unit is further configured to: if it is determined that the check results of the decoded bit sequences corresponding to the L target output paths are all verification failures, stop the i + 1th sequence in the to-be-decoded sequence;
  • the decoding block performs decoding; if it is determined that the verification result of the decoding bit sequence corresponding to at least one of the L target output paths is a verification success, based on the L targets of the i-th decoding block
  • the output path decodes the i + 1th decoding block in the bit sequence to be decoded.
  • the decoding unit is further configured to: if the check unit does not read a check bit after reading the m information bits, based on the i-th decoding The L target output paths of the block decode the i + 1th decoding block in the bit sequence to be decoded.
  • the check unit is specifically configured to read serially m consecutive information bits in the decoded bit sequence, and read the m serially from a first check matrix.
  • the parity unit is further configured to perform the following operations on the decoded bit sequence corresponding to any target output path: use the parity bits in the decoded bit sequence to correct the most recent CRC. Check the sequence for verification;
  • the decoding unit is further configured to: if it is determined that the check results of the decoded bit sequences corresponding to the L target output paths are all verification failures, stop the i + 1th sequence in the to-be-decoded sequence;
  • the decoding block performs decoding; if it is determined that the verification result of the decoding bit sequence corresponding to at least one of the L target output paths is a verification success, the L targets based on the i-th decoding block
  • the output path decodes the i + 1th decoding block in the bit sequence to be decoded.
  • an embodiment of the present application provides a decoding device, the decoding device includes: a processor and a memory; the memory is coupled to the processor, wherein the memory stores a program, and the processor is used for For executing the program stored in the memory, when the program is executed, the decoding device is caused to execute the method as described in the first aspect and any possible design thereof.
  • the decoding device may be a chip or an integrated circuit.
  • an embodiment of the present application provides a decoding device.
  • the decoding device includes: an input interface circuit for acquiring a bit sequence to be decoded; and a logic circuit for performing a first On the one hand and in any possible design method, the decoding result is obtained; and an output interface circuit is used to output the decoding result.
  • an embodiment of the present application provides a computer storage medium for storing a computer program, where the computer program includes instructions for executing the method in the first aspect and any possible design thereof.
  • an embodiment of the present application provides a computer program product containing instructions, which when executed on a computer, causes the computer to perform the method described in the first aspect and any possible design thereof.
  • FIG. 1 is a schematic diagram of a communication system applicable to an embodiment of the present application
  • FIG. 2 is a schematic diagram of an 8 ⁇ 8 coding matrix
  • Figure 3 is a schematic diagram of the encoding and decoding process of Polar code
  • FIG. 5 is a schematic flowchart of a polarization code decoding method according to an embodiment of the present application.
  • 6 is another example diagram of a decoding process
  • FIG. 7 is a schematic structural diagram of a decoding device according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of still another decoding device according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of still another decoding device according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of still another decoding device according to an embodiment of the present application.
  • Figure 1 shows a schematic diagram of a communication system.
  • the communication system 100 applied in the embodiment of the present application includes a sending end 101 and a receiving end 102.
  • the transmitting end 101 may also be called an encoding end, and the receiving end 102 may also be called a decoding end.
  • the sending end 101 may be a network device, and the receiving end 102 is a terminal device; or, the sending end 101 is a terminal device, and the receiving end 102 is a network device.
  • the network device may be any kind of device having a wireless transmitting and receiving function. Including but not limited to: base stations (e.g. base station NodeB, eNodeB evolved base station, base station in the fifth generation (5G) communication system, base stations or network equipment in future communication systems, access nodes in WiFi systems , Wireless relay node, wireless backhaul node).
  • the network device may also be a wireless controller in a cloud radio access network (CRAN) scenario.
  • the network device may also be a network device in a 5G network or a network device in a future evolved network; it may also be a wearable device or a vehicle-mounted device.
  • the network device may also be a small station, a transmission node (transmission reference point, TRP), etc., of course, this application is not limited to this.
  • a terminal device is a device with wireless transceiver capabilities that can be deployed on land, including indoor or outdoor, handheld, wearable, or vehicle-mounted; it can also be deployed on the water (such as a ship, etc.); it can also be deployed in the air (such as an aircraft, Balloons and satellites).
  • the terminal device may be a mobile phone, a tablet, a computer with a wireless transmitting and receiving function, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, or an industrial control device.
  • wireless terminal in industrial control wireless terminal in self driving, wireless terminal in remote medical, wireless terminal in smart grid, transportation safety Wireless terminals, wireless terminals in smart cities, wireless terminals in smart homes, and so on.
  • the embodiment of the present application does not limit the application scenario.
  • Terminal equipment can also be referred to as user equipment (UE), access terminal equipment, UE unit, UE station, mobile station, mobile station, remote station, remote terminal device, mobile device, UE terminal device, terminal device, Wireless communication equipment, UE agent or UE device, etc.
  • UE user equipment
  • access terminal equipment UE unit
  • UE station mobile station
  • mobile station mobile station
  • remote station remote terminal device
  • mobile device UE terminal device
  • terminal device Wireless communication equipment
  • Wireless communication equipment UE agent or UE device, etc.
  • the polarization code decoding method provided in the embodiment of the present application may be executed by a network device, or may be executed by a terminal device.
  • the polarization code decoding method provided in the embodiment of the present application may be applicable to various wireless communication scenarios, and may include, but is not limited to, scenarios applicable to eMBB, mMTC, and URLLC.
  • Polar code is a polar code whose performance is very close to Shannon's limit. It is currently the only error correction code scheme that has been proven to achieve channel capacity under the premise of polynomial processing complexity.
  • an 8 ⁇ 8 encoding matrix is shown, where the vector u is represented by (0, 0, 0, U 4 , 0, U 6 , U 7 , U 8 ).
  • the encoded The bits are represented by vectors (X 1 , X 2 , X 3 , X 4 , X 5 , X 6 , X 7 , X 8 ).
  • the code generated by the coding method of the Polar code and the bit-by-bit elimination (ie SC) decoding method will produce polarization. That is, some bits in the vector u pass through an equivalent highly reliable channel and are translated with a high probability, and some bits pass through an equivalent low reliability channel and are translated with a low probability.
  • a highly reliable channel is used to transmit information bits, and the bits corresponding to the low reliability channel are frozen (such as set to zero), that is, no data is transmitted.
  • setting ⁇ u 1 , u 2 , u 3 , u 5 ⁇ as the position of the frozen bit, and setting ⁇ u 4 , u 6 , u 7 , u 8 ⁇ as the position of the information bit set
  • the information vector ⁇ i 1 , i 2 , i 3 , i 4 ⁇ of length 4 is encoded to generate 8-bit encoded bits.
  • the coded bits are modulated and then passed through a noise channel, and then output.
  • Polar decoding schemes include adopting Serial Cancellation (SC) decoding and Serial Cancellation List (SCL) decoding.
  • SC Serial Cancellation
  • SCL Serial Cancellation List
  • the overall decoding object that is, the bit sequence to be decoded
  • the code block is divided into multiple decoding blocks.
  • the binary tree decoding process is used as an example. In the first stage of the binary tree, the first decoding block is decoded, and its output path has 2; then in the second stage, the second decoding block is performed based on the output path of the previous decoding block.
  • each level of decoding block processes M bits in parallel at the same time.
  • Step 302 The sending end performs check coding to obtain a check code word.
  • Step 303 The sending end performs a distributed cyclic redundancy check (D-CRC) interleaving operation on the check codeword.
  • Step 304 The transmitting end performs Polar code encoding on the check codeword after the interleaving operation.
  • Step 305 The receiving end obtains a bit sequence to be decoded.
  • Step 306 The receiving end performs polarization code decoding on the bit sequence to be decoded.
  • Step 307 The receiving end performs a deinterleaving operation on the decoded sequence.
  • Step 308 The receiving end determines whether the decoding result is successfully decoded through a CRC check.
  • the check bits are interleaved between the information bits to be coded by interleaving. Therefore, when the receiving end adopts sequential decoding, each time a check bit is decoded, the check can be performed. If the check fails, the decoding can be ended in advance, which helps avoid the problem of wasting decoding resources caused by checking after the channel decoding is completed, shortens the decoding time, and improves the decoding efficiency.
  • the receiving end needs to query the D-CRC interleaving table and the D-CRC check matrix to update the CRC check sequence for each information bit decoded during the decoding process.
  • the following describes the implementation of the decoding process in detail with reference to FIG. 4.
  • FIG. 4 is an example diagram of a decoding process.
  • the decoding process is: obtaining the first information bit k0 (numbered 0) obtained by decoding, and first querying the D-CRC interleaving table to solve the problem. After interleaving, the information bit k0 is deinterleaved and the result is still 0. Then check the check matrix according to the deinterleaved result, output the first row vector in the check matrix, and multiply the information bit k0 by the first row vector.
  • the CRC check sequence 0 is obtained; the second information bit k1 (numbered 1) obtained by decoding is obtained, and the D-CRC interleaving table is first searched for deinterleaving, and the result of deinterleaving the information bit k1 is 2, then Query the check matrix according to the deinterleaved result, output the third row vector in the check matrix, multiply the information bit k1 and the third row vector, and accumulate with the CRC check sequence 1 to obtain the updated CRC Check sequence 2; and so on, until the first check bit is obtained, the check bit is compared with the bit at the first position in the CRC check sequence obtained by updating the previous information bit. If they are the same, The check is successful, and the next information bit is obtained. If not the same, then the check fails.
  • the network device in addition to the data itself, there is also an instruction interaction between the network device and the terminal device.
  • the network device completes the scheduling of the terminal device through the instruction and transmits the scheduling format information.
  • the network equipment often does not send or sends some scheduling signaling, but the terminal equipment itself monitors whether there is scheduling in accordance with certain rules.
  • the terminal device needs to perform blind detection and decoding without knowing the exact format. Because there are multiple possible decoding parameters for blind detection decoding, the above-mentioned decoding process needs to be performed multiple times, thereby making it more urgent to simplify the complexity of the Polar code in decoding and reduce the decoding delay.
  • the embodiment of the present application provides a method for decoding a polar code, which is used to simplify the decoding complexity of a Polar code and reduce the decoding delay.
  • the polarization code decoding method may be performed by a receiver illustrated in FIG. 1. Further, in a blind detection scenario, the polarization code decoding method may be performed by a terminal device.
  • FIG. 5 is a schematic flowchart of a polarization code decoding method according to an embodiment of the present application. As shown in FIG. 5, it includes:
  • Step 501 Decode the i-th decoding block in the to-be-decoded bit sequence, and select L target output paths from multiple output paths of the i-th decoding block; the to-be-decoded bit sequence includes information bits. And check bits, the check bits are interspersed between the information bits; where 1 ⁇ i ⁇ N, N is the total number of decoded blocks in the bit sequence to be decoded, and L is an integer.
  • the receiving end may sequentially decode each decoding block in the bit sequence to be decoded.
  • Each decoding block in the bit sequence to be decoded may include one or more bits, for example, 8 bits, which is not limited herein.
  • the check bits are interspersed between the information bits, the bits in the decoded block of the bit sequence to be decoded may include the information bits and the check bits, or the bits in the decoded block may all be information. It is also possible that the bits in the decoding block are all check bits.
  • the specific value of L is related to the decoding algorithm used.
  • the value of L may be 2, 4, or 8, and the like is not limited herein.
  • a path metric (Path Metric, PM) value of each output path of the i-th decoding block may be used.
  • Step 502 if the first m bits in the decoded bit sequence corresponding to any of the target output paths of the L target output paths are information bits, for the decoded bit sequence corresponding to any of the target output paths, execute The operation is as follows: reading consecutive m information bits in the decoded bit sequence, and reading m row vectors corresponding to the m information bits from a first check matrix, where the first check matrix is A matrix obtained by rearranging row vectors in an original check matrix corresponding to the bit sequence to be decoded according to a deinterleaving order of the bit sequence to be decoded; according to the m information bits and the m row vectors, The CRC check sequence is obtained; m is an integer greater than or equal to 1.
  • m information bits in the decoded bit sequence are read, and m row vectors corresponding to the m information bits are read from a first check matrix.
  • a possible implementation manner may be: reading m consecutive information bits in the decoded bit sequence at one time, and reading m row vectors corresponding to the m information bits from the first check matrix at one time, so that The m information bits are processed in parallel to effectively improve the decoding efficiency.
  • the m consecutive information bits in the decoded bit sequence may be sequentially read, and the m row vectors corresponding to the m information bits may be sequentially read from the first check matrix. That is, serial processing is performed on m information bits.
  • the decoding bit sequence corresponding to any target output path of the L target output paths includes k bits
  • the first m bits in the decoding bit sequence corresponding to any target output path are For information bits, the following example scenarios may exist:
  • the first m bits in the decoded bit sequence corresponding to any target output path are information bits, and the last k-m bits are check bits.
  • the decoded bit sequence includes 8 bits, which are [u0, u1, u2, u3, u4, u5, u6, u7], where [u0, u1, u2, u3, u4, u5, u6] is Information bits, u7 is the check bit.
  • 7 information bits in the decoded bit sequence can be read, and 7 row vectors corresponding to the 7 information bits are read from the first check matrix to obtain a CRC check sequence; subsequent reads When the check bit u7 is obtained, the CRC check sequence can be checked by using the check bit u7.
  • the first m bits in the decoded bit sequence corresponding to any target output path are information bits
  • the middle n bits are check bits
  • the last k-m-n bits are information bits.
  • the decoded bit sequence includes 8 bits, which are [u0, u1, u2, u3, u4, u5, u6, u7], where [u0, u1, u2, u4, u5, u6, u7] is Information bits
  • u3 is the check bit.
  • the first three information bits [u0, u1, u2] in the decoded bit sequence can be read, and the three row vectors corresponding to the three information bits are read from the first check matrix.
  • a CRC check sequence is obtained; if a check bit u3 is subsequently read, the CRC check sequence may be checked using the check bit u3. Further, it is necessary to determine whether to process the last 4 information bits [u4, u5, u6, u7] according to the verification results of the decoded bit sequences corresponding to the L target output paths respectively, as described in detail below.
  • the method may further include: step a, judging corresponding translations of the L target output paths respectively If the check result of the code bit sequence is a check failure, if yes, go to step b; otherwise, go to step c.
  • Step b Stop decoding the i + 1th decoding block in the sequence to be decoded.
  • the last 4 information bits [u4, u5, u6, u7] in the decoded bit sequence may no longer be processed.
  • Step c Decode the i + 1th decoding block in the bit sequence to be decoded based on the L target output paths of the ith decoding block.
  • the last 4 information bits [u4, u5, u6, u7] in the decoded bit sequence are continuously processed, that is, the last 4 information bits are read, and the first check
  • the four row vectors corresponding to the four information bits are read in the matrix to obtain the latest CRC check sequence.
  • the L target output path pairs of the i-th decoding block may be used.
  • the i + 1th decoding block is decoded, that is, at this time, the check results of the decoding bit sequences corresponding to the L target output paths respectively do not affect the decoding result of the i + 1th decoding block. Based on the L target output paths, it is possible to avoid raising the false alarm rate.
  • the decoded bit sequence corresponding to any target output path of the L target output paths includes k bits
  • the first m bits in the decoded bit sequence corresponding to any target output path are not
  • the following example scenarios may exist:
  • the decoding of the i + 1th decoding block in the to-be-decoded sequence is stopped. If it is determined that the check result of the decoded bit sequence corresponding to at least one of the L target output paths is a successful check, based on the L target output paths of the i-th decoding block, The i + 1th decoding block in the decoding bit sequence is decoded.
  • the first p bits in the decoded bit sequence corresponding to any target output path are check bits, and the last k-p bits are information bits.
  • the decoded bit sequence includes 8 bits, which are [u0, u1, u2, u3, u4, u5, u6, u7], where u0 is the check bit, and [u1, u2, u3, u4, u5 u6, u7] are information bits.
  • the decoded bit sequence corresponding to any target output path the last p check bits are used to check the most recently obtained CRC check sequence. Further, if it is determined that the check results of the decoding bit sequences corresponding to the L target output paths are all verification failures, the decoding of the i + 1th decoding block in the to-be-decoded sequence is stopped. If it is determined that the check result of the decoded bit sequence corresponding to at least one of the L target output paths is a successful check, based on the L target output paths of the i-th decoding block, The i + 1th decoding block in the decoding bit sequence is decoded.
  • the decoded bit sequence includes 8 bits, which are [u0, u1, u2, u3, u4, u5, u6, u7], where [u0, u7] is the check bit, and [u1, u2, u3 , u4, u5, u6] are information bits.
  • the following operations are performed on the decoded bit sequence corresponding to any target output path: the first p check bits (that is, u0) are used to check the most recently obtained CRC check sequence. Further, if it is determined that the check results of the decoding bit sequences corresponding to the L target output paths are all verification failures, the decoding of the i + 1th decoding block in the to-be-decoded sequence is stopped. , And stop processing other bits in the decoded bit sequence.
  • the information bits in the decoded bit sequence that is, [u1, u2, u3, u4 , u5, u6]) to obtain the latest CRC check sequence; then, use the check bit (ie, u7) to check the latest CRC check sequence, and if the L target output paths are determined, respectively.
  • the check result of the corresponding decoded bit sequence is a check failure, stop decoding the i + 1th decoded block in the to-be-decoded sequence; if at least one of the L target output paths is determined, The check result of the decoded bit sequence corresponding to the target output path is that the check is successful, then the i + 1th decoded block in the to-be-decoded bit sequence is based on the L target output paths of the i-th decoded block. Decoding.
  • the sending end device and the receiving end device may preset (or be specified by a protocol) an interleaving order of multiple different bit sequences for interleaving operations, among which multiple different The bit sequence means that the sequence length of multiple bit sequences is different.
  • the receiving end device may rearrange the row vectors in the original check matrix corresponding to the different bit sequence to be decoded according to the deinterleaving order corresponding to the agreed interleaving order, so as to obtain a plurality of different to be decoded.
  • the check matrix corresponding to the bit sequence may be preset (or be specified by a protocol) an interleaving order of multiple different bit sequences for interleaving operations, among which multiple different The bit sequence means that the sequence length of multiple bit sequences is different.
  • the receiving end device may rearrange the row vectors in the original check matrix corresponding to the different bit sequence to be decoded according to the deinterleaving order corresponding to the agreed interleaving order, so as to obtain a plurality of different to be decoded
  • the receiving end device may calculate offline and obtain a check matrix corresponding to the bit sequence a, bit sequence b, and c to be decoded offline in the above manner.
  • the end device determines that the sequence length of the current bit sequence to be decoded is the same as the sequence length of the bit sequence a to be decoded, and then uses the check matrix corresponding to the bit sequence a to be decoded to correct the decoding result of the current bit sequence to be decoded.
  • Check the check matrix corresponding to the bit sequence a, bit sequence b, and c to be decoded
  • the maximum sequence length of the bit sequence to be decoded may be determined.
  • the receiving end device may calculate and store the check matrix corresponding to the maximum sequence length of the bit sequence to be decoded offline.
  • the The check matrix corresponding to the length of the bit sequence to be decoded obtains the check matrix corresponding to the current bit sequence to be decoded, and then the decoding result of the current bit sequence to be decoded is checked. At this time, the check matrix corresponding to the current bit sequence to be decoded is obtained online.
  • the check matrix corresponding to the maximum sequence length of the bit sequence to be decoded may be obtained in offline mode in advance.
  • the check matrices corresponding to different bit sequences to be decoded are not specifically limited.
  • m row vectors corresponding to m information bits can be directly read from the first check matrix without using D-CRC alternately.
  • the interleaving table and D-CRC check matrix can save chip power consumption, and can effectively simplify the complexity of Polar code decoding and reduce the decoding delay; and no longer need to store the D-CRC interleaving table, effectively saving chip area.
  • the first check matrix can be obtained offline, the decoding efficiency can be further improved.
  • an embodiment of the present application further provides a decoding device 700.
  • the decoding device 700 is configured to perform the polarization code decoding shown in FIG. 5.
  • the decoding device 700 may include one or more functional units, such as a decoding unit 701 and a check unit 702.
  • the decoding unit 701 may be used to perform the above step 501, and the check unit 702 may be used to perform the above. Step 502.
  • the check unit 702 is further configured to: if a check bit is read after reading the m information bits, use the check bit to check the CRC Check the sequence; m is an integer greater than or equal to 1;
  • the decoding unit 701 is further configured to: if it is determined that the verification result of the decoding bit sequences corresponding to the L target output paths is a verification failure, stop decoding the i + th sequence in the to-be-decoded sequence. 1 decoding block for decoding; if it is determined that the check result of the decoding bit sequence corresponding to at least one of the L target output paths is a successful check, the L number of the i-th decoding block is based on the The target output path decodes the i + 1th decoding block in the bit sequence to be decoded.
  • the decoding unit 701 is further configured to: if the check unit 702 does not read a check bit after reading the m information bits, based on the i-th bit
  • the L target output paths of the decoding block decode the i + 1th decoding block in the bit sequence to be decoded.
  • the check unit 702 is specifically configured to read serially m consecutive information bits in the decoded bit sequence, and read the serially from the first check matrix. m row vectors corresponding to m information bits; or, reading m consecutive information bits in the decoded bit sequence in parallel, and reading m corresponding to the m information bits in parallel from a first check matrix Row vectors.
  • the parity unit 702 is further configured to perform the following operations on the decoded bit sequence corresponding to any target output path:
  • the decoding unit 701 is further configured to: if it is determined that the verification result of the decoding bit sequences corresponding to the L target output paths is a verification failure, stop decoding the i + th sequence in the to-be-decoded sequence. 1 decoding block for decoding; if it is determined that the check result of the decoding bit sequence corresponding to at least one of the L target output paths is a successful check, the L number of the i-th decoding block is based on the The target output path decodes the i + 1th decoding block in the bit sequence to be decoded.
  • the division of the units in the embodiments of the present application is schematic, and is only a logical function division. In actual implementation, there may be another division manner.
  • the functional units in the embodiments of the present application may be integrated into one processing unit, or each of the units may exist separately physically, or two or more units may be integrated into one unit.
  • the above integrated unit may be implemented in the form of hardware or in the form of software functional unit.
  • an embodiment of the present application further provides a decoding device 800.
  • the decoding device 800 is configured to perform the polarization code decoding shown in FIG. 5. method. Part or all of the polarization code decoding method shown in FIG. 5 can be implemented by hardware or software.
  • the decoding device 800 includes: an input interface circuit 801 for acquiring a to-be-translated Code bit sequence; logic circuit 802, for performing the polarization code decoding method shown in FIG. 5 above, for details, please refer to the description in the foregoing method embodiment, which will not be repeated here; an output interface circuit 803, for outputting translation Code results.
  • the decoding device 800 may be a chip or an integrated circuit in a specific implementation.
  • the decoding device 800 when part or all of the polarization code decoding method in the above embodiment is implemented by software, as shown in FIG. 9, the decoding device 800 includes: a memory 901 for storing a program; a processor 902, For executing the program stored in the memory 901, when the program is executed, the decoding device 800 can implement the polarization code decoding method provided in FIG. 5 described above.
  • the foregoing memory 901 may be a physically independent unit, or as shown in FIG. 10, the memory 901 and the processor 902 are integrated together.
  • the decoding device 800 may only include a processor 902, and a memory 901 for storing a program is located outside the decoding device 800 and processes
  • the device 902 is connected to the memory 901 through a circuit / wire, and is used to read and execute programs stored in the memory 901.
  • the processor 902 may be a central processing unit (CPU), a network processor (NP), or a combination of a CPU and an NP.
  • CPU central processing unit
  • NP network processor
  • the processor 902 may further include a hardware chip.
  • the above hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof.
  • the PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a general array logic (GAL), or any combination thereof.
  • the memory 901 may include volatile memory (for example, random-access memory (RAM); the memory 901 may also include non-volatile memory (for example, flash memory) memory), hard disk (HDD) or solid-state drive (SSD); memory 901 may also include a combination of the above types of memory.
  • volatile memory for example, random-access memory (RAM)
  • non-volatile memory for example, flash memory
  • HDD hard disk
  • SSD solid-state drive
  • memory 901 may also include a combination of the above types of memory.
  • An embodiment of the present application further provides a computer storage medium storing a computer program, where the computer program includes a method for performing a polarization code decoding method shown in FIG. 5.
  • An embodiment of the present application further provides a computer program product containing instructions, which when executed on a computer, causes the computer to execute the polarization code decoding method shown in FIG. 5.
  • the computer program product includes one or more computer instructions.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be from a website site, a computer, a server, or a data center.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, a data center, or the like that includes one or more available medium integration.
  • the available medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (Solid State Disk (SSD)), and the like.
  • These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to work in a specific manner such that the instructions stored in the computer-readable memory produce a manufactured article including an instruction device, the instructions
  • the device implements the functions specified in one or more flowcharts and / or one or more blocks of the block diagram.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of steps can be performed on the computer or other programmable device to produce a computer-implemented process, which can be executed on the computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more flowcharts and / or one or more blocks of the block diagrams.

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Abstract

一种极化码译码方法及译码装置，其中方法包括：若第i译码块的任一目标输出路径对应的译码比特序列中前m个比特为信息比特，则针对于任一目标输出路径对应的译码比特序列，读取译码比特序列中连续的m个信息比特，并从第一校验矩阵中其对应的m个行向量，第一校验矩阵为根据待译码比特序列的解交织顺序对待译码比特序列对应的原始校验矩阵中的行向量重新排列后得到的矩阵；根据m个信息比特和m个行向量，得到CRC校验序列。如此，在进行译码时，可以直接从第一校验矩阵中读取m个行向量，而无需交替使用D-CRC交织表和D-CRC校验矩阵，从而节省芯片功耗，并能够有效简化极化码码在译码方面的复杂度、降低译码延迟。

Description

一种极化码译码方法及译码装置 技术领域
本申请涉及通信技术领域，尤其涉及一种极化码译码方法及译码装置。
背景技术
无线通信的快速演进预示着未来第五代(5th generation，5G)通信系统将呈现出一些新的特点，最典型的三个通信场景包括增强型移动互联网(enhance mobile broadband，eMBB)、海量机器连接通信(massive machine type communication，mMTC)和高可靠低延迟通信(ultra reliable low latency communication，URLLC)，这些通信场景的需求将对现有长期演进(long term evolution，LTE)技术提出新的挑战。信道编码作为最基本的无线接入技术，是满足5G通信需求的重要研究对象之一。
极化码(Polar Codes)在5G标准中被选作控制信道编码方式。极化码也可以称为Polar码，是第一种、也是已知的唯一一种能够被严格证明“达到”信道容量的信道编码方法。在不同码长下，尤其对于有限码，极化码的性能远优于Turbo码和低密度奇偶校验码(low density parity check，LDPC)码，这些优点让极化码在5G中具有很大的发展和应用前景。
目前，如何简化极化码在译码方面的复杂度、降低译码延迟，仍需进一步研究。
发明内容
本申请实施例提供一种极化码译码方法，用于简化极化码在译码方面的复杂度、降低译码延迟。
第一方面，本申请实施例提供一种极化码译码方法，该方法包括：
对待译码比特序列中的第i译码块进行译码，并从所述第i译码块的多个输出路径中选择L个目标输出路径；所述待译码比特序列包括信息比特和校验比特，所述校验比特穿插在所述信息比特之间；其中，1≤i≤N，N为所述待译码比特序列中的译码块的总个数，L为整数；
若所述L个目标输出路径的任一目标输出路径对应的译码比特序列中前m个比特为信息比特，则针对于所述任一目标输出路径对应的译码比特序列，执行如下操作：
读取所述译码比特序列中连续的m个信息比特，并从第一校验矩阵中读取所述m个信息比特对应的m个行向量，所述第一校验矩阵为根据待译码比特序列的解交织顺序对所述待译码比特序列对应的原始校验矩阵中的行向量重新排列后得到的矩阵；根据所述m个信息比特和所述m个行向量，得到CRC校验序列；m为大于等于1的整数。
如此，本申请实施例可以直接从第一校验矩阵中读取m个信息比特对应的m个行向量，而无需交替使用D-CRC交织表和D-CRC校验矩阵，从而节省芯片功耗，并能够有效简化Polar码在译码方面的复杂度、降低译码延迟；且无需再存储D-CRC交织表，有效节省芯片面积。
在一种可能的设计中，若在读取所述m个信息比特之后，读取到校验比特，则使用所述校验比特对所述CRC校验序列进行校验；m为大于等于1的整数；进一步地，所述方法还包括：若确定所述L个目标输出路径分别对应的译码比特序列的校验结果均为校验失败，则停止对所述待译码序列中的第i+1译码块进行译码；若确定所述L个目标输出路径 中至少一个目标输出路径对应的译码比特序列的校验结果为校验成功，则基于所述第i译码块的L个目标输出路径对所述待译码比特序列中的第i+1译码块进行译码。
如此，在L个目标输出路径分别对应的译码比特序列的校验结果中至少一个校验结果为校验成功的情况下，可基于第i译码块的L个目标输出路径对第i+1译码块进行译码，也就是说，此时，L个目标输出路径分别对应的译码比特序列的校验结果并不影响对第i+1译码块进行译码时所依据的L个目标输出路径，从而能够避免抬高虚警率。
在一种可能的设计中，若在读取所述m个信息比特之后，未读取到校验比特，则所述方法还包括：基于所述第i译码块的L个目标输出路径对所述待译码比特序列中的第i+1译码块进行译码。
在一种可能的设计中，读取所述译码比特序列中连续的m个信息比特，并从第一校验矩阵中读取所述m个信息比特对应的m个行向量，包括：串行读取所述译码比特序列中连续的m个信息比特，并从第一校验矩阵中串行读取所述m个信息比特对应的m个行向量；或者，并行读取所述译码比特序列中连续的m个信息比特，并从第一校验矩阵中并行读取所述m个信息比特对应的m个行向量，从而能够有效提高译码效率。
在一种可能的设计中，若所述L个目标输出路径的任一目标输出路径对应的译码比特序列中的前p个比特为校验比特，且所述译码比特序列中仅有p个校验比特，则针对于任一目标输出路径对应的译码比特序列执行如下操作：使用所述译码比特序列中的p个校验比特对最近一次得到的CRC校验序列进行校验；
所述方法还包括：若确定所述L个目标输出路径分别对应的译码比特序列的校验结果均为校验失败，则停止对所述待译码序列中的第i+1译码块进行译码，从而便于节省处理资源；若确定所述L个目标输出路径中至少一个目标输出路径对应的译码比特序列的校验结果为校验成功，则基于所述第i译码块的L个目标输出路径对所述待译码比特序列中的第i+1译码块进行译码。
第二方面，本申请实施例提供一种译码装置，所述译码装置包括：
译码单元，用于对待译码比特序列中的第i译码块进行译码，并从所述第i译码块的多个输出路径中选择L个目标输出路径；所述待译码比特序列包括信息比特和校验比特，所述校验比特穿插在所述信息比特之间；其中，1≤i≤N，N为所述待译码比特序列中的译码块的总个数，L为整数；
校验单元，用于若所述L个目标输出路径的任一目标输出路径对应的译码比特序列中前m个比特为信息比特，则针对于所述任一目标输出路径对应的译码比特序列，执行如下操作：
读取所述译码比特序列中连续的m个信息比特，并从第一校验矩阵中读取所述m个信息比特对应的m个行向量，所述第一校验矩阵为根据待译码比特序列的解交织顺序对所述待译码比特序列对应的原始校验矩阵中的行向量重新排列后得到的矩阵；根据所述m个信息比特和所述m个行向量，得到CRC校验序列；m为大于等于1的整数。
在一种可能的设计中，所述校验单元还用于：若在读取所述m个信息比特之后，读取到校验比特，则使用所述校验比特对所述CRC校验序列进行校验；m为大于等于1的整数；
所述译码单元还用于：若确定所述L个目标输出路径分别对应的译码比特序列的校验结果均为校验失败，则停止对所述待译码序列中的第i+1译码块进行译码；若确定所述L 个目标输出路径中至少一个目标输出路径对应的译码比特序列的校验结果为校验成功，则基于所述第i译码块的L个目标输出路径对所述待译码比特序列中的第i+1译码块进行译码。
在一种可能的设计中，所述译码单元还用于：若所述校验单元在读取所述m个信息比特之后，未读取到校验比特，则基于所述第i译码块的L个目标输出路径对所述待译码比特序列中的第i+1译码块进行译码。
在一种可能的设计中，所述校验单元具体用于：串行读取所述译码比特序列中连续的m个信息比特，并从第一校验矩阵中串行读取所述m个信息比特对应的m个行向量；或者，并行读取所述译码比特序列中连续的m个信息比特，并从第一校验矩阵中并行读取所述m个信息比特对应的m个行向量。
在一种可能的设计中，若所述L个目标输出路径的任一目标输出路径对应的译码比特序列中的前p个比特为校验比特，且所述译码比特序列中仅有p个校验比特，则所述校验单元还用于针对于任一目标输出路径对应的译码比特序列执行如下操作：使用所述译码比特序列中的校验比特对最近一次得到的CRC校验序列进行校验；
所述译码单元还用于：若确定所述L个目标输出路径分别对应的译码比特序列的校验结果均为校验失败，则停止对所述待译码序列中的第i+1译码块进行译码；若确定所述L个目标输出路径中至少一个目标输出路径对应的译码比特序列的校验结果为校验成功，则基于所述第i译码块的L个目标输出路径对所述待译码比特序列中的第i+1译码块进行译码。
第三方面，本申请实施例提供一种译码装置，所述译码装置包括：处理器、存储器；所述存储器耦合至所述处理器，其中，所述存储器中存储程序，所述处理器用于执行所述存储器存储的程序，当所述程序被执行时，使得所述译码装置执行如第一方面及其可能的任一设计中所述的方法。
在一种可能的设计中，所述译码装置可以为芯片或集成电路。
第四方面，本申请实施例提供一种译码装置，所述译码装置包括：输入接口电路，用于获取待译码比特序列；逻辑电路，用于基于获取的待译码比特序列执行第一方面及其可能的任一设计中的方法，得到译码结果；输出接口电路，用于输出译码结果。
第五方面，本申请实施例提供一种计算机存储介质，用于存储计算机程序，该计算机程序包括用于执行第一方面及其可能的任一设计中的方法的指令。
第六方面，本申请实施例提供一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述第一方面及其可能的任一设计中所述的方法。
附图说明
图1为本申请实施例适用的一种通信系统示意图；
图2为一个8×8的编码矩阵示意图；
图3为Polar码的编译码流程示意图；
图4为译码流程的一种示例图；
图5为本申请实施例提供的一种极化码译码方法对应的流程示意图；
图6为译码流程又一种示例图；
图7为本申请实施例提供的一种译码装置的结构示意图；
图8为本申请实施例提供的又一种译码装置的结构示意图；
图9为本申请实施例提供的又一种译码装置的结构示意图；
图10为本申请实施例提供的又一种译码装置的结构示意图。
具体实施方式
下面将结合附图对本申请实施例作进一步地详细描述。其中，方法和装置是基于同一发明构思的，由于方法及设备解决问题的原理相似，因此装置与方法的实施可以相互参见，重复之处不再赘述。
图1给出了一种通信系统示意图。如图1所示，本申请实施例应用的通信系统100中包括发送端101和接收端102。发送端101也可以称为编码端，接收端102也可以称为译码端。其中，发送端101可以为网络设备，接收端102为终端设备；或者，发送端101为终端设备，接收端102为网络设备。
网络设备可以是任意一种具有无线收发功能的设备。包括但不限于：基站(例如，基站NodeB、演进型基站eNodeB、第五代(the fifth generation，5G)通信系统中的基站、未来通信系统中的基站或网络设备、WiFi系统中的接入节点、无线中继节点、无线回传节点)等。网络设备还可以是云无线接入网络(cloud radio access network，CRAN)场景下的无线控制器。网络设备还可以是5G网络中的网络设备或未来演进网络中的网络设备；还可以是可穿戴设备或车载设备等。网络设备还可以是小站，传输节点(transmission reference point，TRP)等，当然本申请不限于此。
终端设备是一种具有无线收发功能的设备，可以部署在陆地上，包括室内或室外、手持、穿戴或车载；也可以部署在水面上(如轮船等)；还可以部署在空中(例如飞机、气球和卫星上等)。所述终端设备可以是手机(mobile phone)、平板电脑(Pad)、带无线收发功能的电脑、虚拟现实(Virtual Reality，VR)终端设备、增强现实(Augmented Reality，AR)终端设备、工业控制(industrial control)中的无线终端、无人驾驶(self driving)中的无线终端、远程医疗(remote medical)中的无线终端、智能电网(smart grid)中的无线终端、运输安全(transportation safety)中的无线终端、智慧城市(smart city)中的无线终端、智慧家庭(smart home)中的无线终端等等。本申请的实施例对应用场景不做限定。终端设备有时也可以称为用户设备(user equipment，UE)、接入终端设备、UE单元、UE站、移动站、移动台、远方站、远程终端设备、移动设备、UE终端设备、终端设备、无线通信设备、UE代理或UE装置等。
本申请实施例提供的极化码译码方法可以由网络设备来执行，也可以由终端设备来执行。本申请实施例提供的极化码译码方法可以适用于各种无线通信场景，可以但不限于包括适用于eMBB、mMTC和URLLC的场景。
为方便对本申请实施例的理解，下面对Polar码作简单介绍。
Polar码是一种性能十分接近香农极限的极化码，是目前唯一被证明在多项式处理复杂度前提下能够达到信道容量的纠错码方案。
(1)Polar码的编码
Polar码的编码方式可由下式表示：x＝u·F n，其中u为n长二进制向量，F n为克罗内 克幂Kronecker变换矩阵，也为Polar码的编码矩阵。其中
Figure PCTCN2018092500-appb-000001
为2×2矩阵
Figure PCTCN2018092500-appb-000002
的乘积。
如图2所示，展示了一个8×8的编码矩阵，其中向量u用(0，0，0，U 4，0，U 6，U 7，U 8)表示，经过编码矩阵，编码后的比特以向量(X 1，X 2，X 3，X 4，X 5，X 6，X 7，X 8)表示。通过Polar码的编码方式生成的编码，并通过逐比特消除(即SC)译码方法，会产生极化现象。即向量u中的一部分比特经过一个等效高可靠信道并以高概率被译对，另一部分比特经过一个等效低可靠信道并以低概率被译对。一般来说，将高可靠信道用于传输信息比特，而将低可靠信道对应的比特冻结(比如置零)，即不传输数据。如图2中所示，将{u 1,u 2,u 3,u 5}设置为冻结比特的位置，将{u 4,u 6,u 7,u 8}设置为信息比特的位置，将长度为4的信息向量{i 1,i 2,i 3,i 4}经过编码后，生成8位编码后比特。在上述编码后，将编码比特经过调制后再经过噪声信道，然后输出。
(2)Polar码的译码
在Polar码的译码过程中，目前常用的Polar译码方案包括采用串行对消(Successive Cancellation，SC)译码和串行对消列表(Successive Cancellation list，SCL)译码。以SCL译码算法为例，可将整体的译码对象(即待译码比特序列)叫做码块，码块中分成多个译码块，以二叉树的译码过程为例，在译码时，在二叉树的第一级，对第一个译码块进行译码，其输出路径有2条；然后在第二级，基于前一译码块的输出路径，对第二个译码块进行译码，依次类推，完成对码块中的所有译码块的译码，其中最优路径的中的各个节点的值，就表示码块的译码结果，采用并行度为M的SCL译码器进行译码时，每一级译码块都同时并行处理M个比特。
基于上述编码和译码的介绍，以5G新无线(new radio，NR)通信系统为例，其采用Polar码的编译码流程如图3所示，包括：步骤301、发送端获取待编码信息。步骤302、发送端进行校验编码，获得校验编码码字。步骤303、发送端对校验编码码字进行分布式循环冗余校验(distributed cyclic redundancy check，D-CRC)交织操作。步骤304、发送端对交织操作后的校验编码码字进行Polar码编码。步骤305、接收端获取待译码比特序列。步骤306、接收端对待译码比特序列进行极化码译码。步骤307、接收端对译码后的序列进行解交织操作。步骤308，接收端通过CRC校验判断译码结果是否译码成功。
在图3所示意的编码流程中，通过交织方式将校验比特穿插在待编码信息比特之间，因此，当接收端采用顺序译码时，每译码出校验比特，即可进行校验，若校验不通过，则可以提前结束译码，有助于避免在信道译码结束后再进行校验造成译码资源浪费的问题，缩短译码所用时长，提高译码的效率。
然而，采用上述方法，接收端在译码流程中，针对于译出的每一个信息比特，均需要查询D-CRC交织表和D-CRC校验矩阵来更新CRC校验序列。下面结合图4对译码流程的实现方式进行详细说明。
图4为译码流程的一种示例图，如图4所示，该译码流程为：获取译码得到的第1个信息比特k0(编号为0)，先查询D-CRC交织表进行解交织，得到信息比特k0解交织后的结果仍为0，则根据解交织后的结果查询校验矩阵，输出校验矩阵中的第1行向量，将信息比特k0与第1行向量进行乘运算后，得到CRC校验序列0；获取译码得到的第2个信息比特k1(编号为1)，先查询D-CRC交织表进行解交织，得到信息比特k1解交织后 的结果为2，则根据解交织后的结果查询校验矩阵，输出校验矩阵中的第3行向量，将信息比特k1与第3行向量进行乘运算后，与CRC校验序列1进行累加，得到更新后的CRC校验序列2；依次类推，直到获取到第1个校验比特后，将校验比特与前一个信息比特更新得到的CRC校验序列中位于第1个位置上的比特进行比较，若相同，则校验成功，并继续获取下一个信息比特，若不相同，则校验失败。
从上述过程可以看出，由于需要交替使用D-CRC交织表和D-CRC校验矩阵，从而导致CRC校验过程非常复杂，进而使得Polar码译码延迟加大。
进一步地，在5G通信系统中，网络设备和终端设备之间除了数据本身的交互外，还有指令的交互，网络设备通过指令完成对终端设备的调度，以及传递调度的格式信息。为了降低指令交互的开销，网络设备常常不发送或者少发送某些调度信令，而由终端设备按照一定规则自行监听是否存在调度。在监听过程中，终端设备需要在不知道确切格式的情况下做盲检测译码。由于盲检测译码存在多种可能的译码参数，因此需要多次执行上述译码流程，从而使得简化Polar码在译码方面的复杂度、降低译码延迟的需求变得更为迫切。
基于此，本申请实施例提供一种极化码译码方法，用于简化Polar码在译码方面的复杂度、降低译码延迟。该极化码译码方法可由图1中所示意出的接收端来执行，进一步地，在盲检测场景中，该极化码译码方法可由终端设备来执行。
图5为本申请实施例提供的一种极化码译码方法对应的流程示意图，如图5所示，包括：
步骤501，对待译码比特序列中的第i译码块进行译码，从所述第i译码块的多个输出路径中选择L个目标输出路径；所述待译码比特序列包括信息比特和校验比特，所述校验比特穿插在所述信息比特之间；其中，1≤i≤N，N为所述待译码比特序列中的译码块的总个数，L为整数。
此处，接收端接收到待译码比特序列后，可依次对待译码比特序列中的各个译码块进行译码。待译码比特序列中的每个译码块可以包括一个或多个比特，比如包括8个比特，此处不做限定。进一步地，由于校验比特穿插在信息比特之间，因此，待译码比特序列的译码块中的比特可能包括信息比特和校验比特，或者，译码块中的比特也可能全为信息比特，又或者，译码块中的比特也可能全为校验比特。
本申请实施例中，L的具体取值与采用的译码算法相关，比如，L的取值可以为2、4或8等，此处不做限定。以采用SCL译码算法为例，当第i译码块的输出路径的总数超过预设的路径宽度L时，可根据第i译码块的各个输出路径的路径度量(Path Metric，PM)值，选择出PM值最佳的L个目标输出路径。
步骤502，若所述L个目标输出路径的任一目标输出路径对应的译码比特序列中前m个比特为信息比特，则针对于所述任一目标输出路径对应的译码比特序列，执行如下操作：读取所述译码比特序列中连续的m个信息比特，并从第一校验矩阵中读取所述m个信息比特对应的m个行向量，所述第一校验矩阵为根据待译码比特序列的解交织顺序对所述待译码比特序列对应的原始校验矩阵中的行向量重新排列后得到的矩阵；根据所述m个信息比特和所述m个行向量，得到CRC校验序列；m为大于等于1的整数。
此处，若m大于1，则读取所述译码比特序列中的m个信息比特，并从第一校验矩阵中读取所述m个信息比特对应的m个行向量，在一种可能的实现方式中可以为：一次性读取译码比特序列中连续的m个信息比特，以及从第一校验矩阵中一次性读取所述m个 信息比特对应的m个行向量，从而实现对m个信息比特进行并行处理，有效提高译码效率；或者，也可以分多次进行并行处理，以m＝8、分两次进行并行处理为例，则可每一次读取译码比特序列中连续的4个信息比特，以及从第一校验矩阵中读取所述4个信息比特对应的4个行向量。
在另一种可能的实现方式中可以为：依次读取译码比特序列中连续的m个信息比特，以及从第一校验矩阵中依次读取所述m个信息比特对应的m个行向量，即对m个信息比特进行串行处理。
本申请实施例中，假设所述L个目标输出路径的任一目标输出路径对应的译码比特序列中包括k个比特，则任一目标输出路径对应的译码比特序列中前m个比特为信息比特，可能存在如下几种示例情形：
情形a1，任一目标输出路径对应的译码比特序列中的比特全为信息比特(即m＝k)，即在读取所述m个信息比特之后，未读取到校验比特。此种情形下，由于译码比特序列中不存在校验比特，因此，在得到CRC校验序列后，可直接基于第i译码块的L个目标输出路径对所述待译码比特序列中的第i+1译码块进行译码。
情形a2，任一目标输出路径对应的译码比特序列中前m个比特为信息比特，后k-m个比特为校验比特。比如，译码比特序列中包括8个比特，分别为[u0,u1,u2,u3,u4,u5,u6,u7]，其中，[u0,u1,u2,u3,u4,u5,u6]为信息比特，u7为校验比特。此种情形下，可读取译码比特序列中的7个信息比特，并从第一校验矩阵中读取所述7个信息比特对应的7个行向量，得到CRC校验序列；后续读取到校验比特u7，则可使用所述校验比特u7对CRC校验序列进行校验。
情形a3，任一目标输出路径对应的译码比特序列中前m个比特为信息比特，中间n个比特为校验比特，后k-m-n个比特为信息比特。比如，译码比特序列中包括8个比特，分别为[u0,u1,u2,u3,u4,u5,u6,u7]，其中，[u0,u1,u2,u4,u5,u6,u7]为信息比特，u3为校验比特。此种情形下，可读取译码比特序列中的前3个信息比特[u0,u1,u2]，并从第一校验矩阵中读取所述3个信息比特对应的3个行向量，得到CRC校验序列；后续读取到校验比特u3，则可使用所述校验比特u3对CRC校验序列进行校验。进一步地，需根据L个目标输出路径分别对应的译码比特序列的校验结果来确定是否对后4个信息比特[u4,u5,u6,u7]进行处理，具体参见下文中的描述。
针对于上述情形a2和情形a3，即在读取所述m个信息比特之后，读取到校验比特，所述方法还可以包括：步骤a，判断所述L个目标输出路径分别对应的译码比特序列的校验结果是否均为校验失败，若是，则执行步骤b，否则，执行步骤c。
步骤b，停止对所述待译码序列中的第i+1译码块进行译码。
此时，在上述情形a3中，也可以不再对译码比特序列中的后4个信息比特[u4,u5,u6,u7]进行处理。
步骤c，基于所述第i译码块的L个目标输出路径对所述待译码比特序列中的第i+1译码块进行译码。
此时，在上述情形a3中，对译码比特序列中的后4个信息比特[u4,u5,u6,u7]进行继续处理，即：读取后4个信息比特，并从第一校验矩阵中读取所述4个信息比特对应的4个行向量，得到最新的CRC校验序列。
根据上述内容可知，在L个目标输出路径分别对应的译码比特序列的校验结果中至少 一个校验结果为校验成功的情况下，可基于第i译码块的L个目标输出路径对第i+1译码块进行译码，也就是说，此时，L个目标输出路径分别对应的译码比特序列的校验结果并不影响对第i+1译码块进行译码时所依据的L个目标输出路径，从而能够避免抬高虚警率。
本申请实施例中，假设所述L个目标输出路径的任一目标输出路径对应的译码比特序列中包括k个比特，则任一目标输出路径对应的译码比特序列中前m个比特不为信息比特，可能存在如下几种示例情形：
情形b1，任一目标输出路径对应的译码比特序列中的比特全为校验比特。此种情形下，由于译码块中的比特全为校验比特时，因此，可直接使用译码比特序列中的校验比特对最近一次得到的CRC校验序列进行校验即可。
进一步地，若确定所述L个目标输出路径分别对应的译码比特序列的校验结果均为校验失败，则停止对所述待译码序列中的第i+1译码块进行译码；若确定所述L个目标输出路径中至少一个目标输出路径对应的译码比特序列的校验结果为校验成功，则基于所述第i译码块的L个目标输出路径对所述待译码比特序列中的第i+1译码块进行译码。
情形b2，任一目标输出路径对应的译码比特序列中前p个比特为校验比特，后k-p个比特为信息比特。比如，译码比特序列中包括8个比特，分别为[u0,u1,u2,u3,u4,u5,u6,u7]，其中，u0为校验比特，[u1,u2,u3,u4,u5,u6,u7]为信息比特。
此种情形下，针对于任一目标输出路径对应的译码比特序列执行如下操作：使用前p个校验比特对最近一次得到的CRC校验序列进行校验。进一步地，若确定所述L个目标输出路径分别对应的译码比特序列的校验结果均为校验失败，则停止对所述待译码序列中的第i+1译码块进行译码；若确定所述L个目标输出路径中至少一个目标输出路径对应的译码比特序列的校验结果为校验成功，则基于所述第i译码块的L个目标输出路径对所述待译码比特序列中的第i+1译码块进行译码。
情形b3，任一目标输出路径对应的译码比特序列中前p个比特为校验比特，中间q个比特为信息比特，后k-p-q个比特为校验比特。比如，译码比特序列中包括8个比特，分别为[u0,u1,u2,u3,u4,u5,u6,u7]，其中，[u0,u7]为校验比特，[u1,u2,u3,u4,u5,u6]为信息比特。
此种情形下，针对于任一目标输出路径对应的译码比特序列执行如下操作：使用前p个校验比特(即u0)对最近一次得到的CRC校验序列进行校验。进一步地，若确定所述L个目标输出路径分别对应的译码比特序列的校验结果均为校验失败，则停止对所述待译码序列中的第i+1译码块进行译码，以及停止对译码比特序列中的其它比特进行处理。若确定所述L个目标输出路径中至少一个目标输出路径对应的译码比特序列的校验结果为校验成功，则对译码比特序列中的信息比特(即[u1,u2,u3,u4,u5,u6])进行处理，得到最新的CRC校验序列；随后，使用校验比特(即u7)对最新的CRC校验序列进行校验，以及：若确定所述L个目标输出路径分别对应的译码比特序列的校验结果均为校验失败，则停止对所述待译码序列中的第i+1译码块进行译码；若确定所述L个目标输出路径中至少一个目标输出路径对应的译码比特序列的校验结果为校验成功，则基于所述第i译码块的L个目标输出路径对所述待译码比特序列中的第i+1译码块进行译码。
本申请实施例中，在一种可能的实现方式中，发送端设备和接收端设备可以预先约定(或者是由协议规定)多个不同的比特序列进行交织操作的交织顺序，其中，多个不同的比特序列是指多个比特序列的序列长度不同。如此，接收端设备可以分别根据约定的交织 顺序对应的解交织顺序对多个不同的待译码比特序列对应的原始校验矩阵中的行向量进行重新排列，从而得到多个不同的待译码比特序列对应的校验矩阵。比如，在盲检测场景中，接收端设备可以通过上述方式离线计算并得到待译码比特序列a、待译码比特序列b和待译码比特序列c分别对应的校验矩阵并存储；若接收端设备确定当前待译码比特序列的序列长度与待译码比特序列a的序列长度相同，则使用待译码比特序列a对应的校验矩阵对当前待译码比特序列的译码结果进行校验。
在另一种可能的实现方式中，考虑到极化码具有nested特性，如此，当最大序列长度的待译码比特序列的校验矩阵确定后，则可根据最大序列长度的待译码比特序列的校验矩阵得到其它较短序列长度的待译码比特序列对应的校验矩阵。示例性地，接收端设备可以离线计算并存储最大序列长度的待译码比特序列对应的校验矩阵，若接收端设备确定当前待译码比特序列的序列长度小于最大序列长度，则根据最大序列长度的待译码比特序列对应的校验矩阵得到当前待译码比特序列对应的校验矩阵，进而对当前待译码比特序列的译码结果进行校验。此时，当前待译码比特序列对应的校验矩阵是通过在线方式得到的，本申请实施例中，也可以预先根据最大序列长度的待译码比特序列对应的校验矩阵通过离线方式得到多个不同的待译码比特序列对应的校验矩阵，具体不做限定。
综合上述描述，结合图6可以看出，本申请实施例在进行译码时，可以直接从第一校验矩阵中读取m个信息比特对应的m个行向量，而无需交替使用D-CRC交织表和D-CRC校验矩阵，从而节省芯片功耗，并能够有效简化Polar码在译码方面的复杂度、降低译码延迟；且无需再存储D-CRC交织表，有效节省芯片面积。此外，由于第一校验矩阵可以通过离线方式得到，从而能够进一步提高译码效率。
基于图5所示的极化码译码方法，如图7所示，本申请实施例还提供了一种译码装置700，译码装置700用于执行图5所示的极化码译码方法，译码装置700中可以包括一个或多个功能单元，比如译码单元701和校验单元702，其中，译码单元701可以用于执行上述步骤501，校验单元702可以用于执行上述步骤502。
在一种可能的设计中，所述校验单元702还用于：若在读取所述m个信息比特之后，读取到校验比特，则使用所述校验比特对所述CRC校验序列进行校验；m为大于等于1的整数；
所述译码单元701还用于：若确定所述L个目标输出路径分别对应的译码比特序列的校验结果均为校验失败，则停止对所述待译码序列中的第i+1译码块进行译码；若确定所述L个目标输出路径中至少一个目标输出路径对应的译码比特序列的校验结果为校验成功，则基于所述第i译码块的L个目标输出路径对所述待译码比特序列中的第i+1译码块进行译码。
在一种可能的设计中，所述译码单元701还用于：若所述校验单元702在读取所述m个信息比特之后，未读取到校验比特，则基于所述第i译码块的L个目标输出路径对所述待译码比特序列中的第i+1译码块进行译码。
在一种可能的设计中，所述校验单元702具体用于：串行读取所述译码比特序列中连续的m个信息比特，并从第一校验矩阵中串行读取所述m个信息比特对应的m个行向量；或者，并行读取所述译码比特序列中连续的m个信息比特，并从第一校验矩阵中并行读取所述m个信息比特对应的m个行向量。
在一种可能的设计中，若所述L个目标输出路径的任一目标输出路径对应的译码比特 序列中的前p个比特为校验比特，且所述译码比特序列中仅有p个校验比特，则所述校验单元702还用于针对于任一目标输出路径对应的译码比特序列执行如下操作：
使用所述译码比特序列中的校验比特对最近一次得到的CRC校验序列进行校验；
所述译码单元701还用于：若确定所述L个目标输出路径分别对应的译码比特序列的校验结果均为校验失败，则停止对所述待译码序列中的第i+1译码块进行译码；若确定所述L个目标输出路径中至少一个目标输出路径对应的译码比特序列的校验结果为校验成功，则基于所述第i译码块的L个目标输出路径对所述待译码比特序列中的第i+1译码块进行译码。
需要说明的是，本申请实施例中对单元的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。在本申请的实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
基于图5所示的极化码译码方法，如图8所示，本申请实施例还提供了一种译码装置800，译码装置800用于执行图5所示的极化码译码方法。图5所示的极化码译码方法中的部分或全部可以通过硬件来实现也可以通过软件来实现，当通过硬件实现时，译码装置800包括：输入接口电路801，用于获取待译码比特序列；逻辑电路802，用于执行上述图5所示的极化码译码方法，具体请见前面方法实施例中的描述，此处不再赘述；输出接口电路803，用于输出译码结果。
可选的，译码装置800在具体实现时可以是芯片或者集成电路。
可选的，当上述实施例的极化码译码方法中的部分或全部通过软件来实现时，如图9所示，译码装置800包括：存储器901，用于存储程序；处理器902，用于执行存储器901存储的程序，当程序被执行时，使得译码装置800可以实现上述图5提供的极化码译码方法。
可选的，上述存储器901可以是物理上独立的单元，也可以如图10所示，存储器901与处理器902集成在一起。
可选的，当上述图5的译码方法中的部分或全部通过软件实现时，译码装置800也可以只包括处理器902，用于存储程序的存储器901位于译码装置800之外，处理器902通过电路/电线与存储器901连接，用于读取并执行存储器901中存储的程序。
处理器902可以是中央处理器(central processing unit，CPU)，网络处理器(network processor，NP)或者CPU和NP的组合。
处理器902还可以进一步包括硬件芯片。上述硬件芯片可以是专用集成电路(application-specific integrated circuit，ASIC)，可编程逻辑器件(programmable logic device，PLD)或其组合。上述PLD可以是复杂可编程逻辑器件(complex programmable logic device，CPLD)，现场可编程逻辑门阵列(field-programmable gate array，FPGA)，通用阵列逻辑(generic array logic,GAL)或其任意组合。
存储器901可以包括易失性存储器(volatile memory)，例如随机存取存储器(random-access memory，RAM)；存储器901也可以包括非易失性存储器(non-volatile memory)，例如快闪存储器(flash memory)，硬盘(hard disk drive，HDD)或固态硬盘(solid-state drive，SSD)；存储器901还可以包括上述种类的存储器的组合。
本申请实施例还提供了一种计算机存储介质，存储有计算机程序，该计算机程序包括用于执行图5所示的极化码译码方法。
本申请实施例还提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行图5所示的极化码译码方法。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本发明实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘Solid State Disk(SSD))等。
本申请是参照根据本申请的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (13)

  1. 一种极化码译码方法，其特征在于，所述方法包括：
    对待译码比特序列中的第i译码块进行译码，并从所述第i译码块的多个输出路径中选择L个目标输出路径；所述待译码比特序列包括信息比特和校验比特，所述校验比特穿插在所述信息比特之间；其中，1≤i≤N，N为所述待译码比特序列中的译码块的总个数，L为整数；
    若所述L个目标输出路径的任一目标输出路径对应的译码比特序列中前m个比特为信息比特，则针对于所述任一目标输出路径对应的译码比特序列，执行如下操作：
    读取所述译码比特序列中连续的m个信息比特，并从第一校验矩阵中读取所述m个信息比特对应的m个行向量，所述第一校验矩阵为根据待译码比特序列的解交织顺序对所述待译码比特序列对应的原始校验矩阵中的行向量重新排列后得到的矩阵；根据所述m个信息比特和所述m个行向量，得到CRC校验序列；m为大于等于1的整数。
  2. 根据权利要求1所述的方法，其特征在于，若在读取所述m个信息比特之后，读取到校验比特，则使用所述校验比特对所述CRC校验序列进行校验；m为大于等于1的整数；
    所述方法还包括：
    若确定所述L个目标输出路径分别对应的译码比特序列的校验结果均为校验失败，则停止对所述待译码序列中的第i+1译码块进行译码；
    若确定所述L个目标输出路径中至少一个目标输出路径对应的译码比特序列的校验结果为校验成功，则基于所述第i译码块的L个目标输出路径对所述待译码比特序列中的第i+1译码块进行译码。
  3. 根据权利要求1所述的方法，其特征在于，若在读取所述m个信息比特之后，未读取到校验比特，则所述方法还包括：
    基于所述第i译码块的L个目标输出路径对所述待译码比特序列中的第i+1译码块进行译码。
  4. 根据权利要求1至3任一项所述的方法，其特征在于，读取所述译码比特序列中连续的m个信息比特，并从第一校验矩阵中读取所述m个信息比特对应的m个行向量，包括：
    串行读取所述译码比特序列中连续的m个信息比特，并从第一校验矩阵中串行读取所述m个信息比特对应的m个行向量；或者，
    并行读取所述译码比特序列中连续的m个信息比特，并从第一校验矩阵中并行读取所述m个信息比特对应的m个行向量。
  5. 根据权利要求1所述的方法，其特征在于，若所述L个目标输出路径的任一目标输出路径对应的译码比特序列中的前p个比特为校验比特，且所述译码比特序列中仅有p个校验比特，则针对于任一目标输出路径对应的译码比特序列执行如下操作：
    使用所述译码比特序列中的p个校验比特对最近一次得到的CRC校验序列进行校验；
    所述方法还包括：
    若确定所述L个目标输出路径分别对应的译码比特序列的校验结果均为校验失败，则停止对所述待译码序列中的第i+1译码块进行译码；
    若确定所述L个目标输出路径中至少一个目标输出路径对应的译码比特序列的校验结果为校验成功，则基于所述第i译码块的L个目标输出路径对所述待译码比特序列中的第i+1译码块进行译码。
  6. 一种译码装置，其特征在于，所述译码装置包括：
    译码单元，用于对待译码比特序列中的第i译码块进行译码，并从所述第i译码块的多个输出路径中选择L个目标输出路径；所述待译码比特序列包括信息比特和校验比特，所述校验比特穿插在所述信息比特之间；其中，1≤i≤N，N为所述待译码比特序列中的译码块的总个数，L为整数；
    校验单元，用于若所述L个目标输出路径的任一目标输出路径对应的译码比特序列中前m个比特为信息比特，则针对于所述任一目标输出路径对应的译码比特序列，执行如下操作：
    读取所述译码比特序列中连续的m个信息比特，并从第一校验矩阵中读取所述m个信息比特对应的m个行向量，所述第一校验矩阵为根据待译码比特序列的解交织顺序对所述待译码比特序列对应的原始校验矩阵中的行向量重新排列后得到的矩阵；根据所述m个信息比特和所述m个行向量，得到CRC校验序列；m为大于等于1的整数。
  7. 根据权利要求6所述的译码装置，其特征在于，所述校验单元还用于：若在读取所述m个信息比特之后，读取到校验比特，则使用所述校验比特对所述CRC校验序列进行校验；m为大于等于1的整数；
    所述译码单元还用于：
    若确定所述L个目标输出路径分别对应的译码比特序列的校验结果均为校验失败，则停止对所述待译码序列中的第i+1译码块进行译码；
    若确定所述L个目标输出路径中至少一个目标输出路径对应的译码比特序列的校验结果为校验成功，则基于所述第i译码块的L个目标输出路径对所述待译码比特序列中的第i+1译码块进行译码。
  8. 根据权利要求6所述的译码装置，其特征在于，所述译码单元还用于：若所述校验单元在读取所述m个信息比特之后，未读取到校验比特，则基于所述第i译码块的L个目标输出路径对所述待译码比特序列中的第i+1译码块进行译码。
  9. 根据权利要求6至8任一项所述的译码装置，其特征在于，所述校验单元具体用于：
    串行读取所述译码比特序列中连续的m个信息比特，并从第一校验矩阵中串行读取所述m个信息比特对应的m个行向量；或者，
    并行读取所述译码比特序列中连续的m个信息比特，并从第一校验矩阵中并行读取所述m个信息比特对应的m个行向量。
  10. 根据权利要求1所述的译码装置，其特征在于，若所述L个目标输出路径的任一目标输出路径对应的译码比特序列中的前p个比特为校验比特，且所述译码比特序列中仅有p个校验比特，则所述校验单元还用于针对于任一目标输出路径对应的译码比特序列执行如下操作：
    使用所述译码比特序列中的校验比特对最近一次得到的CRC校验序列进行校验；
    所述译码单元还用于：
    若确定所述L个目标输出路径分别对应的译码比特序列的校验结果均为校验失败，则 停止对所述待译码序列中的第i+1译码块进行译码；
    若确定所述L个目标输出路径中至少一个目标输出路径对应的译码比特序列的校验结果为校验成功，则基于所述第i译码块的L个目标输出路径对所述待译码比特序列中的第i+1译码块进行译码。
  11. 一种译码装置，其特征在于，所述译码装置包括：
    存储器，用于存储程序；
    处理器，用于执行所述存储器存储的程序，当所述程序被执行时，使得所述译码装置执行如权利要求1～5任一项所述的方法。
  12. 如权利要求11所述的译码装置，其特征在于，所述译码装置为芯片或集成电路。
  13. 一种译码装置，其特征在于，所述译码装置包括：
    输入接口电路，用于获取待译码比特序列；
    逻辑电路，用于基于获取的待译码比特序列执行所述权利要求1～5任一项所述的方法，得到译码结果；
    输出接口电路，用于输出译码结果。
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