WO2020252792A1 - 一种极化码译码方法、装置、芯片、存储介质及程序产品 - Google Patents

一种极化码译码方法、装置、芯片、存储介质及程序产品 Download PDF

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WO2020252792A1
WO2020252792A1 PCT/CN2019/092415 CN2019092415W WO2020252792A1 WO 2020252792 A1 WO2020252792 A1 WO 2020252792A1 CN 2019092415 W CN2019092415 W CN 2019092415W WO 2020252792 A1 WO2020252792 A1 WO 2020252792A1
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sequence
decoded
decoding
bits
llr
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PCT/CN2019/092415
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English (en)
French (fr)
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颜冯尧
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华为技术有限公司
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Priority to CN201980014050.6A priority Critical patent/CN112425078B/zh
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Publication of WO2020252792A1 publication Critical patent/WO2020252792A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes

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  • This application relates to the field of wireless communication technology, and in particular to a polarization code decoding method, device, chip, storage medium and program product.
  • the rapid evolution of wireless communication indicates that the future 5th generation (5G) communication system will show some new characteristics.
  • the three most typical communication scenarios include enhanced mobile broadband (eMBB) and massive machine connections.
  • Communication massive machine type communication, mMTC
  • high reliability and low latency communication ultra reliable low latency communication, URLLC
  • LTE long term evolution
  • channel coding is one of the important research objects to meet the needs of 5G communication.
  • Polar code is selected as the control channel coding method in the 5G standard.
  • Polar code is the first and only known channel coding method that can be strictly proven to "reach" the channel capacity. Under different code lengths, especially for finite codes, the performance of polar codes is much better than Turbo codes and low density parity check (LDPC) codes.
  • polarization codes have lower computational complexity in encoding and decoding. These advantages make polarization codes have great development and application prospects in 5G.
  • the purpose of the embodiments of the present application is to provide a polarization code decoding method, device, chip, storage medium, and program product, which are used to solve the technical problem of a relatively complicated polarization code decoding process and low efficiency.
  • an embodiment of the present application provides a polarization code decoding method, which includes:
  • the LLR sequence includes the LLR of the N bits to be decoded in the bit sequence to be decoded; according to the LLR sequence, the bit sequence to be decoded is performed Decoding to obtain i decoded bits corresponding to the first i decoded bits in the to-be-decoded bit sequence; and determine the minimum Euclidean distance among the K Euclidean distances of the LLR sequence and the K first sequences, and Obtain the metric value of i decoded bits according to the minimum Euclidean distance; K first sequences are obtained based on K candidate decoded bit sequences, and K candidate decoded bit sequences are based on partial decoded bits of i decoded bits Or all the decoded bits are obtained; further, it is determined whether to terminate the decoding of the bit sequence to be decoded according to the metric value; wherein, i, N, and K are all positive integers, and i ⁇ N.
  • the metric value of i decoded bits is calculated, and the metric value is used to determine whether to terminate the decoding prematurely, for example, when the metric value is greater than or equal to the predetermined
  • the threshold is set, decoding can be terminated early, which can reduce unnecessary power consumption and time delay; and, in this way, most unnecessary candidate sets can be filtered out in advance in blind detection scenarios, reducing decoding complexity Degree; Further, because the decoding is terminated early, it can effectively reduce the false alarms that may occur in the decoding process, so as to achieve the purpose of reducing the probability of false alarms.
  • determining whether to terminate the decoding of the bit sequence to be decoded according to the metric value includes: if the metric value is greater than or equal to a preset threshold, terminating the decoding of the bit sequence to be decoded; and/or If the metric value is less than the preset threshold, then continue to decode the bit sequence to be decoded.
  • determining the minimum Euclidean distance among the K Euclidean distances between the LLR sequence and the K first sequences includes: obtaining K candidate decodings corresponding to the bit sequence to be decoded according to i decoding bits Bit sequence; K candidate decoding bit sequences include the first candidate decoding bit sequence, which is executed for the first candidate decoding bit sequence: the second sequence is obtained according to the first candidate decoding bit sequence and the coding matrix, and the second sequence is Perform inversion processing to obtain the first sequence corresponding to the first candidate decoding bit sequence; calculate the Euclidean distance of the first sequence corresponding to the LLR sequence and the first candidate decoding bit sequence; according to the LLR sequence corresponding to the K candidate decoding bit sequences K Euclidean distances of the K first sequence to obtain the minimum Euclidean distance.
  • K Euclidean distances are calculated through traversal and then the minimum Euclidean distance is determined, which can effectively ensure the accuracy of the calculation.
  • the sequence formed by the LLR of, is mapped to obtain the third sequence; the minimum Euclidean distance is obtained according to the difference between the values of the corresponding positions included in the third sequence and the fourth sequence; the fourth sequence includes the last N in the LLR sequence /2 LLR of bits to be decoded.
  • Y 1 N/2 represents the sequence formed by the LLR of the first N/2 bits to be decoded in the LLR sequence, Represents the sequence composed of the last N/2 bits to be decoded in the LLR sequence, Represents the third sequence, Represents the sequence determined according to i decoding bits and the coding matrix, Represents the value after mapping the LLR of the first N/2 bits to be decoded in the LLR sequence, y 1+(N/2) , y 2+(N/2) ,...y N represents the last N of the LLR sequence /2 LLR of the bits to be decoded; ED i represents the minimum Euclidean distance, m and M are integers, and M is less than or equal to N/2.
  • obtaining the metric value of i decoded bits according to the minimum Euclidean distance includes: obtaining the metric value of i decoded bits according to the ratio of the minimum Euclidean distance to the first value, where the first value is N The average value of the absolute value of the LLR of the bit to be decoded.
  • the present application provides a polarization code decoding device, which has the function of implementing the method described in the first aspect and any one of the possible designs of the first aspect.
  • the function can be realized by hardware, or by hardware executing corresponding software.
  • the hardware or software includes one or more modules corresponding to the above-mentioned functions.
  • the decoding device when part or all of the functions are realized by hardware, includes: an input interface circuit for obtaining the LLR sequence corresponding to the bit sequence to be decoded; and a logic circuit for executing The behavior described in the first aspect and any one of the possible designs of the first aspect; the output interface circuit is used to output the decoding result if the logic circuit obtains the decoding result.
  • the polarization code decoding device may be a chip or an integrated circuit.
  • the decoding device when part or all of the functions are realized by software, the decoding device includes: a memory for storing a program; a processor for executing the program stored in the memory, when When the program is executed, the polarization code decoding device can implement the method described in any one of the foregoing first aspect and the first aspect.
  • the foregoing memory may be a physically independent unit, or may be integrated with the processor.
  • the polarization code decoding device when part or all of the functions are implemented by software, includes a processor.
  • the memory for storing the program is located outside the decoding device, and the processor is connected to the memory through a circuit/wire for reading and executing the program stored in the memory.
  • inventions of the present application provide a communication system.
  • the communication system includes a network device and a terminal device. Both the network device and the terminal device can perform the first aspect or any one of the possibilities of the first aspect. The method described in the design.
  • an embodiment of the present application provides a computer storage medium storing a computer program, and the computer program includes instructions for executing the above-mentioned first aspect or any one of the possible designs of the first aspect.
  • a computer program product containing instructions which when running on a computer, causes the computer to execute the method described in the above-mentioned first aspect or any one of the possible designs of the first aspect.
  • Figure 1 is a schematic diagram of a binary tree structure provided by an embodiment of the application.
  • Figure 2 is a schematic diagram of a grid structure provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of the process of the SC decoding method provided by an embodiment of the application.
  • FIG. 4a is a schematic diagram of a decoding path in an SCL decoding method provided by an embodiment of this application.
  • 4b is a schematic diagram of the decoding calculation process provided by an embodiment of the application.
  • FIG. 5 is a schematic diagram of a network architecture to which an embodiment of this application is applicable.
  • FIG. 6 is a schematic diagram of a polarization code encoding and decoding process provided by an embodiment of the application.
  • Figure 7 is a schematic diagram of the blind detection decoding process
  • FIG. 8 is a schematic flowchart corresponding to a polarization code decoding method provided by an embodiment of this application.
  • FIG. 9 is a possible exemplary block diagram of a device involved in an embodiment of this application.
  • FIG. 10 is a schematic structural diagram of a polarization code decoding apparatus provided by an embodiment of the application.
  • FIG. 11 is a schematic structural diagram of another polarization code decoding device provided by an embodiment of the application.
  • Polarization code is a channel coding method that can theoretically be proved to "reach" the channel capacity.
  • Polarization code is a linear block code, its generator matrix is G N , and its encoding process is Is a binary row vector with length N (ie code length); and
  • B N is an N ⁇ N transposed matrix, such as a bit reverse transposed matrix; among them, B N is an optional quantity, and the operation of generating the matrix G N can omit the operation of B N. It is defined as the Kronecker product of log 2 N matrices F 2 , where x 1 N is the encoded bit (also called codeword), After multiplying with the generator matrix G N , the encoded bits are obtained.
  • the multiplication process is the encoding process.
  • the other part of the bits in the set is a fixed value pre-appointed by the sender and receiver, which is called a fixed bit.
  • the index set is Complement Said.
  • the fixed bit is usually set to 0, and it only needs to be agreed in advance by the transceiver, and the fixed bit sequence can be set arbitrarily.
  • Polarization code decoding is processed layer by node and node by node, as shown in the binary tree structure in Figure 1, ⁇ represents the layer number, and each layer includes at least one node.
  • the soft bit data sequence of node 0 is ⁇ S 00 , S 01 , S 02 , S 03 , S 04 , S 05 , S 06 , S 07 ⁇ .
  • node 0, node 1, and node 2 are non-leaf nodes, and node 3, node 4, node 5, and node 6 are leaf nodes.
  • the soft bit data of node 4 is ⁇ S 22 , S 23 ⁇ ; since node 4 is a leaf node, the soft bit data of node 4 is obtained by decoding Two hard bits; according to the hard bits obtained by decoding the soft bit data of node 3 and node 4, perform G operation on node 0 to obtain the soft bit data of node 2, and the soft bit data of node 2 is ⁇ S 14 , S 15 , S 16 , S 17 ⁇ ; because node 2 is a non-leaf node, perform F operation on node 2 to get the soft bit data of node 5, and the soft bit data of node 5 is ⁇ S 24 , S 25 ⁇ ; because node 5 As a leaf node, decode the soft bit data of node 5 to obtain two hard bits, and perform G operation on node 2 according to the obtained two hard bits to obtain the soft bit data of node 6, and the soft bit data of node 6 is ⁇ S 26 , S 27 ⁇ , thereby completing the decoding.
  • F calculation adopts simplified calculation, and the F calculation formula is:
  • G operation adopts simplified operation, and the G operation formula is:
  • the grid structure shown in Fig. 2 is a detailed description of the F/G operation between nodes in the binary tree structure of Fig. 1.
  • the solid arrow between nodes is the F operation
  • the dashed arrow is the G operation
  • two arrows that only go to the same position form a pair.
  • the two inputs a and b of the F/G operation are the data corresponding to the source positions of the two pairs of arrows in the grid structure; and the position pointed to by the arrows stores the output of the F/G operation.
  • the input u of the G operation is the decoding result (hard bit, value 0 or 1) of the output position of the F operation that has the same input a and b.
  • FIG. 3 is a schematic diagram of the SC decoding calculation process. Taking 4 decoding bits as an example, there are 8 calculation nodes in Figure 3, including 4 F nodes, 4 G nodes, and F nodes and G nodes respectively correspond to F operations. Calculate with G.
  • the operation of the F node requires the 2 LLR inputs on the right side
  • the operation of the G node requires the 2 LLR inputs on the right and the output of the previous stage as inputs.
  • the output can only be calculated after the input items are calculated. According to the above calculation rules, in Figure 3, starting from the right side, 8 nodes are calculated in order, and the decoded bits obtained are 1 ⁇ 2 ⁇ 3 ⁇ 4, and the decoding is completed.
  • FIG. 4a shows SCL decoding.
  • select L paths with the best path metric (PM) value Save and continue to develop the path to decode the subsequent decoded bits.
  • PM path metric
  • the PM value is used to judge the path, and the PM value is calculated by LLR. For each level of decoding bits, the PM values of the L paths are sorted from small to large, and the correct path is filtered by the PM value, and so on, until the last bit is decoded.
  • the right side is the LLR input side, or called the codeword side; the left side is the information side, or called the decoding bit side.
  • yi is the information to be decoded
  • u i is the decoded bit.
  • N 16
  • the LLR is read from the codeword side, and the probability is passed to obtain the LLR value of the first decoded bit.
  • the LLR value is judged to obtain the decoded result of the first decoded bit.
  • the decoded bits contain fixed bits and information bits.
  • the fixed bit position has a decision bit value of 0 regardless of the LLR; the decision bit value of the information bit position can have two types, 0 and 1, so it can be split into two paths.
  • FIG. 5 is a schematic diagram of a network architecture to which an embodiment of this application is applicable.
  • the network architecture may include at least one network device 100 (only one is shown) and one or more terminal devices 200 connected to the network device 100.
  • the network device 100 may be a device that can communicate with the terminal device 200.
  • the network device 100 may be any device with a wireless transceiver function. Including but not limited to: base station (for example, base station NodeB, evolved base station eNodeB, base station in the fifth generation (5G) communication system, base station or network equipment in future communication system, access node in WiFi system , Wireless relay node, wireless backhaul node), etc.
  • the network device 100 may also be a wireless controller in a cloud radio access network (cloud radio access network, CRAN) scenario.
  • the network device 100 may also be a small station, a transmission reference point (TRP), etc.
  • TRP transmission reference point
  • the terminal device 200 is a device with wireless transceiver function that can be deployed on land, including indoor or outdoor, handheld, wearable or vehicle-mounted; it can also be deployed on water (such as ships, etc.); it can also be deployed in the air (such as airplanes, Balloons and satellites are classy).
  • the terminal device may be a mobile phone (mobile phone), a tablet computer (Pad), a computer with wireless transceiver function, a virtual reality (VR) terminal device, an augmented reality (Augmented Reality, AR) terminal device, an industrial control ( Wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical, wireless terminals in smart grids, and transportation safety Wireless terminal, wireless terminal in smart city, wireless terminal in smart home, etc.
  • VR virtual reality
  • AR Augmented Reality
  • Wireless terminals in industrial control Wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical, wireless terminals in smart grids, and transportation safety Wireless terminal, wireless terminal in smart city,
  • Terminal equipment can sometimes be called user equipment (UE), access terminal equipment, UE unit, UE station, mobile station, mobile station, remote station, remote terminal equipment, mobile equipment, UE terminal equipment, terminal equipment, Wireless communication equipment, UE agent or UE device, etc.
  • UE user equipment
  • access terminal equipment UE unit
  • UE station mobile station
  • mobile station mobile station
  • remote station remote terminal equipment
  • mobile equipment UE terminal equipment
  • terminal equipment Wireless communication equipment
  • UE agent or UE device etc.
  • network architecture can be applied to communication systems of various wireless access technologies, for example, 5G communication systems and other possible communication systems.
  • the sending end device (such as network device 100) can encode information bits (such as polarization code encoding); accordingly, the receiving end device (such as terminal The device 200) can perform decoding (for example, polarization code decoding) to obtain information bits.
  • decoding for example, polarization code decoding
  • FIG. 6 the polarization code encoding and decoding process involved in the communication process between the transmitting end device and the receiving end device is shown in FIG. 6, including: step 601, the transmitting end device obtains a bit sequence input for coding (a bit sequence input for coding) ,
  • the coded input bit sequence can include information bits and fixed bits.
  • Step 602 The sender device performs verification (such as cyclic redundancy check (CRC)) encoding to obtain a verification codeword.
  • Step 603 The sending end device performs an interleaving operation on the verification coded word.
  • Step 604 The transmitting-end device performs polarization code encoding on the check-coded codeword after the interleaving operation to obtain a bit sequence output for coding.
  • Step 605 The transmitting end device maps the coded output bit sequence into modulation symbols, and processes and sends the coded output bit sequence through the channel.
  • Step 606 The receiving end device obtains the LLR sequence corresponding to the bit sequence to be decoded, where the LLR sequence includes multiple LLRs of the bit to be decoded.
  • step 607 the receiving end device performs polarization code decoding according to the LLR sequence.
  • step 608 The receiving end device performs a de-interleaving operation on the decoded sequence.
  • step 609 The receiving end device judges whether the decoding result is successfully decoded through the CRC check.
  • RNTI radio network tempory identity
  • Descrambling, de-rate matching, etc. which are not specifically limited.
  • the network device 100 and the terminal device 200 also interact with instructions (for example, the network device 100 communicates to the terminal device 200 via the physical downlink control channel (PDCCH)).
  • PDCCH physical downlink control channel
  • Send instruction the network device 100 completes the scheduling of the terminal device 200 through the instruction, and transmits the format information of the scheduling.
  • the network device 100 often does not send or less sends some scheduling signaling, and the terminal device 200 monitors whether there is a scheduling by itself according to certain rules. During the monitoring process, the terminal device 200 needs to perform blind detection and decoding without knowing the exact format.
  • blind detection decoding process Most of the blind detection decoding process is shown in Figure 7. First, all possible decoding parameters are listed, and each hypothesis is combined according to the decoding parameters and the LLR sequence (demodulation soft value) corresponding to the bit sequence to be decoded. A candidate set (candidate) is used for decoding, and the decoding result is checked (such as CRC) to determine whether it is right or wrong. This process continues until the correct decoding result is searched or the whole set is traversed or a certain preset condition is reached. In the general blind detection hypothesis, there may be 44 candidate sets. In other words, the maximum number of blind detection configurations is 44, that is, a maximum of 44 complete decoding processes are required.
  • the polarization code decoding method (such as the SCL decoding method) is used for blind detection decoding, only after all the information bits are decoded can it be determined whether the current decoding result is valid. In this way, in the case of a long code length, the decoding complexity is relatively high, and the decoding delay will be correspondingly prolonged, which makes it difficult to meet the scenes with strict requirements on the signal delay (such as the URLLC scene).
  • an embodiment of the present application provides a polarization code decoding method, which is used to reduce the complexity of polarization code decoding and thereby reduce the decoding delay.
  • the polarization code decoding method provided in the embodiments of the present application may be executed by a receiving end device, where the receiving end device may be the network device 100 shown in FIG. 5 or the terminal device 200 shown in FIG. 5.
  • the decoding method provided in the embodiment of the present application may be executed by the terminal device 200.
  • N can also be considered as the length of the polarization code mother code.
  • the bit sequence to be decoded is decoded to obtain the decoding result (ie, decoded bit sequence).
  • the transceiver end pre-appoints the position of the fixed bit, and the fixed bit is usually set to 0. In fact, the content of the information bit needs to be obtained through the decoding process. In practical applications, the number of N may be very large.
  • the LLR vector of length N corresponding to the LLR sequence passes through multiple levels of F/G operations to reach the last level, and the bit decision is performed on the LLR of the last level to obtain a decoding Bits, using bit-by-bit splitting paths, when the number of paths is greater than L, select the optimal L paths according to the PM value, and continue to split the paths until the last bit is translated, and the computational complexity and delay are very high.
  • the embodiment of the present application can calculate the metric value of i decoded bits when i (i ⁇ N) decoded bits are obtained, and determine whether to terminate the decoding in advance according to the metric value.
  • decoding When the metric value is greater than or equal to the predetermined
  • decoding can be terminated early, which can reduce unnecessary power consumption and time delay; and, in this way, most unnecessary candidate sets can be filtered out in advance in blind detection scenarios, reducing decoding complexity Degree; Further, because the decoding is terminated early, it can effectively reduce the false alarms that may occur in the decoding process, so as to achieve the purpose of reducing the probability of false alarms.
  • FIG. 8 is a schematic flowchart of a decoding method provided by an embodiment of this application. As shown in Figure 8, the method includes:
  • Step 801 Obtain an LLR sequence corresponding to the bit sequence to be decoded, where the LLR sequence includes LLRs of N bits to be decoded.
  • N is the length of the mother code of the polarization code; if the sending end device does not perform rate matching when sending the bit sequence, the receiving end device can receive N bits to be decoded from the sending end; if the sending end device is sending bits When rate matching is performed during the sequence, the receiving end device can receive N'(N' can be a value less than N, which is not limited) from the transmitting end device, and proceed according to the N'number of bits to be decoded. Derate rate matching, and obtain N bits to be decoded.
  • the receiving end device can calculate the LLR of the N bits to be decoded according to the noise variance of the channel.
  • the LLR of the bit to be decoded can be calculated by the following formula:
  • t represents the bit to be decoded
  • LLR(t) represents the LLR of the bit to be decoded
  • 0) represents the probability that the bit to be decoded is 0
  • 1) represents the bit to be decoded
  • ⁇ represents the noise variance of the channel.
  • the LLR sequence is [1.5, 2, -1, -3].
  • Step 802 Decode the bit sequence to be decoded according to the LLR sequence to obtain i decoded bits corresponding to the first i bits to be decoded in the bit sequence to be decoded.
  • the SCL decoding method (such as the SCL8 decoding method) may be used to decode the bit sequence to be decoded.
  • Step 803 Determine the minimum Euclidean distance among the K Euclidean distances of the LLR sequence and the K first sequences, and obtain the metric value of i decoded bits according to the minimum Euclidean distance.
  • Step 804 Determine whether to terminate the decoding of the bit sequence to be decoded according to the metric value.
  • the metric value of i decoding bits may be obtained according to the smallest Euclidean distance among the K Euclidean distances between the LLR sequence and the K first sequences, where the K first sequences are based on the K candidate decoding Obtained by a bit sequence, the K candidate decoding bit sequences are obtained based on part of the decoding bits or all of the i decoding bits.
  • the smallest Euclidean distance among the K Euclidean distances between the LLR sequence and the K first sequences is the Euclidean distance between the LLR sequence and the first sequence a.
  • the metric value of i decoded bits is based on the LLR sequence The Euclidean distance from the first sequence a is obtained. Therefore, the metric value of i decoded bits can indicate how close the LLR sequence is to the first sequence a.
  • the decoding process performed by the receiving end device is actually the inverse process of the encoding process performed by the transmitting end device.
  • the encoding process is based on the encoded input bit sequence to obtain the encoded output bit sequence.
  • the decoding process is based on the LLR sequence to get the decoded bit sequence. If the decoding result is completely accurate, the decoded bit sequence is the coded input bit sequence of the transmitting end device, and further, the second sequence obtained based on the decoded bit sequence and the coding matrix is the coded output bit encoded by the transmitting end device.
  • Sequence and then flip the second sequence to obtain a higher degree of closeness between the first sequence and the LLR sequence (for example, the two can be exactly the same in theory); if the decoding result is not accurate enough, the bit sequence is decoded and sent The coded input bit sequence of the end device will be different, and further, the second sequence obtained based on the decoded bit sequence and coding matrix and the coded output bit sequence coded by the transmitting end device will also be different, and the second sequence is reversed. The processing results in a low degree of closeness between the first sequence and the LLR sequence.
  • the first sequence a is the sequence closest to the LLR sequence among the K first sequences; further, if the first sequence a closest to the LLR sequence is closer to the LLR, it will be decoded
  • the metric value of i decoded bits can indicate the closeness of the LLR sequence to the first sequence a, for example, the smaller the metric value of i decoded bits, the higher the closeness of the LLR sequence to the first sequence a (also That is, the accuracy of decoding is higher), the greater the metric value of i decoded bits, the lower the closeness of the LLR sequence to the first sequence a (that is, the lower the accuracy of decoding), therefore, based on i The metric value of each decoded bit.
  • the decoding accuracy is low (for example, the decoding may be caused by the inaccuracy of the decoding parameters based on the LLR sequence. (The accuracy rate is low), at this time, the decoding can be terminated early, which can reduce unnecessary power consumption and time delay.
  • the inaccuracy of the decoding parameters based on the LLR sequence decoding can be understood as: taking the blind detection scenario as an example, for example, if the number of information bits in the N bits to be decoded is N1, and The number of information bits in the decoding parameter based on the LLR sequence decoding is N2 (N2 is not equal to N1). At this time, it can be understood that the decoding parameter based on the LLR sequence decoding is not accurate. It should be understood that the decoding parameters can also include other possible information. Therefore, there can be many situations where the decoding parameters based on the LLR sequence are not accurate, and one is listed here for ease of understanding. Possible simple example.
  • K candidate decoding bit sequences corresponding to the bit sequence to be decoded can be obtained according to the i decoding bits; among them, the K candidate decoding bit sequences include the first candidate decoding bit sequence, and for the first A candidate decoding bit sequence is executed: the second sequence is obtained according to the first candidate decoding bit sequence and the coding matrix, and the second sequence is inverted to obtain the first sequence corresponding to the first candidate decoding bit sequence; calculating the LLR sequence and the first candidate decoding bit sequence The Euclidean distance of the first sequence corresponding to a candidate decoding bit sequence; further, the minimum Euclidean distance can be obtained according to the K Euclidean distances of the K first sequences corresponding to the LLR sequence and the K candidate decoding bit sequences.
  • candidate decoding bit sequence 1 is [0, 0, 0, 0]
  • candidate decoding bit sequence 2 is [0, 0, 0, 1]
  • candidate decoding bit sequence 3 Is [0, 0, 1, 0]
  • the candidate decoding bit sequence 4 is [0, 0, 1, 1].
  • the second sequence 1 corresponding to the candidate decoding bit sequence 1 can be obtained as [0, 0, 0, 0]; according to the candidate decoding bit sequence 2 and the coding matrix, the candidate can be obtained
  • the second sequence 2 corresponding to the decoding bit sequence 2 is [1, 1, 1, 1]; according to the candidate decoding bit sequence 3 and the coding matrix, the second sequence 3 corresponding to the candidate decoding bit sequence 3 can be obtained as [1 , 0, 1, 0]; According to the candidate decoding bit sequence 4 and the coding matrix, the second sequence 4 corresponding to the candidate decoding bit sequence 3 can be obtained as [0, 1, 0, 1].
  • the second sequence 1 is reversed, and the first sequence sequence 1 corresponding to the second sequence 1 can be obtained as [1, 1, 1, 1]; and then calculate [1, 1, 1, 1 ] And [1.5, 2, -1, -3] Euclidean distance.
  • the Euclidean distance of [1, 1, 1, 1] and [1.5, 2, -1, -3] there can be many specific ways to calculate the Euclidean distance of [1, 1, 1, 1] and [1.5, 2, -1, -3], one possible way (in the embodiment of this application) This method is mainly used as an example to describe).
  • [1, 1, 1, 1] can be understood as a position point in four-dimensional space (called position point 1), and [1.5, 2 , -1, -3] is understood as another location point in the four-dimensional space (called location point 2), and then the Euclidean distance between location point 1 and location point 2 is calculated according to the calculation formula of Euclidean distance, the Euclidean distance is Is the Euclidean distance between the first sequence sequence 1 and the LLR sequence.
  • the minimum Euclidean distance can be obtained as 3.
  • the sequence formed by the LLRs of the first N/2 bits to be decoded in the LLR sequence can be mapped to obtain the third sequence, and then according to the corresponding positions included in the third sequence and the fourth sequence The difference between the values of to obtain the minimum Euclidean distance; where the fourth sequence includes the LLR of the last N/2 bits to be decoded in the LLR sequence.
  • G N represents the coding matrix
  • Represents the coded output bit sequence (can be understood as the coded output bit sequence generated by the sending device), Represents the sequence composed of the first N/2 bits in the encoded output bit sequence, Represents a sequence composed of the last N/2 bits in the encoded output bit sequence;
  • Represents the coded input bit sequence Represents a sequence composed of the first N/2 bits in the encoded input bit sequence, Represents a sequence composed of the last N/2 bits in the encoded input bit sequence.
  • Y 1 N/2 represents the sequence formed by the LLR of the first N/2 bits to be decoded in the LLR sequence
  • the minimum Euclidean distance can be determined by the following formula:
  • ED i represents the minimum Euclidean distance, Indicates the value after mapping the LLR of the first N/2 bits to be decoded in the LLR sequence, y 1+(N/2) , y 2+(N/2) ,...y N represents the last of the LLR sequence LLR of N/2 bits to be decoded, m and M are integers.
  • the foregoing implementation 2 is described based on the N/2 decoded bits obtained by decoding to determine the minimum Euclidean distance as an example.
  • i can also be smaller than N/2.
  • it can be processed based on the above formula 3, formula 4, and formula 5.
  • the coded output bit sequence can be divided into smaller granularity based on the recursive form of the coding matrix (the above formula 3 is The encoded output bit sequence is divided into with Two sequences), for example, the coded output bit sequence is divided into four sequences or eight sequences, etc., so that the minimum Euclidean distance can also be determined based on derivation.
  • the metric value of i decoded bits can be obtained according to the ratio of the minimum Euclidean distance to the first value, where the first value is the average value of the absolute values of the LLRs of the N bits to be decoded . See the following formula:
  • R i represents the metric value of i decoding bits
  • ED i represents the minimum Euclidean distance
  • ave represents the first value.
  • LLR sequence is [1.5, 2, -1, -3]
  • the N bits to be decoded are signals of a normal additive white gaussian noise (AWGN) channel, the smaller the interference, the smaller the Rate( ⁇ ); if the N bits to be decoded The bit is a pure noise signal, and the Rate ( ⁇ ) tends to 0.5.
  • AWGN additive white gaussian noise
  • the N bits to be decoded can be understood as pure noise signals, that is, if the decoding based on the LLR sequence is based on If the decoding parameter of is not accurate, the Rate( ⁇ ) tends to 0.5.
  • the preset threshold may be a certain value less than 0.5.
  • the preset threshold may be 0.2.
  • the preset threshold may be set by the technology in the art according to actual needs, and the specifics are not limited. .
  • the decoding of the bit sequence to be decoded can be terminated. For example, in a blind detection scenario, after this decoding is terminated, other The decoding parameter is decoded next time to obtain the decoding result and output; if it is less than the preset threshold, the decoding bit sequence can be continued to be decoded to obtain the decoding result and output. In this way, by determining the metric value of i decoded bits through the foregoing implementation manner 1 or implementation manner 2, it can be determined whether it is greater than or equal to a preset threshold (assumed to be 0.2).
  • the polarization code decoding apparatus may include corresponding hardware structures and/or software modules for performing various functions.
  • the embodiments of the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed by hardware or computer software-driven hardware depends on the specific application and design constraint conditions of the technical solution. Professionals and technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered beyond the scope of this application.
  • FIG. 9 shows a possible exemplary block diagram of a device involved in an embodiment of the present application, and the device 900 may exist in the form of software.
  • the apparatus 900 may include:
  • the obtaining module 901 is configured to obtain a log-likelihood ratio LLR sequence corresponding to the bit sequence to be decoded, where the LLR sequence includes the log-likelihood ratio LLRs of N bits to be decoded in the bit sequence to be decoded;
  • the decoding module 902 is configured to decode the bit sequence to be decoded according to the LLR sequence to obtain i decoded bits corresponding to the first i bits to be decoded in the bit sequence to be decoded. Determine the minimum Euclidean distance of the K Euclidean distances between the LLR sequence and the K first sequences, and obtain the metric value of the i decoding bits according to the minimum Euclidean distance; the K first sequences Is obtained based on K candidate decoding bit sequences, the K candidate decoding bit sequences are obtained based on part or all of the i decoding bits; and, according to the metric value Determining whether to terminate the decoding of the bit sequence to be decoded;
  • i, N, and K are all positive integers, i ⁇ N.
  • the decoding module 902 is specifically configured to: if the metric value is greater than or equal to a preset threshold, terminate the decoding of the bit sequence to be decoded; and/or if If the metric value is less than the preset threshold, then continue to decode the bit sequence to be decoded.
  • the decoding module 902 is specifically configured to:
  • K candidate decoded bit sequences corresponding to the to-be decoded bit sequence are obtained; the K candidate decoded bit sequences include the first candidate decoded bit sequence, and are directed to the first Execution of a candidate decoding bit sequence: obtaining a second sequence according to the first candidate decoding bit sequence and coding matrix, and performing inversion processing on the second sequence to obtain the first sequence corresponding to the first candidate decoding bit sequence Calculate the Euclidean distance of the first sequence corresponding to the LLR sequence and the first candidate decoding bit sequence; according to K of the K first sequences corresponding to the LLR sequence and the K candidate decoding bit sequences Euclidean distance, the minimum Euclidean distance is obtained.
  • the decoding module 902 is specifically configured to: perform mapping processing on a sequence composed of the first N/2 bits to be decoded in the LLR sequence to obtain The third sequence; the minimum Euclidean distance is obtained according to the difference between the numerical values at the corresponding positions included in the third sequence and the fourth sequence; the fourth sequence includes the last N/2 in the LLR sequence The LLR of the bits to be decoded.
  • the decoding module 902 is specifically used to:
  • Y 1 N/2 represents a sequence composed of the LLRs of the first N/2 bits to be decoded in the LLR sequence
  • Represents the third sequence Represents the sequence determined according to the i decoding bits and the coding matrix, Indicates the value after mapping the LLR of the first N/2 bits to be decoded in the LLR sequence, y 1+(N/2) , y 2+(N/2) ,...
  • y N represents the LLR
  • ED i represents the minimum Euclidean distance
  • m and M are integers
  • M is less than or equal to N/2.
  • the decoding module 902 is specifically configured to: obtain the metric value of the i decoding bits according to the ratio of the minimum Euclidean distance to a first value, where the first value is the The average value of the absolute value of the LLR of the N bits to be decoded.
  • the polarization code decoding device shown in FIG. 9 in the embodiment of the present application divides the modules into schematic form, which is only a logical function division, and there may be other division methods in actual implementation.
  • the functional units in the various embodiments of the present application may be integrated into one processing unit, or may exist alone physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.
  • an embodiment of the present application also provides a polarization code decoding device 1000, and the polarization code decoding device 1000 is configured to execute the polarization code decoding method shown in FIG. Part or all of the polarization code decoding method shown in FIG. 8 can be implemented by hardware or software.
  • the polarization code decoding device 1000 includes: an input interface circuit 1001 for Obtain the LLR sequence corresponding to the bit sequence to be decoded; the logic circuit 1002 is used to implement the polarization code decoding method shown in FIG. 8; the output interface circuit 1003 is used to output the decoded result if the logic circuit obtains the decoding result Code result.
  • the polarization code decoding device 1000 may be a chip or an integrated circuit in specific implementation.
  • the polarization code decoding device 1100 when part or all of the polarization code decoding method shown in FIG. 8 is implemented by software, as shown in FIG. 11, the polarization code decoding device 1100 includes: a memory 1101 for storing programs; The processor 1102 is configured to execute a program stored in the memory 1101, and when the program is executed, the polarization code decoding device 1100 can implement the polarization code decoding method shown in FIG. 8.
  • the foregoing memory 1101 may be a physically independent unit, or may be integrated with the processor 1102.
  • the polarization code decoding apparatus 1100 may also only include the processor 1102.
  • the memory 1101 for storing programs is located outside the polarization code decoding device 1100, and the processor 1102 is connected to the memory 1101 through a circuit/wire for reading and executing the programs stored in the memory 1101.
  • the processor 1102 may be a central processing unit (CPU), a network processor (NP), or a combination of a CPU and an NP.
  • CPU central processing unit
  • NP network processor
  • the processor 1102 may further include a hardware chip.
  • the aforementioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof.
  • ASIC application-specific integrated circuit
  • PLD programmable logic device
  • the above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.
  • CPLD complex programmable logic device
  • FPGA field-programmable gate array
  • GAL generic array logic
  • the memory 1101 may include a volatile memory (volatile memory), such as random-access memory (RAM); the memory 1101 may also include a non-volatile memory (non-volatile memory), such as flash memory (flash memory). memory), a hard disk drive (HDD) or a solid-state drive (SSD); the memory 1101 may also include a combination of the foregoing types of memories.
  • volatile memory such as random-access memory (RAM)
  • non-volatile memory such as flash memory (flash memory).
  • flash memory flash memory
  • HDD hard disk drive
  • SSD solid-state drive
  • the memory 1101 may also include a combination of the foregoing types of memories.
  • An embodiment of the present application also provides a computer storage medium storing a computer program, and the computer program includes a method for performing the polarization code decoding provided in the foregoing method embodiment.
  • the embodiments of the present application also provide a computer program product containing instructions, which when run on a computer, cause the computer to execute the polarization code decoding method provided in the foregoing method embodiments.
  • Any polarization code decoding device provided in the embodiments of the present application may also be a chip.
  • the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, this application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.
  • a computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing equipment to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction device.
  • the device implements the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.
  • These computer program instructions can also be loaded on a computer or other programmable data processing equipment, so that a series of operation steps are executed on the computer or other programmable equipment to produce computer-implemented processing, so as to execute on the computer or other programmable equipment.
  • the instructions provide steps for implementing functions specified in a flow or multiple flows in the flowchart and/or a block or multiple blocks in the block diagram.

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Abstract

一种极化码译码方法、装置、芯片、存储介质及程序产品，其中方法包括：获取待译码比特序列对应的对数似然比LLR序列，根据LLR序列，对待译码比特序列进行译码，得到待译码比特序列中的前i个待译码比特分别对应的i个译码比特；以及，确定LLR序列与K个第一序列的K个欧式距中的最小欧式距，并根据最小欧式距得到i个译码比特的度量值；进而，根据度量值确定是否对终止对待译码比特序列进行译码。采用上述方法，在得到i个译码比特时，计算i个译码比特的度量值，并根据度量值来判别是否提前终止该次译码，比如在度量值大于或等于预设阈值时，可以提前终止译码，从而能够减少不必要的功耗和时延。

Description

一种极化码译码方法、装置、芯片、存储介质及程序产品 技术领域
本申请涉及无线通信技术领域，特别涉及一种极化码译码方法、装置、芯片、存储介质及程序产品。
背景技术
无线通信的快速演进预示着未来第五代(5th generation，5G)通信系统将呈现出一些新的特点，最典型的三个通信场景包括增强型移动互联网(enhance mobile broadband，eMBB)、海量机器连接通信(massive machine type communication，mMTC)和高可靠低延迟通信(ultra reliable low latency communication，URLLC)，这些通信场景的需求将对现有长期演进(long term evolution，LTE)技术提出新的挑战。信道编码作为最基本的无线接入技术，是满足5G通信需求的重要研究对象之一。
极化(Polar)码在5G标准中被选作控制信道编码方式，极化码是第一种、也是已知的唯一能够被严格证明“达到”信道容量的信道编码方法。在不同码长下，尤其对于有限码，极化码的性能远优于Turbo码和低密度奇偶校验码(low density parity check，LDPC)码。另外，极化码在编译码方面具有较低的计算复杂度。这些优点让极化码在5G中具有很大的发展和应用前景。
然而，如何降低极化码译码过程的复杂度、进而降低译码时延，仍需进一步研究。
发明内容
本申请实施方式的目的在于提供一种极化码译码方法、装置、芯片、存储介质及程序产品，用于解决极化码译码过程较为复杂、效率较低的技术问题。
第一方面，本申请实施例提供一种极化码译码方法，该方法包括：
获取待译码比特序列对应的对数似然比LLR序列，LLR序列包括待译码比特序列中的N个待译码比特的对数似然比LLR；根据LLR序列，对待译码比特序列进行译码，得到待译码比特序列中的前i个待译码比特分别对应的i个译码比特；以及，确定LLR序列与K个第一序列的K个欧式距中的最小欧式距，并根据最小欧式距得到i个译码比特的度量值；K个第一序列是基于K个候选译码比特序列得到的，K个候选译码比特序列基于i个译码比特中的部分译码比特或全部译码比特得到的；进而，根据度量值确定是否对终止对待译码比特序列进行译码；其中，i、N、K均为正整数，i<N。
采用上述方法，在得到i(i<N)个译码比特时，计算i个译码比特的度量值，并根据度量值来判别是否提前终止该次译码，比如在度量值大于或等于预设阈值时，可以提前终止译码，从而能够减少不必要的功耗和时延；并且，通过这种方式，在盲检测场景中能够提前筛选掉大部分不需要的候选集，降低译码复杂度；进一步地，由于提前终止了该次译码，能够有效降低译码过程中可能出现的虚警，从而能够达到降低虚警概率的目的。
在一种可能的设计中，根据度量值确定是否对终止对待译码比特序列进行译码，包括：若度量值大于或等于预设阈值，则终止对待译码比特序列进行译码；和/或，若度量值小于预设阈值，则继续对待译码比特序列进行译码。
在一种可能的设计中，当i<N/2时，K个候选译码比特序列可以是基于i个译码比特中的全部译码比特得到的，此时K＝2 N-i；由于i<N/2，即译码比特的个数较少，此时为保证计算得到的最小欧式距的准确性，可以依据i个译码比特中的全部译码比特。当i≥N/2时，K个候选译码比特序列可以是基于i个译码比特中的前N/2个译码比特得到的，此时K＝2 N/2，从而当i≥N/2时，通过设置K＝2 N/2能够有效降低计算量和处理的复杂度。
在一种可能的设计中，确定LLR序列与K个第一序列的K个欧式距中的最小欧式距，包括：根据i个译码比特，得到待译码比特序列对应的K个候选译码比特序列；K个候选译码比特序列中包括第一候选译码比特序列，针对第一候选译码比特序列执行：根据第一候选译码比特序列和编码矩阵得到第二序列，对第二序列进行翻转处理得到第一候选译码比特序列对应的第一序列；计算LLR序列与第一候选译码比特序列对应的第一序列的欧式距；根据LLR序列与K个候选译码比特序列对应的K个第一序列的K个欧式距，得到最小欧式距。
采用上述方法，通过遍历计算出K个欧式距进而确定出最小欧式距，能够有效保证计算的准确性。
在一种可能的设计中，i≥N/2；确定LLR序列与K个第一序列的K个欧式距中的最小欧式距，包括：对LLR序列中的前N/2个待译码比特的LLR构成的序列进行映射处理，得到第三序列；根据第三序列和第四序列所包括的对应位置上的数值之间的差异，得到最小欧式距；第四序列包括LLR序列中的后N/2个待译码比特的LLR。
采用上述方法来确定最小欧式距，能够有效降低计算的复杂度，节省处理资源。
在一种可能的设计中，通过如下公式得到第三序列：
Figure PCTCN2019092415-appb-000001
通过如下公式得到最小欧式距：
Figure PCTCN2019092415-appb-000002
Figure PCTCN2019092415-appb-000003
与y j+(N/2)正负相反
Figure PCTCN2019092415-appb-000004
其中，Y 1 N/2表示LLR序列中的前N/2个待译码比特的LLR构成的序列，
Figure PCTCN2019092415-appb-000005
表示LLR序列中的后N/2个待译码比特的LLR构成的序列，
Figure PCTCN2019092415-appb-000006
表示第三序列，
Figure PCTCN2019092415-appb-000007
表示根据i个译码比特和编码矩阵确定的序列，
Figure PCTCN2019092415-appb-000008
表示对LLR序列的前N/2个待译码比特的LLR进行映射处理后的值，y 1+(N/2)，y 2+(N/2)，…y N表示LLR序列的后N/2个待译码比特的LLR；ED i表示最小欧式距，m、M为整数，M小于或等于N/2。
在一种可能的设计中，根据最小欧式距得到i个译码比特的度量值，包括：根据最小欧式距和第一数值的比值得到i个译码比特的度量值，第一数值为N个待译码比特的LLR的绝对值的平均值。
第二方面，本申请提供一种极化码译码装置，该装置具有实现上述第一方面和第一方面的任一种可能的设计中所述的方法的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。
在一个可能的设计中，当所述功能的部分或全部通过硬件实现时，所述译码装置包括：输入接口电路，用于获取待译码比特序列对应的LLR序列；逻辑电路，用于执行上述第一 方面和第一方面的任一种可能的设计中所述的行为；输出接口电路，用于若所述逻辑电路得到译码结果，则输出译码结果。
可选的，所述极化码译码装置可以是芯片或者集成电路。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，所述译码装置包括：存储器，用于存储程序；处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述极化码译码装置可以实现如上述第一方面和第一方面的任一种可能的设计中所述的方法。
可选的，上述存储器可以是物理上独立的单元，也可以与处理器集成在一起。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，所述极化码译码装置包括处理器。用于存储程序的存储器位于所述译码装置之外，处理器通过电路/电线与存储器连接，用于读取并执行所述存储器中存储的程序。
第三方面，本申请实施例提供一种通信系统，该通信系统包括网络设备和终端设备，所述网络设备、所述终端设备均可以执行如上述第一方面或第一方面的任一种可能的设计所述的方法。
第四方面，本申请实施例提供一种计算机存储介质，存储有计算机程序，该计算机程序包括用于执行上述上述第一方面或第一方面的任一种可能的设计所述的方法的指令。
第五方面，提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述上述第一方面或第一方面的任一种可能的设计所述的方法。
附图说明
图1为本申请实施例提供的二叉树结构示意图；
图2为本申请实施例提供的网格结构示意图；
图3为本申请实施例提供的SC译码方法的过程示意图；
图4a为本申请实施例提供的SCL译码方法中的译码路径示意图；
图4b为本申请实施例提供的译码计算过程示意图；
图5为本申请实施例适用的一种网络架构示意图；
图6为本申请实施例提供的一种极化码编译码过程示意图；
图7为盲检测译码流程示意图；
图8为本申请实施例提供的一种极化码译码方法对应的流程示意图；
图9为本申请实施例中所涉及的装置的可能的示例性框图；
图10为本申请实施例提供的一种极化码译码装置的结构示意图；
图11为本申请实施例提供的又一种极化码译码装置的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。其中，方法和装置是基于同一发明构思的，由于方法及装置解决问题的原理相似，因此装置与方法的实施可以相互参考，重复之处不再赘述。
以下，对本申请中的部分用语和极化码的基础知识进行解释说明，以便于本领域技术 人员理解。
1)极化码
极化码是一种在理论上能够被证明“达到”信道容量的信道编码方法。极化码是一种线性块码，其生成矩阵为G N，其编码过程为
Figure PCTCN2019092415-appb-000009
是一个二进制的行矢量，长度为N(即码长)；且
Figure PCTCN2019092415-appb-000010
这里
Figure PCTCN2019092415-appb-000011
B N是一个N×N的转置矩阵，例如比特逆序转置矩阵；其中，B N是可选量，生成矩阵G N的运算过程可以省略B N的运算。
Figure PCTCN2019092415-appb-000012
定义为log 2N个矩阵F 2的克罗内克(Kronecker)乘积，x 1 N是编码后的比特(也叫码字)，
Figure PCTCN2019092415-appb-000013
与生成矩阵G N相乘后就得到编码后的比特，相乘的过程就是编码的过程。在极化码的编码过程中，
Figure PCTCN2019092415-appb-000014
中的一部分比特用来携带信息，称为信息比特，信息比特的索引的集合记作
Figure PCTCN2019092415-appb-000015
Figure PCTCN2019092415-appb-000016
中另外的一部分比特置为收发端预先约定的固定值，称之为固定比特，其索引的集合用
Figure PCTCN2019092415-appb-000017
的补集
Figure PCTCN2019092415-appb-000018
表示。固定比特通常被设为0，只需要收发端预先约定，固定比特序列可以被任意设置。
2)极化码译码
极化码译码是逐层逐节点进行处理，如图1所示的二叉树结构，ν表示层号，每层包括至少一个节点。其中，译码器输入的对数似然比(log likelihood ratio，LLR)序列为二叉树结构中ν＝0层，且为节点0。如在图1中所示，节点0的软比特数据序列为{S 00、S 01、S 02、S 03、S 04、S 05、S 06、S 07}。假设该二叉树结构中节点0、节点1和节点2为非叶子节点，节点3、节点4、节点5和节点6为叶子节点。对节点0做F运算得到节点1的软比特数据，节点1的软比特数据为{S 10、S 11、S 12、S 13}；由于节点1为非叶子节点，对节点1做F运算得到节点3的软比特数据，节点3的软比特数据为{S 20、S 21}；由于节点3为叶子节点，对节点3的软比特数据进行译码得到两个硬比特，根据得到的两个硬比特对节点1做G运算，得到节点4的软比特数据，节点4的软比特数据为{S 22、S 23}；由于节点4为叶子节点，对节点4的软比特数据进行译码得到两个硬比特；根据对节点3、节点4的软比特数据进行译码得到的硬比特，对节点0进行G运算，得到节点2的软比特数据，节点2的软比特数据为{S 14、S 15、S 16、S 17}；由于节点2为非叶子节点，对节点2做F运算得到节点5的软比特数据，节点5的软比特数据为{S 24、S 25}；由于节点5为叶子节点，对节点5的软比特数据进行译码得到两个硬比特，根据得到的两个硬比特对节点2做G运算，得到节点6的软比特数据，节点6的软比特数据为{S 26、S 27}，从而完成译码。
其中，F运算采用简化运算，F运算公式为：
F(a,b)＝sign(a)sign(b)min(|a|,|b|)；
G运算采用简化运算，G运算公式为：
Figure PCTCN2019092415-appb-000019
如图2所示的网格结构，为对图1的二叉树结构中节点之间F/G运算的详细描述。其中，节点之间的实线箭头为F运算，虚线箭头为G运算，两个只向同一位置的箭头组成一对。F/G运算的两个输入a、b，即对应网格结构中两个成对的箭头的源头位置的数据；而箭头所指向的位置存F/G运算的输出。G运算的输入u是与之有共同的a、b输入的F运算的输出位置的译码结果(硬bit、取值0或1)。
3)SC译码方法
根据待译码比特序列对应的LLR序列逐个计算每一个译码比特的LLR，进行逐比特判决。当译码比特为信息比特时，若译码比特的LLR>0，则该译码比特为0，若译码比特的LLR<0，则该译码比特为1；当译码比特为固定比特时，无论LLR为多少译码结果都置为0。图3为SC译码计算过程示意图，以译码比特为4个为例，图3中共有8个计算节点，其中有4个F节点，4个G节点，F节点和G节点分别对应F运算和G运算。F节点的运算需要其右侧2项LLR输入，G节点的运算需要其右侧2项LLR输入以及上一级的输出也作为输入，只有输入项计算完成后，才能计算输出。按照上述计算规则，图3中从右侧开始，按序计算8个节点，获得的译码比特依次为①→②→③→④，至此译码完成。
4)SCL译码方法
根据待译码比特序列对应的LLR序列，在译码每个信息比特时，将0和1对应的译码结果都保存作为2个分支译码路径(简称路径分裂)，图4a为SCL译码方法中的译码路径示意图，如图4a所示，每一层代表1个译码比特，若译码结果为0，则沿着左子树发展路径，若译码结果为1，则沿着右子树发展路径，当译码路径的总数超过预设的路径宽度L(一般L＝4、8、16或32)时，选择出路径度量(path metric，PM)值最佳的L条路径保存并继续发展路径以译出后续的译码比特，其中的PM值用于判断路径的好坏，PM值通过LLR计算得出。对于每一级的译码比特，对L条路径的PM值按照从小到大排序，并通过PM值筛选出正确的路径，如此反复，直到译完最后一个比特。
下面再结合图4b来介绍一下译码运算，如图4b所示，右侧为LLR输入侧，或者称为码字侧；左侧为信息侧，或者称为译码比特侧。y i为待译码信息，u i为译码比特。从译码开始，层级依次为s＝4、s＝3、s＝2、s＝1和s＝0。假设待译码信息的长度N＝16，若采用SCL译码方法，则在s＝4的层级上，待译码信息对应的16个LLR进行F/G运算，得到s＝3的层级上的8个LLR。则s＝3的层级上的8个LLR继续进行F/G运算，得到s＝2的层级上的4个LLR，s＝2的层级上的4个LLR继续进行F/G运算，得到s＝1的层级上的2个LLR，s＝1的层级上的2个LLR继续进行F/G运算，得到s＝0的层级上的1个LLR，在s＝0的层级上逐比特分裂路径。译码开始时，从码字侧读入LLR，并进行概率传递，得到第一个译码比特的LLR值，对LLR值进行判决，得到第一个译码比特的译码结果，第一个译码比特的判决比特值作为第二个译码比特的输入，进行第二个译码比特的计算，直到计算完s＝0层级上的所有译码比特。译码比特中包含固定比特和信息比特，固定比特位置无论LLR为多少判决比特值都为0；信息比特位置的判决比特值可以有0和1两种，因此可以分裂为两个路径。
5)本申请实施例中涉及的第一、第二等各种数字编号仅为描述方便进行的区分，并不用来限制本申请实施例的范围，也不表示先后顺序。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。“至少一个”是指一个或者多个。至少两个是指两个或者多个。“至少一个”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b，或c中的至少一项(个、种)，可以表示：a，b，c，a-b，a-c，b-c，或a-b-c，其中a，b，c可以是单个，也可以是多个。
以下介绍一下本申请实施例适用的网络架构。
图5为本申请实施例适用的一种网络架构示意图。该网络架构可以包括至少一个网络设备100(仅示出1个)以及与网络设备100连接的一个或多个终端设备200。
网络设备100可以是能和终端设备200通信的设备。网络设备100可以是任意一种具有无线收发功能的设备。包括但不限于：基站(例如，基站NodeB、演进型基站eNodeB、第五代(the fifth generation，5G)通信系统中的基站、未来通信系统中的基站或网络设备、WiFi系统中的接入节点、无线中继节点、无线回传节点)等。网络设备100还可以是云无线接入网络(cloud radio access network，CRAN)场景下的无线控制器。网络设备100还可以是小站，传输节点(transmission reference point，TRP)等。当然不申请不限于此。
终端设备200是一种具有无线收发功能的设备可以部署在陆地上，包括室内或室外、手持、穿戴或车载；也可以部署在水面上(如轮船等)；还可以部署在空中(例如飞机、气球和卫星上等)。所述终端设备可以是手机(mobile phone)、平板电脑(Pad)、带无线收发功能的电脑、虚拟现实(Virtual Reality，VR)终端设备、增强现实(Augmented Reality，AR)终端设备、工业控制(industrial control)中的无线终端、无人驾驶(self driving)中的无线终端、远程医疗(remote medical)中的无线终端、智能电网(smart grid)中的无线终端、运输安全(transportation safety)中的无线终端、智慧城市(smart city)中的无线终端、智慧家庭(smart home)中的无线终端等等。本申请的实施例对应用场景不做限定。终端设备有时也可以称为用户设备(user equipment，UE)、接入终端设备、UE单元、UE站、移动站、移动台、远方站、远程终端设备、移动设备、UE终端设备、终端设备、无线通信设备、UE代理或UE装置等。
需要说明的是，上述所示意的网络架构可以适用于各种无线接入技术的通信系统中，例如，5G通信系统以及其它可能的通信系统中。
本申请实施例描述的系统架构以及业务场景是为了更加清楚的说明本申请实施例的技术方案，并不构成对于本申请实施例提供的技术方案的限定，本领域普通技术人员可知，随着通信系统架构的演变和新业务场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
在图5所示意的网络架构中，为对抗信息发送中的干扰，发送端设备(比如网络设备100)可以对信息比特进行编码(比如极化码编码)；相应地，接收端设备(比如终端设备200)可以进行译码(比如极化码译码)以得到信息比特。示例性地，发送端设备和接收端设备通信过程中所涉及的极化码编译码流程如图6所示，包括：步骤601、发送端设备获取编码输入比特序列(a bit sequence input for coding)，编码输入比特序列中可以包括信息比特和固定比特。步骤602、发送端设备进行校验(比如循环冗余校验(cyclic redundancy check，CRC))编码，获得校验编码码字。步骤603、发送端设备对校验编码码字进行交织操作。步骤604、发送端设备对交织操作后的校验编码码字进行极化码编码，得到编码输出比特序列(a bit sequence output for coding)。步骤605，发送端设备将编码输出比特序列映射成调制符号，并通过信道来处理和发送编码输出比特序列。步骤606、接收端设备获取待译码比特序列对应的LLR序列，LLR序列包括多个待译码比特的LLR。步骤与607，接收端设备根据LLR序列进行极化码译码。步骤608、接收端设备对译码后的序列进行解交织操作。步骤609，接收端设备通过CRC校验判断译码结果是否译码成功。需要说明的是，图6仅是一种简单示例，具体实施中，还可以在图6的基础上增加其它可能的步骤，比如无线网络临时标识(radio network tempory identity，RNTI)加扰、速率匹配、解扰、解速率匹配等，具体不做限定。
以5G通信系统为例，网络设备100和终端设备200之间除了数据本身的交互外，还 有指令的交互(比如网络设备100通过物理下行控制信道(physical downlink control channel，PDCCH)向终端设备200发送指令)，网络设备100通过指令完成对终端设备200的调度，以及传递调度的格式信息。为了降低指令交互的开销，网络设备100常常不发送或者少发送某些调度信令，而由终端设备200按照一定规则自行监听是否存在调度。在监听过程中，终端设备200需要在不知道确切格式的情况下做盲检测译码。
盲检测译码流程大多如图7所示，首先列出所有可能的译码参数，根据译码参数和待译码比特序列对应的LLR序列(解调软值)组合成的每一种假设作为一个候选集(candidate)来译码，译码结果通过校验(比如CRC)来判断对错，持续这个过程直到搜索到正确的译码结果或遍历全部集合或达到某个预设条件。在一般的盲检测假设中，可能有44个候选集。也就是说，盲检配置的次数最大为44次，即最多需要44次完整的译码流程。
若采用极化码译码方法(比如SCL译码方法)进行盲检测译码，则只有译出所有信息比特后才能判别当前译码结果是否有效。如此，在码长较长的情况下，译码复杂度较高，译码的时延也会相应延长，从而导致难以满足对信号的时延要求比较严格的场景(比如URLLC场景)。
基于此，本申请实施例提供一种极化码译码方法，用于降低极化码译码的复杂度、进而降低译码时延。
本申请实施例提供的极化码译码方法可以由接收端设备执行，其中，接收端设备可以为图5中所示意的网络设备100，或者也可以为图5中所示意的终端设备200。示例性地，当应用于盲检测译码场景中时，本申请实施例提供的译码方法可以由终端设备200来执行。
以下简单介绍本申请实施例的基本思想。
假设待译码比特序列的长度为N，N也可认为是极化码母码长度，根据待译码比特序列对应的LLR序列对待译码比特序列进行译码获得译码结果(即译码比特序列)。收发端预先约定了固定比特的位置，固定比特通常设为0，通过译码过程实际上需要获得信息比特的内容。实际应用中，N的数目可能会很大。若采用现有SCL译码方法，则：LLR序列对应的长度为N的LLR向量经过多个层级的F/G运算，到达最后一个层级，对最后一个层级的LLR进行比特判决，得到一个译码比特，采用逐比特分裂路径，在路径数量大于L时，根据PM值选择最优的L条路径，并继续分裂路径，直到译完最后一个比特，计算复杂度和时延非常高。本申请实施例可以在得到i(i<N)个译码比特时，计算i个译码比特的度量值，并根据度量值来判别是否提前终止该次译码，在度量值大于或等于预设阈值时，可以提前终止译码，从而能够减少不必要的功耗和时延；并且，通过这种方式，在盲检测场景中能够提前筛选掉大部分不需要的候选集，降低译码复杂度；进一步地，由于提前终止了该次译码，能够有效降低译码过程中可能出现的虚警，从而能够达到降低虚警概率的目的。
以下具体介绍本申请实施例提供的极化码译码方法。
图8为本申请实施例提供的译码方法所对应的流程示意图。如图8所示，该方法包括：
步骤801，获取待译码比特序列对应的LLR序列，LLR序列包括N个待译码比特的LLR。
此处，N为极化码母码的长度；若发送端设备在发送比特序列时未进行速率匹配，则 接收端设备可以从发送端接收N个待译码比特；若发送端设备在发送比特序列时进行了速率匹配，则接收端设备可以从发送端设备接收N’(N’可以为小于N的数值，具体不做限定)个待译码比特，并根据N’个待译码比特进行解速率匹配，得到N个待译码比特。
进一步地，接收端设备可以根据信道的噪声方差，计算得到N个待译码比特的LLR。在一个示例中，可以通过如下公式计算待译码比特的LLR：
Figure PCTCN2019092415-appb-000020
其中，t表示待译码比特，LLR(t)表示待译码比特的LLR，p(t|0)表示待译码比特取值为0的概率，p(t|1)表示待译码比特取值为1的概率，σ表示信道的噪声方差。
举个例子，N＝4，N个待译码比特分别为t 1、t 2、t 3、t 4，N个待译码比特的LLR分别为：LLR(t 1)＝1.5、LLR(t 2)＝2、LLR(t 3)＝-1、LLR(t 3)＝-3。如此可得LLR序列为[1.5、2、-1、-3]。
步骤802，根据LLR序列对待译码比特序列进行译码，得到待译码比特序列中的前i个待译码比特分别对应的i个译码比特。示例性地，可以采用SCL译码方法(比如SCL8译码方法)对待译码比特序列进行译码。
步骤803，确定LLR序列与K个第一序列的K个欧式距中的最小欧式距，并根据最小欧式距得到i个译码比特的度量值。
步骤804，根据度量值确定是否对终止对待译码比特序列进行译码。
示例性地，i个译码比特的度量值可以是根据LLR序列与K个第一序列的K个欧式距中的最小欧式距得到的，其中，K个第一序列是基于K个候选译码比特序列得到的，所述K个候选译码比特序列基于所述i个译码比特中的部分译码比特或全部译码比特得到的。比如，LLR序列与K个第一序列的K个欧式距中的最小欧式距是LLR序列与第一序列a的欧式距，此种情形下，由于i个译码比特的度量值是基于LLR序列与第一序列a的欧式距得到的，因此，i个译码比特的度量值能够指示出LLR序列与第一序列a的接近程度。
根据图6中所示意的编译码流程可以看出，接收端设备所执行的译码过程实际为发送端设备所执行的编码过程的逆过程，编码过程是基于编码输入比特序列得到编码输出比特序列，而译码过程是基于LLR序列得到译码比特序列。若译码结果完全准确，则译码比特序列即为发送端设备的编码输入比特序列，进一步地，基于译码比特序列和编码矩阵得到的第二序列即为发送端设备编码得到的编码输出比特序列，进而对第二序列进行翻转处理得到第一序列与LLR序列之间的接近程度较高(比如在理论上二者可以完全相同)；若译码结果不够准确，则译码比特序列与发送端设备的编码输入比特序列会存在差异，进一步地，基于译码比特序列和编码矩阵得到的第二序列与发送端设备编码得到的编码输出比特序列也会存在差异，进而对第二序列进行翻转处理得到第一序列与LLR序列之间的接近程度较低。
沿用上述示例，由于第一序列a为K个第一序列中最接近LLR序列的序列；进一步地，若最接近LLR序列的第一序列a与LLR之间的接近程度越高，则对待译码比特序列继续译码得到的译码结果的准确率越高，若第一序列a与LLR之间的接近程度越低，则对待译码比特序列继续译码得到的译码结果的准确率越低。由于i个译码比特的度量值能够指示出LLR序列与第一序列a的接近程度，比如i个译码比特的度量值越小，则LLR序 列与第一序列a的接近程度越高(也即译码的准确率较高)，i个译码比特的度量值越大，则LLR序列与第一序列a的接近程度越低(也即译码的准确率较低)，因此，基于i个译码比特的度量值，当度量值大于预设阈值时，说明译码的准确率较低(比如可能是由于基于LLR序列进行译码时所依据的译码参数不准确而导致译码的准确率较低)，此时可以提前终止该次译码，从而能够减少不必要的功耗和时延。
示例性地，基于LLR序列进行译码时所依据的译码参数不准确可以理解为：以盲检测场景为例，举个例子，若N个待译码比特中信息比特的数量为N1，而基于LLR序列进行译码时所依据的译码参数中信息比特的数量为N2(N2不等于N1)，此时，可以理解为基于LLR序列进行译码时所依据的译码参数不准确。应理解，译码参数还可以包括其它可能的信息，因此，基于LLR序列进行译码时所依据的译码参数不准确的情形也可以有多种，此处仅为便于理解而列出一种可能的简单示例。
下面对LLR序列与K个第一序列的K个欧式距中的最小欧式距进行详细说明。
首先对i的取值进行说明：本申请实施例中，i的取值可以为小于N的任一数值，具体不做限定，比如i＝2 q，q为整数。考虑到若i的取值较小，比如远小于N，则说明译码比特的个数较少，从而导致计算最小欧式距的复杂度可能较高，若i的取值较大，比如接近N，则说明已经译码得到较多的译码比特，即便确定提前终止该次译码，也可能导致降低时延和降低虚警概率的效果不够明显。因此，i的取值可以为接近N/2(比如i＝N/2)的数值，从而能够有效降低时延和降低虚警概率。
在一个示例中，当i<N/2时，K个候选译码比特序列可以是基于i个译码比特中的全部译码比特得到的，此时K＝2 N-i；由于i<N/2，即译码比特的个数较少，此时为保证计算得到的最小欧式距的准确性，可以依据i个译码比特中的全部译码比特。当i≥N/2时，K个候选译码比特序列可以是基于i个译码比特中的前N/2个译码比特得到的，此时K＝2 N/2，从而当i≥N/2时，通过设置K＝2 N/2能够有效降低计算量和处理的复杂度。
本申请实施例中，确定最小欧式距的实现方式可以有多种，下面具体描述两种可能的实现方式。
实现方式1
在该实现方式中，可以根据i个译码比特得到待译码比特序列对应的K个候选译码比特序列；其中，K个候选译码比特序列中包括第一候选译码比特序列，针对第一候选译码比特序列执行：根据第一候选译码比特序列和编码矩阵得到第二序列，对第二序列进行翻转处理得到第一候选译码比特序列对应的第一序列；计算LLR序列与第一候选译码比特序列对应的第一序列的欧式距；进而，根据LLR序列与K个候选译码比特序列对应的K个第一序列的K个欧式距可以得到最小欧式距。
举个例子，i＝2，i个译码比特的取值为[0、0]，而剩余的N-i个译码比特的取值共有4种可能，如此可以得到4(K＝2 N-i＝4)个的候选译码比特序列，即候选译码比特序列1为[0、0、0、0]、候选译码比特序列2为[0、0、0、1]、候选译码比特序列3为[0、0、1、0]、候选译码比特序列4为[0、0、1、1]。
根据候选译码比特序列1和编码矩阵，可以得到候选译码比特序列1对应的第二序列1为[0、0、0、0]；根据候选译码比特序列2和编码矩阵，可以得到候选译码比特序列2对应的第二序列2为[1、1、1、1]；根据候选译码比特序列3和编码矩阵，可以得到候选译码比特序列3对应的第二序列3为[1、0、1、0]；根据候选译码比特序列4和编码矩阵， 可以得到候选译码比特序列3对应的第二序列4为[0、1、0、1]。
针对于第二序列1，对第二序列1进行翻转处理，可得到第二序列1对应的第一序列序列1为[1、1、1、1]；进而计算[1、1、1、1]与[1.5、2、-1、-3]的欧式距。本申请实施例中，计算[1、1、1、1]与[1.5、2、-1、-3]的欧式距的具体方式可以有多种，一种可能的方式(本申请实施例中主要以此方式为例进行描述)为，比如可以比较两个序列中对应位置的数值是否正负一致，确定出数值不一致的p个位置(即第三个位置和第四个位置)，进而将LLR序列中p个位置上的数值的绝对值进行相加，得到欧式距，即ED1＝1+3＝4。或者，也可以参照欧式距离的计算公式来计算，示例性地，可以将[1、1、1、1]理解为四维空间中的一个位置点(称为位置点1)，将[1.5、2、-1、-3]理解为四维空间中的另一个位置点(称为位置点2)，进而根据欧式距离的计算公式计算位置点1和位置点2之间的欧式距，该欧式距即为第一序列序列1与LLR序列之间的欧式距。
示例性地，将第二序列1表示C，第一序列1表示为X，则翻转处理可以理解为X＝1-2C。
针对于第二序列2，对第二序列2进行翻转处理，可得到第一序列2为[-1、-1、-1、-1]；进而计算[-1、-1、-1、-1]与[1.5、2、-1、-3]的欧式距，由于两个序列中第一个位置和第二个位置上数值的正负不同，故可得到ED2＝1.5+2＝3.5。
针对于第二序列3，对第二序列3进行翻转处理，可得到第一序列3为[-1、1、-1、1]；进而计算[-1、1、-1、1]与[1.5、2、-1、-3]的欧式距，由于两个序列中第一个位置和第四个位置上数值的正负不同，故可得到ED3＝1.5+3＝4.5。
针对于第二序列4，对第二序列4进行翻转处理，可得到第一序列4为[1、-1、1、-1]；进而计算[1、-1、1、-1]与[1.5、2、-1、-3]的欧式距，由于两个序列中第二个位置和第三个位置上数值的正负不同，故可得到ED4＝2+1＝3。
根据上述4个欧式距(ED1＝4、ED2＝3.5、ED3＝4.5、ED4＝3)，可得到最小欧式距为3。
实现方式2
在该实现方式中，可以对LLR序列中的前N/2个待译码比特的LLR构成的序列进行映射处理，得到第三序列，进而根据第三序列和第四序列所包括的对应位置上的数值之间的差异，得到最小欧式距；其中，第四序列包括LLR序列中的后N/2个待译码比特的LLR。
下面针对该实现方式的一种可能的理论推导过程进行描述。
在一个示例中，基于编码矩阵的递归形式，可以得到如下内容：
Figure PCTCN2019092415-appb-000021
其中，G N表示编码矩阵，
Figure PCTCN2019092415-appb-000022
表示编码输出比特序列(可以理解为发送端设备生成的编码输出比特序列)，
Figure PCTCN2019092415-appb-000023
表示编码输出比特序列中的前N/2个比特构成的序列，
Figure PCTCN2019092415-appb-000024
表示编码输出比特序列中的后N/2个比特构成的序列；
Figure PCTCN2019092415-appb-000025
表示编码输入比特序列，
Figure PCTCN2019092415-appb-000026
表示编码输入比特序列中的前N/2个比特构成的序列，
Figure PCTCN2019092415-appb-000027
表示编码输入比特序列中的后N/2个比特构成的序列。
上述公式3中，
Figure PCTCN2019092415-appb-000028
因此，从LLR序列的角度来看，在译码的准确率较高的情况下，存在
Figure PCTCN2019092415-appb-000029
趋向于
Figure PCTCN2019092415-appb-000030
其中，由于公式3中对
Figure PCTCN2019092415-appb-000031
进行映射处理(即
Figure PCTCN2019092415-appb-000032
)，因此也需对Y 1 N/2进行映射处理(即
Figure PCTCN2019092415-appb-000033
)。同样地，由于上述公式3中，
Figure PCTCN2019092415-appb-000034
因此，从LLR序列的角度来看，在译码的准确率较高的情况下，存在
Figure PCTCN2019092415-appb-000035
趋向于
Figure PCTCN2019092415-appb-000036
可以表示为：
Figure PCTCN2019092415-appb-000037
其中，Y 1 N/2表示LLR序列中的前N/2个待译码比特的LLR构成的序列，
Figure PCTCN2019092415-appb-000038
表示LLR序列中的后N/2个待译码比特的LLR构成的序列，
Figure PCTCN2019092415-appb-000039
表示对Y 1 N/2进行映射处理得到的第三序列，
Figure PCTCN2019092415-appb-000040
表示根据N/2个译码比特得到的比特序列。进一步地，
Figure PCTCN2019092415-appb-000041
Figure PCTCN2019092415-appb-000042
为N/2个译码比特构成的序列。
进而根据公式4，可以得知，在译码的准确率较高的情况下，
Figure PCTCN2019092415-appb-000043
与
Figure PCTCN2019092415-appb-000044
的接近程度较高，因此，可以根据
Figure PCTCN2019092415-appb-000045
与
Figure PCTCN2019092415-appb-000046
的接近程度来确定最小欧式距。
示例性地，基于译码得到的N/2个译码比特，可以通过如下公式确定最小欧式距：
Figure PCTCN2019092415-appb-000047
Figure PCTCN2019092415-appb-000048
Figure PCTCN2019092415-appb-000049
与y j+(N/2)正负相反……公式4
其中，ED i表示最小欧式距，
Figure PCTCN2019092415-appb-000050
表示对LLR序列的前N/2个待译码比特的LLR进行映射处理后的值，y 1+(N/2)，y 2+(N/2)，…y N表示对LLR序列的后N/2个待译码比特的LLR，m、M为整数。
举个例子，沿用上述示例，LLR序列为[1.5、2、-1、-3]，
Figure PCTCN2019092415-appb-000051
为[1.5、2]，y j+(N/2)为[-1、-3]，进而可得R i＝1+2＝3。可以看出该结果与采用上述实现方式1中所得的最小欧式距的结果一致。
示例性地，考虑到在
Figure PCTCN2019092415-appb-000052
为G运算的输入，也就是说，本申请实施例中在计算最小欧式距时，可以直接从译码过程的临时变量中获取
Figure PCTCN2019092415-appb-000053
从而能够极大地降低计算的复杂度。
基于上文中的介绍可知，当i≥N/2时，均可以基于于i个译码比特中的前N/2个译码比特来计算最小欧式距，从而能够有效降低处理的复杂度。
需要说明的是，上述实现方式2是以基于译码得到的N/2个译码比特确定最小欧式距为例进行描述的，在其它可能的实施例中，i也可以取小于N/2的值，此种情形下，可以基于上述公式3、公式4和公式5的思路进行处理，比如可以基于编码矩阵的递归形式，对编码输出比特序列进行更小粒度的划分(上述公式3中是将编码输出比特序列划分为
Figure PCTCN2019092415-appb-000054
和
Figure PCTCN2019092415-appb-000055
两个序列)，比如，将编码输出比特序列划分为四个序列或八个序列等，从而也可以基于推导确定出最小欧式距。
示例性地，根据最小欧式距得到i个译码比特的度量值的实现方式可以有多种。在一种可能的实现方式中，可以根据最小欧式距和第一数值的比值得到i个译码比特的度量值，其中，第一数值为N个待译码比特的LLR的绝对值的平均值。参见下述公式：
Figure PCTCN2019092415-appb-000056
其中，R i表示i个译码比特的度量值，ED i表示最小欧式距，|LLR(t)| ave表示第一数值。在上述示例，LLR序列为[1.5、2、-1、-3]时，|LLR(t)| ave＝(1.5+2+1+3)/4＝1.875。
经理论推导可知：R i＝Rate(σ)，Rate(σ)表示噪声方差的单调递增函数，即方差越大，Rate(σ)越接近于0.5。也就是说，如果N个待译码比特是正常过加性高斯白噪声(additive white gaussian noise，AWGN)信道的信号，则当干扰越小时，Rate(σ)越小；若N个待译码比特是纯噪声信号，则Rate(σ)趋向于0.5。需要说明的是，当基于LLR序列进行译码时所依据的译码参数不准确时，N个待译码比特可以理解为纯噪声信号，也就是说，若基于LLR序列进行译码时所依据的译码参数不准确，则Rate(σ)趋向于0.5。
基于此，本申请实施例中，预设阈值可以为小于0.5的某一数值，比如预设阈值可以为0.2，具体实施中，可以由本领域技术根据实际需要来设置预设阈值，具体不做限定。
在一个示例中，若i个译码比特的度量值大于或等于预设阈值，则可以终止对待译码比特序列进行译码，比如在盲检测场景中，终止此次译码后，可以依据其它译码参数进行下一次译码，以得到译码结果并输出；若小于预设阈值，则可以继续对待译码比特序列进行译码，以得到译码结果并输出。如此，通过上述实现方式1或实现方式2确定出i个译码比特的度量值，可以判断其是否大于或等于预设阈值(假设为0.2)，比如上述示例中，i个译码比特的度量值为3/1.875＝1.6，其大于0.2，说明此次译码的译码参数不准确，故可以终止进行译码。需要说明的是，由于上述示例中的数值为随机选取的数值，故计算得到的i个译码比特的度量值大于0.5，从理论上来看，当译码参数不准确时，i个译码比特的度量值可能为趋近于0.5的数值，但若i个译码比特的度量值大于0.5，同样能够说明译码参数不准确，并不影响本申请实施例的实现。
可以理解的是，为了实现上述功能，极化码译码装置可以包括执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，本申请的实施例能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
在采用集成的单元(模块)的情况下，图9示出了本申请实施例中所涉及的装置的可能的示例性框图，该装置900可以以软件的形式存在。装置900可以包括：
获取模块901，用于获取待译码比特序列对应的对数似然比LLR序列，所述LLR序列包括所述待译码比特序列中的N个待译码比特的对数似然比LLR；
译码模块902，用于根据所述LLR序列，对所述待译码比特序列进行译码，得到所述待译码比特序列中的前i个待译码比特分别对应的i个译码比特；确定所述LLR序列与K个第一序列的K个欧式距，中的最小欧式距，并根据所述最小欧式距得到所述i个译码比特的度量值；所述K个第一序列是基于K个候选译码比特序列得到的，所述K个候选译码比特序列基于所述i个译码比特中的部分译码比特或全部译码比特得到的；以及，根据所述度量值确定是否对终止对所述待译码比特序列进行译码；
其中，i、N、K均为正整数，i<N。
在一种可能的设计中，所述译码模块902具体用于：若所述度量值大于或等于预设阈值，则终止对所述待译码比特序列进行译码；和/或，若所述度量值小于所述预设阈值，则继续对所述待译码比特序列进行译码。
在一种可能的设计中，当i<N/2时，所述K个候选译码比特序列是基于所述i个译码比特中的全部译码比特得到的，K＝2 N-i；当i≥N/2时，所述K个候选译码比特序列是基于所述i个译码比特中的前N/2个译码比特得到的，K＝2 N/2。
在一种可能的设计中，所述译码模块902具体用于：
根据所述i个译码比特，得到所述待译码比特序列对应的K个候选译码比特序列；所述K个候选译码比特序列中包括第一候选译码比特序列，针对所述第一候选译码比特序列执行：根据所述第一候选译码比特序列和编码矩阵得到第二序列，对所述第二序列进行翻转处理得到所述第一候选译码比特序列对应的第一序列；计算所述LLR序列与所述第一候选译码比特序列对应的第一序列的欧式距；根据所述LLR序列与所述K个候选译码比特序列对应的K个第一序列的K个欧式距，得到所述最小欧式距。
在一种可能的设计中，i≥N/2；所述译码模块902具体用于：对所述LLR序列中的前N/2个待译码比特的LLR构成的序列进行映射处理，得到第三序列；根据所述第三序列和第四序列所包括的对应位置上的数值之间的差异，得到所述最小欧式距；所述第四序列包括所述LLR序列中的后N/2个待译码比特的LLR。
在一种可能的设计中，译码模块902具体用于：
通过如下公式得到所述第三序列：
Figure PCTCN2019092415-appb-000057
通过如下公式得到所述最小欧式距：
Figure PCTCN2019092415-appb-000058
Figure PCTCN2019092415-appb-000059
与y j+(N/2)正负相反
Figure PCTCN2019092415-appb-000060
其中，Y 1 N/2表示所述LLR序列中的前N/2个待译码比特的LLR构成的序列，
Figure PCTCN2019092415-appb-000061
表示所述LLR序列中的后N/2个待译码比特的LLR构成的序列，
Figure PCTCN2019092415-appb-000062
表示所述第三序列，
Figure PCTCN2019092415-appb-000063
表示根据所述i个译码比特和编码矩阵确定的序列，
Figure PCTCN2019092415-appb-000064
表示对所述LLR序列的前N/2个待译码比特的LLR进行映射处理后的值，y 1+(N/2)，y 2+(N/2)，…y N表示所述LLR序列的后N/2个待译码比特的LLR；ED i表示所述最小欧式距，m、M为整数，M小于或等于N/2。
在一种可能的设计中，所述译码模块902具体用于：根据所述最小欧式距和第一数值 的比值得到所述i个译码比特的度量值，所述第一数值为所述N个待译码比特的LLR的绝对值的平均值。
需要说明的是，本申请实施例中图9所示的极化码译码装置对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
如图10所示，本申请实施例中还提供一种极化码译码装置1000，该极化码译码装置1000用于执行图8所示的极化码译码方法。图8所示的极化码译码方法中的部分或全部可以通过硬件来实现也可以通过软件来实现，当通过硬件实现时，极化码译码装置1000包括：输入接口电路1001，用于获取待译码比特序列对应的LLR序列；逻辑电路1002，用于执行图8所示的极化码译码方法；输出接口电路1003，用于若所述逻辑电路得到译码结果，则输出译码结果。
可选的，极化码译码装置1000在具体实现时可以是芯片或者集成电路。
可选的，当图8所示的极化码译码方法中的部分或全部通过软件来实现时，如图11所示，极化码译码装置1100包括：存储器1101，用于存储程序；处理器1102，用于执行存储器1101存储的程序，当程序被执行时，使得极化码译码装置1100可以实现图8所示的极化码译码方法。
可选的，上述存储器1101可以是物理上独立的单元，也可以与处理器1102集成在一起。
可选的，当图8所示的极化码译码方法中的部分或全部通过软件实现时，极化码译码装置1100也可以只包括处理器1102。用于存储程序的存储器1101位于极化码译码装置1100之外，处理器1102通过电路/电线与存储器1101连接，用于读取并执行存储器1101中存储的程序。
处理器1102可以是中央处理器(central processing unit，CPU)，网络处理器(network processor，NP)或者CPU和NP的组合。
处理器1102还可以进一步包括硬件芯片。上述硬件芯片可以是专用集成电路(application-specific integrated circuit，ASIC)，可编程逻辑器件(programmable logic device，PLD)或其组合。上述PLD可以是复杂可编程逻辑器件(complex programmable logic device，CPLD)，现场可编程逻辑门阵列(field-programmable gate array，FPGA)，通用阵列逻辑(generic array logic,GAL)或其任意组合。
存储器1101可以包括易失性存储器(volatile memory)，例如随机存取存储器(random-access memory，RAM)；存储器1101也可以包括非易失性存储器(non-volatile memory)，例如快闪存储器(flash memory)，硬盘(hard disk drive，HDD)或固态硬盘(solid-state drive，SSD)；存储器1101还可以包括上述种类的存储器的组合。
本申请实施例还提供一种计算机存储介质，存储有计算机程序，该计算机程序包括用于执行上述方法实施例提供的极化码译码方法。
本申请实施例还提供一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述方法实施例提供的极化码译码方法。
本申请实施例提供的任一种极化码译码装置还可以是一种芯片。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的精神和范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (21)

  1. 一种极化码译码方法，其特征在于，所述方法包括：
    获取待译码比特序列对应的对数似然比LLR序列，所述LLR序列包括所述待译码比特序列中的N个待译码比特的LLR；
    根据所述LLR序列，对所述待译码比特序列进行译码，得到所述待译码比特序列中的前i个待译码比特分别对应的i个译码比特；
    确定所述LLR序列与K个第一序列的K个欧式距中的最小欧式距，并根据所述最小欧式距得到所述i个译码比特的度量值；所述K个第一序列是基于K个候选译码比特序列得到的，所述K个候选译码比特序列基于所述i个译码比特中的部分译码比特或全部译码比特得到的；
    根据所述度量值确定是否对终止对所述待译码比特序列进行译码；
    其中，i、N、K均为正整数，i<N。
  2. 根据权利要求1所述的方法，其特征在于，根据所述度量值确定是否对终止对所述待译码比特序列进行译码，包括：
    若所述度量值大于或等于预设阈值，则终止对所述待译码比特序列进行译码；
    若所述度量值小于所述预设阈值，则继续对所述待译码比特序列进行译码。
  3. 根据权利要求1或2所述的方法，其特征在于：
    当i<N/2时，所述K个候选译码比特序列是基于所述i个译码比特中的全部译码比特得到的，K＝2 N-i；
    当i≥N/2时，所述K个候选译码比特序列是基于所述i个译码比特中的前N/2个译码比特得到的，K＝2 N/2。
  4. 根据权利要求1至3中任一项所述的方法，其特征在于，确定所述LLR序列与K个第一序列的K个欧式距中的最小欧式距，包括：
    根据所述i个译码比特，得到所述待译码比特序列对应的K个候选译码比特序列；
    所述K个候选译码比特序列中包括第一候选译码比特序列，针对所述第一候选译码比特序列执行：根据所述第一候选译码比特序列和编码矩阵得到第二序列，对所述第二序列进行翻转处理得到所述第一候选译码比特序列对应的第一序列；计算所述LLR序列与所述第一候选译码比特序列对应的第一序列的欧式距；
    根据所述LLR序列与所述K个候选译码比特序列对应的K个第一序列的K个欧式距，得到所述最小欧式距。
  5. 根据权利要求1至3中任一项所述的方法，其特征在于，i≥N/2；
    所述确定所述LLR序列与K个第一序列的K个欧式距中的最小欧式距，包括：
    对所述LLR序列中的前N/2个待译码比特的LLR构成的序列进行映射处理，得到第三序列；
    根据所述第三序列和第四序列所包括的对应位置上的数值之间的差异，得到所述最小欧式距；所述第四序列包括所述LLR序列中的后N/2个待译码比特的LLR。
  6. 根据权利要求5所述的方法，其特征在于，通过如下公式得到所述第三序列：
    Figure PCTCN2019092415-appb-100001
    通过如下公式得到所述最小欧式距：
    Figure PCTCN2019092415-appb-100002
    与y j+(N/2)正负相反
    Figure PCTCN2019092415-appb-100003
    其中，Y 1 N/2表示所述LLR序列中的前N/2个待译码比特的LLR构成的序列，
    Figure PCTCN2019092415-appb-100004
    表示所述LLR序列中的后N/2个待译码比特的LLR构成的序列，
    Figure PCTCN2019092415-appb-100005
    表示所述第三序列，
    Figure PCTCN2019092415-appb-100006
    表示根据所述i个译码比特和编码矩阵确定的序列，
    Figure PCTCN2019092415-appb-100007
    表示对所述LLR序列的前N/2个待译码比特的LLR进行映射处理后的值，y 1+(N/2)，y 2+(N/2)，…y N表示所述LLR序列的后N/2个待译码比特的LLR；ED i表示所述最小欧式距，m、M为整数，M小于或等于N/2。
  7. 根据权利要求1至6中任一项所述的方法，其特征在于，根据所述最小欧式距得到所述i个译码比特的度量值，包括：
    根据所述最小欧式距和第一数值的比值得到所述i个译码比特的度量值，所述第一数值为所述N个待译码比特的LLR的绝对值的平均值。
  8. 一种极化码译码装置，其特征在于，所述装置包括：
    获取模块，用于获取待译码比特序列对应的LLR序列，所述LLR序列包括所述待译码比特序列中的N个待译码比特的LLR；
    译码模块，用于根据所述LLR序列，对所述待译码比特序列进行译码，得到所述待译码比特序列中的前i个待译码比特分别对应的i个译码比特；确定所述LLR序列与K个第一序列的K个欧式距，中的最小欧式距，并根据所述最小欧式距得到所述i个译码比特的度量值；所述K个第一序列是基于K个候选译码比特序列得到的，所述K个候选译码比特序列基于所述i个译码比特中的部分译码比特或全部译码比特得到的；以及，根据所述度量值确定是否对终止对所述待译码比特序列进行译码；
    其中，i、N、K均为正整数，i<N。
  9. 根据权利要求8所述的装置，其特征在于，所述译码模块具体用于：
    若所述度量值大于或等于预设阈值，则终止对所述待译码比特序列进行译码；和/或，
    若所述度量值小于所述预设阈值，则继续对所述待译码比特序列进行译码。
  10. 根据权利要求8或9所述的装置，其特征在于：
    当i<N/2时，所述K个候选译码比特序列是基于所述i个译码比特中的全部译码比特得到的，K＝2 N-i；
    当i≥N/2时，所述K个候选译码比特序列是基于所述i个译码比特中的前N/2个译码比特得到的，K＝2 N/2。
  11. 根据权利要求8至10中任一项所述的装置，其特征在于，所述译码模块具体用于：
    根据所述i个译码比特，得到所述待译码比特序列对应的K个候选译码比特序列；
    所述K个候选译码比特序列中包括第一候选译码比特序列，针对所述第一候选译码比特序列执行：根据所述第一候选译码比特序列和编码矩阵得到第二序列，对所述第二序列进行翻转处理得到所述第一候选译码比特序列对应的第一序列；计算所述LLR序列与所述第一候选译码比特序列对应的第一序列的欧式距；
    根据所述LLR序列与所述K个候选译码比特序列对应的K个第一序列的K个欧式距， 得到所述最小欧式距。
  12. 根据权利要求8至10中任一项所述的装置，其特征在于，i≥N/2；
    所述译码模块具体用于：
    对所述LLR序列中的前N/2个待译码比特的LLR构成的序列进行映射处理，得到第三序列；
    根据所述第三序列和第四序列所包括的对应位置上的数值之间的差异，得到所述最小欧式距；所述第四序列包括所述LLR序列中的后N/2个待译码比特的LLR。
  13. 根据权利要求12所述的装置，其特征在于，通过如下公式得到所述第三序列：
    Figure PCTCN2019092415-appb-100008
    通过如下公式得到所述最小欧式距：
    Figure PCTCN2019092415-appb-100009
    与y j+(N/2)正负相反
    Figure PCTCN2019092415-appb-100010
    其中，Y 1 N/2表示所述LLR序列中的前N/2个待译码比特的LLR构成的序列，
    Figure PCTCN2019092415-appb-100011
    表示所述LLR序列中的后N/2个待译码比特的LLR构成的序列，
    Figure PCTCN2019092415-appb-100012
    表示所述第三序列，
    Figure PCTCN2019092415-appb-100013
    表示根据所述i个译码比特和编码矩阵确定的序列，
    Figure PCTCN2019092415-appb-100014
    表示对所述LLR序列的前N/2个待译码比特的LLR进行映射处理后的值，y 1+(N/2)，y 2+(N/2)，…y N表示所述LLR序列的后N/2个待译码比特的LLR；ED i表示所述最小欧式距，m、M为整数，M小于或等于N/2。
  14. 根据权利要求8至13中任一项所述的装置，其特征在于，所述译码模块具体用于：
    根据所述最小欧式距和第一数值的比值得到所述i个译码比特的度量值，所述第一数值为所述N个待译码比特的LLR的绝对值的平均值。
  15. 一种极化码译码装置，其特征在于，包括：
    存储器，用于存储程序；
    处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于执行如权利要求1～7任一项所述的方法。
  16. 根据权利要求15所述的装置，其特征在于，所述极化码译码装置为芯片或集成电路。
  17. 一种极化码译码装置，其特征在于，包括：
    输入接口电路，用于获取待译码比特序列对应的LLR序列；
    逻辑电路，用于基于获取的LLR序列执行所述权利要求1～7任一项所述的方法；
    输出接口电路，用于若所述逻辑电路得到译码结果，则输出所述译码结果。
  18. 一种芯片，其特征在于，包括：
    存储器，用于存储程序；
    处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于执行如权利要求1～7任一项所述的方法。
  19. 一种芯片，其特征在于，包括：
    输入接口电路，用于获取待译码比特序列对应的LLR序列；
    逻辑电路，用于基于获取的LLR序列执行所述权利要求1～7任一项所述的方法；
    输出接口电路，用于若所述逻辑电路得到译码结果，则输出译码结果。
  20. 一种计算机可读存储介质，其特征在于，所述计算机存储介质中存储有计算机可读指令，当计算机读取并执行所述计算机可读指令时，使得计算机执行如权利要求1～7任意一项所述的方法。
  21. 一种计算机程序产品，其特征在于，当计算机读取并执行所述计算机程序产品时，使得计算机执行如权利要求1～7任意一项所述的方法。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113872613A (zh) * 2021-09-30 2021-12-31 广州慧睿思通科技股份有限公司 极化码译码中g函数的计算方法、装置、电子设备及介质
CN116073948A (zh) * 2021-11-04 2023-05-05 Oppo广东移动通信有限公司 译码方法及装置、终端设备、芯片、存储介质

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114499548B (zh) * 2022-04-02 2022-07-05 哲库科技(北京)有限公司 一种译码方法、装置及存储介质
CN117200934A (zh) * 2022-05-27 2023-12-08 华为技术有限公司 一种通信方法及装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101425869A (zh) * 2007-11-02 2009-05-06 华为技术有限公司 一种译码方法及装置
US20140177740A1 (en) * 2012-10-10 2014-06-26 Texas Instruments Incorporated Hexagonal constellations and decoding same in digital communication systems
CN107204779A (zh) * 2013-12-24 2017-09-26 华为技术有限公司 极性码的编码方法和编码装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2310186A1 (en) * 2000-06-02 2001-12-02 Jeffrey P. Castura Method and system for decoding
US10153811B2 (en) * 2012-06-14 2018-12-11 Samsung Electronics Co., Ltd. Communication system with communication-layer maximization mechanism and method of operation thereof
JP2014165646A (ja) * 2013-02-25 2014-09-08 Yokohama National Univ Ｍｉｍｏシステムにおける信号分離方法および受信装置
CN106130690A (zh) * 2016-06-21 2016-11-16 东南大学 结合极化码的mimo系统联合检测译码方法
GB201712840D0 (en) * 2017-08-10 2017-09-27 Univ Surrey Apparatus and method for detecting mutually interfering information streams
CN107769894A (zh) * 2017-11-16 2018-03-06 东南大学 极化码编码的mimo系统的联合检测译码方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101425869A (zh) * 2007-11-02 2009-05-06 华为技术有限公司 一种译码方法及装置
US20140177740A1 (en) * 2012-10-10 2014-06-26 Texas Instruments Incorporated Hexagonal constellations and decoding same in digital communication systems
CN107204779A (zh) * 2013-12-24 2017-09-26 华为技术有限公司 极性码的编码方法和编码装置

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
LG ELECTRONICS: "Discussion on the receiver types", 3GPP DRAFT; R1-1810262 DISCUSSION ON THE RECEIVER TYPES, 3RD GENERATION PARTNERSHIP PROJECT (3GPP), MOBILE COMPETENCE CENTRE ; 650, ROUTE DES LUCIOLES ; F-06921 SOPHIA-ANTIPOLIS CEDEX ; FRANCE, vol. RAN WG1, no. Chengdu, China; 20181008 - 20181012, 29 September 2018 (2018-09-29), Mobile Competence Centre ; 650, route des Lucioles ; F-06921 Sophia-Antipolis Cedex ; France, XP051517676 *
LG ELECTRONICS: "Discussion on the receiver types", 3GPP DRAFT; R1-1812553 DISCUSSION ON THE RECEIVER TYPES, 3RD GENERATION PARTNERSHIP PROJECT (3GPP), MOBILE COMPETENCE CENTRE ; 650, ROUTE DES LUCIOLES ; F-06921 SOPHIA-ANTIPOLIS CEDEX ; FRANCE, vol. RAN WG1, no. Spokane, USA; 20181112 - 20181116, 3 November 2018 (2018-11-03), Mobile Competence Centre ; 650, route des Lucioles ; F-06921 Sophia-Antipolis Cedex ; France, XP051478783 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113872613A (zh) * 2021-09-30 2021-12-31 广州慧睿思通科技股份有限公司 极化码译码中g函数的计算方法、装置、电子设备及介质
CN116073948A (zh) * 2021-11-04 2023-05-05 Oppo广东移动通信有限公司 译码方法及装置、终端设备、芯片、存储介质

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