WO2023226689A1 - 一种编码、译码方法及装置 - Google Patents

一种编码、译码方法及装置 Download PDF

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Publication number
WO2023226689A1
WO2023226689A1 PCT/CN2023/091491 CN2023091491W WO2023226689A1 WO 2023226689 A1 WO2023226689 A1 WO 2023226689A1 CN 2023091491 W CN2023091491 W CN 2023091491W WO 2023226689 A1 WO2023226689 A1 WO 2023226689A1
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Prior art keywords
bits
bit sequence
bit
matrix
frozen
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PCT/CN2023/091491
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English (en)
French (fr)
Inventor
王献斌
张华滋
秦康剑
童佳杰
李榕
王俊
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华为技术有限公司
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Publication of WO2023226689A1 publication Critical patent/WO2023226689A1/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes

Definitions

  • the embodiments of the present application relate to the field of communication technology, and in particular, to an encoding and decoding method and device.
  • eMBB enhanced mobile broadband
  • mMTC massive machine type of communication
  • URLLC ultra-reliable low-power Delayed communication
  • eMBB enhanced mobile broadband
  • mMTC massive machine type of communication
  • URLLC ultra-reliable low-power Delayed communication
  • channel coding is one of the important research objects to meet the needs of 5G communication.
  • Polar code is selected as the control coding scheme in the 5G standard.
  • Polar codes also known as polar codes, are the first and only known channel coding scheme that can be strictly proven to "reach" the Shannon channel capacity. Under different code lengths, especially for finite codes, the performance of polar codes is far better than turbo codes and low density parity check (LDPC) codes.
  • LDPC low density parity check
  • polar codes have lower computational complexity in encoding and decoding.
  • System polar codes refer to polar codes in which information bits are directly carried on the system bits on the code word side. Compared with non-systematic polar codes, system polar codes have better bit error ratio (BER) performance, more convenience and other It has the advantages of code concatenation and wide application (such as the ability to perform joint source-channel coding (JSCC)).
  • BER bit error ratio
  • JSCC joint source-channel coding
  • Embodiments of the present application provide an encoding and decoding method and device. By introducing bit mapping, the system bits and frozen bits of the system polar code can be decoupled, in order to bring greater coding design space and reduce coding complexity. complexity and improve coding flexibility.
  • embodiments of the present application provide a coding method, which method includes: obtaining an information bit sequence; encoding the information bit sequence according to a system polar code to determine the coded bit sequence, where the system polar code includes a polarization transformation matrix and N first bits and N second bits corresponding to the polarization transformation matrix.
  • the N second bits include the systematic bit set A and the non-systematic bit set M A
  • the N first bits includes a frozen bit set B and a non-frozen bit set M B
  • the frozen bits in C are the same as the non-frozen bits in D Mutual mapping
  • C is determined based on the intersection of the bit indexes of B and A
  • D is determined based on the intersection of the bit indexes of M B and M A
  • A is determined based on the information bit sequence
  • the coded bit sequence includes Information bit sequence; output coded bit sequence.
  • the above-mentioned encoding method can be executed by encoding equipment, such as network equipment or terminal equipment, or by components of the encoding equipment (such as processors, chips, or chip systems, etc.), or by a system that can realize all or part of the functions of the encoding equipment.
  • encoding equipment such as network equipment or terminal equipment, or by components of the encoding equipment (such as processors, chips, or chip systems, etc.), or by a system that can realize all or part of the functions of the encoding equipment.
  • Logic module or software implementation can be executed by encoding equipment, such as network equipment or terminal equipment, or by components of the encoding equipment (such as processors, chips, or chip systems, etc.), or by a system that can realize all or part of the functions of the encoding equipment.
  • Logic module or software implementation can be executed by encoding equipment, such as network equipment or terminal equipment, or by components of the encoding equipment (such as processors, chips, or chip systems, etc.), or by
  • the system bits can be used to carry the information bit sequence, and the total number of system bits and frozen bits is equal to the code length N of the system polar code. Therefore, in the embodiment of the present application , A can be determined based on the information bit sequence. For example: the length of the information bit sequence is K, then A includes K systematic bits, B includes NK frozen bits, M A includes NK non-systematic bits, and M B includes K non-frozen bits. .
  • the value of the frozen bit in C corresponds to the value of the bit in D in a one-to-one correspondence
  • the value of the non-frozen bits in i.e., the bits carried by the non-frozen bits
  • the value of the non-frozen bits in can be determined based on the value of the frozen bits (i.e., the bits carried by the frozen bits) in C.
  • the value of the frozen bits in C The value can be determined based on the value of the non-frozen bit in D, which enables the frozen bits of the system polar code and the bit index of the system bit to overlap, decoupling the system bits and frozen bits of the system polar code bit, bringing a larger coding design space, thereby reducing coding complexity and improving coding flexibility.
  • the bit index of the frozen bits is It can be 0, 1, 2, and 4.
  • the bit index of the system bit can be 4, 5, 6, and 7.
  • the value of the non-frozen bit with the bit index of 3 can be based on the bit index of 4.
  • the coding problem of the system polar code with a code length of 8 corresponding to the bit index 0, 1, 2, 3, 4, 5, 6, and 7 can be split into corresponding bits Two sub-coding problems with indexes 0, 1, 2, and 3 and corresponding bit indexes 4, 5, 6, and 7.
  • Each sub-coding problem can be encoded in parallel, and the encoding complexity is equivalent to performing a non-systematic polar code encoding process. , can reduce the coding complexity, and can be applied to a variety of system bit setting methods, which can improve the flexibility of coding.
  • the mutual mapping between the frozen bits in C and the non-frozen bits in D includes: the frozen bits in C and the non-frozen bits in D are mapped to each other according to a mapping matrix, and the mapping matrix is a full N C -dimensional
  • the rank matrix may be an identity matrix of N C dimensions, where N C is equal to the number of frozen bits in C.
  • encoding the information bit sequence according to the system polar code and determining the coded bit sequence includes: determining the first intermediate coded bit sequence according to the information bit sequence and the first polarization transformation sub-matrix, where the first intermediate coded bit sequence is determined.
  • a polarization transformation sub-matrix is the polarization transformation sub-matrix corresponding to A in the polarization transformation matrix; according to the first intermediate coding bit sequence, the mutual mapping relationship between the frozen bits in C and the non-frozen bits in D, and B
  • the intersection with the bit index of M A determines the second intermediate coded bit sequence, where the length of the second intermediate coded bit sequence is equal to the number of second bits contained in M A ; according to the second intermediate coded bit sequence, the second polarization
  • the transformation sub-matrix and the information bit sequence determine the encoding bit sequence, where the second polarization transformation sub-matrix is the polarization transformation sub-matrix corresponding to M A in the polarization transformation matrix.
  • the coding problem of the system polar code with code length N corresponding to the bit indexes 0, 1,...N can be split into two sub-codings corresponding to the bit index of A and the bit index of M A respectively.
  • each sub-coding problem is coded in parallel, and the coding complexity is equivalent to executing a non-systematic polar code coding process, which can reduce the coding complexity.
  • A is composed of the last K second bits among the N second bits; and/or, B is composed of NK selected according to channel reliability or code weight among the N first bits. It consists of the first bits, K is greater than or equal to 1 and less than N.
  • B can be selected from the N first bits according to the channel reliability with the highest channel reliability. It is composed of the lowest NK first bits, or it is composed of the NK first bits with the lowest code weight selected according to the code weight among the N first bits.
  • the last K second bits among the N second bits are directly used as system bits, which can simplify the encoding process and improve the encoding efficiency.
  • the system polar code is cascaded with a precoding matrix, and the precoding matrix is an upper triangular matrix.
  • the number of rows of TA and TB is determined by the number of non-systematic bits in M A
  • the number of rows of TC is determined by the number of systematic bits in A
  • the number of columns of TA is determined by the number of non-systematic bits in M A. Determine, the number of columns of TB and TC is determined based on the number of system bits in A;
  • Encoding the information bit sequence according to the system polar code and determining the coded bit sequence includes: determining the first intermediate coded bit sequence according to the information bit sequence and the first polarization transformation sub-matrix, wherein the first polarization transformation The submatrix is the polarization transformation submatrix corresponding to the A in the polarization transformation matrix; according to the first intermediate coding bit sequence, TC and TB, the third intermediate coding bit sequence is determined; according to the third intermediate coding bit sequence, C
  • the mutual mapping relationship between the frozen bits in and the non-frozen bits in D, and the intersection of the bit indexes of B and M A determine the fourth intermediate coded bit sequence; according to the fourth intermediate coded bit sequence and TA, determine the second intermediate Coded bit sequence; determine the coded bit sequence according to the second intermediate coded bit sequence, the second polarization transformation sub-matrix, and the information bit sequence, where the second polarization transformation sub-matrix is the polarization corresponding to M A in the polarization transformation matrix Trans
  • the code spectrum of the system polar code can be optimized by cascading precoding matrices to improve the performance of the system polar code.
  • A is determined based on the information bit sequence, including: A includes the position of the information bit and the position of the cyclic redundancy check (cyclic redundancy check, CRC) bit corresponding to the information bit.
  • CRC cyclic redundancy check
  • the first intermediate coded bit sequence includes a fifth intermediate coded bit sequence and CRC bits
  • the fifth intermediate coded bit sequence is determined based on the information bit sequence and the first polarization transformation submatrix
  • the CRC bits are determined based on the fifth intermediate coded bit sequence.
  • the intermediate coded bit sequence is determined.
  • the CRC bits are set on the side to be encoded (that is, the non-codeword side) of the system polar code, and the CRC bits form a check relationship with the encoded bit sequence on the side to be encoded, which is conducive to early stopping of decoding.
  • the first intermediate coded bit sequence includes a fifth intermediate coded bit sequence and CRC bits.
  • the fifth intermediate coded bit sequence is determined based on the information bit sequence and the first polarization transformation submatrix.
  • the CRC bits are determined based on the information bits. Sequence determined.
  • the error correction capability of decoding can be improved and the reliability of decoding can be improved.
  • embodiments of the present application provide a decoding method, which method includes: obtaining a sequence of symbols to be decoded; decoding the sequence of symbols to be decoded according to a systematic polar code to determine an information bit sequence, where the systematic polar code Including a polarization transformation matrix and N first bits and N second bits corresponding to the polarization transformation matrix.
  • the N second bits include a systematic bit set A and a non-systematic bit set M A
  • the first bits include a frozen bit set B and a non-frozen bit set M B . There is a frozen bit subset C in B and a non-frozen bit subset D in M B .
  • the frozen bits in C are the same as those in D
  • the non-frozen bits are mapped to each other, C is determined based on the intersection of the bit indexes of B and A, D is determined based on the intersection of the bit indexes of M B and M A , and A is determined based on the information bit sequence.
  • the above decoding method can be executed by a decoding device, such as a network device or a terminal device, or by a decoding device. It is executed by a component (such as a processor, a chip, or a chip system, etc.), and can also be implemented by a logic module or software that can realize all or part of the functions of the decoding device.
  • a decoding device such as a network device or a terminal device, or by a decoding device. It is executed by a component (such as a processor, a chip, or a chip system, etc.), and can also be implemented by a logic module or software that can realize all or part of the functions of the decoding device.
  • the system bits can be used to carry the information bit sequence, and the total number of system bits and frozen bits is equal to the code length N of the system polar code. Therefore, in the embodiment of the present application , A can be determined based on the information bit sequence. For example: the length of the information bit sequence is K, then A includes K systematic bits, B includes NK frozen bits, M A includes NK non-systematic bits, and M B includes K non-frozen bits. .
  • the mutual mapping between the frozen bits in C and the non-frozen bits in D includes: the frozen bits in C and the non-frozen bits in D are mapped to each other according to a mapping matrix, and the mapping matrix is a full N C -dimensional
  • the rank matrix may be an identity matrix of N C dimensions, where N C is equal to the number of frozen bits in C.
  • the sequence of symbols to be decoded is decoded according to the system polar code to determine the sequence of information bits, including: based on the sequence of symbols to be decoded, the polarization transformation matrix, the frozen bits in C and the sequence of bits in D
  • the mutual mapping relationship between non-frozen bits and the intersection of the bit indexes of B and M A determine the first intermediate decoding bit sequence; the information bit sequence is determined according to the first intermediate decoding bit sequence and the polarization transformation matrix.
  • A is composed of the last K second bits among the N second bits; and/or, B is composed of N-K selected according to channel reliability or code weight among the N first bits. It consists of the first bits, K is greater than or equal to 1 and less than N.
  • A is determined based on the information bit sequence, including: the position of the information bit included in A and the position of the CRC bit corresponding to the information bit.
  • the first intermediate decoding bit sequence includes a second intermediate decoding bit sequence and CRC bits, and the CRC bits are used to check the second intermediate decoding bit sequence, wherein the second intermediate decoding bit sequence
  • the bit sequence corresponds to the position of the information bit
  • the CRC bit corresponds to the position of the CRC bit.
  • the first intermediate decoding bit sequence includes a second intermediate decoding bit sequence and CRC bits.
  • the CRC bits are used to verify the information bit sequence, where the second intermediate decoding bit sequence corresponds to the information.
  • the position of the bit, the CRC bit corresponds to the position of the CRC bit.
  • inventions of the present application provide a communication device.
  • the communication device may include: an input and output unit and a processing unit.
  • the input and output unit is used to obtain an information bit sequence;
  • a processing unit is used to process the information according to the system polarization code.
  • the bit sequence is encoded to determine the encoded bit sequence.
  • the system polar code includes a polarization transformation matrix and N first bits and N second bits corresponding to the polarization transformation matrix.
  • the N second bits include System bit set A and non-system bit set M A
  • the N first bits include frozen bit set B and non-frozen bit set M B
  • non-frozen bit set M B Frozen bit subset D
  • the frozen bits in C map to the non-frozen bits in D
  • C is determined based on the intersection of the bit indexes of B and A
  • D is determined based on the intersection of the bit indexes of M B and M A
  • the mutual mapping between the frozen bits in C and the non-frozen bits in D includes: the frozen bits in C and the non-frozen bits in D are mapped to each other according to a mapping matrix, and the mapping matrix is a full N C -dimensional
  • the rank matrix may be an identity matrix of N C dimensions, where N C is equal to the number of frozen bits in C.
  • the processing unit encodes the information bit sequence according to the system polar code, and when determining the coded bit sequence, is specifically configured to determine the first intermediate coded bits based on the information bit sequence and the first polarization transformation sub-matrix. sequence, where the first polarization transformation sub-matrix is the polarization transformation sub-matrix corresponding to A in the polarization transformation matrix; according to the first The inter-coded bit sequence, the mutual mapping relationship between the frozen bits in C and the non-frozen bits in D, and the intersection of the bit indexes of B and M A determine the second intermediate coded bit sequence, where the second intermediate coded bit sequence The length is equal to the number of second bits contained in M A ; and the coded bit sequence is determined according to the second intermediate coded bit sequence, the second polarization transformation sub-matrix, and the information bit sequence, where the second polarization transformation sub-matrix is The polarization transformation sub-matrix corresponding to M A in the polarization transformation matrix.
  • A is composed of the last K second bits among the N second bits; and/or, B is composed of N-K selected according to channel reliability or code weight among the N first bits. It consists of the first bits, K is greater than or equal to 1 and less than N.
  • the system polar code is cascaded with a precoding matrix, and the precoding matrix is an upper triangular matrix.
  • the number of rows of TA and TB is determined by the number of non-systematic bits in M A
  • the number of rows of TC is determined by the number of systematic bits in A
  • the number of columns of TA is determined by the number of non-systematic bits in M A. Determine, the number of columns of TB and TC is determined based on the number of system bits in A;
  • the processing unit encodes the information bit sequence according to the system polar code, and when determining the coded bit sequence, is specifically used to determine the first intermediate coded bit sequence based on the information bit sequence and the first polarization transformation sub-matrix, where the first polarization transformation
  • the submatrix is the polarization transformation submatrix corresponding to A in the polarization transformation matrix; according to the first intermediate coding bit sequence, TC and TB, the third intermediate coding bit sequence is determined; according to the third intermediate coding bit sequence, the frozen bits in C
  • the mapping relationship between the bits and the non-frozen bits in D, and the intersection of the bit indexes of B and M A determine the fourth intermediate coded bit sequence; according to the fourth intermediate coded bit sequence and TA, the second intermediate coded bit sequence is determined;
  • the coded bit sequence is determined according to the second intermediate coded bit sequence, the second polarization transformation sub-matrix, and the information bit sequence, where the second polarization transformation sub-matrix is the polarization
  • A is determined based on the information bit sequence, including: the position of the information bit included in A and the position of the CRC bit corresponding to the information bit.
  • the first intermediate coded bit sequence includes a fifth intermediate coded bit sequence and CRC bits
  • the fifth intermediate coded bit sequence is determined based on the information bit sequence and the first polarization transformation submatrix
  • the CRC bits are determined based on the fifth intermediate coded bit sequence.
  • the intermediate coded bit sequence is determined.
  • the first intermediate coded bit sequence includes a fifth intermediate coded bit sequence and CRC bits.
  • the fifth intermediate coded bit sequence is determined based on the information bit sequence and the first polarization transformation submatrix.
  • the CRC bits are determined based on the information bits. Sequence determined.
  • inventions of the present application provide a communication device.
  • the communication device may include: an input and output unit and a processing unit.
  • the input and output unit is used to obtain the symbol sequence to be decoded;
  • the processing unit is used to obtain the symbol sequence according to the system polar code.
  • the bits include a systematic bit set A and a non-systematic bit set M A .
  • the N first bits include a frozen bit set B and a non-frozen bit set M B . There are frozen bit subsets C and M in B.
  • D There is a subset D of non-frozen bits in B.
  • the frozen bits in C map to the non-frozen bits in D.
  • C is determined based on the intersection of the bit indexes of B and A.
  • D is determined based on the bit index of M B and M A. The intersection is determined, and A is determined based on the information bit sequence.
  • the mutual mapping between the frozen bits in C and the non-frozen bits in D includes: the frozen bits in C and the non-frozen bits in D are mapped to each other according to a mapping matrix, and the mapping matrix is a full N C -dimensional
  • the rank matrix may be an identity matrix of N C dimensions, where N C is equal to the number of frozen bits in C.
  • the processing unit decodes the symbol sequence to be decoded according to the system polar code and determines the signal information bit sequence, specifically based on the symbol sequence to be decoded, the polarization transformation matrix, the mutual mapping relationship between the frozen bits in C and the non-frozen bits in D, and the intersection of the bit indexes of B and M A , Determine the first intermediate decoding bit sequence; determine the information bit sequence according to the first intermediate decoding bit sequence and the polarization transformation matrix.
  • A is composed of the last K second bits among the N second bits; and/or, B is composed of N-K selected according to channel reliability or code weight among the N first bits. It consists of the first bits, K is greater than or equal to 1 and less than N.
  • A is determined based on the information bit sequence, including: the position of the information bit included in A and the position of the CRC bit corresponding to the information bit.
  • the first intermediate decoding bit sequence includes a second intermediate decoding bit sequence and CRC bits, and the CRC bits are used to check the second intermediate decoding bit sequence, wherein the second intermediate decoding bit sequence
  • the bit sequence corresponds to the position of the information bit
  • the CRC bit corresponds to the position of the CRC bit.
  • the first intermediate decoding bit sequence includes a second intermediate decoding bit sequence and CRC bits.
  • the CRC bits are used to verify the information bit sequence, where the second intermediate decoding bit sequence corresponds to the information.
  • the position of the bit, the CRC bit corresponds to the position of the CRC bit.
  • inventions of the present application provide a communication device.
  • the communication device includes an interface circuit and a processor, and the processor and the interface circuit are coupled to each other.
  • the processor is used to implement the method in the above first aspect or any possible design of the first aspect through logic circuits or execution of code instructions.
  • the interface circuit is used to receive signals from other communication devices other than the communication device and transmit them to the processor or to send signals from the processor to other communication devices other than the communication device. It can be understood that the interface circuit may be a transceiver or a transceiver or a transceiver or an input-output interface.
  • the communication device may also include a memory for storing instructions executed by the processor or input data required for the processor to run the instructions or data generated after the processor executes the instructions.
  • the memory can be a physically separate unit, or it can be coupled to the processor, or the processor can include the memory.
  • inventions of the present application provide a communication device.
  • the communication device includes an interface circuit and a processor, and the processor and the interface circuit are coupled to each other.
  • the processor is used to implement the method in the above second aspect or any possible design of the second aspect through logic circuits or execution of code instructions.
  • the interface circuit is used to receive signals from other communication devices other than the communication device and transmit them to the processor or to send signals from the processor to other communication devices other than the communication device. It can be understood that the interface circuit may be a transceiver or a transceiver or a transceiver or an input-output interface.
  • the communication device may also include a memory for storing instructions executed by the processor or input data required for the processor to run the instructions or data generated after the processor executes the instructions.
  • the memory can be a physically separate unit, or it can be coupled to the processor, or the processor can include the memory.
  • inventions of the present application provide a communication system.
  • the communication system includes an encoding device and a decoding device.
  • the encoding device can implement the method in the above-mentioned first aspect or any possible design of the first aspect.
  • the decoding device The device may implement the method in the above second aspect or any possible design of the second aspect.
  • embodiments of the present application provide a computer-readable storage medium.
  • Computer programs or instructions are stored in the storage medium.
  • the above-mentioned first aspect or any one of the first aspects can be implemented.
  • embodiments of the present application further provide a computer program product, including a computer program or instructions.
  • a computer program product including a computer program or instructions.
  • the above-mentioned first aspect or any possible design of the first aspect can be implemented.
  • method, or a method in implementing the above second aspect or any possible design of the second aspect can be implemented.
  • embodiments of the present application further provide a chip, which is coupled to a memory and used to read and execute the memory.
  • the program or instruction stored in the memory implements the method in the above-mentioned first aspect or any possible design of the first aspect, or implements the method in the above-mentioned second aspect or any possible design of the second aspect.
  • Figure 1 is a schematic architectural diagram of a communication system provided by an embodiment of the present application.
  • Figure 2 is a schematic diagram of the encoding and decoding process provided by the embodiment of the present application.
  • Figure 3 is a schematic diagram of the encoding process provided by the embodiment of the present application.
  • Figure 4 is a schematic diagram of the decoding path in the SCL algorithm provided by the embodiment of the present application.
  • Figure 5 is one of the system polar code schematic diagrams provided by the embodiment of the present application.
  • Figure 6 is a schematic diagram of parallel coding of system polar codes provided by the embodiment of the present application.
  • Figure 7 is a schematic diagram of the encoding and decoding method according to the embodiment of the present application.
  • Figure 8 is the second schematic diagram of the system polar code provided by the embodiment of the present application.
  • Figure 9 is one of the schematic diagrams of the system polar code encoding process provided by the embodiment of the present application.
  • Figure 10 is a schematic diagram of the polar code of the pre-conversion system provided by the embodiment of the present application.
  • Figure 11 is a schematic diagram of a precoding matrix provided by an embodiment of the present application.
  • Figure 12 is the second schematic diagram of the system polar code encoding process provided by the embodiment of the present application.
  • Figure 13 is a schematic diagram of the system polar code decoding process provided by the embodiment of the present application.
  • Figure 14 is one of the schematic diagrams of the check bit bearing in the system polar code provided by the embodiment of the present application.
  • Figure 15 is the second schematic diagram of the check bit bearing in the system polar code provided by the embodiment of the present application.
  • Figure 16 is the third schematic diagram of the check bit bearing in the system polar code provided by the embodiment of the present application.
  • Figure 17 is one of the schematic diagrams of a communication device provided by an embodiment of the present application.
  • Figure 18 is a second schematic diagram of a communication device provided by an embodiment of the present application.
  • GSM global system for mobile communications
  • EDGE enhanced data rate for GSM evolution
  • WCDMA wideband code division multiple access
  • TD-SCDMA time division synchronous code division multiple access system
  • long term evolution long term evolution, LTE
  • WiMAX global interconnection Microwave access
  • 5G fifth generation mobile communication system
  • new radio new radio, NR
  • the technical solution provided by this application can also be applied to future communication systems, such as the sixth generation mobile communication system.
  • the communication system can also be a Bluetooth (bluetooth) communication system, a wireless local area network (WLAN)/wireless communication technology (WiFi) communication system, a narrowband internet of things (NB-IoT) communication system, etc.
  • FIG. 1 is a schematic architectural diagram of a communication system applied in an embodiment of the present application.
  • the communication system includes network equipment and terminal equipment.
  • the number of network equipment is one, and the number of terminal equipment is two (terminal equipment A and terminal equipment B).
  • terminal equipment A and terminal equipment B terminal equipment A and terminal equipment B.
  • the above-mentioned terminal equipment may also be called a terminal, user equipment (UE), mobile station, mobile terminal, etc.
  • Terminal devices can be widely used in various scenarios, such as device-to-device (D2D), vehicle to everything (V2X) communication, machine-type communication (MTC), things Internet of things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grid, smart furniture, smart office, smart wear, smart transportation, smart city, etc.
  • Terminal devices can be mobile phones, tablets, computers with wireless transceiver functions, wearable devices, vehicles, drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, vehicle terminals, IoT terminals, and wearable devices wait.
  • the embodiments of this application do not limit the specific technology and specific equipment form used by the terminal equipment.
  • Network equipment may also be called access network (AN) equipment or radio access network (RAN) equipment. It can be a base station, an evolved base station (evolved NodeB, eNodeB), a transmitter and receiver point (TRP), an integrated access and backhauling (IAB) node, or a fifth generation (5th Generation, 5G) next generation base station (next generation NodeB, gNB) in the mobile communication system, base station in the sixth generation (6th generation, 6G) mobile communication system, base station in other future mobile communication systems or access points in the WiFi system Ingress node, home base station (for example, home evolved nodeB, or home node B, HNB), access point (AP) in wireless fidelity (wireless fidelity, WIFI) system, wireless relay node, wireless backhaul Nodes etc.
  • AN access network
  • RAN radio access network
  • the base station can also be a module or unit that completes some functions of the base station.
  • it can be a centralized unit (central unit, CU) or a distributed unit (distributed unit, DU).
  • the CU here completes the functions of the base station's radio resource control protocol and packet data convergence protocol (PDCP), and can also complete the functions of the service data adaptation protocol (SDAP);
  • SDAP service data adaptation protocol
  • DU completes the functions of the base station
  • the functions of the wireless link control layer and medium access control (MAC) layer can also complete some or all of the physical layer functions.
  • 3GPP Third Generation Partner Program
  • Network equipment can also be non-terrestrial base stations, such as low earth orbit (LEO)/very low earth orbit (VLEO) satellites, high-attitude platform station (HAPS) ), it can also be a terminal that assumes network device functions in V2X, D2D and machine to machine (M2M) communications.
  • LEO low earth orbit
  • VLEO very low earth orbit
  • HAPS high-attitude platform station
  • M2M machine to machine
  • the functions of the network device may also be executed by modules (such as chips) in the network device, or may be executed by a control subsystem that includes the functions of the network device.
  • the control subsystem here that includes network equipment functions can be the control center in the above application scenarios such as smart grid, industrial control, smart transportation, smart city, etc.
  • the functions of the terminal equipment can also be performed by modules in the terminal equipment (such as chips or modems), or can be performed by devices containing the functions of the terminal equipment.
  • the information can be encoded and decoded.
  • the source of the sending end passes through the information in sequence.
  • Modulation symbols are output after source coding, channel coding and modulation.
  • the receiving end undergoes demodulation, channel decoding and source recovery in order to obtain the information sink.
  • the receiving end can obtain useful information based on the information sink.
  • Upper triangular matrix a square matrix with zeros below the main diagonal is called an upper triangular matrix.
  • An upper triangular matrix has properties such as the determinant being the multiplication of diagonal elements, an upper triangular matrix being multiplied by a coefficient and also being an upper triangular matrix, and the result of addition, subtraction and multiplication operations between upper triangular matrices still being an upper triangular matrix.
  • Polar code is also a linear block code.
  • the polarization transformation matrix is G N .
  • the polarization transformation matrix can also be recorded as G.
  • the polarization transformation matrix can also be called a coding matrix or a generating matrix.
  • the coding process is in is a binary row vector, that is, a binary sequence with a length of N , where N is the length of the polar code; G N is an N ⁇ N matrix, and It can be defined as the Kronecker product of log 2 N matrices F 2 . in
  • bits that carry information are called information bits.
  • This part of the bits that are used to carry information form a set of information bits.
  • the set of bit indexes of these bits is denoted as Another part of the bits is set to a fixed value pre-agreed by the receiving end and the transmitting end, which is called a fixed bit set or a frozen bit set (frozen bits).
  • the set of bit indexes is complement of express.
  • G N (A) is the set in G N consisting of The submatrix obtained by the rows corresponding to the bit indexes in
  • G N (A C ) is the set in G N The submatrix obtained by those rows corresponding to the bit indexes in .
  • the set of information bits in the number is K;
  • the frozen bit set in whose number is (NK), is a known bit.
  • These freeze bits are usually set to 0, but as long as the receiving end and the sending end agree in advance, the freezing bits can be set arbitrarily.
  • the encoding output of polar code can be simplified to: here for The set of information bits in , is a row vector of length K, that is
  • the submatrix obtained by those rows corresponding to the bit index in is a K ⁇ N matrix.
  • the construction process of polar code is a set
  • the selection process determines the performance of polar codes.
  • the construction process of polar codes is usually as follows: according to the code length N, it is determined that there are N polar channels in total, corresponding to N rows of the polar transformation matrix, calculating the channel reliability of the polar channels, and placing the top K channels with higher channel reliability bit index of polarized channels as a set elements, the bit indexes corresponding to the remaining (NK) polarization channels are used as the bit index set of frozen bits Elements. gather Determines the position of the information bits, the set Determines the location of the frozen bit.
  • FIG. 3 exemplarily shows a specific encoding process.
  • the left side can be understood as the side to be encoded, and the bits on the left are represented by u.
  • the right side can be understood as the encoding side (or codeword side), and the bits on the right side are represented by x.
  • the process from left to right is the process of the transmitter encoding the bit sequence to be encoded.
  • the information bits to be encoded are represented by the sequence u(0,0,0,0,0,0,1,1).
  • the encoded bits are represented by the sequence x(0,1,0,1, 0, 1, 0, 1) means that mapping x into a modulation symbol can be transmitted on channel W.
  • the bits corresponding to high channel reliability are used to map information bits
  • the bits corresponding to low channel reliability are used to map frozen bits.
  • ⁇ u0, u1, u2, u4 ⁇ are frozen bits, which are the positions of the frozen bits
  • ⁇ u3, u5, u6, u7 ⁇ are information bits, which are the positions of the information bits.
  • two adjacent columns are a coding layer.
  • the bits in the left column are the input bits of the coding layer
  • the bits in the right column are the output bits of the coding layer.
  • the input bit sequence (0, 0, 0, 0, 0, 0, 1, 1)
  • the output bit sequence (0, 0, 0, 0, 0, 0, 0, 1)
  • the operation symbol " ⁇ " in the middle of the coding layer represents an XOR operation.
  • " ⁇ " represents an XOR operation between the bits in the row where " ⁇ " is located and the bits in the row reached by " ⁇ ”.
  • the bits on the right side of " ⁇ ” are for the operation result.
  • the first input bit (take Value 0) and the second input bit (value 0) perform the " ⁇ " operation to obtain the first output bit (value 0).
  • the consecutive cancellation (SC) decoding method is an effective polar code decoding algorithm.
  • the decoding device After the decoding device obtains the symbol sequence to be decoded, it calculates the log likelihood ratio (LLR) of the information bits one by one based on the symbol sequence to be decoded. If the LLR of the information bits is > 0, the decoding result is 0. If the LLR of the information bit is ⁇ 0, the decoding result is 1. The decoding result of the frozen bit is set to 0 regardless of the LLR.
  • LLR log likelihood ratio
  • FIG. 4 is a schematic diagram of the decoding path in the SCL algorithm. As shown in Figure 4, each layer represents 1 decoding bit. If the decoding result is 0, then the development path is along the left subtree. If If the decoding result is 1, then develop the path along the right subtree.
  • the path metric selects the path metric (PM)
  • the L paths with the best values are saved and continue to develop paths to decode subsequent decoding bits.
  • the PM value is used to judge the quality of the path.
  • the PM value is calculated by LLR.
  • the PM values of the L paths are sorted from small to large, and the correct path is selected by the PM value. This is repeated until the last bit is decoded.
  • System polar code refers to a polar code in which information bits are directly carried on the encoding side (codeword side). Compared with non-system polar codes, system polar codes have better BER performance and are more convenient to compare with other code levels. It has the advantages of connection and wide application (such as the ability to perform joint source channel coding).
  • Figure 5 is a schematic diagram of an 8 ⁇ 8 system polar code. u0, u1, u2, and u4 on the side to be encoded are frozen bits, which can be used to carry frozen bits. x3, x5, x6, and x7 on the encoding side are actual carriers. System bits of information bits.
  • the role of the system bits is similar to the role of the information bits of non-systematic polar codes.
  • the coding process of the system polar code can be understood as based on the frozen bits carried by the frozen bits and the actual carried by the system bits.
  • Information bits are the process of determining the check bits carried by the check bits (x0, x1, x2, x4). The combination of the check bits and the information bits actually carried by the system bits is output as an encoded bit sequence.
  • serial coding scheme Since the positional relationship between the system bits and the frozen bits of the system polar code are mutually coupled, one current scheme for encoding the system polar code is the serial coding scheme.
  • the system polar code Nlog 2 N A coding problem is continuously decomposed into Nlog 2 N sub-coding problems. By serially executing these Nlog 2 N sub-coding problems, the coding process is completed.
  • the algorithm complexity is Nlog 2 N.
  • this encoding process requires serial execution, it will bring a large encoding delay.
  • a common scenario for the application of serial coding schemes is the coding process for biased information sources (that is, 0/1 is not a uniformly distributed information bit sequence).
  • this application provides an encoding and decoding method and device.
  • bit mapping the bit index of the frozen bits of the system polar code and the system bits (bits that actually carry information bits) can be There are overlapping, decoupling system bits and frozen bits of the system polar code, in order to bring greater coding design space, reduce coding complexity, and improve coding flexibility.
  • first and second are used to distinguish multiple objects and are not used to limit the size, content, order, timing, etc. of multiple objects. Priority or importance, etc.
  • first threshold and the second threshold can be the same threshold or different thresholds, and such names do not indicate the values, corresponding parameters, priorities or importance of the two thresholds. s difference.
  • the number of nouns means “singular noun or plural noun", that is, “one or more”, unless otherwise specified.
  • At least one means one or more
  • plural means two or more.
  • “And/or” describes the relationship between associated objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A exists alone, A and B exist simultaneously, and B exists alone, where A, B can be singular or plural.
  • the character “/” generally indicates that the related objects are in an "or” relationship.
  • A/B means: A or B.
  • At least one of the following or similar expressions thereof refers to any combination of these items, including any combination of a single item (items) or a plurality of items (items).
  • at least one of a, b, or c means: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, c Can be single or multiple.
  • Figure 7 is a schematic diagram of an encoding and decoding method provided by an embodiment of the present application.
  • the encoding device and the decoding device are used as execution subjects as an example to illustrate the method.
  • the encoding device can be a network device, and the decoding device can be It is a terminal device; or the encoding device is a terminal device, the decoding device is a network device, etc.
  • This application does not limit the execution subject of this method.
  • the encoding device in Figure 7 can also be a chip, chip system, or processor that can support the encoding device to implement the method, or it can also be a encoding device that can implement all or part of it.
  • the decoding device in Figure 7 can also be a chip, chip system, or processor that supports the decoding device to implement the method, or can be a logic module that can realize all or part of the functions of the decoding device. or software.
  • the method includes:
  • the encoding device obtains the information bit sequence.
  • the encoding device encodes the information bit sequence according to the system polar code and determines the encoded bit sequence.
  • the systematic polar code includes a polarization transformation matrix and N first bits and N second bits corresponding to the polarization transformation matrix.
  • the N second bits include a systematic bit set A and a non-systematic bit.
  • the bit set M A , the N first bits include the frozen bit set B and the non-frozen bit set M B , there is a frozen bit subset C in B, and there is a non-frozen bit subset D in M B , and in C
  • the frozen bits map to the non-frozen bits in D.
  • C is determined based on the intersection of the bit indexes of B and A.
  • D is determined based on the intersection of the bit indexes of M B and M A.
  • A is determined based on the information bit sequence.
  • the encoded bit sequence Contains a sequence of information bits.
  • both sides of the polarization transformation matrix correspond to N bits, including the N first bits on the left side of the polarization transformation matrix (i.e., the side to be encoded), and the polarization transformation
  • the N second bits, N first bits and N second bits on the right side of the matrix i.e. the coding side
  • the bits carried by the N first bits correspond to N
  • the bits carried by the second bit can be converted through the polarization transformation matrix.
  • the system bits can be used to carry an information bit sequence, and the total number of system bits and frozen bits is equal to the code length N of the system polar code. Therefore, in the embodiment of the present application, A can rely on the letter
  • the information bit sequence is determined. For example: the length of the information bit sequence is K, then A includes K systematic bits, B includes NK frozen bits, M A includes NK non-systematic bits, and M B includes K non-frozen bits. .
  • non-frozen bits in the system polar code can also be called information bits, but the information bits (non-frozen bits) in the system polar code are not used to actually carry information bits, but The information bit sequence is carried by the systematic bits in the systematic polar code.
  • the role of systematic bits in systematic polar codes is equivalent to the role of information bits in non-systematic polar codes.
  • the bit indexes of the system bits and frozen bits are completely staggered System polar code, such as the system polar code shown in Figure 5 in which the system bits and frozen bits are completely staggered.
  • the bit index of the system bit and the bit index of the frozen bit may not be completely staggered, that is, the system bit sets A and N among the N second bits
  • the bit indexes of the frozen bit set B whose first bit is in may have intersections.
  • the last K second bits among the N second bits can be determined as the system bits, where K is equal to the length of the information bit sequence.
  • K can also be equal to the length of the information bit sequence + the check code bits (such as CRC bits) obtained by check codes such as cyclic redundancy check (CRC) length.
  • CRC cyclic redundancy check
  • K second bits among the N second bits can also be determined as system bits according to the bit inverse order (BIV) criterion or random selection.
  • BIV bit inverse order
  • the binary expansion of 0-7 is 000 001 010 011 100 101 110 111. Invert the binary bits to get 000 100 010 110 001 101 011 111 .
  • this order take out the original corresponding K bit indexes from large to small, that is, 7, 3, 5, 1, and index the 4th bits in the N second bits to 7, 3, 5, and 1.
  • the two bits are determined as system bits.
  • the 4 (i.e. K) second bits of 7 (x4, x5, x6, x7) are determined as the system bits of the system polar code, and the 4 (i.e. NK) bit indexes are 0, 1, 2, and 3.
  • the second bit (x0, x1, x2, x3) is determined to be the non-systematic bit of the systematic polar code, and then the systematic bit set A of the systematic polar code can be determined to be ⁇ x4, x5, x6, x7 ⁇ , non-systematic
  • the bit set M A is ⁇ x0, x1, x2, x3 ⁇ .
  • the 4 (i.e. NK) first bits (u0, u1, u2, u4) with the lowest channel reliability corresponding to the polarized channel can be determined as the frozen bits of the system polar code, and the remaining 4 (i.e. K)
  • the first bit (u3, u5, u6, u7) is determined as the non-frozen bit of the system polar code
  • the frozen bit set B of the system polar code can be determined as ⁇ u0, u1, u2, u4 ⁇
  • the non-frozen bit set M B is ⁇ u3, u5, u6, u7 ⁇ .
  • the intersection of the bit indexes of B and A is 4, and the frozen bit subset C can be determined to be ⁇ u4 ⁇ .
  • the intersection of the bit indexes of M B and M A is 3.
  • the non-frozen bit subset D can be determined to be ⁇ u3 ⁇ .
  • the frozen bit u4 in C and the non-frozen bit u3 in D map to each other
  • the frozen bits in C and the non-frozen bits in D are mapped to each other, which can be a one-to-one correspondence between the value of the frozen bit in C and the value of the non-frozen bit in D in sequence.
  • Y can be an Nc-dimensional (that is, Nc*Nc) full-rank matrix or identity matrix.
  • N C is equal to the number of frozen bits in C.
  • the one-to-one correspondence is the same in sequence.
  • Y can also be an Nc-dimensional permutation matrix. In this case, the frozen bits in C and the non-frozen bits in D may not correspond to the same one-to-one in sequence.
  • the information bit sequence is encoded according to the system polar code, and determining the encoded bit sequence can be implemented based on the following steps:
  • Step A1 Determine the first intermediate coded bit sequence according to the information bit sequence and the first polarization transformation sub-matrix, where the first polarization transformation sub-matrix is the polarization transformation sub-matrix corresponding to A in the polarization transformation matrix, that is, the first polarization transformation sub-matrix.
  • a polarization change sub-matrix is the sub-matrix of those rows in the polarization transformation matrix corresponding to the bit index of the second bit in A.
  • Step A2 Determine the second intermediate coded bit sequence based on the first intermediate coded bit sequence, the mutual mapping relationship between the frozen bits in C and the non-frozen bits in D, and the intersection of the bit indexes of B and M A , where The length of the second intermediate coded bit sequence is equal to the number of second bits contained in M A.
  • Step A3 Determine the coded bit sequence based on the second intermediate coded bit sequence, the second polarization transformation sub-matrix, and the information bit sequence, where the second polarization transformation sub-matrix is the polarization transformation corresponding to M A in the polarization transformation matrix.
  • the sub-matrix, that is, the second polarization change sub-matrix is the sub-matrix of those rows in the polarization transformation matrix corresponding to the bit index of the second bit in M A.
  • Step A1 The encoding device obtains the information bit sequence U (corresponding to the bit carried by A, which can also be called the value corresponding to A) and the rows in the polarization transformation matrix G corresponding to the bit index of the second bit in A.
  • the first polarization transformation sub-matrix G 1 is multiplied to obtain the first intermediate coded bit sequence X 1 , where X 1 corresponds to the bits carried by u4-u7.
  • Step A2 The encoding device can determine the bit carried by u3 based on the mutual mapping relationship between the frozen bit u4 in C and the non-frozen bit u3 in D, and the bit carried by the corresponding u4 in X 1.
  • B ⁇ u0 The intersection of bit indexes ⁇ 0, 1, 2 ⁇ between u1, u2, u4 ⁇ and M A ⁇ x0, x1, x2, x3 ⁇ can determine that u0, u1 and u2 carry frozen bits, and the value of the frozen bit is set to 0
  • Step A3 The encoding device multiplies X 2 with the second polarization transformation sub-matrix G 2 obtained from the rows in the polarization transformation matrix G corresponding to the bit index of the second bit in M A to obtain the intermediate check bit sequence.
  • C 1 and XOR the intermediate check bit sequence C 1 with the information bit sequence U, you can get the check bit sequence C, where C corresponds to the bits carried by x1-x4; splice C and U, and you can Get the coded bit sequence.
  • the middle parity bits in C 1 and the information bits in U perform XOR operations one by one in sequence.
  • the middle parity bits corresponding to x0 in C 1 correspond to those in U.
  • the information bits of x4 perform an XOR operation.
  • the middle parity bits corresponding to x1 in C 1 perform an XOR operation with the information bits corresponding to x5 in U.
  • the middle parity bits corresponding to x2 in C 1 perform an XOR operation with the information bits corresponding to x6 in U.
  • Perform XOR operation the middle parity bit corresponding to x3 in C 1 and
  • bits corresponding to the bit index 0 and the bits corresponding to the bit index N/2 can perform the XOR operation, and the bits corresponding to the bit index 1 and The bits corresponding to the bit index N/2+1 perform the XOR operation,..., the corresponding bit index N/2-1 bits and the corresponding bit index N-1 perform the XOR operation.
  • bits included in A and M A are the same, that is, the lengths of the information bit sequence U and the intermediate check bit sequence C 1 are equal. It can be understood that in some embodiments, the bits included in A and M A may also be different, that is, the lengths of U and C 1 may be different.
  • the intermediate check bit sequence C 1 includes The 5 intermediate check bits correspond to x0, x1, x2, x3, and x4 respectively.
  • the information bit sequence U includes 3 information bits, corresponding to x5, x6, and x7 respectively.
  • C 1 The middle check bit corresponding to x0 in the XOR operation is performed with the middle check bit corresponding to x4 to obtain the check bit corresponding to x0 in the check bit sequence C; the middle check bit corresponding to x1 in C 1 and the corresponding x5 in U Perform an XOR operation on the information bits in the check bit sequence C to obtain the check bits corresponding to x1 in the check bit sequence C; perform an XOR operation on the intermediate check bits corresponding to x2 in C 1 and the information bits corresponding to x6 in U to obtain the check bit sequence
  • the check bits corresponding to x2 in C; the intermediate check bits corresponding to x3 in C 1 are XORed with the information bits corresponding to x7 in U to obtain the check bits corresponding to x3 in the check bit sequence C; the corresponding The middle check bit of x4 is XORed with the middle check bit corresponding to x0 to obtain the check bit corresponding to x4
  • the reliability sequence of 16 polarization channels sorted according to channel reliability M [0, 1, 2, 4, 8, 3, 5, 9 , 6, 10, 12, 7, 11, 13, 14, 15]
  • the system bit set A is ⁇ x7, x8, x9, x10, x11, x12, x13, x14, x15 ⁇
  • the non-systematic bit set M A is ⁇ x0, x1, x2, x3, x4, x5, x6 ⁇
  • the frozen bit set B is ⁇ u0, u1, u2, u4, u8, u3, u5 ⁇
  • the non-frozen bit set M B is ⁇ u9 , u6u10, u12, u7, u11, u13, u14, u15 ⁇ , where the intersection of the bit indexes of A and B is ⁇ 8 ⁇ , the intersection of the bit indexes of M B and the M A is ⁇ 6 ⁇ , the freezing
  • the frozen bit u8 in C and the non-frozen bit u6 in D map to each other.
  • the determined intermediate check bit sequence C 1 includes 7 intermediate check bits, corresponding to x0, x1, x2, x3, x4, x5, x6 respectively.
  • Information The bit sequence U includes 9 information bits, corresponding to x7, x8, x9, x10, x11, x12, x13, x14, x15 respectively.
  • the middle check bit corresponding to x0 in C 1 Perform an XOR operation with the information bits corresponding to x8 in U to obtain the check bits corresponding to x0 in the check bit sequence C; perform an XOR operation with the intermediate check bits corresponding to x1 in C 1 and the information bits corresponding to x9 in U, Obtain the check bits corresponding to x1 in the check bit sequence C; perform an XOR operation on the intermediate check bits corresponding to x2 in C 1 and the information bits corresponding to x10 in U, and obtain the check bits corresponding to x2 in the check bit sequence C.
  • the middle check bit corresponding to x3 in C 1 is XORed with the information bit corresponding to x11 in U to obtain the check bit corresponding to x3 in the check bit sequence C; the middle check bit corresponding to x4 in C 1 is compared with U Perform an XOR operation on the information bits corresponding to x12 in the check bit sequence C to obtain the check bits corresponding to The check bit corresponding to x5 in the check bit sequence C; the middle check bit corresponding to x6 in C 1 is XORed with the information bit corresponding to x14 in U to obtain the check bit corresponding to x6 in the check bit sequence C.
  • the above-mentioned encoding of the information bit sequence according to the system polar code determines that the encoding complexity of the encoded bit sequence does not exceed K(log2N-1)+(NK)(log2N-1)+N, where K(log2N-1) corresponds to the steps Coding complexity of A1,
  • the coding complexity corresponding to step A3 does not exceed (NK)(log2N-1)+N.
  • the coding complexity of the XOR operation between C 1 and U in the above step A3 does not exceed N.
  • Step A2 is the mapping between bits. Involves coding complexity.
  • the complexity of the second non-systematic code encoding process is 2*8*log 2 (8); the encoding complexity of the embodiment of the present application is 1/2 of the two non-systematic code encoding processes.
  • a check code or a convolutional code can also be cascaded before the system polar code to improve the performance of the system polar code.
  • Different coding forms such as convolutional codes can be unified into pre-transforms corresponding to precoding matrices, and different coding forms correspond to different precoding matrices.
  • the schematic diagram of the pre-conversion system polar code can be cascaded between the pre-coding matrix and the polar transformation matrix of the system polar code. Through the pre-transformation corresponding to the pre-coding matrix and the polarization corresponding to the polar transformation matrix, It uses polar transform to encode, thereby reducing BER and improving the performance of the system polar code.
  • the precoding matrix may be an N-dimensional upper triangular matrix, that is, the upper triangular matrix has N rows and N columns, and N is the code length of the system polar code.
  • the N-dimensional upper triangular matrix T can be expressed as The number of rows of TA and TB is determined by the number of non-systematic bits in M A , the number of rows of TC is determined by the number of systematic bits in A, and the number of columns of TA is determined by the number of non-systematic bits in M A. The number of columns of TB and TC is determined based on the number of system bits in A.
  • the number of rows of TA and TB is NK
  • the number of rows of 0 and TC is K
  • the number of columns of 0 and TA is K
  • the number of columns of TA and TB is NK
  • 0 represents a matrix with all zero elements.
  • the information bit sequence is encoded according to the system polar code, and determining the encoded bit sequence can be implemented based on the following steps:
  • Step B1 Determine the first intermediate coding bit sequence according to the information bit sequence and the first polarization transformation sub-matrix, where the first polarization transformation sub-matrix is the polarization transformation sub-matrix corresponding to A in the polarization transformation matrix, that is, the first polarization transformation sub-matrix.
  • a polarization change sub-matrix is the sub-matrix of those rows in the polarization transformation matrix corresponding to the bit index of the second bit in A.
  • Step B2 Determine the third intermediate coded bit sequence based on the first intermediate coded bit sequence, TC and TB.
  • Step B3 Determine the fourth intermediate coded bit sequence based on the third intermediate coded bit sequence, the mutual mapping relationship between the frozen bits in C and the non-frozen bits in D, and the intersection of the bit indexes of B and M A.
  • Step B4 Determine the second intermediate coded bit sequence according to the fourth intermediate coded bit sequence and TA.
  • Step B5 Determine the coded bit sequence based on the second intermediate coded bit sequence, the second polarization transformation sub-matrix, and the information bit sequence, where the second polarization transformation sub-matrix is the polarization transformation corresponding to M A in the polarization transformation matrix.
  • the sub-matrix, that is, the second polarization change sub-matrix is the sub-matrix of those rows in the polarization transformation matrix corresponding to the bit index of the second bit in M A.
  • steps B1 and B5 can refer to the implementation of A1 and A3, and will not be described again.
  • X 3 (4) is the determined value of the corresponding bit index 3 in X 4 based on the value of the bit index 4 in When the values are in one-to-one correspondence, X 3 (4) is the value of the corresponding bit index 4 in X 3 .
  • Step B4 Multiply X 4 and A to get X 2 .
  • the encoding device outputs the encoded bit sequence, and accordingly, the decoding device obtains the symbol sequence to be decoded.
  • the coded bit sequence is modulated by the transmitter to obtain a modulation symbol, and the modulation symbol is received by the decoding device after being transmitted through the channel.
  • the decoding device demodulates the received modulation symbols to obtain a sequence of symbols to be decoded, where the sequence of symbols to be decoded corresponds to the sequence of coded bits, which is usually transformed by the coded bit sequence being interfered by factors such as noise in the channel, that is, the sequence of symbols to be decoded is obtained by demodulating the received modulation symbols.
  • the decoded symbol sequence can be understood as a coded bit sequence that is subject to channel interference.
  • the decoding device decodes the symbol sequence to be decoded according to the system polar code and determines the information bit sequence.
  • the decoding device determines the implementation of the above-mentioned A, MA , B, MB , C, and D
  • decoding methods such as SC decoding and SCL decoding may be used for decoding.
  • the decoding device can first use the symbol sequence to be decoded, the polarization transformation matrix, the mutual mapping relationship between the frozen bits in C and the non-frozen bits in D, and the bit indexes of B and M A. The intersection determines the first intermediate decoding bit sequence. Then, the information bit sequence is determined based on the first intermediate decoding bit sequence and the polarization transformation matrix.
  • the value of the non-frozen bit in D can be decoded first, and the value of the frozen bit in C is determined based on the value of the non-frozen bit in D.
  • the value of the non-frozen bit in D can be decoded first.
  • the decoding device can first use the SCL decoding method to determine the first intermediate decoding based on the symbol sequence X to be decoded, that is, the values of x0-x7, and the polarization transformation matrix G.
  • the bit sequence D 1 is the value of u0-u7.
  • the second decoding intermediate sequence D 2 is determined based on the determined product of D 1 and G.
  • the value corresponding to A(x4-x7) in D 2 is the information bit sequence.
  • the decoding device can use the CRC-assisted SCL decoding method to decode, that is, first decode according to the SCL decoding method to obtain L decoding paths.
  • the L decoding paths are The code path determines the value of the CRC encoding bit according to the value of the CRC bit, and selects the path determined by the CRC from the L decoding paths according to the decision result to output as the final decoding result.
  • K can also be equal to the length of the information bit sequence + the length of the check code bits (such as CRC bits) obtained by check encoding. That is, the position of the information bit included in A And the position of the check code bit (such as CRC bit) corresponding to the information bit.
  • the bit index of the bits included in A is equal to the sum of the bit index of the system bits that actually carry the information bit sequence and the bit index of the check encoding bits (such as CRC bits).
  • the check code is a CRC check code
  • the check code bits are CRC bits
  • the check code bits are CRC bits.
  • the CRC bits can be on the encoding side.
  • the CRC bits carried by the CRC bits are obtained by performing check encoding on the information bit sequence.
  • the obtained CRC bits and the information bit sequence are encoded by the system polar code together. .
  • the information bit sequence carried by the system bits (x5, x6, x7) that actually carries the information bit sequence can be CRC check encoded to determine the CRC bit (x4)
  • the carried CRC bits that is, the value of the CRC bits, concatenate the information bit sequence and the CRC bits as a new information bit sequence for encoding.
  • CRC bit x4 (that is, the carried CRC bit) needs to be satisfied, and the values of x5, x6, and x7 (that is, the actual carried information bit sequence) are verified and passed.
  • the check encoding is simple to implement, and by setting the CRC bits, the error correction capability of decoding can be improved and the reliability of decoding can be improved.
  • the CRC bits may be located on the side to be encoded, and the CRC bits carried by the CRC bits may be determined based on the non-CRC bit portion of the first intermediate coded bit sequence.
  • the first intermediate coded bit sequence may include a fifth intermediate coded bit sequence and CRC bits, the fifth intermediate coded bit sequence is determined according to the information bit sequence and the first polarization transform submatrix, and the CRC bit is determined according to the fifth intermediate coded bit sequence.
  • the value of the second bit corresponding to the CRC bit i.e., the coding side bit
  • the value of The product of the rows corresponding to the bit index is determined.
  • the first intermediate decoding bit sequence includes the second intermediate decoding bit sequence (corresponding to the values of u5, u6, u7) and CRC bits (corresponding to the value of u4).
  • the CRC bits are used to encode the second intermediate decoding bit sequence.
  • the code bit sequence is checked, in which the second intermediate decoding bit sequence corresponds to the position of the information bit (bit index 5, 6, 7), and the CRC bit corresponds to the position of the CRC bit (bit index 4).
  • the CRC bits are set on the side to be encoded (that is, the non-codeword side) of the system polar code, and the CRC bits form a check relationship with the encoded bit sequence on the side to be encoded, which is conducive to early stopping of decoding.
  • the CRC bits may also be located on the side to be encoded, and the CRC bits carried by the CRC bits are obtained by performing check encoding on the information bit sequence. That is, the first intermediate coded bit sequence may include a fifth intermediate coded bit sequence and CRC bits, the fifth intermediate coded bit sequence is determined based on the information bit sequence and the first polarization transform submatrix, and the CRC bits are determined based on the information bit sequence.
  • the sequence continues to be encoded.
  • the value of the second bit corresponding to the CRC bit i.e., the coding side bit
  • the value of The product of the rows corresponding to the bit index is determined.
  • the CRC bits (corresponding to the value of u4) in the first intermediate decoding bit sequence are used to check the information bit sequence (that is, the values of x5, x6, and x7).
  • This implementation can balance performance between the above two parity bit settings, and can obtain a performance balance between simple implementation of parity encoding and early decoding stop.
  • the encoding device and the decoding device include corresponding hardware structures and/or software modules that perform each function.
  • the units and method steps of each example described in conjunction with the embodiments disclosed in this application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed by hardware or computer software driving the hardware depends on the specific application scenarios and design constraints of the technical solution.
  • Figures 17 and 18 are schematic structural diagrams of possible communication devices provided by embodiments of the present application. These communication devices can be used to implement the functions of the encoding device or decoding device in the above method embodiments, and therefore can also achieve the beneficial effects of the above method embodiments.
  • the communication device 1700 includes a processing unit 1710 and an input and output unit 1720, where the input and output unit 1720 may also be a transceiver unit or an interface unit or an input and output interface.
  • the communication device 1700 may be used to implement the functions of the encoding device or the decoding device in the above method embodiment shown in FIG. 7 .
  • Input and output unit 1720 used to obtain the information bit sequence
  • the processing unit 1710 is configured to encode the information bit sequence according to the system polar code and determine the coded bit sequence, where the system polar code includes a polarization transformation matrix and N first bits and N corresponding to the polarization transformation matrix.
  • the second bits, the N second bits include the systematic bit set A and the non-systematic bit set M A
  • the N first bits include the frozen bit set B and the non-frozen bit set M B
  • B There is a frozen bit subset C in M and a non-frozen bit subset D in B.
  • the frozen bits in C map to the non-frozen bits in D.
  • C is determined based on the intersection of the bit indexes of B and A.
  • D is determined based on The intersection of bit indexes of M B and M A is determined
  • A is determined based on the information bit sequence
  • the coded bit sequence includes the information bit sequence;
  • the input and output unit 1720 is also used to output the encoded bit sequence.
  • the processing unit 1710 encodes the information bit sequence according to the system polar code.
  • the coded bit sequence it is specifically used to determine the first intermediate code according to the information bit sequence and the first polarization transformation submatrix.
  • Bit sequence where the first polarization transformation sub-matrix is the polarization transformation sub-matrix corresponding to A in the polarization transformation matrix; according to the first intermediate coded bit sequence, the frozen bits in C and the non-frozen bits in D are mapped to each other and the intersection of the bit indexes of B and M A to determine the second intermediate coded bit sequence, where the length of the second intermediate coded bit sequence is equal to the number of second bits included in M A ; and according to the second intermediate coded bits
  • the sequence, the second polarization transformation sub-matrix, and the information bit sequence determine the encoded bit sequence, where the second polarization transformation sub-matrix is the polarization transformation sub-matrix corresponding to M A in the polarization transformation matrix.
  • A is composed of the last K second bits among the N second bits; and/or, B is composed of NK selected according to channel reliability or code weight among the N first bits.
  • K is greater than or equal to At 1, and less than N.
  • the system polar code is cascaded with a precoding matrix, and the precoding matrix is an upper triangular matrix.
  • the number of rows of TA and TB is determined by the number of non-systematic bits in M A
  • the number of rows of TC is determined by the number of systematic bits in A
  • the number of columns of TA is determined by the number of non-systematic bits in M A. Determine, the number of columns of TB and TC is determined based on the number of system bits in A;
  • the processing unit 1710 encodes the information bit sequence according to the system polar code, and when determining the coded bit sequence, is specifically used to determine the first intermediate coded bit sequence according to the information bit sequence and the first polarization transformation sub-matrix, where the first polarization
  • the transformation submatrix is the polarization transformation submatrix corresponding to A in the polarization transformation matrix; according to the first intermediate coding bit sequence, TC and TB, the third intermediate coding bit sequence is determined; according to the third intermediate coding bit sequence, the freeze in C
  • the mutual mapping relationship between the bits and the non-frozen bits in D, and the intersection of the bit indexes of B and M A determine the fourth intermediate coded bit sequence; according to the fourth intermediate coded bit sequence and TA, the second intermediate coded bit sequence is determined ; Determine the coded bit sequence based on the second intermediate coded bit sequence, the second polarization transformation sub-matrix, and the information bit sequence, where the second polarization transformation sub-matrix is the polarization
  • A is determined based on the information bit sequence, including: the position of the information bit included in A and the position of the CRC bit corresponding to the information bit.
  • the first intermediate coded bit sequence includes a fifth intermediate coded bit sequence and CRC bits
  • the fifth intermediate coded bit sequence is determined based on the information bit sequence and the first polarization transformation submatrix
  • the CRC bits are determined based on the fifth intermediate coded bit sequence.
  • the intermediate coded bit sequence is determined.
  • the first intermediate coded bit sequence includes a fifth intermediate coded bit sequence and CRC bits.
  • the fifth intermediate coded bit sequence is determined based on the information bit sequence and the first polarization transformation submatrix.
  • the CRC bits are determined based on the information bits. Sequence determined.
  • the mutual mapping of the frozen bits in C and the non-frozen bits in D includes: the frozen bits in C and the non-frozen bits in D are mapped to each other according to a mapping matrix, and the mapping matrix is N A C -dimensional full-rank matrix or an N C -dimensional identity matrix, N C is equal to the number of frozen bits in C.
  • Input and output unit 1720 used to obtain the symbol sequence to be decoded
  • the processing unit 1710 is configured to decode the sequence of symbols to be decoded according to the system polar code and determine the information bit sequence, where the system polar code includes a polarization transformation matrix and the N first bits corresponding to the polarization transformation matrix.
  • the N second bits include the systematic bit set A and the non-systematic bit set M A
  • the N first bits include the frozen bit set B and the non-frozen bit set M B
  • there is a non-frozen bit subset D in B there is a non-frozen bit subset D in B.
  • the frozen bits in C map to the non-frozen bits in D.
  • C is determined based on the intersection of the bit indexes of B and A.
  • D is determined based on the intersection of bit indexes of MB and MA
  • A is determined based on the information bit sequence.
  • the processing unit 1710 decodes the symbol sequence to be decoded according to the system polar code.
  • the information bit sequence it is specifically used to decode the symbol sequence to be decoded, the polarization transformation matrix, and the frozen value in C
  • the mutual mapping relationship between the bits and the non-frozen bits in D, and the intersection of the bit indexes of B and M A determine the first intermediate decoding bit sequence; according to the first intermediate decoding bit sequence and the polarization transformation matrix, determine sequence of information bits.
  • A is composed of the last K second bits among the N second bits; and/or, B is composed of NK selected according to channel reliability or code weight among the N first bits. It consists of the first bits, K is greater than or equal to 1 and less than N.
  • A is determined based on the information bit sequence, including: the position of the information bit included in A and the position of the CRC bit corresponding to the information bit.
  • the first intermediate decoding bit sequence includes a second intermediate decoding bit sequence and CRC bits, and the CRC bits are used to check the second intermediate decoding bit sequence, wherein the second intermediate decoding bit sequence
  • the bit sequence corresponds to the position of the information bit
  • the CRC bit corresponds to the position of the CRC bit.
  • the first intermediate decoding bit sequence includes a second intermediate decoding bit sequence and CRC bits.
  • the CRC bits are used to verify the information bit sequence, where the second intermediate decoding bit sequence corresponds to the information.
  • the position of the bit, the CRC bit corresponds to the position of the CRC bit.
  • the mutual mapping of the frozen bits in C and the non-frozen bits in D includes: the frozen bits in C and the non-frozen bits in D are mapped to each other according to a mapping matrix, and the mapping matrix is N A C -dimensional full-rank matrix or an N C -dimensional identity matrix, N C is equal to the number of frozen bits in C.
  • the communication device 1800 includes a processor 1810 and an interface circuit 1820 .
  • the processor 1810 and the interface circuit 1820 are coupled to each other.
  • the interface circuit 1820 may be a transceiver or an input-output interface.
  • the communication device 1800 may also include a memory 1830 for storing instructions executed by the processor 1810 or input data required for the processor 1810 to run the instructions or data generated after the processor 1810 executes the instructions.
  • the memory 1830 can also be integrated with the processor 1810.
  • the processor 1810 is used to implement the functions of the above-mentioned processing unit 1710
  • the interface circuit 1820 is used to implement the functions of the above-mentioned input and output unit 1720.
  • processor in the embodiment of the present application can be a central processing unit (CPU), or other general-purpose processor, digital signal processor (DSP), or application-specific integrated circuit (application specific integrated circuit, ASIC), field programmable gate array (field programmable gate array, FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof.
  • CPU central processing unit
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • a general-purpose processor can be a microprocessor or any conventional processor.
  • the method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions.
  • Software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory In memory, register, hard disk, mobile hard disk, CD-ROM or any other form of storage medium well known in the art.
  • An exemplary storage medium is coupled to the processor such that the processor can read information from the storage medium and write information to the storage medium.
  • the storage medium can also be an integral part of the processor.
  • the processor and storage media may be located in an ASIC. Additionally, the ASIC can be located in network equipment or terminal equipment. Of course, the processor and the storage medium can also exist as discrete components in network equipment or terminal equipment.
  • the computer program product includes one or more computer programs or instructions.
  • the computer may be a general purpose computer, a special purpose computer, a computer network, a network device, a user equipment, or other programmable device.
  • the computer program or instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another.
  • the computer program or instructions may be transmitted from a website, computer, A server or data center transmits via wired or wireless means to another website site, computer, server, or data center.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer or may be an integrated Data storage equipment such as media servers and data centers.
  • the available media may be magnetic media, such as floppy disks, hard disks, and tapes; optical media, such as digital video optical disks; or semiconductor media, such as solid-state hard drives.
  • the computer-readable storage medium may be volatile or nonvolatile storage media, or may include both volatile and nonvolatile types of storage media.
  • information information
  • signal signal
  • message messages
  • channel channel

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Abstract

本申请涉及通信技术领域，公开了一种编码、译码方法及装置，通过引入比特位映射，能够解耦系统极化码的系统比特位和冻结比特位，带来更大的编码设计空间，降低系统极化码编码的复杂度。该方法包括：获取信息比特序列；根据系统极化码对信息比特序列进行编码，确定编码比特序列，系统极化码包括与极化变换矩阵对应的N个第一比特位和N个第二比特位，N个第二比特位中包括系统比特位集合A和非系统比特位集合MA，N个第一比特位中包括冻结比特位集合B和非冻结比特位集合MB，B中存在子集C、MB中存在子集D，C与D比特位相互映射，C根据B与A的比特位索引交集确定，D根据MB与MA的比特位索引交集确定，A根据信息比特序列确定。

Description

一种编码、译码方法及装置
相关申请的交叉引用
本申请要求在2022年05月23日提交中国专利局、申请号为202210566961.3、申请名称为“一种编码、译码方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及通信技术领域，尤其涉及一种编码、译码方法及装置。
背景技术
第五代(5th generation，5G)移动通信系统中，最典型的三个通信场景包括增强移动宽带(enhanced mobile broadband，eMBB)、海量机器类通信(massive machine type of communication，mMTC)和超可靠低延迟通信(ultra reliable low latency communication，URLLC)。信道编码作为基本的无线接入技术，是满足5G通信需求的重要研究对象之一。极化码(polar code)在5G标准中被选作控制编码方案。极化码也可以称为polar码，是第一种、也是已知的唯一一种能够被严格证明“达到”香农信道容量的信道编码方案。在不同码长下，尤其对于有限码，polar码的性能远优于Turbo码和低密度奇偶校验码(low density parity check，LDPC)码。另外，polar码在编译码方面具有较低的计算复杂度。这些优点让polar码在5G中具有很大的发展和应用前景。
系统polar码是指信息比特直接承载在码字侧的系统比特位的polar码，相对于非系统polar码，系统polar码具有比特出错概率(bit error ratio，BER)性能更好、更方便与其它码级联、应用广泛(如能够进行联合信源信道编码(joint source-channel coding，JSCC))等优点。然而，现有系统polar码在编码时，由于系统比特位与冻结比特位之间的位置关系存在相互耦合，编码过程要求串行执行，或者多次并行执行非系统polar码编码过程，存在编码复杂度高、灵活性不足的问题。
发明内容
本申请实施例提供一种编码、译码方法及装置，通过引入比特位映射，能够解耦系统极化码的系统比特位和冻结比特位，以期带来更大的编码设计空间，降低编码的复杂度，提高编码的灵活性。
第一方面，本申请实施例提供一种编码方法，该方法包括：获取信息比特序列；根据系统极化码对信息比特序列进行编码，确定编码比特序列，其中系统极化码包括极化变换矩阵和与极化变换矩阵对应的N个第一比特位和N个第二比特位，N个第二比特位中包括系统比特位集合A和非系统比特位集合MA，N个第一比特位中包括冻结比特位集合B和非冻结比特位集合MB，B中存在冻结比特位子集C、MB中存在非冻结比特位子集D，C中的冻结比特位与D中的非冻结比特位相互映射，C根据B与A的比特位索引交集确定，D根据MB与MA的比特位索引交集确定，A根据信息比特序列确定，编码比特序列包括 信息比特序列；输出编码比特序列。
上述编码方法，可以由编码设备，如网络设备或终端设备等执行，也可以由编码设备的部件(例如处理器、芯片、或芯片系统等)执行，还可以由能实现全部或部分编码设备功能的逻辑模块或软件实现。
另外，需要理解的是，对于系统极化码，系统比特位可用于承载信息比特序列，系统比特位和冻结比特位的总数量等于系统极化码的码长N，因此在本申请实施例中，A可以根据信息比特序列确定。例如：信息比特序列的长度为K，则A中包括K个系统比特位、B中包括N-K个冻结比特位，MA中包括N-K个非系统比特位、MB中包括K个非冻结比特位。
采用上述方法，通过引入C中的冻结比特位与D中的非冻结比特位相互映射的关系(比如C中的冻结比特位的值与D中比特位的值一一对应相同)，编码时D中的非冻结比特位的值(即非冻结比特位所承载的比特)可以根据C中冻结比特位的值(即冻结比特位所承载的比特)来确定，译码时C中冻结比特位的值可以根据D中的非冻结比特位的值来确定，能够使得系统极化码的冻结比特位和系统比特位的比特位索引可以有重叠，解耦系统极化码的系统比特位和冻结比特位，带来更大的编码设计空间，从而降低编码的复杂度，提高编码的灵活性。
作为一种示例：对于码长为8的系统极化码，通过引入比特位索引为4的冻结比特位与比特位索引为3的非冻结比特位相互映射的关系，冻结比特位的比特位索引可以为0、1、2、4，系统比特位的比特位索引可以为4、5、6、7，在编码过程中比特位索引为3的非冻结比特位的值可以根据比特位索引为4的冻结比特位的值来确定，可以将码长为8的系统极化码对应比特位索引0、1、2、3、4、5、6、7的编码问题，拆分成分别对应比特位索引0、1、2、3和对应比特位索引4、5、6、7的两个子编码问题，每个子编码问题均可以进行并行编码，编码复杂度与执行一次非系统极化码编码过程相当，能够降低编码复杂度，并且可以适用于多种系统比特位设置方式，能够提高编码的灵活性。
可选地，C中的冻结比特位与D中的非冻结比特位相互映射包括：C中的冻结比特位与D中的非冻结比特位根据映射矩阵相互映射，映射矩阵为NC维的满秩矩阵或者为NC维的单位阵，NC等于C中冻结比特位的个数。
在一种可能的设计中，根据系统极化码对信息比特序列进行编码，确定编码比特序列，包括：根据信息比特序列和第一极化变换子矩阵，确定第一中间编码比特序列，其中第一极化变换子矩阵为极化变换矩阵中对应A的极化变换子矩阵；根据第一中间编码比特序列、C中的冻结比特位与D中的非冻结比特位相互映射的关系、以及B与MA的比特位索引交集，确定第二中间编码比特序列，其中第二中间编码比特序列长度等于MA包含的第二比特位的个数；根据第二中间编码比特序列、第二极化变换子矩阵、以及信息比特序列，确定编码比特序列，其中第二极化变换子矩阵为极化变换矩阵中对应MA的极化变换子矩阵。
采用上述方法，可以将码长为N的系统极化码对应比特位索引0、1、…N的编码问题，拆分成分别对应A的比特位索引和MA的比特位索引的两个子编码问题，每个子编码问题进行并行编码，编码复杂度与执行一次非系统极化码编码过程相当，能够降低编码复杂度。
在一种可能的设计中，A由N个第二比特位中的后K个第二比特位构成；和/或，B由N个第一比特位中按照信道可靠度或者码重选取的N-K个第一比特位构成，K大于或等于1、且小于N。例如，B可以由N个第一比特位中按照信道可靠度选取的信道可靠度最 低的N-K个第一比特构成，或者由N个第一比特位中按照码重选取的码重最低的N-K个第一比特构成。
上述设计中，直接将N个第二比特位中的后K个第二比特位作为系统比特位，可以简化编码过程，提高编码效率。
在一种可能的设计中，系统极化码与预编码矩阵级联，预编码矩阵为上三角矩阵其中TA和TB的行数根据MA中非系统比特位的个数确定、TC的行数根据A中系统比特位的个数确定，TA的列数根据MA中非系统比特位的个数确定、TB和TC的列数根据A中系统比特位的个数确定；
根据系统极化码对信息比特序列进行编码，确定编码比特序列，包括：根据所述信息比特序列和第一极化变换子矩阵，确定第一中间编码比特序列，其中所述第一极化变换子矩阵为所述极化变换矩阵中对应所述A的极化变换子矩阵；根据第一中间编码比特序列、TC和TB，确定第三中间编码比特序列；根据第三中间编码比特序列、C中的冻结比特位与D中的非冻结比特位相互映射的关系、B与MA的比特位索引交集，确定第四中间编码比特序列；根据第四中间编码比特序列和TA，确定第二中间编码比特序列；根据第二中间编码比特序列、第二极化变换子矩阵、以及信息比特序列，确定编码比特序列，其中第二极化变换子矩阵为极化变换矩阵中对应MA的极化变换子矩阵。
上述设计中，可以通过级联预编码矩阵来对系统极化码的码谱进行优化，提高系统极化码的性能。
在一种可能的设计中，A根据信息比特序列确定，包括：A中包括信息比特的位置以及信息比特对应的循环冗余校验(cyclic redundancy check，CRC)比特的位置。
上述设计中，通过设置信息比特对应的CRC比特，可以提高译码的纠错能力，提高译码的可靠性，且实现简单。
在一种可能的设计中，第一中间编码比特序列包括第五中间编码比特序列和CRC比特，第五中间编码比特序列根据信息比特序列和第一极化变换子矩阵确定，CRC比特根据第五中间编码比特序列确定。
上述设计中，将CRC比特设置在系统极化码的待编码侧(即非码字侧)，且CRC比特与待编码侧的编码比特序列形成校验关系，有利于译码的早停。
在一种可能的设计中，第一中间编码比特序列包括第五中间编码比特序列和CRC比特，第五中间编码比特序列根据信息比特序列和第一极化变换子矩阵确定，CRC比特根据信息比特序列确定。
上述设计中，通过设置信息比特对应的CRC比特，可以提高译码的纠错能力，提高译码的可靠性。
第二方面，本申请实施例提供一种译码方法，该方法包括：获取待译码符号序列；根据系统极化码对待译码符号序列进行译码，确定信息比特序列，其中系统极化码包括极化变换矩阵和与极化变换矩阵对应的N个第一比特位和N个第二比特位，N个第二比特位中包括系统比特位集合A和非系统比特位集合MA，N个第一比特位中包括冻结比特位集合B和非冻结比特位集合MB，B中存在冻结比特位子集C、MB中存在非冻结比特位子集D，C中的冻结比特位与D中的非冻结比特位相互映射，C根据B与A的比特位索引交集确定，D根据MB与MA的比特位索引交集确定，A根据信息比特序列确定。
上述译码方法，可以由译码设备，如网络设备或终端设备等执行，也可以由译码设备 的部件(例如处理器、芯片、或芯片系统等)执行，还可以由能实现全部或部分译码设备功能的逻辑模块或软件实现。
另外，需要理解的是，对于系统极化码，系统比特位可用于承载信息比特序列，系统比特位和冻结比特位的总数量等于系统极化码的码长N，因此在本申请实施例中，A可以根据信息比特序列确定。例如：信息比特序列的长度为K，则A中包括K个系统比特位、B中包括N-K个冻结比特位，MA中包括N-K个非系统比特位、MB中包括K个非冻结比特位。
可选地，C中的冻结比特位与D中的非冻结比特位相互映射包括：C中的冻结比特位与D中的非冻结比特位根据映射矩阵相互映射，映射矩阵为NC维的满秩矩阵或者为NC维的单位阵，NC等于C中冻结比特位的个数。
在一种可能的设计中，根据系统极化码对待译码符号序列进行译码，确定信息比特序列，包括：根据待译码符号序列、极化变换矩阵、C中的冻结比特位与D中的非冻结比特位相互映射的关系、以及B与MA的比特位索引交集，确定第一中间译码比特序列；根据第一中间译码比特序列和极化变换矩阵，确定信息比特序列。
在一种可能的设计中，A由N个第二比特位中的后K个第二比特位构成；和/或，B由N个第一比特位中按照信道可靠度或者码重选取的N-K个第一比特位构成，K大于或等于1、且小于N。
在一种可能的设计中，A根据信息比特序列确定，包括：A中包括信息比特的位置以及信息比特对应的CRC比特的位置。
在一种可能的设计中，第一中间译码比特序列中包括第二中间译码比特序列和CRC比特，CRC比特用于对第二中间译码比特序列进行校验，其中第二中间译码比特序列对应信息比特的位置，CRC比特对应CRC比特的位置。
在一种可能的设计中，第一中间译码比特序列中包括第二中间译码比特序列和CRC比特，CRC比特用于对信息比特序列进行校验，其中第二中间译码比特序列对应信息比特的位置，CRC比特对应CRC比特的位置。
第三方面，本申请实施例提供一种通信装置，该通信装置可以包括：输入输出单元和处理单元，输入输出单元，用于获取信息比特序列；处理单元，用于根据系统极化码对信息比特序列进行编码，确定编码比特序列，其中系统极化码包括极化变换矩阵和与极化变换矩阵对应的N个第一比特位和N个第二比特位，N个第二比特位中包括系统比特位集合A和非系统比特位集合MA，N个第一比特位中包括冻结比特位集合B和非冻结比特位集合MB，B中存在冻结比特位子集C、MB中存在非冻结比特位子集D，C中的冻结比特位与D中的非冻结比特位相互映射，C根据B与A的比特位索引交集确定，D根据MB与MA的比特位索引交集确定，A根据信息比特序列确定，编码比特序列包括信息比特序列；输入输出单元，还用于输出编码比特序列。
可选地，C中的冻结比特位与D中的非冻结比特位相互映射包括：C中的冻结比特位与D中的非冻结比特位根据映射矩阵相互映射，映射矩阵为NC维的满秩矩阵或者为NC维的单位阵，NC等于C中冻结比特位的个数。
在一种可能的设计中，处理单元根据系统极化码对信息比特序列进行编码，确定编码比特序列时，具体用于根据信息比特序列和第一极化变换子矩阵，确定第一中间编码比特序列，其中第一极化变换子矩阵为极化变换矩阵中对应A的极化变换子矩阵；根据第一中 间编码比特序列、C中的冻结比特位与D中的非冻结比特位相互映射的关系、以及B与MA的比特位索引交集，确定第二中间编码比特序列，其中第二中间编码比特序列长度等于MA包含的第二比特位的个数；以及根据第二中间编码比特序列、第二极化变换子矩阵、以及信息比特序列，确定编码比特序列，其中第二极化变换子矩阵为极化变换矩阵中对应MA的极化变换子矩阵。
在一种可能的设计中，A由N个第二比特位中的后K个第二比特位构成；和/或，B由N个第一比特位中按照信道可靠度或者码重选取的N-K个第一比特位构成，K大于或等于1、且小于N。
在一种可能的设计中，系统极化码与预编码矩阵级联，预编码矩阵为上三角矩阵其中TA和TB的行数根据MA中非系统比特位的个数确定、TC的行数根据A中系统比特位的个数确定，TA的列数根据MA中非系统比特位的个数确定、TB和TC的列数根据A中系统比特位的个数确定；
处理单元根据系统极化码对信息比特序列进行编码，确定编码比特序列时，具体用于根据信息比特序列和第一极化变换子矩阵，确定第一中间编码比特序列，其中第一极化变换子矩阵为极化变换矩阵中对应A的极化变换子矩阵；根据第一中间编码比特序列、TC和TB，确定第三中间编码比特序列；根据第三中间编码比特序列、C中的冻结比特位与D中的非冻结比特位相互映射的关系、B与MA的比特位索引交集，确定第四中间编码比特序列；根据第四中间编码比特序列和TA，确定第二中间编码比特序列；根据第二中间编码比特序列、第二极化变换子矩阵、以及信息比特序列，确定编码比特序列，其中第二极化变换子矩阵为极化变换矩阵中对应MA的极化变换子矩阵。
在一种可能的设计中，A根据信息比特序列确定，包括：A中包括信息比特的位置以及信息比特对应的CRC比特的位置。
在一种可能的设计中，第一中间编码比特序列包括第五中间编码比特序列和CRC比特，第五中间编码比特序列根据信息比特序列和第一极化变换子矩阵确定，CRC比特根据第五中间编码比特序列确定。
在一种可能的设计中，第一中间编码比特序列包括第五中间编码比特序列和CRC比特，第五中间编码比特序列根据信息比特序列和第一极化变换子矩阵确定，CRC比特根据信息比特序列确定。
第四方面，本申请实施例提供一种通信装置，该通信装置可以包括：输入输出单元和处理单元，输入输出单元，用于获取待译码符号序列；处理单元，用于根据系统极化码对待译码符号序列进行译码，确定信息比特序列，其中系统极化码包括极化变换矩阵和与极化变换矩阵对应的N个第一比特位和N个第二比特位，N个第二比特位中包括系统比特位集合A和非系统比特位集合MA，N个第一比特位中包括冻结比特位集合B和非冻结比特位集合MB，B中存在冻结比特位子集C、MB中存在非冻结比特位子集D，C中的冻结比特位与D中的非冻结比特位相互映射，C根据B与A的比特位索引交集确定，D根据MB与MA的比特位索引交集确定，A根据信息比特序列确定。
可选地，C中的冻结比特位与D中的非冻结比特位相互映射包括：C中的冻结比特位与D中的非冻结比特位根据映射矩阵相互映射，映射矩阵为NC维的满秩矩阵或者为NC维的单位阵，NC等于C中冻结比特位的个数。
在一种可能的设计中，处理单元根据系统极化码对待译码符号序列进行译码，确定信 息比特序列时，具体用于根据待译码符号序列、极化变换矩阵、C中的冻结比特位与D中的非冻结比特位相互映射的关系、以及B与MA的比特位索引交集，确定第一中间译码比特序列；根据第一中间译码比特序列和极化变换矩阵，确定信息比特序列。
在一种可能的设计中，A由N个第二比特位中的后K个第二比特位构成；和/或，B由N个第一比特位中按照信道可靠度或者码重选取的N-K个第一比特位构成，K大于或等于1、且小于N。
在一种可能的设计中，A根据信息比特序列确定，包括：A中包括信息比特的位置以及信息比特对应的CRC比特的位置。
在一种可能的设计中，第一中间译码比特序列中包括第二中间译码比特序列和CRC比特，CRC比特用于对第二中间译码比特序列进行校验，其中第二中间译码比特序列对应信息比特的位置，CRC比特对应CRC比特的位置。
在一种可能的设计中，第一中间译码比特序列中包括第二中间译码比特序列和CRC比特，CRC比特用于对信息比特序列进行校验，其中第二中间译码比特序列对应信息比特的位置，CRC比特对应CRC比特的位置。
第五方面，本申请实施例提供一种通信装置，该通信装置包括接口电路和处理器，处理器和接口电路之间相互耦合。处理器通过逻辑电路或执行代码指令用于实现上述第一方面或者第一方面的任一种可能的设计中的方法。接口电路用于接收来自该通信装置之外的其它通信装置的信号并传输至处理器或将来自处理器的信号发送给该通信装置之外的其它通信装置。可以理解的是，接口电路可以为收发器或收发机或收发信机或输入输出接口。
可选的，通信装置还可以包括存储器，用于存储处理器执行的指令或存储处理器运行指令所需要的输入数据或存储处理器运行指令后产生的数据。存储器可以是物理上独立的单元，也可以与处理器耦合，或者处理器包括该存储器。
第六方面，本申请实施例提供一种通信装置，该通信装置包括接口电路和处理器，处理器和接口电路之间相互耦合。处理器通过逻辑电路或执行代码指令用于实现上述第二方面或者第二方面的任一种可能的设计中的方法。接口电路用于接收来自该通信装置之外的其它通信装置的信号并传输至处理器或将来自处理器的信号发送给该通信装置之外的其它通信装置。可以理解的是，接口电路可以为收发器或收发机或收发信机或输入输出接口。
可选的，通信装置还可以包括存储器，用于存储处理器执行的指令或存储处理器运行指令所需要的输入数据或存储处理器运行指令后产生的数据。存储器可以是物理上独立的单元，也可以与处理器耦合，或者处理器包括该存储器。
第七方面，本申请实施例提供一种通信系统，该通信系统包括编码设备和译码设备，编码设备可以实现上述第一方面或者第一方面的任一种可能的设计中的方法，译码设备可以实现上述第二方面或者第二方面的任一种可能的设计中的方法。
第八方面，本申请实施例提供一种计算机可读存储介质，在存储介质中存储有计算机程序或指令，当计算机程序或指令被执行时，可以实现上述第一方面或者第一方面的任一种可能的设计中的方法，或实现上述第二方面或者第二方面的任一种可能的设计中的方法。
第九方面，本申请实施例还提供一种计算机程序产品，包括计算机程序或指令，当计算机程序或指令被执行时，可以实现上述第一方面或者第一方面的任一种可能的设计中的方法，或实现上述第二方面或者第二方面的任一种可能的设计中的方法。
第十方面，本申请实施例还提供一种芯片，该芯片与存储器耦合，用于读取并执行存 储器中存储的程序或指令，实现上述第一方面或者第一方面的任一种可能的设计中的方法，或实现上述第二方面或者第二方面的任一种可能的设计中的方法。
上述第二方面至第十方面所能达到的技术效果请参照上述第一方面所能达到的技术效果，这里不再重复赘述。
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图1为本申请实施例提供的通信系统的架构示意图；
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图5为本申请实施例提供的系统极化码示意图之一；
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具体实施方式
本申请实施例的技术方案可以应用于各种通信系统，例如：全球移动通信系统(global system for mobile communications，GSM)、增强型数据速率GSM演进系统(enhanced data rate for GSM evolution，EDGE)、宽带码分多址系统(wideband code division multiple access，WCDMA)、时分同步码分多址系统(time division-synchronization code division multiple access，TD-SCDMA)、长期演进(long term evolution，LTE)系统、全球互联微波接入(worldwide interoperability for microwave access，WiMAX)通信系统、第五代(5th generation，5G)移动通信系统，如新无线(new radio，NR)系统等。本申请提供的技术方案还可以应用于未来的通信系统，如第六代移动通信系统等。通信系统还可以是蓝牙(bluetooth)通信系统、无线局域网(wireless local area network，WLAN)/无线通信技术(WiFi)通信系统、窄带物联网(narrow band internet of things，NB-IoT)通信系统等。
图1为本申请的实施例应用的一种通信系统的架构示意图。如图1所示，该通信系统包括网络设备和终端设备，其中网络设备的数量是以1个，终端设备的数量是以2个(终端设备A和终端设备B)为例。其中，网络设备为发送端时，终端设备A或终端设备B 为接收端；当终端设备A或终端设备B为发送端时，网络设备为接收端。
上述的终端设备也可以称为终端、用户设备(user equipment，UE)、移动台、移动终端等。终端设备可以广泛应用于各种场景，例如，设备到设备(device-to-device，D2D)、车到一切(vehicle to everything，V2X)通信、机器类通信(machine-type communication，MTC)、物联网(internet of things，IoT)、虚拟现实、增强现实、工业控制、自动驾驶、远程医疗、智能电网、智能家具、智能办公、智能穿戴、智能交通、智慧城市等。终端设备可以是手机、平板电脑、带无线收发功能的电脑、可穿戴设备、车辆、无人机、直升机、飞机、轮船、机器人、机械臂、智能家居设备、车载终端、IoT终端、可穿戴设备等。本申请的实施例对终端设备所采用的具体技术和具体设备形态不做限定。
网络设备也可以称为接入网(access network，AN)设备，或无线接入网(radio access network，RAN)设备。可以是基站(base station)、演进型基站(evolved NodeB，eNodeB)、收发点(transmitter and receiver point，TRP)、集成接入和回传(integrated access and backhauling，IAB)节点、第五代(5th generation，5G)移动通信系统中的下一代基站(next generation NodeB，gNB)、第六代(6th generation，6G)移动通信系统中的基站、其他未来移动通信系统中的基站或WiFi系统中的接入节点、家庭基站(例如，home evolved nodeB，或home node B，HNB)、无线保真(wireless fidelity，WIFI)系统中的接入点(access point，AP)、无线中继节点、无线回传节点等。也可以是完成基站部分功能的模块或单元，例如，可以是集中式单元(central unit，CU)，也可以是分布式单元(distributed unit，DU)。这里的CU完成基站的无线资源控制协议和分组数据汇聚层协议(packet data convergence protocol，PDCP)的功能，还可以完成业务数据适配协议(service data adaptation protocol，SDAP)的功能；DU完成基站的无线链路控制层和介质访问控制(medium access control，MAC)层的功能，还可以完成部分物理层或全部物理层的功能，有关上述各个协议层的具体描述，可以参考第三代合作伙伴计划(3rd generation partnership project，3GPP)的相关技术规范。网络设备还可以是非地面(non-terrestrial)基站，如低地球轨道(low earth orbit，LEO)/极低地球轨道(very low earth orbit，VLEO)卫星、高空平台站(high-attitude platform station，HAPS)，还可以是V2X、D2D和机器到机器(machine to machine，M2M)通信中承担网络设备功能的终端等。
在本申请的实施例中，网络设备的功能也可以由网络设备中的模块(如芯片)来执行，也可以由包含有网络设备功能的控制子系统来执行。这里的包含有网络设备功能的控制子系统可以是智能电网、工业控制、智能交通、智慧城市等上述应用场景中的控制中心。终端设备的功能也可以由终端设备中的模块(如芯片或调制解调器)来执行，也可以由包含有终端设备功能的装置来执行。
仍以图1所示的通信系统为例，为了保证设备间通信的可靠性，可对信息进行编译码处理，可参阅图2所示的编译码流程进行处理，发送端的信源依序经过信源编码、信道编码以及调制后输出调制符号，接收端接收到调制符号后依序经过解调、信道译码、信源恢复得到信宿，接收端基于信宿可以获取有用信息。
为了便于本领域技术人员理解，下面对本申请实施例中的部分用语进行解释说明。
1)、上三角矩阵，主对角线以下都是零的方阵称为上三角矩阵。上三角矩阵具有行列式为对角线元素相乘、上三角矩阵乘以系数后也是上三角矩阵、上三角矩阵间的加减法和乘法运算的结果仍是上三角矩阵等性质。
2)、polar码编码，polar码也是一种线性块码，极化变换矩阵为GN，极化变换矩阵也可以记为G，极化变换矩阵也可以称为编码矩阵或生成矩阵。编码过程为其中是一个二进制的行矢量，也即一个二进制的序列，长度为N，N为polar码码长；GN是一个N×N的矩阵，且 可定义为log2N个矩阵F2的克罗内克(kronecker)乘积。其中
polar码的编码过程中，中的一部分比特用来携带信息，携带信息的比特称为信息比特，用来携带信息的这部分比特形成信息比特集合，这些比特的比特位索引的集合记作另外的一部分比特设置为接收端和发送端预先约定的固定值，称之为固定比特集合或冻结比特集合(frozen bits)，其比特位索引的集合用的补集表示。polar码的编码过程相当于：这里，GN(A)是GN中由集合中的比特位索引对应的那些行得到的子矩阵，GN(AC)是GN中由集合中的比特位索引对应的那些行得到的子矩阵。为中的信息比特集合，数量为K；为中的冻结比特集合，其数量为(N-K)，是已知比特。这些冻结比特通常被设置为0，但是只要接收端和发送端预先约定，冻结比特可以被任意设置。从而，polar码的编码输出可简化为：这里为中的信息比特集合，为长度K的行矢量，即|·|表示集合中元素的个数，K为信息块大小或者K为信息比特的数目，或者K为信息比特集合的大小，是矩阵GN中由集合中的比特位索引对应的那些行得到的子矩阵，是一个K×N的矩阵。
polar码的构造过程即集合的选取过程，决定了polar码的性能。polar码的构造过程通常是，根据码长N确定共存在N个极化信道，分别对应极化变换矩阵的N个行，计算极化信道的信道可靠度，将信道可靠度较高的前K个极化信道的比特位索引作为集合的元素，剩余(N-K)个极化信道对应的比特位索引作为冻结比特的比特位索引集合的元素。集合决定了信息比特的位置，集合决定了冻结比特的位置。
如图3所示，展示了一个8×8的极化变换矩阵，图3示例性示出一种具体的编码的过程，其中左侧可理解为待编码侧，左侧的比特位用u表示，右侧可理解为编码侧(或码字侧)，右侧的比特位用x表示，从左往右的过程即发送端对待编码比特序列进行编码的过程。其中待编码的信息比特以序列u(0，0，0，0，0，0，1，1)表示，经过极化变换矩阵，编码后的比特以序列x(0，1，0，1，0，1，0，1)表示，将x映射成调制符号则可在信道W传输。其中，高信道可靠度对应的比特位用于映射信息比特，低信道可靠度对应的比特位用于映射冻结比特。如图3中所示，{u0，u1，u2，u4}为冻结比特位，即为冻结比特的位置，{u3，u5，u6，u7}为信息比特位，即为信息比特的位置。
参见图3继续说明，在编码过程中，相邻两列即为一个编码层，左边一列比特为编码层的输入比特，右边一列比特为编码层的输出比特。比如最左侧的编码层中，输入比特序列(0，0，0，0，0，0，1，1)，输出比特序列(0，0，0，0，0，0，0，1)。编码层中间的操作符号“⊕”表示异或操作，“⊕”表示“⊕”所在行的比特与“⊕”所达行的比特之间的一次异或操作，“⊕”右侧的比特即为操作结果。比如最左侧编码层中，第一个输入比特(取 值0)与第二个输入比特(取值0)执行“⊕”操作得到第一个输出比特(取值0)。
3)、polar码译码，连续删除(successive cancellation，SC)译码方法是一种有效的polar码的译码算法。译码设备获取到待译码符号序列后，基于待译码符号序列，逐个计算信息比特的对数似然比(log likelihood ratio，LLR)，若信息比特的LLR>0，则译码结果为0，若信息比特的LLR<0，则译码结果为1，冻结比特无论LLR为多少译码结果都置为0。
SC译码方法的性能较差，前一个译码比特的结果作为后一个译码比特计算的一个输入，一旦判错，会导致错误扩散，且没有机会挽回，因此译码性能不高。为解决这一问题，在逐次消除列表算法(successive cancellation list，SCL)中，SCL算法在译码每个信息比特时，将0和1对应的译码结果都保存作为2个分支译码路径(简称路径分裂)，图4为SCL算法中的译码路径示意图，如图4所示，每一层代表1个译码比特，若译码结果为0，则沿着左子树发展路径，若译码结果为1，则沿着右子树发展路径，当译码路径的总数超过预设的路径宽度L(一般L为2的整数次幂)时，选择出路径度量(path metric，PM)值最佳的L条路径保存并继续发展路径以译出后续的译码比特，其中的PM值用于判断路径的好坏，PM值通过LLR计算得出。对于每一级的译码比特，对L条路径的PM值按照从小到大排序，并通过PM值筛选出正确的路径，如此反复，直到译完最后一个比特。
4)、系统polar码，系统polar码是指信息比特直接承载在编码侧(码字侧)的polar码，相对于非系统polar码，系统polar码具有BER性能更好、更方便与其它码级联、应用广泛(如能够进行联合信源信道编码)等优点。如图5为8×8系统polar码的示意图，其中待编码侧的u0，u1，u2，u4为冻结比特位，可用于承载冻结比特，编码侧的x3，x5，x6，x7为真实的承载信息比特的系统比特位，系统比特位的作用与非系统polar码的信息比特位的作用类似，系统polar码编码过程可以理解为基于冻结比特位所承载的冻结比特和系统比特位所真实承载的信息比特，确定校验比特位(x0，x1，x2，x4)所承载的校验比特的过程，校验比特和系统比特位所真实承载的信息比特的组合作为编码后的比特序列输出。
由于系统polar码的系统比特位与冻结比特位之间的位置关系存在相互耦合，目前一种对系统polar码编码的方案为串行编码方案，在串行编码方案中系统polar码的Nlog2N个编码问题不断分解，分解为成Nlog2N个子编码问题，通过串行地执行这Nlog2N个子编码问题，完成编码过程，算法复杂度是Nlog2N。但是，由于这个编码过程要求串行执行，会带来较大的编码时延。另外，串行编码方案应用的一个通用场景是针对有偏信源(即0/1不是均匀分布的信息比特序列)的编码过程。这种需要要求将有偏信源作为信息比特进行编码，然后将得到的校验比特输出。然而现有的串行编码框架下找到最优的码构造十分困难。具体来说，需要遍历所有的可能的信息比特放置方式，然后计算各自的错误概率，再从中选择一个最优的信息比特放置方式，复杂度较高。
另一种对系统polar码编码的方案是一种并行编码方法。如图6所示。为了将信息比特承载在编码侧的x3，x5，x6，x7，编码过程中首先将真实信息比特承载在对应的待编码侧的u3，u5，u6，u7，先执行一次非系统polar码编码过程；进一步将得到序列的冻结比特位对应的比特强制设为0，再将该序列再执行一次非系统polar码编码过程，然后将得到的结果输出，即完成编码过程。可以看到，这个方法保留了非系统polar码的高并行度编码。但是，由于需要完成两次非系统polar码编码过程，计算复杂度是2Nlog2N，为非系统polar码编码过程的2倍。
由上述系统极化码编码方案可知，由于系统极化(polar)码的系统比特位与冻结比特位之间的位置关系存在相互耦合，编码过程要求串行执行，或者多次并行执行非系统极化码编码过程，存在编码复杂度高、灵活性不足的问题。基于此，本申请提供一种编码、译码方法及装置，通过引入比特位映射，能够使得系统极化码的冻结比特位和系统比特位(真实承载信息比特的比特位)的比特位索引可以有重叠，解耦系统极化码的系统比特位和冻结比特位，以期带来更大的编码设计空间，降低编码的复杂度，提高编码的灵活性。下面将结合附图，对本申请实施例进行详细描述。
另外，需要理解的是，本申请实施例提及“第一”、“第二”等序数词是用于对多个对象进行区分，不用于限定多个对象的大小、内容、顺序、时序、优先级或者重要程度等。例如，第一阈值和第二阈值，可以是同一个阈值，也可以是不同的阈值，且，这种名称也并不是表示这两个阈值的取值、对应的参数、优先级或者重要程度等的不同。
本申请实施例中，对于名词的数目，除非特别说明，表示“单数名词或复数名词”，即"一个或多个”。“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A,B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。例如，A/B，表示：A或B。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a,b,或c中的至少一项(个)，表示：a,b,c,a和b,a和c,b和c,或a和b和c，其中a,b,c可以是单个，也可以是多个。
图7为本申请实施例提供的一种编码、译码方法示意图，图7中以编码设备和译码设备作为执行主体为例来示意该方法，其中编码设备可以是网络设备、译码设备可以是终端设备；或者编码设备是终端设备、译码设备是网络设备等等。本申请并不限制该方法的执行主体，例如：图7中的编码设备还可以是能支持该编码设备实现该方法的芯片、芯片系统、或处理器，还可以是能实现全部或部分编码设备功能的逻辑模块或软件；图7中的译码设备也可以是支持该译码设备实现该方法的芯片、芯片系统、或处理器，还可以是能实现全部或部分译码设备功能的逻辑模块或软件。该方法包括：
S701：编码设备获取信息比特序列。
S702：编码设备根据系统极化码对信息比特序列进行编码，确定编码比特序列。
其中，系统极化码包括极化变换矩阵和与极化变换矩阵对应的N个第一比特位和N个第二比特位，N个第二比特位中包括系统比特位集合A和非系统比特位集合MA，N个第一比特位中包括冻结比特位集合B和非冻结比特位集合MB，B中存在冻结比特位子集C、MB中存在非冻结比特位子集D，C中的冻结比特位与D中的非冻结比特位相互映射，C根据B与A的比特位索引交集确定，D根据MB与MA的比特位索引交集确定，A根据信息比特序列确定，编码比特序列包括信息比特序列。
对于码长为N的系统极化码，其极化变换矩阵两侧分别对应N个比特位，包括极化变换矩阵左侧(即待编码侧)的N个第一比特位，以及极化变换矩阵右侧(即编码侧)的N个第二比特位，N个第一比特位和N个第二比特位可以通过极化变换矩阵对应，例如N个第一比特位所承载的比特与N个第二比特位所承载的比特可以通过极化变换矩阵进行转换。
另外，对于码长为N系统极化码，系统比特位可用于承载信息比特序列，系统比特位和冻结比特位的总数量等于系统极化码的码长N，因此在本申请实施例中，A可以根据信 息比特序列确定。例如：信息比特序列的长度为K，则A中包括K个系统比特位、B中包括N-K个冻结比特位，MA中包括N-K个非系统比特位、MB中包括K个非冻结比特位。其中，对于信息比特序列的长度K，编码设备和译码设备可以预先约定，也可以由编码设备指示给译码设备等。例如编码设备和解码设备预先约定码率为P，P小于或等于1，则K＝NP。
此外，需要理解的是，系统极化码中的非冻结比特位也可以称为信息比特位，但是系统极化码中的信息比特位(非冻结比特位)不用于真实承载信息比特，而是由系统极化码中的系统比特位来承载信息比特序列。也就是说，系统比特位在系统极化码中的作用与信息比特位在非系统极化码的作用相当。
不同于按照码长N所对应的N个极化信道的信道可靠度，确定系统极化码中系统比特位和冻结比特位的比特位索引，系统比特位和冻结比特位的比特位索引完全错开的系统极化码，比如图5所示的系统比特位和冻结比特位完全错开的系统极化码。在本申请实施例提供的系统极化码中，系统比特位的比特位索引和冻结比特位的比特位索引可以不完全错开，也即N个第二比特位中的系统比特位集合A和N个第一比特为中的冻结比特位集合B的比特位索引可以存在交集。
对于A中的系统比特位，在一种可能的实现中，可以将N个第二比特位中的后K个第二比特位确定为系统比特位，其中K等于信息比特序列的长度，在一些实施中，如果对信息比特序列进行校验编码，K还可以等于信息比特序列的长度+循环冗余校验(cyclic redundancy check，CRC)等校验编码得到的校验编码比特(如CRC比特)的长度。以N＝8、K＝4为例进行说明，可以将N个第二比特位中的比特位索引为4、5、6、7的4个第二比特位确定为系统比特位。
在另一种可能的实现中，还可以按照倒序位(bit inverse order，BIV)准则或随机选取等方式，将N个第二比特位中的K个第二比特位确定为系统比特位。以N＝8、K＝4为例进行说明，0-7用二进制展开分别是000 001 010 011 100 101 110 111，将该二进制位反转(bit inverse)，得到000 100 010 110 001 101 011 111。按照该顺序从大到小取出原来对应的K个比特位索引，即7、3、5、1，将N个第二比特位中的比特位索引为7、3、5、1的4个第二比特位确定为系统比特位。
对于B中的冻结比特位，在一种可能的实现中，可以按照信道可靠度或者码重在N个第一比特位中选取N-K个第一比特位作为冻结比特位，比如将信道可靠度最低或码重最低的N-K个第一比特位作为冻结比特位。仍以N＝8、K＝4为例进行说明，8个极化信道按照信道可靠度排序的可靠度序列M＝[0，1，2，4，3，5，6，7]，则可以将N个第一比特位中的比特位索引为0、1、2、4的4个第一比特位确定为冻结比特位。
继续以N＝8、K＝4为例进行说明，如图8所示，在本申请实施例中，可以将8(N＝8)第二比特位中比特位索引为4、5、6、7的4(即K)个第二比特位(x4，x5，x6，x7)确定为系统极化码的系统比特位，比特位索引为0、1、2、3的4(即N-K)个第二比特位(x0，x1，x2，x3)确定为系统极化码非系统比特位，进而可以确定系统极化码的系统比特位集合A为{x4，x5，x6，x7}、非系统比特位集合MA为{x0，x1，x2，x3}。
并可以将对应极化信道的信道可靠度最低的4(即N-K)个第一比特位(u0，u1，u2，u4)确定为系统极化码的冻结比特位，剩余4(即K)个第一比特位(u3，u5，u6，u7)确定为系统极化码的非冻结比特位，进而可以确定系统极化码的冻结比特位集合B为{u0， u1，u2，u4}、非冻结比特位集合MB为{u3，u5，u6，u7}。其中B与A的比特位索引交集为4，可以确定冻结比特位子集C为{u4}，MB与MA的比特位索引交集为3，可以确定非冻结比特位子集D为{u3}，C中的冻结比特位u4与D中的非冻结比特位u3相互映射。
在本申请实施例中，C中的冻结比特位与D中的非冻结比特位相互映射，可以为C中的冻结比特位的值与D中的非冻结比特位的值按照先后顺序一一对应相同，或者C中的冻结比特位与D中的非冻结比特位的值可以通过映射矩阵Y实现映射，可以表示为D＝YC，Y为二进制矩阵(binary matrix)。其中Y可以为Nc维(也即Nc*Nc)满秩矩阵或单位阵，NC等于C中冻结比特位的个数，这种情况下C中的冻结比特位与D中的非冻结比特位按先后顺序一一对应相同。在一些实现中，Y还可以为Nc维的置换矩阵，这种情况下C中的冻结比特位与D中的非冻结比特位可以不按照先后顺序一一对应相同。
在一种可能的实施中，根据系统极化码对信息比特序列进行编码，确定编码比特序列可以基于如下步骤实现：
步骤A1：根据信息比特序列和第一极化变换子矩阵，确定第一中间编码比特序列，其中第一极化变换子矩阵为极化变换矩阵中对应A的极化变换子矩阵，也即第一极化变化子矩阵为极化变换矩阵中对应A中第二比特位的比特位索引的那些行的子矩阵。
步骤A2：根据第一中间编码比特序列、C中的冻结比特位与D中的非冻结比特位相互映射的关系、以及B与MA的比特位索引交集，确定第二中间编码比特序列，其中第二中间编码比特序列长度等于MA包含的第二比特位的个数。
步骤A3：根据第二中间编码比特序列、第二极化变换子矩阵、以及信息比特序列，确定编码比特序列，其中第二极化变换子矩阵为极化变换矩阵中对应MA的极化变换子矩阵，也即第二极化变化子矩阵为极化变换矩阵中对应MA中第二比特位的比特位索引的那些行的子矩阵。
仍以图8所示的系统极化码为例，根据系统极化码对信息比特序列进行编码，确定编码比特序列可以参照图9所示的实现。步骤A1：编码设备根据信息比特序列U(对应A所承载的比特，也可以称为对应A的值)，与极化变换矩阵G中对应A中第二比特位的比特位索引的那些行得到的第一极化变换子矩阵G1相乘，得到第一中间编码比特序列X1，其中X1对应u4-u7所承载的比特。
步骤A2：编码设备根据C中的冻结比特位u4与D中的非冻结比特位u3相互映射关系，以及X1中对应u4所承载的比特，可以确定u3所承载的比特，根据B{u0，u1，u2，u4}与MA{x0，x1，x2，x3}的比特位索引交集{0，1，2}，可以确定u0、u1和u2承载冻结比特，以冻结比特的值设置为0为例，则可以得到第二中间编码比特序列X2，X2＝[0，0，0，u3]。
步骤A3：编码设备根据X2与极化变换矩阵G中对应MA中第二比特位的比特位索引的那些行得到的第二极化变换子矩阵G2相乘，得到中间校验比特序列C1，并将中间校验比特序列C1与信息比特序列U进行异或操作，则可以得到校验比特序列C，其中C对应x1-x4所承载的比特；将C和U拼接，即可得到编码比特序列。
其中C1和U进行异或操作时，C1中的中间校验比特与U中的信息比特按先后顺序一一进行异或操作，如C1中对应x0的中间校验比特与U中对应x4的信息比特进行异或操作，C1中对应x1的中间校验比特与U中对应x5的信息比特进行异或操作，C1中对应x2的中间校验比特与U中对应x6的信息比特进行异或操作，C1中对应x3的中间校验比特与 U中对应x7的信息比特进行异或操作。
需要理解的是，C1和U进行异或操作时，可以遵循对应比特位索引为0的比特与对应比特位索引为N/2的比特进行异或操作，对应比特位索引为1的比特与对应比特位索引为N/2+1的比特进行异或操作，…，对应比特位索引为N/2-1的比特与对应比特位索引为N-1的比特进行异或操作的原则。
上述是以A和MA中包括的比特位相同为例，也即信息比特序列U和中间校验比特序列C1的长度相等为例，进行说明的。可以理解，在一些实施例中，A和MA中包括的比特位也可以不同，也即U和C1的长度可以不等。
作为一种示例，以N＝8、K＝3，A为{x5，x6，x7}，MA为{x0，x1，x2，x3，x4}为例，则中间校验比特序列C1包括5个中间校验比特，分别对应x0，x1，x2，x3，x4，信息比特序列U包括3个信息比特，分别对应x5，x6，x7，在C1和U进行异或操作时，C1中对应x0的中间校验比特与对应x4的中间校验比特进行异或操作，得到校验比特序列C中对应x0的校验比特；C1中对应x1的中间校验比特与U中对应x5的信息比特进行异或操作，得到校验比特序列C中对应x1的校验比特；C1中对应x2的中间校验比特与U中对应x6的信息比特进行异或操作，得到校验比特序列C中对应x2的校验比特；C1中对应x3的中间校验比特与U中对应x7的信息比特进行异或操作，得到校验比特序列C中对应x3的校验比特；C1中对应x4的中间校验比特与对应x0的中间校验比特进行异或操作，得到校验比特序列C中对应x4的校验比特。
作为另一示例，以N＝16、K＝9为例进行说明，16个极化信道按照信道可靠度排序的可靠度序列M＝[0，1，2，4，8，3，5，9，6，10，12，7，11，13，14，15]，则系统比特位集合A为{x7，x8，x9，x10，x11，x12，x13，x14，x15}、非系统比特位MA为{x0，x1，x2，x3，x4，x5，x6}，冻结比特位集合B为{u0，u1，u2，u4，u8，u3，u5}、非冻结比特位集合MB为{u9，u6u10，u12，u7，u11，u13，u14，u15}，其中A和B的比特位索引交集为{8}，MB与所述MA的比特位索引交集为{6}，可以确定冻结比特位子集C为{u8}，确定非冻结比特位子集D为{u6}，C中的冻结比特位u8与D中的非冻结比特位u6相互映射。对于该N＝16、K＝9的系统极化码，确定出的中间校验比特序列C1包括7个中间校验比特，分别对应x0，x1，x2，x3，x4，x5，x6，信息比特序列U包括9个信息比特，分别对应x7，x8，x9，x10，x11，x12，x13，x14，x15，在C1和U进行异或操作时，C1中对应x0的中间校验比特与U中对应x8的信息比特进行异或操作，得到校验比特序列C中对应x0的校验比特；C1中对应x1的中间校验比特与U中对应x9的信息比特进行异或操作，得到校验比特序列C中对应x1的校验比特；C1中对应x2的中间校验比特与U中对应x10的信息比特进行异或操作，得到校验比特序列C中对应x2的校验比特；C1中对应x3的中间校验比特与U中对应x11的信息比特进行异或操作，得到校验比特序列C中对应x3的校验比特；C1中对应x4的中间校验比特与U中对应x12的信息比特进行异或操作，得到校验比特序列C中对应x4的校验比特；C1中对应x5的中间校验比特与U中对应x13的信息比特进行异或操作，得到校验比特序列C中对应x5的校验比特；C1中对应x6的中间校验比特与U中对应x14的信息比特进行异或操作，得到校验比特序列C中对应x6的校验比特。
上述根据系统极化码对信息比特序列进行编码，确定编码比特序列的编码复杂度不超过K(log2N-1)+(N-K)(log2N-1)+N，其中K(log2N-1)对应步骤A1的编码复杂度， 对应步骤A3的编码复杂度不超过(N-K)(log2N-1)+N，其中上述步骤A3中C1和U进行异或操作的编码复杂度不超过N，步骤A2为比特位间的映射不涉及编码复杂度。
仍以上述N＝8、K＝4为例，图9的编码复杂度是4log2(4)+4*log2(4)+8＝8*log2(8)；而如图6所示的两次非系统码编码过程的复杂度是2*8*log2(8)；本申请实施例的编码复杂度是两次非系统码编码过程的1/2。
需要理解的是，本申请实施例并不限制对系统极化码编码所使用的编码方式，也可以使用串行编码等编码方式，实现编码。
系统极化码本身并不是针对码谱优化的，导致短码(码长N较小时)性能较差。为解决该问题，在本申请实施例中，还可以在系统极化码之前级联一个校验码、或卷积码(conventional code)等来改善系统极化码的性能。其中卷积码等不同的编码形式可以统一为对应预编码矩阵的预变换(pre-transform)，不同的编码形式对应于不同的预编码矩阵。如图10所示的预变换系统极化码示意图，可以将预编码矩阵和系统极化码的极化变换矩阵级联，通过预编码矩阵所对应的预变换和极化变换矩阵所对应的极化变换(polar transform)来进行编码，从而降低BER，改善系统极化码的性能。
在本申请实施例中，预编码矩阵可以为N维上三角矩阵，也即上三角矩阵为N行、N列，N为系统极化码的码长。具体的，如图11所示，N维的上三角矩阵T可以表示为其中TA和TB的行数根据MA中非系统比特位的个数确定、TC的行数根据A中系统比特位的个数确定，TA的列数根据MA中非系统比特位的个数确定、TB和TC的列数根据A中系统比特位的个数确定。也即TA和TB的行数为N-K、0和TC的行数为K，0和TA的列数为K，TA和TB的列数为N-K，0表示元素全为零的矩阵。
在一种可能的实施中，在预编码矩阵为上三角矩阵时，根据系统极化码对信息比特序列进行编码，确定编码比特序列可以基于如下步骤实现：
步骤B1：根据信息比特序列和第一极化变换子矩阵，确定第一中间编码比特序列，其中第一极化变换子矩阵为极化变换矩阵中对应A的极化变换子矩阵，也即第一极化变化子矩阵为极化变换矩阵中对应A中第二比特位的比特位索引的那些行的子矩阵。
步骤B2：根据第一中间编码比特序列、TC和TB，确定第三中间编码比特序列。
步骤B3：根据第三中间编码比特序列、C中的冻结比特位与D中的非冻结比特位相互映射的关系、B与MA的比特位索引交集，确定第四中间编码比特序列。
步骤B4：根据第四中间编码比特序列和TA，确定第二中间编码比特序列。
步骤B5：根据第二中间编码比特序列、第二极化变换子矩阵、以及信息比特序列，确定编码比特序列，其中第二极化变换子矩阵为极化变换矩阵中对应MA的极化变换子矩阵，也即第二极化变化子矩阵为极化变换矩阵中对应MA中第二比特位的比特位索引的那些行的子矩阵。
其中步骤B1和B5的实现，可以参照A1和A3的实现，不再进行赘述。
以图12所示的系统极化码级联预编码矩阵T(T如图11所示)为例，其中，X1表示第一中间编码序列，X2表示第二中间编码序列，X3表示第三中间编码序列，X4表示第四中间编码序列，其中X1和X2通过预变换矩阵T可以与X3和X4进行转换。
步骤B2：由于[X3X4]T＝[X1X2]，即[X4TB+X3TC]＝X1，由于u4和u3相互映射，X4是可以根据X3确定的，比如u4的值和u3的值一一对应相同，X4中对应u3的值可以与X3中对应u4的值相等，也即X4中比特位索引为3的值可以与X3中比特位索引为4的值相等，所以[X4TB+X3TC]＝X1可以转换为其中，表示根据TB中对 应D集合中比特位索引的行与0矩阵构成，也即TB中(u3)对应的行与0矩阵构造的矩阵。因此，基于根据第一中间编码比特序列X1、TC和TB，可以确定第三中间编码比特序列X3。
步骤B3：可以根据C中的冻结比特位u4与D中的非冻结比特位u3相互映射的关系，可以确定X4中对应比特位索引为3的值，比如相互映射关系为u4的值和u3的值一一对应相同，可以令X4中对应比特位索引为3的值与X3中对应比特位索引为4的值相同，结合B(u0，u1，u2，u4)与MA(x0，x1，x2，x3)的比特位索引交集{0，1，2}，可以得到X4，X4＝[0，0，0，X3(4)]。其中X3(4)为基于X3中比特位索引为4的值和上述相互映射的关系，确定的X4中对应比特位索引为3的值，比如相互映射关系为u4的值和u3的值一一对应相同时，X3(4)为X3中对应比特位索引为4的值。
步骤B4：将X4与A相乘，即可得到X2。
S703：编码设备输出编码比特序列，相应地，译码设备获取待译码符号序列。
编码比特序列经过发送端调制后得到调制符号，调制符号经信道传输后被译码设备接收。译码设备对接收到的调制符号进行解调得到待译码符号序列，其中待译码符号序列对应于编码比特序列，通常由编码比特序列受到信道中噪声等因素的干扰变换得到，也即待译码符号序列可以理解为受到信道等干扰的编码比特序列。
S704：译码设备根据系统极化码对待译码符号序列进行译码，确定信息比特序列。
对于译码设备如何确定上述A、MA、B、MB、C、以及D的实现，可以参照编码设备侧的实现，不再进行赘述。
在本申请实施例中，可以采用SC译码，SCL译码等译码方法进行译码。
作为一种示例：译码设备可以首先根据待译码符号序列、极化变换矩阵、C中的冻结比特位与D中的非冻结比特位相互映射的关系、以及B与MA的比特位索引交集，确定第一中间译码比特序列。再根据第一中间译码比特序列和极化变换矩阵，确定信息比特序列。
需要理解的是，在译码时可以先译码D中非冻结比特位的值，C中冻结比特位的值根据D中非冻结比特位的值来确定，比如在译码过程中，先译码u3，并且在译码u4时，由于u3与u4相互映射，可以根据u3确定u4，u4可以直接作为冻结比特对待，在后续示例中以u3与u4相互映射为u3的值等于u4的值进行说明。
作为一种示例，如图13所示，译码设备可以首先基于待译码符号序列X，也即x0-x7的值，以及极化变换矩阵G，采用SCL译码方法确定第一中间译码比特序列D1，也即u0-u7的值，其中译码过程中需要保持u0-u2为预先约定的冻结比特的值，u4的值等于u3的值的约束条件。并根据确定的D1和G的乘积确定第二译码中间序列D2，D2中对应A(x4-x7)的值，即为信息比特序列。
在一些实施中，还可以是在系统极化码中加一个校验编码，如循环冗余校验(cyclic redundancy check，CRC)编码，设置校验编码比特位，如CRC比特位，来提高译码可靠度。以CRC编码为例，译码设备可以利用CRC辅助的SCL译码方法进行译码，即首先根据SCL译码方法进行译码，得到L条译码路径，在译码结束时，针对L条译码路径，分别根据CRC比特位的值，对进行CRC编码的比特位的值进行判决，根据判决结果从L条译码路径中选出通过CRC判决的路径输出作为最后的译码结果。
需要理解的是，如果对信息比特序列进行校验编码，K还可以等于信息比特序列的长度+校验编码得到的校验编码比特(如CRC比特)的长度。也即A中包括信息比特的位置 以及信息比特对应的校验编码比特(如CRC比特)的位置。如A中包括比特位的比特位索引，等于真实承载了信息比特序列的系统比特位的比特位索引与校验编码比特(如CRC比特)位的比特位索引的和。下面以校验编码为CRC校验编码，校验编码比特为CRC比特，校验编码比特位为CRC比特位为例进行说明。
在一种可能的实现中，CRC比特位可以在编码侧，CRC比特位所承载的CRC比特根据对信息比特序列进行校验编码得到，得到的CRC比特和信息比特序列一起进行系统极化码编码。
作为一种示例：如图14所示，可以将真实承载了信息比特序列的系统比特位(x5，x6，x7)所承载的信息比特序列进行CRC校验编码，确定CRC比特位(x4)的所承载的CRC比特，也即CRC比特位的值，将信息比特序列和CRC比特级联作为新的信息比特序列进行编码。
在译码时，需要满足CRC比特位x4的值(也即所承载的CRC比特)，对x5，x6，x7的值(也即真实承载的信息比特序列)校验通过。
该实现中，校验编码的实现简单，且通过设置CRC比特位，可以提高译码的纠错能力，提高译码的可靠性。
在另一种可能的实现中，CRC比特位可以位于待编码侧，CRC比特位所承载的CRC比特可以根据第一中间编码比特序列中非CRC比特部分确定。例如，第一中间编码比特序列可以包括第五中间编码比特序列和CRC比特，第五中间编码比特序列根据信息比特序列和第一极化变换子矩阵确定，CRC比特根据第五中间编码比特序列确定。
作为一种示例：如图15所示，可以将真实承载了信息比特序列的系统比特位(x5，x6，x7)所承载的信息比特序列和第一极化变换子矩阵(如第一极化变换子矩阵中对应比特位索引为5，6，7的行)的乘积，确定第五中间编码比特序列(对应u5，u6，u7的值)，将第五中间编码比特序列进行CRC校验编码，确定CRC比特位(u4)的所承载的CRC比特，也即CRC比特位的值，将第五中间编码比特序列和CRC比特级联作为第一中间编码序列继续进行编码。其中对于CRC比特位所对应的第二比特位(也即编码侧比特位)的值，如图15中x4的值，可以通过CRC比特与第一极化编码子矩阵中与CRC比特位的比特位索引对应的行的乘积确定。
在译码时，第一中间译码比特序列中包括第二中间译码比特序列(对应u5，u6，u7的值)和CRC比特(对应u4的值)，CRC比特用于对第二中间译码比特序列进行校验，其中第二中间译码比特序列对应信息比特的位置(比特位索引5，6，7)，CRC比特对应CRC比特的位置(比特位索引4)。
该实现中，将CRC比特位设置在系统极化码的待编码侧(即非码字侧)，且CRC比特与待编码侧的编码比特序列形成校验关系，有利于译码的早停。
在另一种可能的实现中，CRC比特位还可以位于待编码侧，CRC比特位所承载的CRC比特根据对信息比特序列进行校验编码得到。也即第一中间编码比特序列可以包括第五中间编码比特序列和CRC比特，第五中间编码比特序列根据信息比特序列和第一极化变换子矩阵确定，CRC比特根据信息比特序列确定。
作为一种示例：如图16所示，可以将真实承载了信息比特序列的系统比特位(x5，x6，x7)所承载的信息比特序列和第一极化变换子矩阵(如第一极化变换子矩阵中对应比特位索引为5，6，7的行)乘积，确定第五中间编码比特序列(对应u5，u6，u7的值)， 并将信息比特序列进行CRC校验编码，确定CRC比特位(u4)的所承载的CRC比特，也即CRC比特位的值，将第五中间编码比特序列和CRC比特级联作为第一中间编码序列继续进行编码。其中对于CRC比特位所对应的第二比特位(也即编码侧比特位)的值，如图16中x4的值，可以通过CRC比特与第一极化编码子矩阵中与CRC比特位的比特位索引对应的行的乘积确定。
在译码时，第一中间译码比特序列中CRC比特(对应u4的值)，用于对信息比特序列(也即x5，x6，x7的值)进行校验。
该实现可以在上述两种校验比特设置中平衡性能，可以在校验编码的实现简单和译码早停之间是获得性能的平衡。
可以理解的是，为了实现上述实施例中功能，编码设备和译码设备包括了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本申请中所公开的实施例描述的各示例的单元及方法步骤，本申请能够以硬件或硬件和计算机软件相结合的形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用场景和设计约束条件。
图17和图18为本申请的实施例提供的可能的通信装置的结构示意图。这些通信装置可以用于实现上述方法实施例中编码设备或译码设备的功能，因此也能实现上述方法实施例所具备的有益效果。
如图17所示，通信装置1700包括处理单元1710和输入输出单元1720，其中输入输出单元1720还可以为收发单元或接口单元或输入输出接口。通信装置1700可用于实现上述图7中所示的方法实施例中编码设备或解码设备的功能。
当通信装置1700用于实现图7所示的方法实施例中编码设备的功能时：
输入输出单元1720，用于获取信息比特序列；
处理单元1710，用于根据系统极化码对信息比特序列进行编码，确定编码比特序列，其中系统极化码包括极化变换矩阵和与极化变换矩阵对应的N个第一比特位和N个第二比特位，N个第二比特位中包括系统比特位集合A和非系统比特位集合MA，N个第一比特位中包括冻结比特位集合B和非冻结比特位集合MB，B中存在冻结比特位子集C、MB中存在非冻结比特位子集D，C中的冻结比特位与D中的非冻结比特位相互映射，C根据B与A的比特位索引交集确定，D根据MB与MA的比特位索引交集确定，A根据信息比特序列确定，编码比特序列包括信息比特序列；
输入输出单元1720，还用于输出编码比特序列。
在一种可能的设计中，处理单元1710根据系统极化码对信息比特序列进行编码，确定编码比特序列时，具体用于根据信息比特序列和第一极化变换子矩阵，确定第一中间编码比特序列，其中第一极化变换子矩阵为极化变换矩阵中对应A的极化变换子矩阵；根据第一中间编码比特序列、C中的冻结比特位与D中的非冻结比特位相互映射的关系、以及B与MA的比特位索引交集，确定第二中间编码比特序列，其中第二中间编码比特序列长度等于MA包含的第二比特位的个数；以及根据第二中间编码比特序列、第二极化变换子矩阵、以及信息比特序列，确定编码比特序列，其中第二极化变换子矩阵为极化变换矩阵中对应MA的极化变换子矩阵。
在一种可能的设计中，A由N个第二比特位中的后K个第二比特位构成；和/或，B由N个第一比特位中按照信道可靠度或者码重选取的N-K个第一比特位构成，K大于或等 于1、且小于N。
在一种可能的设计中，系统极化码与预编码矩阵级联，预编码矩阵为上三角矩阵其中TA和TB的行数根据MA中非系统比特位的个数确定、TC的行数根据A中系统比特位的个数确定，TA的列数根据MA中非系统比特位的个数确定、TB和TC的列数根据A中系统比特位的个数确定；
处理单元1710根据系统极化码对信息比特序列进行编码，确定编码比特序列时，具体用于根据信息比特序列和第一极化变换子矩阵，确定第一中间编码比特序列，其中第一极化变换子矩阵为极化变换矩阵中对应A的极化变换子矩阵；根据第一中间编码比特序列、TC和TB，确定第三中间编码比特序列；根据第三中间编码比特序列、C中的冻结比特位与D中的非冻结比特位相互映射的关系、B与MA的比特位索引交集，确定第四中间编码比特序列；根据第四中间编码比特序列和TA，确定第二中间编码比特序列；根据第二中间编码比特序列、第二极化变换子矩阵、以及信息比特序列，确定编码比特序列，其中第二极化变换子矩阵为极化变换矩阵中对应MA的极化变换子矩阵。
在一种可能的设计中，A根据信息比特序列确定，包括：A中包括信息比特的位置以及信息比特对应的CRC比特的位置。
在一种可能的设计中，第一中间编码比特序列包括第五中间编码比特序列和CRC比特，第五中间编码比特序列根据信息比特序列和第一极化变换子矩阵确定，CRC比特根据第五中间编码比特序列确定。
在一种可能的设计中，第一中间编码比特序列包括第五中间编码比特序列和CRC比特，第五中间编码比特序列根据信息比特序列和第一极化变换子矩阵确定，CRC比特根据信息比特序列确定。
在一种可能的设计中，C中的冻结比特位与D中的非冻结比特位相互映射包括：C中的冻结比特位与D中的非冻结比特位根据映射矩阵相互映射，映射矩阵为NC维的满秩矩阵或者为NC维的单位阵，NC等于C中冻结比特位的个数。
当通信装置1700用于实现图7所示的方法实施例中译码设备的功能时：
输入输出单元1720，用于获取待译码符号序列；
处理单元1710，用于根据系统极化码对待译码符号序列进行译码，确定信息比特序列，其中系统极化码包括极化变换矩阵和与极化变换矩阵对应的N个第一比特位和N个第二比特位，N个第二比特位中包括系统比特位集合A和非系统比特位集合MA，N个第一比特位中包括冻结比特位集合B和非冻结比特位集合MB，B中存在冻结比特位子集C、MB中存在非冻结比特位子集D，C中的冻结比特位与D中的非冻结比特位相互映射，C根据B与A的比特位索引交集确定，D根据MB与MA的比特位索引交集确定，A根据信息比特序列确定。
在一种可能的设计中，处理单元1710根据系统极化码对待译码符号序列进行译码，确定信息比特序列时，具体用于根据待译码符号序列、极化变换矩阵、C中的冻结比特位与D中的非冻结比特位相互映射的关系、以及B与MA的比特位索引交集，确定第一中间译码比特序列；根据第一中间译码比特序列和极化变换矩阵，确定信息比特序列。
在一种可能的设计中，A由N个第二比特位中的后K个第二比特位构成；和/或，B由N个第一比特位中按照信道可靠度或者码重选取的N-K个第一比特位构成，K大于或等于1、且小于N。
在一种可能的设计中，A根据信息比特序列确定，包括：A中包括信息比特的位置以及信息比特对应的CRC比特的位置。
在一种可能的设计中，第一中间译码比特序列中包括第二中间译码比特序列和CRC比特，CRC比特用于对第二中间译码比特序列进行校验，其中第二中间译码比特序列对应信息比特的位置，CRC比特对应CRC比特的位置。
在一种可能的设计中，第一中间译码比特序列中包括第二中间译码比特序列和CRC比特，CRC比特用于对信息比特序列进行校验，其中第二中间译码比特序列对应信息比特的位置，CRC比特对应CRC比特的位置。
在一种可能的设计中，C中的冻结比特位与D中的非冻结比特位相互映射包括：C中的冻结比特位与D中的非冻结比特位根据映射矩阵相互映射，映射矩阵为NC维的满秩矩阵或者为NC维的单位阵，NC等于C中冻结比特位的个数。
如图18所示，通信装置1800包括处理器1810和接口电路1820。处理器1810和接口电路1820之间相互耦合。可以理解的是，接口电路1820可以为收发器或输入输出接口。可选的，通信装置1800还可以包括存储器1830，用于存储处理器1810执行的指令或存储处理器1810运行指令所需要的输入数据或存储处理器1810运行指令后产生的数据。可选的，存储器1830还可以和处理器1810集成在一起。
当通信装置1800用于实现图7所示的方法时，处理器1810用于实现上述处理单元1710的功能，接口电路1820用于实现上述输入输出单元1720的功能。
可以理解的是，本申请的实施例中的处理器可以是中央处理单元(central processing unit，CPU)，还可以是其它通用处理器、数字信号处理器(digital signal processor，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现场可编程门阵列(field programmable gate array，FPGA)或者其它可编程逻辑器件、晶体管逻辑器件，硬件部件或者其任意组合。通用处理器可以是微处理器，也可以是任何常规的处理器。
本申请的实施例中的方法步骤可以通过硬件的方式来实现，也可以由处理器执行软件指令的方式来实现。软件指令可以由相应的软件模块组成，软件模块可以被存放于随机存取存储器、闪存、只读存储器、可编程只读存储器、可擦除可编程只读存储器、电可擦除可编程只读存储器、寄存器、硬盘、移动硬盘、CD-ROM或者本领域熟知的任何其它形式的存储介质中。一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器和存储介质可以位于ASIC中。另外，该ASIC可以位于网络设备或终端设备中。当然，处理器和存储介质也可以作为分立组件存在于网络设备或终端设备中。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机程序或指令。在计算机上加载和执行所述计算机程序或指令时，全部或部分地执行本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、网络设备、用户设备或者其它可编程装置。所述计算机程序或指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机程序或指令可以从一个网站站点、计算机、服务器或数据中心通过有线或无线方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是集成一个或多个可 用介质的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，例如，软盘、硬盘、磁带；也可以是光介质，例如，数字视频光盘；还可以是半导体介质，例如，固态硬盘。该计算机可读存储介质可以是易失性或非易失性存储介质，或可包括易失性和非易失性两种类型的存储介质。
在本申请的各个实施例中，如果没有特殊说明以及逻辑冲突，不同的实施例之间的术语和/或描述具有一致性、且可以相互引用，不同的实施例中的技术特征根据其内在的逻辑关系可以组合形成新的实施例。
另外，需要理解，在本申请实施例中，“示例的”一词用于表示作例子、例证或说明。本申请中被描述为“示例”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用示例的一词旨在以具体方式呈现概念。
此外，本申请实施例中，信息(information)，信号(signal)，消息(message)，信道(channel)有时可以混用，应当指出的是，在不强调其区别时，其所要表达的含义是一致的。“的(of)”，“相应的(corresponding，relevant)”和“对应的(corresponding)”有时可以混用，应当指出的是，在不强调其区别时，其所要表达的含义是一致的。
可以理解的是，在本申请的实施例中涉及的各种数字编号仅为描述方便进行的区分，并不用来限制本申请的实施例的范围。上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定。

Claims (31)

  1. 一种编码方法，其特征在于，包括：
    获取信息比特序列；
    根据系统极化码对所述信息比特序列进行编码，确定编码比特序列，其中所述系统极化码包括极化变换矩阵和与所述极化变换矩阵对应的N个第一比特位和N个第二比特位，所述N个第二比特位中包括系统比特位集合A和非系统比特位集合MA，所述N个第一比特位中包括冻结比特位集合B和非冻结比特位集合MB，所述B中存在冻结比特位子集C、所述MB中存在非冻结比特位子集D，所述C中的冻结比特位与所述D中的非冻结比特位相互映射，所述C根据所述B与所述A的比特位索引交集确定，所述D根据所述MB与所述MA的比特位索引交集确定，所述A根据所述信息比特序列确定，所述编码比特序列包括所述信息比特序列；
    输出所述编码比特序列。
  2. 如权利要求1所述的方法，其特征在于，所述A由所述N个第二比特位中的后K个第二比特位构成；和/或，
    所述B由所述N个第一比特位中按照信道可靠度或者码重选取的N-K个第一比特位构成，所述K大于或等于1、且小于所述N。
  3. 如权利要求1或2所述的方法，其特征在于，所述根据系统极化码对所述信息比特序列进行编码，确定编码比特序列，包括：
    根据所述信息比特序列和第一极化变换子矩阵，确定第一中间编码比特序列，其中所述第一极化变换子矩阵为所述极化变换矩阵中对应所述A的极化变换子矩阵；
    根据所述第一中间编码比特序列、所述C中的冻结比特位与所述D中的非冻结比特位相互映射的关系、以及所述B与所述MA的比特位索引交集，确定第二中间编码比特序列，其中所述第二中间编码比特序列长度等于所述MA包含的第二比特位的个数；
    根据所述第二中间编码比特序列、第二极化变换子矩阵、以及所述信息比特序列，确定所述编码比特序列，其中所述第二极化变换子矩阵为所述极化变换矩阵中对应所述MA的极化变换子矩阵。
  4. 如权利要求1-3中任一项所述的方法，其特征在于，所述系统极化码与预编码矩阵级联，所述预编码矩阵为上三角矩阵其中所述TA和所述TB的行数根据所述MA中非系统比特位的个数确定、所述TC的行数根据所述A中系统比特位的个数确定，所述TA的列数根据所述MA中非系统比特位的个数确定、所述TB和所述TC的列数根据所述A中系统比特位的个数确定；
    所述根据系统极化码对所述信息比特序列进行编码，确定编码比特序列，包括：
    根据所述信息比特序列和第一极化变换子矩阵，确定第一中间编码比特序列，其中所述第一极化变换子矩阵为所述极化变换矩阵中对应所述A的极化变换子矩阵；
    根据第一中间编码比特序列、所述TC和TB，确定第三中间编码比特序列；
    根据所述第三中间编码比特序列、所述C中的冻结比特位与所述D中的非冻结比特位相互映射的关系、所述B与所述MA的比特位索引交集，确定第四中间编码比特序列；
    根据所述第四中间编码比特序列和所述TA，确定所述第二中间编码比特序列；
    根据所述第二中间编码比特序列、第二极化变换子矩阵、以及所述信息比特序列，确定所述编码比特序列，其中所述第二极化变换子矩阵为所述极化变换矩阵中对应所述MA 的极化变换子矩阵。
  5. 如权利要求3或4所述的方法，其特征在于，所述A根据所述信息比特序列确定，包括：
    所述A中包括所述信息比特的位置以及所述信息比特对应的循环冗余校验CRC比特的位置。
  6. 如权利要求5所述的方法，其特征在于，所述第一中间编码比特序列包括第五中间编码比特序列和所述CRC比特，所述第五中间编码比特序列根据所述信息比特序列和所述第一极化变换子矩阵确定，所述CRC比特根据所述第五中间编码比特序列确定。
  7. 如权利要求1-6中任一项所述的方法，其特征在于，所述C中的冻结比特位与所述D中的非冻结比特位相互映射包括：所述C中的冻结比特位与所述D中的非冻结比特位根据映射矩阵相互映射，所述映射矩阵为NC维的满秩矩阵或者为NC维的单位阵，所述NC等于所述C中冻结比特位的个数。
  8. 一种译码方法，其特征在于，包括：
    获取待译码符号序列；
    根据系统极化码对所述待译码符号序列进行译码，确定信息比特序列，其中所述系统极化码包括极化变换矩阵和与所述极化变换矩阵对应的N个第一比特位和N个第二比特位，所述N个第二比特位中包括系统比特位集合A和非系统比特位集合MA，所述N个第一比特位中包括冻结比特位集合B和非冻结比特位集合MB，所述B中存在冻结比特位子集C、所述MB中存在非冻结比特位子集D，所述C中的冻结比特位与所述D中的非冻结比特位相互映射，所述C根据所述B与所述A的比特位索引交集确定，所述D根据所述MB与所述MA的比特位索引交集确定，所述A根据所述信息比特序列确定。
  9. 如权利要求8所述的方法，其特征在于，所述A由所述N个第二比特位中的后K个第二比特位构成；和/或，
    所述B由所述N个第一比特位中按照信道可靠度或者码重选取的N-K个第一比特位构成，所述K大于或等于1、且小于所述N。
  10. 如权利要求8或9所述的方法，其特征在于，所述根据系统极化码对所述待译码符号序列进行译码，确定信息比特序列，包括：
    根据所述待译码符号序列、所述极化变换矩阵、所述C中的冻结比特位与所述D中的非冻结比特位相互映射的关系、以及所述B与所述MA的比特位索引交集，确定第一中间译码比特序列；
    根据所述第一中间译码比特序列和所述极化变换矩阵，确定所述信息比特序列。
  11. 如权利要求10所述的方法，其特征在于，所述A根据所述信息比特序列确定，包括：
    所述A中包括所述信息比特的位置以及所述信息比特对应的循环冗余校验CRC比特的位置。
  12. 如权利要求11所述的方法，其特征在于，所述第一中间译码比特序列中包括第二中间译码比特序列和所述CRC比特，所述CRC比特用于对所述第二中间译码比特序列进行校验，其中所述第二中间译码比特序列对应所述信息比特的位置，所述CRC比特对应所述CRC比特的位置。
  13. 如权利要求8-12中任一项所述的方法，其特征在于，所述C中的冻结比特位与所 述D中的非冻结比特位相互映射包括：所述C中的冻结比特位与所述D中的非冻结比特位根据映射矩阵相互映射，所述映射矩阵为NC维的满秩矩阵或者为NC维的单位阵，所述NC等于所述C中冻结比特位的个数。
  14. 一种通信装置，其特征在于，包括输入输出单元和处理单元；
    所述输入输出单元，用于获取信息比特序列；
    所述处理单元，用于根据系统极化码对所述信息比特序列进行编码，确定编码比特序列，其中所述系统极化码包括极化变换矩阵和与所述极化变换矩阵对应的N个第一比特位和N个第二比特位，所述N个第二比特位中包括系统比特位集合A和非系统比特位集合MA，所述N个第一比特位中包括冻结比特位集合B和非冻结比特位集合MB，所述B中存在冻结比特位子集C、所述MB中存在非冻结比特位子集D，所述C中的冻结比特位与所述D中的非冻结比特位相互映射，所述C根据所述B与所述A的比特位索引交集确定，所述D根据所述MB与所述MA的比特位索引交集确定，所述A根据所述信息比特序列确定，所述编码比特序列包括所述信息比特序列；
    所述输入输出单元，还用于输出所述编码比特序列。
  15. 如权利要求14所述的装置，其特征在于，所述A由所述N个第二比特位中的后K个第二比特位构成；和/或，
    所述B由所述N个第一比特位中按照信道可靠度或者码重选取的N-K个第一比特位构成，所述K大于或等于1、且小于所述N。
  16. 如权利要求14或15所述的装置，其特征在于，所述处理单元根据系统极化码对所述信息比特序列进行编码，确定编码比特序列时，具体用于根据所述信息比特序列和第一极化变换子矩阵，确定第一中间编码比特序列，其中所述第一极化变换子矩阵为所述极化变换矩阵中对应所述A的极化变换子矩阵；根据所述第一中间编码比特序列、所述C中的冻结比特位与所述D中的非冻结比特位相互映射的关系、以及所述B与所述MA的比特位索引交集，确定第二中间编码比特序列，其中所述第二中间编码比特序列长度等于所述MA包含的第二比特位的个数；以及根据所述第二中间编码比特序列、第二极化变换子矩阵、以及所述信息比特序列，确定所述编码比特序列，其中所述第二极化变换子矩阵为所述极化变换矩阵中对应所述MA的极化变换子矩阵。
  17. 如权利要求14-16中任一项所述的装置，其特征在于，所述系统极化码与预编码矩阵级联，所述预编码矩阵为上三角矩阵其中所述TA和所述TB的行数根据所述MA中非系统比特位的个数确定、所述TC的行数根据所述A中系统比特位的个数确定，所述TA的列数根据所述MA中非系统比特位的个数确定、所述TB和所述TC的列数根据所述A中系统比特位的个数确定；
    所述处理单元根据系统极化码对所述信息比特序列进行编码，确定编码比特序列时，具体用于根据所述信息比特序列和第一极化变换子矩阵，确定第一中间编码比特序列，其中所述第一极化变换子矩阵为所述极化变换矩阵中对应所述A的极化变换子矩阵；根据第一中间编码比特序列、所述TC和TB，确定第三中间编码比特序列；根据所述第三中间编码比特序列、所述C中的冻结比特位与所述D中的非冻结比特位相互映射的关系、所述B与所述MA的比特位索引交集，确定第四中间编码比特序列；根据所述第四中间编码比特序列和所述TA，确定所述第二中间编码比特序列；根据所述第二中间编码比特序列、第二极化变换子矩阵、以及所述信息比特序列，确定所述编码比特序列，其中所述第二极化变换子矩阵为所述极化变换矩阵中对应所述MA的极化变换子矩阵。
  18. 如权利要求16或17所述的装置，其特征在于，所述A根据所述信息比特序列确定，包括：
    所述A中包括所述信息比特的位置以及所述信息比特对应的循环冗余校验CRC比特的位置。
  19. 如权利要求18所述的装置，其特征在于，所述第一中间编码比特序列包括第五中间编码比特序列和所述CRC比特，所述第五中间编码比特序列根据所述信息比特序列和所述第一极化变换子矩阵确定，所述CRC比特根据所述第五中间编码比特序列确定。
  20. 如权利要求14-19中任一项所述的装置，其特征在于，所述C中的冻结比特位与所述D中的非冻结比特位相互映射包括：所述C中的冻结比特位与所述D中的非冻结比特位根据映射矩阵相互映射，所述映射矩阵为NC维的满秩矩阵或者为NC维的单位阵，所述NC等于所述C中冻结比特位的个数。
  21. 一种通信装置，其特征在于，包括输入输出单元和处理单元；
    所述输入输出单元，用于获取待译码符号序列；
    所述处理单元，用于根据系统极化码对所述待译码符号序列进行译码，确定信息比特序列，其中所述系统极化码包括极化变换矩阵和与所述极化变换矩阵对应的N个第一比特位和N个第二比特位，所述N个第二比特位中包括系统比特位集合A和非系统比特位集合MA，所述N个第一比特位中包括冻结比特位集合B和非冻结比特位集合MB，所述B中存在冻结比特位子集C、所述MB中存在非冻结比特位子集D，所述C中的冻结比特位与所述D中的非冻结比特位相互映射，所述C根据所述B与所述A的比特位索引交集确定，所述D根据所述MB与所述MA的比特位索引交集确定，所述A根据所述信息比特序列确定。
  22. 如权利要求21所述的装置，其特征在于，所述A由所述N个第二比特位中的后K个第二比特位构成；和/或，
    所述B由所述N个第一比特位中按照信道可靠度或者码重选取的N-K个第一比特位构成，所述K大于或等于1、且小于所述N。
  23. 如权利要求21或22所述的装置，其特征在于，所述处理单元根据系统极化码对所述待译码符号序列进行译码，确定信息比特序列时，具体用于根据所述待译码符号序列、所述极化变换矩阵、所述C中的冻结比特位与所述D中的非冻结比特位相互映射的关系、以及所述B与所述MA的比特位索引交集，确定第一中间译码比特序列；根据所述第一中间译码比特序列和所述极化变换矩阵，确定所述信息比特序列。
  24. 如权利要求23所述的装置，其特征在于，所述A根据所述信息比特序列确定，包括：所述A中包括所述信息比特的位置以及所述信息比特对应的循环冗余校验CRC比特的位置。
  25. 如权利要求24所述的装置，其特征在于，所述第一中间译码比特序列中包括第二中间译码比特序列和所述CRC比特，所述CRC比特用于对所述第二中间译码比特序列进行校验，其中所述第二中间译码比特序列对应所述信息比特的位置，所述CRC比特对应所述CRC比特的位置。
  26. 如权利要求21-25中任一项所述的装置，其特征在于，所述C中的冻结比特位与所述D中的非冻结比特位相互映射包括：所述C中的冻结比特位与所述D中的非冻结比特位根据映射矩阵相互映射，所述映射矩阵为NC维的满秩矩阵或者为NC维的单位阵，所述 NC等于所述C中冻结比特位的个数。
  27. 一种通信装置，其特征在于，包括处理器和接口电路，所述接口电路用于接收来自所述通信装置之外的其它通信装置的信号并传输至所述处理器，或将来自所述处理器的信号发送给所述通信装置之外的其它通信装置，所述处理器通过逻辑电路或执行代码指令用于实现如权利要求1-7中任一项所述的方法，或用于实现如权利要求8-13中任一项所述的方法。
  28. 一种计算机程序产品，其特征在于，包括程序代码，当所述程序代码被执行，使得如权利要求1-7中任一项所述的方法被实现，或如权利要求8-13中任一项所述的方法被实现。
  29. 一种芯片，其特征在于，所述芯片用于实现如权利要求1-7中任一项所述的方法，或用于实现如权利要求8-13中任一项所述的方法。
  30. 一种计算机可读存储介质，其特征在于，所述存储介质中存储有计算机程序或指令，当所述计算机程序或指令被执行时，使得如权利要求1-7中任一项所述的方法被实现，或如权利要求8-13中任一项所述的方法被实现。
  31. 一种通信系统，其特征在于，所述通信系统包括编码设备和译码设备；
    所述编码设备用于实现如权利要求1-7中任一项所述的方法；
    所述译码设备用于实现如权利要求8-13中任一项所述的方法。
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CN110495106A (zh) * 2017-04-18 2019-11-22 杜塞尔多夫华为技术有限公司 带有动态冻结比特的极化编码
CN111800172A (zh) * 2019-04-09 2020-10-20 华为技术有限公司 一种通信方法及装置
CN112886969A (zh) * 2019-11-30 2021-06-01 华为技术有限公司 一种极化码编码方法及装置
CN113162634A (zh) * 2021-04-20 2021-07-23 中山大学 一种基于比特翻转的码长自适应极化码译码方法

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CN110495106A (zh) * 2017-04-18 2019-11-22 杜塞尔多夫华为技术有限公司 带有动态冻结比特的极化编码
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