WO2018171764A1 - 一种构造极化码序列的方法及装置 - Google Patents

一种构造极化码序列的方法及装置 Download PDF

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WO2018171764A1
WO2018171764A1 PCT/CN2018/080347 CN2018080347W WO2018171764A1 WO 2018171764 A1 WO2018171764 A1 WO 2018171764A1 CN 2018080347 W CN2018080347 W CN 2018080347W WO 2018171764 A1 WO2018171764 A1 WO 2018171764A1
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Prior art keywords
sequence
rate matching
reliability
length
constructing
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PCT/CN2018/080347
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English (en)
French (fr)
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黄凌晨
张公正
徐晨
张朝龙
王俊
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华为技术有限公司
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Priority to EP18746067.0A priority Critical patent/EP3422620A4/en
Priority to US16/058,118 priority patent/US10880038B2/en
Publication of WO2018171764A1 publication Critical patent/WO2018171764A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0002—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission rate
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H04L1/0058—Block-coded modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/618—Shortening and extension of codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching

Definitions

  • the present application relates to the field of communications, and in particular, to a technical solution for constructing a polarization code sequence.
  • the rapid evolution of wireless communication indicates that the future 5G communication system will present some new features.
  • the most typical three communication scenarios include eMBB (English full name: Enhanced Mobile Broadband, Chinese full name: enhanced mobile broadband), mMTC (English full name: Massive Machine Type Communication, full name in Chinese: massive machine connection communication) and URLLC (English full name: Ultra Reliable Low Latency Communication, full name in Chinese: high reliability and low latency communication), the demand for these communication scenarios will propose new LTE technology challenge.
  • channel coding is one of the important research objects to meet the needs of 5G communication.
  • Shannon's theory was put forward, researchers from all over the world have been working on finding a codec method that can reach the Shannon limit and have relatively low complexity.
  • the LDPC code has been adopted as the data channel coding scheme of the eMBB scenario
  • the Polar code sequence has been adopted as the control channel coding scheme of the eMBB scenario.
  • the URLLC and mMTC scenarios impose strict requirements on the delay and reliability of channel coding.
  • Polar Codes are An encoding method based on channel polarization.
  • the polarization code sequence is the first and only known channel coding method that can be rigorously proven to "reach" the channel capacity.
  • the Polar code sequence is a linear block code. Its generator matrix is F N and its encoding process is among them Is a binary line vector of length N (ie code length); F N is an N ⁇ N matrix, and Here
  • a part of the bits are used to carry information, called information bits, and the set of indexes of these bits is recorded as It is called a set of information bit positions or a set of information bit numbers; another part of the bits is set to a fixed value pre-agreed by the transceiver, which is called a fixed bit, and the set of indexes is used.
  • the information bits are the part carrying the information.
  • the check bits are included in the information bits.
  • the construction process of the Polar code sequence includes online calculation of the reliability (error probability) of each subchannel and the offline storage construction sequence, the reliability ranking sequence and the like.
  • the present application provides a method and a corresponding apparatus for constructing a polarization code sequence.
  • the technical solution provided by the embodiment of the present application is to map each element of the reliability ranking sequence ⁇ Q i , 0 ⁇ i ⁇ N max ⁇ (hereinafter referred to as the sequence Q) one by one into one deformation when constructing the Polar code sequence.
  • the constructed sequence ⁇ P i , 0 ⁇ i ⁇ N max ⁇ (hereinafter referred to as sequence P)
  • the rate matching is implicit in the mapped constructed sequence P.
  • the present application provides an apparatus for constructing a polarization code sequence, comprising: a memory for storing a construction sequence P; the construction sequence P is generated according to a reliability ranking sequence Q and a rate matching rule;
  • a processor for reading from the construction sequence P a construction sequence P' having the same length as the code length of the polarization code sequence to be constructed; the processor is further configured to use the construction sequence P according to a rate matching rule 'De-mapping into a reliability ranking sequence Q'; constructing a polarization code sequence according to the reliability ranking sequence Q'.
  • the rate matching rule is a rate matching function or a rate matching sequence, and the rate matching sequence is any one of the following five types:
  • the rate matching rule is a combination of two rate matching sequences, and the two rate matching sequences are any one of the following four types:
  • a terminal provided by the embodiment of the present application may be implemented by using a hardware, and the structure includes a transceiver and a processor.
  • the corresponding software implementation can also be performed by hardware.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the modules can be software and/or hardware.
  • the network side device provided by the embodiment of the present application may be a base station or a control node.
  • the embodiment of the present application provides a base station, which has a function of realizing the behavior of a base station in the foregoing method.
  • the functions may be implemented by hardware or by corresponding software implemented by hardware.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the structure of the base station includes a processor and a transceiver configured to support the base station to perform the corresponding functions in the above methods.
  • the transceiver is configured to support communication between the base station and the UE, and send information or signaling involved in the foregoing method to the UE, and receive information or instructions sent by the base station.
  • the base station can also include a memory for coupling with the processor that stores the necessary program instructions and data for the base station.
  • an embodiment of the present application provides a control node, which may include a controller/processor, a memory, and a communication unit.
  • the controller/processor can be used to coordinate resource management and configuration between multiple base stations, and can be used to perform the methods described in the above embodiments.
  • the memory can be used to store program code and data for the control node.
  • the communication unit is configured to support the control node to communicate with the base station.
  • an embodiment of the present application provides a communication system, where the system includes the base station and the terminal in the foregoing aspect.
  • the control node in the above embodiment may also be included.
  • the embodiment of the present application provides a computer storage medium for storing computer software instructions used by the base station, which includes a program designed to perform the above aspects.
  • the embodiment of the present application provides a computer storage medium for storing computer software instructions used by the terminal, which includes a program designed to execute the above aspects.
  • FIG. 1 is a schematic diagram of a method for implementing a method for constructing a polarization code sequence provided by the present application
  • Embodiment 1 is a schematic diagram of Embodiment 1 of a method for constructing a polarization code sequence provided by the present application;
  • Embodiment 3 is a flowchart of Embodiment 1 of a method for constructing a polarization code sequence provided by the present application;
  • Embodiment 4 is a schematic diagram of Embodiment 2 of a method for constructing a polarization code sequence provided by the present application;
  • Embodiment 5 is a flowchart of Embodiment 2 of a method for constructing a polarization code sequence provided by the present application;
  • Embodiment 3 is a schematic diagram of Embodiment 3 of a method for constructing a polarization code sequence provided by the present application;
  • FIG. 7 is a flowchart of Embodiment 3 of a method for constructing a polarization code sequence provided by the present application;
  • Embodiment 8 is a schematic diagram of Embodiment 4 of a method for constructing a polarization code sequence provided by the present application;
  • Embodiment 9 is a flowchart of Embodiment 4 of a method for constructing a polarization code sequence provided by the present application.
  • FIG. 10 is a schematic structural diagram of an apparatus for constructing a polarization code sequence provided by the present application.
  • Channel coding which improves data transmission reliability and guarantees communication quality, is the most basic wireless access technology.
  • the source information is first channel-coded, and then the encoded information is rate-matched and digitally modulated.
  • the code-modulated information is transmitted to the receiving end through the channel, and corresponding digital demodulation is performed at the receiving end.
  • the solution rate is matched, and finally the information is obtained by a decoding technique corresponding to the channel coding.
  • the embodiment of the present application provides a technical solution for constructing a sequence of a Polar code sequence in the channel coding process as shown in FIG. 1.
  • the subchannels corresponding to the values of the elements having the smaller sequence number i have lower reliability (the reliability is sorted from low to high) or the subcorresponding to the values of the elements having the smaller sequence number i.
  • the reliability of the channel is high (the reliability is ordered from high to low).
  • sequence Q each element of the reliability ranking sequence Q (hereinafter referred to as sequence Q) is mapped one by one into a deformed construction sequence P (hereinafter referred to as sequence P), and the rate matching rule is implicit in the mapped construction sequence P.
  • the process of calculating the sequence P is usually calculated offline. Before constructing the polarization code sequence, the calculated sequence P (one or more) is stored, and the reliability ordering sequence Q is usually not stored. .
  • the sequence P is read and the polarization code sequence to be constructed is read. Constructing a sequence P' of the same length of the code length M; then de-mapping the constructed sequence P' into a reliability sorting sequence Q' according to the rate matching rule; finally, according to the reliability sorting sequence Q', the length of the constructed information is K, and the encoding length is The polarization code sequence of M.
  • K info + K check is selected to have the highest reliability except the punctured bits, where K info is the number of information bits, K check is the number of check bits, and the check
  • the bits include, but are not limited to, CRC bits or dynamic check bits, K check ⁇ 0.
  • the corresponding information sequence and dynamic check bit sequence (if any) are then mapped to these most reliable locations; the rest is a set of static freeze bit positions whose values are set to fixed values agreed upon at both ends.
  • the check bits are included in the information bits.
  • the information bit number set is first obtained as an example for description. First, the frozen bit number set is obtained, and then the complement is obtained to obtain the information bit sequence. The principle of the combination is the same, and details are not described herein.
  • This embodiment mainly describes a reliability ranking sequence ⁇ Q i , 0 ⁇ i ⁇ N for any single rate matching rule (ie, there is no need to switch between multiple rate matching rules according to working conditions) and a given Polar code sequence.
  • N 2 n ⁇
  • N is the length of the Q sequence
  • the construction code length M The process of the Polar code sequence of information length K.
  • the reliability ranking sequence Q calculates the construction sequence P, and then constructs the Polar code sequence using this construction sequence P.
  • FIG. 2 The process of constructing a Polar code sequence in the embodiment of the present application is shown in FIG. 2, and the flow thereof is shown in FIG. 3, and the implementation steps are as follows:
  • step 100 a construction sequence P' having a length of code length M is read from a construction sequence P of length N.
  • Step 101 Demap the constructed sequence P' into a reliability sorting sequence Q' according to a rate matching rule
  • Step 102 reading K elements having the largest reliability value from the sequence of reliability ranking sequence Q', to obtain a set of information bit numbers Its complement (relative to the set ⁇ 0, 1, 2, ..., N-1 ⁇ ) is a set of frozen bit positions.
  • the configuration sequence P of length N in the foregoing step 100 is obtained by offline calculation based on the reliability ranking sequence Q and rate matching, and the calculation steps are as follows:
  • a rate matching sequence ⁇ RM i , 0 ⁇ i ⁇ N ⁇ is obtained, wherein the larger the number i, indicates that the corresponding bit position RM i will be preferentially punctured or shortened;
  • the foregoing step 101 demaps the constructed sequence P′ into a sequence of the reliability sorting sequence Q′ according to the rate matching rule, and may be mapped in a function form or a sequence form.
  • the rate matching rules applicable to the puncturing or shortening sequence include, but are not limited to, the following Table 1. Five kinds.
  • Matching rules at the second rate BIV(.) is an example of bit reverse order.
  • the rate matching sequence is as shown in Table 3:
  • mapping is performed in a sequence form, but the embodiment of the present application may also be mapped in other forms such as a function.
  • the information bit sequence set may also be referred to as a information bit position set.
  • This implementation will describe the process of constructing a Polar code sequence based on a reliability ordering sequence Q with nested features.
  • the rate matching sequence ⁇ RM i , 0 ⁇ i ⁇ N max ⁇ is obtained, wherein the larger the number i is, the representation
  • the corresponding bit position RM i will be preferentially punctured or shortened;
  • Step 200 reading a subset of P i ⁇ M from a constructed sequence ⁇ P i , 0 ⁇ i ⁇ N max ⁇ corresponding to a mother code sequence having a maximum length of N max to form a structural sequence P′;
  • Step 201 demap the constructed sequence P' into a reliability sorting sequence Q';
  • Step 202 Read K elements with the highest reliability value from the sequence of reliability ordering sequence Q' to obtain a set of information bit numbers Its complement (relative to the set ⁇ 0, 1, 2, ..., N-1 ⁇ ) is a set of frozen bit positions.
  • step 201 of the embodiment when the structure sequence P′ is demapped into the reliability ordering sequence Q′ according to the rate matching rule, the used mapping sequence MAP n is calculated as follows.
  • the rate matching rules applicable to the puncturing or shortening sequence include but are not limited to the five shown in Table 1. Kind.
  • the rate matching rule 1 is used.
  • the reliability ranking sequence Q is as shown in Table 6.
  • the rate matching sequence is as shown in Table 7, and the generated structure sequence P is as shown in Table 8. Shown.
  • Q i MAP n ([P i ]), 0 ⁇ i ⁇ N
  • This embodiment will describe a process of constructing a Polar code sequence based on the reliability ranking sequence Q and the combined rate matching rule.
  • the rate matching rule is a combination of two rate matching rules, and the maximum puncturing or shortened set complement of the two rate matching rules (because the length of the Polar code sequence is 2, any single puncturing or shortening
  • the two rate matching rules are rate matching rule 1 and rate matching rule 2, respectively, and the combination of the two is a combined rate matching rule.
  • the construction sequence P sequence and the mapping MAP are calculated, so that the schematic diagram of the construction process of the Polar code sequence of the code length M and the information length K is as shown in FIG. 6.
  • the flow is shown in FIG. 7, and the implementation steps are as follows:
  • Step 300 according to the switching condition of the combined rate matching, reading the structure sequence P' of the length M in the structure P;
  • Step 301 according to the mapping MAP, mapping the construction sequence P' to the reliability ranking sequence Q';
  • Step 302 reading K elements having the largest reliability value from the reliability sorting sequence Q' to obtain a set of information bit numbers Its complement (relative to the set ⁇ 0, 1, ..., N-1 ⁇ ) is a set of frozen bit positions.
  • the structural sequence P of length N is obtained according to the reliability sorting sequence Q sequence and the rate matching rule, and the calculation steps are as follows:
  • a rate matching sequence ⁇ RM i , 0 ⁇ i ⁇ N ⁇ is obtained, wherein the larger the number i, the corresponding The bit position RM i will be preferentially punctured or shortened by the rate matching rule 1. The smaller the number i is, the corresponding bit position RM i will be preferentially punctured or shortened by the rate matching rule 2;
  • the rate matching rules applicable to the puncturing or shortening sequence include, but are not limited to, the following Table 9. Four.
  • the generated P sequence is shown in Table 3.3.
  • the encoding code length 6 and the information length 4 of the Polar code sequence are assumed to be the rate matching rule 1.
  • the implementation steps of this embodiment are as follows:
  • Reading six sequence elements whose element values are less than 6 in the construction sequence P, and composing a structure sequence P' ⁇ 0,4,1,2,5,3 ⁇ ;
  • the encoding code length 6 and the information length 4 of the Polar code sequence are assumed to be the rate matching rule 2.
  • the implementation steps of this embodiment are as follows:
  • Reading 6 elements whose reliability P is greater than or equal to 2 and less than 8, forming a structural sequence P' ⁇ 4, 2, 6, 5, 3, 7 ⁇ ;
  • This implementation will describe a process of constructing a Polar code sequence based on a reliability ordering sequence Q with nested features and a combined rate matching rule.
  • the two rate matching rules are rate matching rule 1 and rate matching rule 2, respectively, and the combination of the two is a combined rate matching rule.
  • Figure 9 shows the following:
  • Step 400 according to the switching condition of the combined rate matching, the structural sequence P' of the encoding code length M is read from the structural sequence P having the largest length N max ;
  • Step 401 mapping P' to the sequence Q' according to the mapping MAP
  • Step 402 reading K elements having the largest reliability value from the sequence Q' to obtain a set of information bit numbers Its complement (relative to the set ⁇ 0, 1, ..., N-1 ⁇ ) is a set of frozen bit positions.
  • the P sequence in step 400 is obtained according to the reliability sorting Q sequence and the combined rate matching rule, and the calculation steps are as follows:
  • mapping MAP demaps the P' sequence into a Q' sequence, and the mapping process may take the form of a function or a sequence.
  • N 2 n ⁇ N max , the MAP calculation steps are as follows:
  • the rate matching rules applicable to the puncturing or shortening sequence include but are not limited to those shown in the foregoing Table 9. Five kinds.
  • the rate matching rule 1 is used.
  • the reliability ranking sequence Q is as shown in Table 13.
  • the sequence corresponding to the combined rate matching rule is as shown in Table 14. If the rate matching rule 1 is adopted, , the order of punching or shortening is [15,14,13,12,11,7,10,6]. If rate matching rule 2 is used, the order of punching or shortening is [0,1,2,3,4 , 8, 5, 9].
  • the generated construction sequence P is as shown in Table 15.
  • the reliability ranking sequence Q' can be mapped, and the mapping in the form of a sequence is used here, but other forms including functions and the like are not excluded.
  • a Polar code sequence with an encoding code length of 12 and an information length of 8 is constructed. Assuming that the rate matching rule 1 is used, the process of obtaining the information bit number set is as follows:
  • a Polar code sequence with an encoding code length of 12 and an information length of 6 is constructed. Assuming that the rate matching rule 2 is used, the process of obtaining the information bit number set is as follows:
  • the reliability matching sequence is mapped, and the rate matching process is incorporated into the sequence construction process, so that the constructed sequence can better match the subsequent rate matching process.
  • the rate matching process is incorporated into the sequence construction process, so that the constructed sequence can better match the subsequent rate matching process.
  • each scheme for constructing a polarization code sequence provided by the embodiment of the present application is introduced from the perspective of constructing a sequence by combining a construct sequence and a rate matching sequence, and obtaining a set of information bit numbers.
  • each network element such as a terminal, a base station, a control node, etc., includes a hardware structure and/or a software module corresponding to each function.
  • the present application can be implemented in a combination of hardware or hardware and computer software in combination with the elements and algorithm steps of the various examples described in the embodiments disclosed herein.
  • the device for constructing a polarization code sequence provided by the present application, in a specific implementation, as shown in FIG. 10, includes:
  • a memory 403 configured to store a construction sequence P; the construction sequence P is generated according to a reliability ranking sequence Q and a rate matching rule;
  • controller/processor 402 for reading, from the construction sequence P, a construction sequence P' having the same length as the code length of the polarization code sequence to be constructed;
  • the controller/processor 402 is further configured to demap the constructed sequence P′ into a reliability sorting sequence Q′ according to a rate matching rule; construct a polarization code sequence according to the reliability sorting sequence Q′.
  • controller/processor 402 is further configured to read an element RM i from a rate matching sequence that characterizes rate matching one by one, wherein ⁇ RM i , 0 ⁇ i ⁇ N ⁇ , and
  • the reliability ranking sequence Q is that the controller/processor 402 reads the sequential position sequence from the maximum length reliability ranking sequence.
  • the controller/processor 402 demaps the constructed sequence P' into a reliability ordering sequence Q' according to rate matching, in the form of sequence mapping or function mapping.
  • the rate matching rule RM may be a rate matching sequence or a combination of two rate matching sequences.
  • the controller/processor 402 is further configured to select a rate matching sequence from a combination of two rate matching sequences according to a code length, an information bit length, and a code rate of the constructed polarization code sequence.
  • the method for constructing the polarization code sequence provided by the present application may perform the method steps in the first method to the fourth embodiment of the foregoing method, and details are not described herein again.
  • controller/processor 402 may be implemented by circuitry or by general purpose hardware executing software code which, when employed, is also used to store program code that can be executed by the controller/processor 402. The foregoing functions are performed when the controller/processor 402 runs the program code stored in the memory 403.
  • the apparatus for constructing a polarization code sequence may further include an encoder 4051, a modulator 4052, a demodulator 4054, and a decoder 4053.
  • the encoder 4051 is configured to acquire data/signaling that the network side device is to send to the terminal or the terminal is to be sent to the network side device, and encode the data/signaling.
  • the modulator 4052 modulates the data/signal coded by the encoder 4051 and transmits it to the transceiver 401, which is sent by the transceiver 401 to the terminal or other network side device.
  • the demodulator 4054 is configured to acquire data and signaling sent by the terminal or other network side device, and perform demodulation.
  • the decoder 4053 is configured to decode the demodulated data/signal of the demodulator 4054.
  • the encoder 4051, the modulator 4052, the demodulator 4054, and the decoder 4053 described above may be implemented by a synthesized modem processor 405. These units are processed according to the radio access technology employed by the radio access network (e.g., access technologies of LTE and other evolved systems).
  • the radio access network e.g., access technologies of LTE and other evolved systems.
  • the network side device may further include a communication interface 404 for supporting communication between the device configuring the polarization code sequence and other network entities.
  • a communication interface 404 for supporting communication between the device configuring the polarization code sequence and other network entities.
  • Figure 10 only shows a simplified design of the apparatus for constructing a polarization code sequence.
  • the transceiver 401 described above may include a transmitter and a receiver, and the device may include any number of transceivers, processors, controllers/processors, memories, and/or communication interfaces, and the like.
  • the foregoing device may be a terminal or a network side device.
  • the network side device can in turn be a base station or a control node.
  • the controller/processor of the above base station, terminal, or control node of the present application may be a central processing unit (CPU), a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), and a field programmable gate array ( FPGA) or other programmable logic device, transistor logic device, hardware component, or any combination thereof. It is possible to implement or carry out the various illustrative logical blocks, modules and circuits described in connection with the present disclosure.
  • the processor may also be a combination of computing functions, for example, including one or more microprocessor combinations, a combination of a DSP and a microprocessor, and the like.
  • the steps of a method or algorithm described in connection with the present disclosure may be implemented in a hardware or may be implemented by a processor executing software instructions (eg, program code).
  • the software instructions may be comprised of corresponding software modules that may be stored in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable hard disk, CD-ROM, or any other form of storage well known in the art.
  • An exemplary storage medium is coupled to the processor to enable the processor to read information from, and write information to, the storage medium.
  • the storage medium can also be an integral part of the processor.
  • the processor and the storage medium can be located in an ASIC. Additionally, the ASIC can be located in the terminal.
  • the processor and the storage medium can also exist as discrete components in the terminal.
  • the functions described herein can be implemented in hardware, software, firmware, or any combination thereof.
  • the functions may be stored in a computer readable medium or transmitted as one or more instructions or code on a computer readable medium.
  • Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another.
  • a storage medium may be any available media that can be accessed by a general purpose or special purpose computer.

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Abstract

本申请实施例提供了一种构造极化码序列的方法及装置，所述方法包括：从构造序列P中读取与所要构造的极化码序列的编码码长相同长度的构造序列P'；所述构造序列P是根据可靠度排序序列Q和速率匹配规则生成的；根据速率匹配，将所述构造序列P'解映射为可靠度排序序列Q'；根据所述可靠度排序序列Q'构造极化码序列。实施本申请，将速率匹配过程与极化码序列构造过程结合在一起，有效的提升了构造极化码序列的效率，能更好的适应速率匹配过程。

Description

一种构造极化码序列的方法及装置
本申请要求于2017年3月24日提交中国专利局、申请号为201710184924.5、申请名称为“一种构造极化码序列的方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信领域，尤其涉及一种构造极化码序列的技术方案。
背景技术
无线通信的快速演进预示着未来5G通信系统将呈现出一些新的特点，最典型的三个通信场景包括eMBB(英文全称：Enhanced Mobile Broadband，中文全称：增强型移动宽带)，mMTC(英文全称：Massive Machine Type Communication，中文全称：海量机器连接通信)和URLLC(英文全称：Ultra Reliable Low Latency Communication，中文全称：高可靠低时延通信)，这些通信场景的需求将对现有LTE技术提出新的挑战。
信道编码作为最基本的无线接入技术，是满足5G通信需求的重要研究对象之一。在香农理论提出后，各国学者一直致力于寻找能够达到香农极限同时具有相对较低复杂度的编译码方法。在5G的标准制定进展中，LDPC码已经被采纳为eMBB场景的数据信道编码方案，而Polar码序列已经被采纳为eMBB场景的控制信道编码方案。而URLLC与mMTC场景则对信道编码的时延和可靠度提出了严格的要求。
极化码序列(Polar Codes)是
Figure PCTCN2018080347-appb-000001
基于信道极化提出的一种编码方式。极化码序列是第一种、也是已知的唯一一种能够被严格证明“达到”信道容量的信道编码方法。
Polar码序列的编译码的简单描述如下：
Polar码序列是一种线性块码。其生成矩阵为F N,其编码过程为
Figure PCTCN2018080347-appb-000002
其中
Figure PCTCN2018080347-appb-000003
是一个二进制的行矢量，长度为N(即码长)；F N是一个N×N的矩阵，且
Figure PCTCN2018080347-appb-000004
这里
Figure PCTCN2018080347-appb-000005
Figure PCTCN2018080347-appb-000006
定义为log 2N个矩阵F 2的克罗内克(Kronecker)乘积；以上涉及的加法、乘法操作均为二进制伽罗华域(Galois Field)上的加法、乘法操作。Polar码序列的编码过程中，
Figure PCTCN2018080347-appb-000007
中的一部分比特用来携带信息，称为信息比特，这些比特的索引的集合记作
Figure PCTCN2018080347-appb-000008
称为信息比特位置集合或者信息比特 序号集合；另外的一部分比特置为收发端预先约定的固定值，称之为固定比特，其索引的集合用
Figure PCTCN2018080347-appb-000009
的补集
Figure PCTCN2018080347-appb-000010
表示。
注意到，在经典的Polar码序列中，信息比特为携带信息的部分。而实际中，由于Polar码序列编码之前，信息比特还会经历循环冗余校验编码、奇偶校验编码等，Polar码序列的构造过程的索引集合
Figure PCTCN2018080347-appb-000011
包括K_info+K_check个除打孔比特外可靠度最高的信息比特序号，其中，K_info为信息比特数量，K_check为校验比特数量，校验比特包括但不限于CRC比特和动态校验比特，K_check>＝0。不失一般性的，下文在Polar的构造举例中，以信息比特数量K为例，校验比特包含在信息比特中。
根据信息比特长度、编码码字的长度，确定信息比特集合
Figure PCTCN2018080347-appb-000012
的过程称为Polar码序列的构造过程。目前，Polar码序列的构造包括在线计算每个子信道的可靠度(错误概率)和离线存储构造序列、可靠度排序序列等方法。
但是，发明人在本申请的创造过程中发现，现有技术构造极化码序列的构造序列的效率较低。
发明内容
为解决现有技术中存在的构造极化码序列时，效率低下的问题，本申请提供了一种构造极化码序列的方法和相应的装置。
本申请实施例提供的技术方案是在进行Polar码序列构造的时候，将可靠度排序序列{Q i,0≤i＜N max}(后续简称序列Q)的每个元素一一映射为一个变形的构造序列{P i,0≤i＜N max}(后续简称序列P)，速率匹配隐含在映射后的构造序列P中。在构造极化码序列时，首先从构造序列P中读取与所要构造的极化码序列的码长相同长度的构造序列P'；然后根据速率匹配规则将构造序列P'解映射为可靠度排序序列Q'；最后根据所述可靠度排序序列Q'构造极化码序列。
另一方面，本申请提供了一种构造极化码序列的装置，包括：存储器，用于存储构造序列P；所述构造序列P是根据可靠度排序序列Q和速率匹配规则生成的；
处理器，用于从构造序列P中读取与所要构造的极化码序列的编码码长相同长度的构造序列P'；所述处理器还用于根据速率匹配规则，将所述构造序列P'解映射为可靠度排序序列Q'；根据所述可靠度排序序列Q'构造极化码序列。
其中，所述速率匹配规则为速率匹配函数或速率匹配序列，所述速率匹配序列为如下五种中的任意一种：
Figure PCTCN2018080347-appb-000013
Figure PCTCN2018080347-appb-000014
所述速率匹配规则为两种速率匹配序列的组合，所述两种速率匹配序列为如下四种中的任意一种：
Figure PCTCN2018080347-appb-000015
本申请实施例提供的一种终端，该所述功能可以通过硬件实现，其结构中包括收发器和处理器。也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。所述模块可以是软件和/或硬件。
再一方面，本申请实施例提供的网络侧设备，该网络侧设备可以是一种基站，也可以是一种控制节点。
另一方面，本申请实施例提供了一种基站，该基站具有实现上述方法实际中基站 行为的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。
在一个可能的设计中，基站的结构中包括处理器和收发器，所述处理器被配置为支持基站执行上述方法中相应的功能。所述收发器用于支持基站与UE之间的通信，向UE发送上述方法中所涉及的信息或者信令，接收基站所发送的信息或指令。所述基站还可以包括存储器，所述存储器用于与处理器耦合，其保存基站必要的程序指令和数据。
又一方面，本申请实施例提供了一种控制节点，可以包括控制器/处理器，存储器以及通信单元。所述控制器/处理器可以用于协调多个基站之间的资源管理和配置，可以用于执行上述实施例描述的方法。存储器可以用于存储控制节点的程序代码和数据。所述通信单元，用于支持该控制节点与基站进行通信。
又一方面，本申请实施例提供了一种通信系统，该系统包括上述方面所述的基站和终端。可选地，还可以包括上述实施例中的控制节点。
再一方面，本申请实施例提供了一种计算机存储介质，用于储存为上述基站所用的计算机软件指令，其包含用于执行上述方面所设计的程序。
再一方面，本申请实施例提供了一种计算机存储介质，用于储存为上述终端所用的计算机软件指令，其包含用于执行上述方面所设计的程序。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图作简单地介绍，显而易见地，下面所描述的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请提供的构造极化码序列的方法实施场景示意图；
图2是本申请提供的构造极化码序列的方法实施例一的示意图；
图3是本申请提供的构造极化码序列的方法实施例一的流程图；
图4是本申请提供的构造极化码序列的方法实施例二的示意图；
图5是本申请提供的构造极化码序列的方法实施例二的流程图；
图6是本申请提供的构造极化码序列的方法实施例三的示意图；
图7是本申请提供的构造极化码序列的方法实施例三的流程图；
图8是本申请提供的构造极化码序列的方法实施例四的示意图；
图9是本申请提供的构造极化码序列的方法实施例四的流程图；
图10是本申请提供的构造极化码序列的装置的结构示意图。
具体实施方式
下面将描述本申请所提供的实施例。
下一代通信网络中，最典型的三个通信场景包括eMBB,mMTC和URLLC，这些 通信场景的需求将对现有LTE技术提出新的挑战。作为提高数据传输可靠性，保证通信质量的信道编码是最基本的无线接入技术。如图1所示，首先对信源信息进行信道编码，然后对编码后的信息进行速率匹配和数字调制，经过编码调制后的信息经过信道传输至接收端，在接收端进行对应的数字解调和解速率匹配，最后通过与信道编码对应的译码技术，获得信息。
本申请实施例提供一种在如图1所示的信道编码过程中，构造Polar码序列构造序列的技术方案。
首先对给定长度的可靠度排序序列Q，序号i较小的元素的值对应的子信道的可靠度较低(可靠度由低到高排序)或者序号i较小的元素的值对应的子信道的可靠度较高(可靠度由高到低排序)。
然后将可靠度排序序列Q(后续简称序列Q)的每个元素一一映射为一个变形的构造序列P(后续简称序列P)，将速率匹配规则隐含在映射后的构造序列P中。
根据序列Q和速率匹配，计算序列P的过程通常是离线计算的，在构造极化码序列之前，会存储计算好的序列P(1个或者多个)，通常不会存储可靠度排序序列Q。
在构造极化码序列时，首先从母码序列(可能是最大长度的母码序列，也可能是多个母码序列中的一个)构造序列P中读取与所要构造的极化码序列的编码码长M相同长度的构造序列P'；然后根据速率匹配规则将构造序列P'解映射为可靠度排序序列Q'；最后根据可靠度排序序列Q'，构造信息长度为K，编码长度为M的极化码序列。具体的，从可靠度排序序列Q'中，选择K info+K check个除打孔比特外可靠度最高的位置集合，其中，K info为信息比特数量，K check为校验比特数量，校验比特包括但不限于CRC比特或动态校验比特，K check≥0。然后将对应的信息序列和动态校验比特序列(如果有)映射到这些可靠度最高的位置；剩余的为静态冻结比特位置集合，其值设置为收发两端约定的固定值。不失一般性的，下文在Polar码序列的构造举例中，以信息比特数量K为例，校验比特包含在信息比特中。
后续的实施例的举例中，以首先获得信息比特序号集合为例进行说明，先获得冻结比特序号集合，然后再取其补集获得信息比特序列结合原理相同，不再赘述。
以下将分实施例一至实施例四，描述本申请提供的构造极化码序列的方法。
实施例一
本实施例主要描述对任意单一速率匹配规则(即不需要根据工作条件在多种速率匹配规则之间切换)和给定的Polar码序列构造的可靠度排序序列{Q i,0≤i＜N,N＝2 n}，N为Q序列长度，计算映射有速率匹配规则的构造序列P序列，构造码长M
Figure PCTCN2018080347-appb-000016
信息长度K的Polar码序列的过程。
需要说明的是：对于码长
Figure PCTCN2018080347-appb-000017
时，会基于长度为
Figure PCTCN2018080347-appb-000018
的可靠度排序序列Q计算构造序列P，然后使用这个构造序列P构造Polar码序列。
本申请实施例构造Polar码序列的过程示意如图2所示，其流程如图3所示，其实现步骤如下：
步骤100，从长度为N的构造序列P中读取长度为编码码长M的构造序列P'。
步骤101，根据速率匹配规则，将构造序列P'解映射为可靠度排序序列Q'；
步骤102，从可靠度排序序列Q'序列中读取可靠度值最大的K个元素，得到信息比特序号集合
Figure PCTCN2018080347-appb-000019
其补集
Figure PCTCN2018080347-appb-000020
(相对于集合{0,1,2,...,N-1})为冻结比特位置集合。
需要说明的是，前述步骤100中长度为N的构造序列P，是根据可靠度排序序列Q和速率匹配离线计算得到的，计算步骤如下：
(1)根据速率匹配，得到速率匹配序列{RM i,0≤i＜N}，其中序号i越大，表示对应的比特位置RM i将优先被打孔或缩短；
(2)根据长度为N＝2 n的可靠度排序序列Q和速率匹配序列{RM i,0≤i＜N}，按照从后往前的顺序逐个读取该速率匹配序列中的元素，并在靠度排序序列Q中搜索满足Q j＝RM i的元素；
(3)设置P j＝i；
(4)重复以上步骤，直到读取完所有的速率匹配序列的元素，组成长度为N的构造序列P。
另外，上述步骤101根据速率匹配规则，将构造序列P'解映射为可靠度排序序列Q'序列的过程，可以采用函数形式或者序列形式进行映射。
本实施例一中，对编码后的码字c 0,c 1,c 2,...c N-1，其打孔或缩短顺序适用的速率匹配规则包括但不限于下表1所示的五种。
表1
Figure PCTCN2018080347-appb-000021
Figure PCTCN2018080347-appb-000022
以第二种速率匹配规则
Figure PCTCN2018080347-appb-000023
BIV(.)为比特逆序为例，对于码长为N＝8的可靠度排序序列Q如表2所示，速率匹配序列如表3所示：
表2 可靠度排序序列Q
0 1 2 4 3 5 6 7
表3 速率匹配序列
7 3 5 1 6 2 4 0
根据表2所示的可靠度排序序列Q，按照从后往前的顺序逐个读取表3所示的速率匹配序列中的元素，并在表2的Q序列中搜索满足Q j＝RM i的元素；设置P j＝i；其过程表示如表4所示：
表4 构造序列P的生成过程
7              
7     6        
7   5 6        
7   5 6     4  
7 3 5 6     4  
7 3 5 6   2 4  
7 3 5 6 1 2 4  
7 3 5 6 1 2 4 0
重复以上步骤，直到读取完所有的速率匹配序列的元素，组成长度为N的构造序列P如表5所示。
表5 构造序列P
7 3 5 6 1 2 4 0
本实施例一中是采用序列形式的进行映射，但本申请实施例还可以采用函数等其它的形式进行映射。
对于编码码长6、信息长度4的构造Polar码序列的过程如下：
(1)从构造序列P＝{7,3,5,6,1,2,4,0}中读取元素值小于6的6个序列元素，不改变元素先后位置关系，组成构造序列P'＝{3,5,1,2,4,0}；
(2)根据映射序列MAP＝{RM i,0≤i＜N}＝{7,3,5,1,6,2,4,0}，对构造序列P'进行解映射，得到可靠度排序序列Q'＝{1,2,3,5,6,7}；
(3)选择Q'序列的后4个元素作为信息比特序号集合
Figure PCTCN2018080347-appb-000024
对应的冻结比特位置集合
Figure PCTCN2018080347-appb-000025
需要说明的是，所述信息比特序号集合还可以称为信息比特位置集合。
实施例二
本实施将描述依据具有嵌套特征的可靠度排序序列Q，构造Polar码序列的过程。
所谓的具有嵌套特征，是指的码长为N＝2 n的可靠度排序序列{Q i,0≤i＜N}可以从最大长度N max的母码序列对应的可靠度排序序列{Q i,0≤i＜N max}中保持先后位置取出Q i＜N的元素组成的集合。
本实施例中，根据{Q i,0≤i＜N max}计算序列{P i,0≤i＜N max}，结合映射MAP＝{RM i,0≤i＜N max}，使得对码长M、信息长度K的Polar码序列，构造Polar码序列的示意图如图4所示，流程如图5所示
首先，根据最大长度为N max的母码序列对应的可靠度排序序列Q max和速率匹配得到最大长度为N max的母码序列对应的构造序列P max的，计算步骤如下：
(1)对于最大长度为N max的母码序列对应的可靠度排序序列Q max，根据速率匹配规则，得到速率匹配序列{RM i,0≤i＜N max}，其中序号i越大，表示对应的比特位置RM i将优先被打孔或缩短；
(2)根据速率匹配序列{RM i,0≤i＜N max}，按照从后往前的顺序逐个读取该速率匹 配序列中的元素，并在最大长度为N max的Q max序列中搜索满足Q j＝RM i的元素；
(3)设置P j＝i；
(4)重复以上步骤，直到读取完所有的速率匹配序列的元素，组成最大长度为N max的构造序列P max。
利用组成最大长度为N max的母码序列对应的构造序列P max，构造Polar码序列的过程如下：
步骤200，从最大长度为N max的母码序列对应的构造序列{P i,0≤i＜N max}中保持先后顺序读取P i＜M的子集，形成构造序列P'；
步骤201，根据速率匹配规则，将构造序列P'解映射为可靠度排序序列Q'；
步骤202，从可靠度排序序列Q'序列中读取可靠度值最大的K个元素，得到信息比特序号集合
Figure PCTCN2018080347-appb-000026
其补集
Figure PCTCN2018080347-appb-000027
(相对于集合{0,1,2,...,N-1})为冻结比特位置集合。
需要说明的是，本实施例步骤201中，根据速率匹配规则，将构造序列P'解映射为可靠度排序序列Q'时，用到的映射序列MAP n是通过如下方式计算得到。
(1)从最大长度为N max的母码序列对应的构造序列{P i,0≤i＜N max}中保持先后顺序读取P i＜N的子集，形成构造序列P'；
(2)从最大长度为Q max的母码序列对应的构造序列{Q i,0≤i＜N max}中保持先后顺序读取Q i＜N的子集，形成构造序列Q'；
(3)根据Q i＝MAP n([P i]),0≤i＜N，计算映射MAP n；
对于不同的N＝2 n≤N max，重复步骤(1)到步骤(3)，计算不同长度的构造序列P'对应的映射MAP n。
本实施例二中，对编码后的码字c 0,c 1,c 2,...c N-1，其打孔或缩短顺序适用的速率匹配规则包括但不限于表1所示的五种。
以速率匹配规则1举例，对码长为N max＝16的Polar码序列，其可靠度排序序列Q如表6所示，速率匹配序列如表7所示，则生成的构造序列P如表8所示。
表6 最大长度N max＝16的母码序列对应的可靠度排序序列Q
0 1 2 4 8 3 5 6 9 10 12 7 11 13 14 15
表7 最大长度N max＝16的速率匹配序列
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
表8 最大长度N max＝16的构造序列P
15 14 13 11 7 12 10 9 6 5 3 8 4 2 1 0
根据最大长度N max＝16的构造序列P，采用函数形式的映射MAP x＝N-1-x，其中
Figure PCTCN2018080347-appb-000028
M为编码码长，
Figure PCTCN2018080347-appb-000029
为向上取整。根据Q i＝MAP n([P i]),0≤i＜N，计算得到映射MAP 4＝{15,14,13,12,11,7,10,6,9,5,8,4,3,2,1,0}，MAP 3＝{7,6,5,2,3,4,1,0}。
对Polar码序列的编码码长M＝12、信息长度K＝8的构造过程，如下：
(1)根据编码码长确定母码长度N＝16；
(2)从最大长度N max＝16的构造序列P中，读取值小于12的12个序列元素，组成构造序列P'＝{11,7,10,9,6,5,3,8,4,2,1,0}；
(3)根据映射MAP x＝N-1-x，得到可靠度排序序列Q'＝{4,8,5,6,9,10,12,7,11,13,14,15}；
(4)选择Q'序列的后8个元素作为信息比特序号集合
Figure PCTCN2018080347-appb-000030
对应的冻结比特位置集合
Figure PCTCN2018080347-appb-000031
对Polar码序列的编码码长6、信息长度4的构造过程，
(1)根据编码码长确定母码长度N＝8；
(2)从最大长度N max＝16的构造序列P中，读取值小于6的6个序列元素，组成构造序列P'＝{5,3,4,2,1,0}；
(3)根据映射MAP，得到可靠度排序序列Q'＝{2,4,3,5,6,7}；
(3)选择Q'序列的后4个元素作为信息比特序号集合
Figure PCTCN2018080347-appb-000032
对应的冻结比特位置集合
Figure PCTCN2018080347-appb-000033
实施例三
本实施将描述依据可靠度排序序列Q和组合速率匹配规则，构造Polar码序列的过程。
当速率匹配规则是两种速率匹配规则的组合，且这两种速率匹配规则的最大打孔或缩短的集合互补(由于Polar码序列母码长度为2的幂次，任意单一打孔或缩短的比特数量小 于母码长度的一半)，则可以使用构造序列P将组合的速率匹配序列和可靠度排序序列{Q i,0≤i＜N}(N为可靠度排序序列Q的长度)进行结合。本实施例中,两种速率匹配规则分别为速率匹配规则1和速率匹配规则2，两者的组合为组合速率匹配规则。据此，计算构造序列P序列和映射MAP，使得对码长M、信息长度K的Polar码序列的构造过程示意图如图6所示，其流程如图7所示，其实现步骤如下：
步骤300，根据组合速率匹配的切换条件，读取构造P中的长度为M的构造序列P'；
步骤301，根据映射MAP，将构造序列P'映射为可靠度排序序列Q'；
步骤302，从可靠度排序序列Q'中读取可靠度值最大的K个元素，得到信息比特序号集合
Figure PCTCN2018080347-appb-000034
其补集
Figure PCTCN2018080347-appb-000035
(相对于集合{0,1,…,N-1})为冻结比特位置集合。
需要说明的是，前述步骤300中长度为N的构造序列P，是根据可靠度排序序列Q序列和速率匹配规则得到的，计算步骤如下：
(1)对于码长为N＝2 n≤N max的可靠度排序序列Q，根据组合速率匹配规则，得到速率匹配序列{RM i,0≤i＜N}，其中序号i越大，表示对应的比特位置RM i将优先被速率匹配规则1打孔或缩短，序号i越小，则表示对应的比特位置RM i将优先被速率匹配规则2打孔或缩短；
(2)根据速率匹配序列{RM i,0≤i＜N}，按照从后往前的顺序逐个读取该速率匹配序列中的元素，并在Q序列中搜索满足Q j＝RM i的元素；
(3)设置P j＝i；
(4)重复以上步骤，直到读取完所有的速率匹配序列的元素，组成长度为N的构造序列P。
另外，上述步骤301根据速率匹配规则，将构造序列P'解映射为可靠度排序序列Q'的过程，可以采用函数形式或者序列形式进行映射，若采用序列形式，映射序列表示为MAP＝{RM i,0≤i＜N}。
本实施例三中，对编码后的码字c 0,c 1,c 2,...c N-1，其打孔或缩短顺序适用的速率匹配规则包括但不限于下表9所示的四种。
表9
Figure PCTCN2018080347-appb-000036
Figure PCTCN2018080347-appb-000037
以速率匹配规则3为例，对N＝8的Polar码序列码长，其可靠度排序序列Q如表10所示，组合速率匹配规则对应的序列如表11所示，若采用缩短的速率匹配(简称为速率匹配规则1)，则缩短顺序为[7,3,5,1]，若采用打孔的速率匹配(简称为速率匹配规则2)，则打孔顺序为[0,2,4,6]，因此组合的速率匹配序列为[0,2,4,6,1,5,3,7]。生成的P序列如表3.3所示。
表10 可靠度排序序列Q
0 1 2 4 3 5 6 7
表11 速率匹配序列
0 2 4 6 1 5 3 7
表12 构造序列P
0 4 1 2 6 5 3 7
本实施例中采用序列形式的映射，但不排除包括函数等其它的形式，MAP＝{0,2,4,6,1,5,3,7}。
对Polar码序列的编码码长6、信息长度4，假设采用速率匹配规则1，本实施例的实现步骤如下：
读取构造序列P中元素值小于6的6个序列元素，组成构造序列P'＝{0,4,1,2,5,3}；
根据MAP＝{0,2,4,6,1,5,3,7}，得到可靠度排序序列Q'＝{0,1,2,4,5,6}；
选择可靠度排序序列Q'的后4个元素作为信息比特序号集合
Figure PCTCN2018080347-appb-000038
对应的冻结比特位置集合
Figure PCTCN2018080347-appb-000039
对Polar码序列的编码码长6、信息长度4，假设采用速率匹配规则2，本实施例的实现步骤如下：
读取可靠度P中值大于等于2且小于8的6个元素，组成构造序列P'＝{4,2,6,5,3,7}；
根据MAP＝{0,2,4,6,1,5,3,7}，对构造序列P'＝{4,2,6,5,3,7}解映射，得到可靠度排序序列Q'＝{1,4,3,5,6,7}；
选择可靠度排序序列Q'的后4个元素作为信息比特序号集合
Figure PCTCN2018080347-appb-000040
对应的冻结比特位置集合
Figure PCTCN2018080347-appb-000041
实施例四
本实施将描述依据具有嵌套特征的可靠度排序序列Q和组合速率匹配规则，构造Polar码序列的过程。
若构造Polar码序列的可靠度排序序列{Q i,0≤i＜N max}(N max为Q序列长度)具有嵌套特征，则对N＝2 n＜N max，可靠度排序序列{Q i,0≤i＜N}为从序列{Q i,0≤i＜N max}中保持先后位置取出Q i＜N的元素组成的集合。
当速率匹配规则是两种速率匹配的组合，且这两种速率匹配规则的最大打孔或缩短的集合互补(由于Polar码序列母码长度N＝2 n≤N max，任意单一打孔或缩短的比特数量小于母码长度的一半)，则可以使用P序列将组合的速率匹配和可靠度排序序列Q i＜N进行结合。两种速率匹配规则分别为速率匹配规则1和速率匹配规则2，两者的组合为组合速率匹配规则。
基于实施例三，计算P序列和映射MAP，使得对编码码长M、母码码长N＝2 n≤N max、信息长度K的Polar码序列，构造过程如图8所示，其流程如图9所示，如下：
步骤400，根据组合速率匹配的切换条件，从最大长度为N max的构造序列P中读取编码码长M的构造序列P'；
步骤401，根据映射MAP，将P'映射为序列Q'；
步骤402，从序列Q'中读取可靠度值最大的K个元素，得到信息比特序号集合
Figure PCTCN2018080347-appb-000042
其补集
Figure PCTCN2018080347-appb-000043
(相对于集合{0,1,…,N-1})为冻结比特位置集合。
其中，步骤400中的P序列根据可靠度排序Q序列和组合速率匹配规则获得，计算步骤如下：
(1)根据组合速率匹配规则，计算速率匹配序列{RM i,0≤i＜N max}。其中，序号i越大，对应的比特位置RM i将优先被速率匹配规则1打孔或缩短；序号i越小，对应的比特位置RM i将优先被速率匹配规则2打孔或缩短；
(2)从后往前逐个读取速率匹配序列{RM i,0≤i＜N max}，并在Q序列中搜索Q j＝RM i；
(3)设置P j＝i；
重复以上步骤，直到读取完所有的速率匹配序列的元素，组成最大长度为N max的构造序列P。
映射MAP将P'序列解映射为Q'序列，映射过程可以采用函数形式或序列形式等。对不同N＝2 n≤N max，MAP计算步骤如下：
(1)从序列{P i,0≤i＜N max}中保持先后顺序读取P i＜N的子序列；
(2)从序列{Q i,0≤i＜N max}中保持先后顺序读取Q i＜N的子序列；
(3)根据Q i＝MAP n([P i]),0≤i＜N，计算映射MAP n
对不同N＝2 n≤N max，重复步骤(1)-(3)；
本实施例四中，对编码后的码字c 0,c 1,c 2,...c N-1，其打孔或缩短顺序适用的速率匹配规则包括但不限于前表9所示的五种。
以速率匹配规则1举例，对最大长度N max＝16的Polar码序列，其可靠度排序序列Q如表13所示，组合速率匹配规则对应的序列如表14所示，若采用速率匹配规则1，则打孔或缩短顺序为[15,14,13,12,11,7,10,6]，若采用速率匹配规则2，则打孔或缩短顺序为[0,1,2,3,4,8,5,9]。生成的构造序列P如表15所示。
表13 长度为16的可靠度排序序列Q
0 1 2 4 8 3 5 6 9 10 12 7 11 13 14 15
表14 长度为16的速率匹配序列
0 1 2 3 4 8 5 9 6 10 7 11 12 13 14 15
表15 长度为16的构造序列P
0 1 2 4 5 3 6 8 7 9 12 10 11 13 14 15
根据P序列和组合速率匹配规则，即可映射得到可靠度排序序列Q'，这里采用序列形式的映射，但不排除包括函数等其它的形式。组合映射MAP为，MAP 4＝{0,1,2,3,4,8,5,9,6,10,7,11,12,13,14,15}；MAP 3＝{0,1,2,5,4,3,6,7}。
构造编码码长为12、信息长度为8的Polar码序列，假设采用速率匹配规则1，得到信息比特序号集合的过程如下：
(1)根据编码码长确定母码长度N＝16；
(2)读取构造序列P中值小于12的12个元素，组成构造序列P'＝{0,1,2,4,5,3,6,8,7,9,10,11}；
(3)根据MAP 4，得到Q'＝{0,1,2,4,8,3,5,6,9,10,7,11}；
(4)选择Q'序列的后8个元素作为信息比特序号集合
Figure PCTCN2018080347-appb-000044
对应的冻结比特位置集合
Figure PCTCN2018080347-appb-000045
构造编码码长为12、信息长度为6的Polar码序列，假设采用速率匹配规则2，得到信息比特序号集合的过程如下：
(1)根据编码码长确定母码长度N＝16；
(2)读取构造序列P中值大于等于4且小于16的12个元素，组成构造序列P'＝{4,5,6,8,7,9,12,10,11,13,14,15}；
(3)根据MAP 4，对构造序列P'＝{4,5,6,8,7,9,12,10,11,13,14,15}解映射，得到可靠度排序序列Q'＝{4,8,5,6,9,10,12,7,11,13,14,15}；
(4)选择可靠度排序序列Q'序列的后6个元素作为信息比特序号集合
Figure PCTCN2018080347-appb-000046
Figure PCTCN2018080347-appb-000047
对应的冻结比特位置集合
Figure PCTCN2018080347-appb-000048
采用本申请实施例提供的构造极化码序列的方法，通过对可靠度排序序列进行映射，将速率匹配过程结合到序列的构造过程中，使得构造的序列能够更好的与后续的速率匹配过程向适配。
上述本申请提供的实施例中，从将构造序列和速率匹配序列相结合构造序列，并获得信息比特序号集合的角度对本申请实施例提供的构造极化码序列的各方案进行了介绍。可以理解的是，上述方法可以在各个网元中实现。各个网元，例如终端、基站，控制节点等为了实现上述功能，其包含了执行各个功能相应的硬件结构和/或软件模块。 本领域技术人员应该很容易意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，本申请能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
本申请提供的构造极化码序列的装置在具体实现中，如图10所示，包括：
存储器403，用于存储构造序列P；所述构造序列P是根据可靠度排序序列Q和速率匹配规则生成的；
控制器/处理器402，用于从构造序列P中读取与所要构造的极化码序列的编码码长相同长度的构造序列P'；
所述控制器/处理器402还用于根据速率匹配规则，将所述构造序列P'解映射为可靠度排序序列Q'；根据所述可靠度排序序列Q'构造极化码序列。
另外，所述控制器/处理器402，还用于从后往前逐个从表征速率匹配的速率匹配序列中，读取元素RM i，其中，{RM i,0≤i＜N}，并在可靠度排序序列Q中搜索Q j＝RM i；将满足Q j＝RM i的序号i设置为映射有速率匹配的构造序列P的元素。
在一种可能的实施方式中，所述可靠度排序序列Q是所述控制器/处理器402从最大长度的可靠度排序序列中，保持先后位置顺序读取得到。所述控制器/处理器402根据速率匹配，采用序列映射或者函数映射的形式，将所述构造序列P'解映射为可靠度排序序列Q'。
所述的速率匹配规则RM可以是一种速率匹配序列，也可以是两种速率匹配序列的组合。
所述控制器/处理器402还用于根据构造极化码序列的码长，信息比特长度以及码率，从两种速率匹配序列的组合中选择一种速率匹配序列。
本申请提供的极化码序列构造装置可以执行前面方法实施例一至实施例四中的方法步骤，在此不再赘述。
上述控制器/处理器402的功能可以通过电路实现也可以通过通用硬件执行软件代码实现，当采用后者时，所述存储器403还用于存储可被控制器/处理器402执行的程序代码。当控制器/处理器402运行存储器403存储的程序代码时就执行前述功能。
进一步地，所述构造极化码序列的装置还可以包括编码器4051、调制器4052、解调器4054和解码器4053。编码器4051用于获取网络侧设备将要发给终端或者终端即将发给网络侧设备的数据/信令，并对该数据/信令进行编码。调制器4052对编码器4051编码后的数据/信令进行调制后传递给收发器401，由收发器401发送给终端或者其他网络侧设备。
解调器4054用于获取终端或者其他网络侧设备发送的数据/信令，并进行解调。解码器4053用于对解调器4054解调后的数据/信令进行解码。
上述编码器4051、调制器4052、解调器4054和解码器4053可以由合成的调制解调 处理器405来实现。这些单元根据无线接入网采用的无线接入技术(例如，LTE及其他演进系统的接入技术)来进行处理。
所述网络侧设备还可以包括通信接口404，用于支持该构造极化码序列的装置与其他网络实体之间进行通信。可以理解的是，图10仅仅示出了构造极化码序列的装置的简化设计。在实际应用中，上述收发器401可以包括发射器和接收器，该装置可以包含任意数量的收发器，处理器，控制器/处理器，存储器，和/或通信接口等。
上述装置在具体实现中，可以是终端或者网络侧设备。网络侧设备又可以是基站或者控制节点。
本申请上述基站，终端、或控制节点的控制器/处理器可以是中央处理器(CPU)，通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)，现场可编程门阵列(FPGA)或者其他可编程逻辑器件、晶体管逻辑器件，硬件部件或者其任意组合。其可以实现或执行结合本申请公开内容所描述的各种示例性的逻辑方框，模块和电路。所述处理器也可以是实现计算功能的组合，例如包含一个或多个微处理器组合，DSP和微处理器的组合等等。
结合本申请公开内容所描述的方法或者算法的步骤可以硬件的方式来实现，也可以是由处理器执行软件指令(例如，程序代码)的方式来实现。软件指令可以由相应的软件模块组成，软件模块可以被存放于RAM存储器、闪存、ROM存储器、EPROM存储器、EEPROM存储器、寄存器、硬盘、移动硬盘、CD-ROM或者本领域熟知的任何其它形式的存储介质中。一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器和存储介质可以位于ASIC中。另外，该ASIC可以位于终端中。当然，处理器和存储介质也可以作为分立组件存在于终端中。
本领域技术人员应该可以意识到，在上述一个或多个示例中，本申请所描述的功能可以用硬件、软件、固件或它们的任意组合来实现。当使用软件实现时，可以将这些功能存储在计算机可读介质中或者作为计算机可读介质上的一个或多个指令或代码进行传输。计算机可读介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是通用或专用计算机能够存取的任何可用介质。
以上所述的具体实施方式，对本申请的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本申请的具体实施方式而已，并不用于限定本申请的保护范围，凡在本申请的技术方案的基础之上，所做的任何修改、等同替换、改进等，均应包括在本申请的保护范围之内

Claims (12)

  1. 一种构造极化码序列的方法，其特征在于，所述方法由终端或者网络设备执行，所述方法包括：
    从长度为N的构造序列P中读取长度为编码码长M的构造序列P'；
    根据速率匹配规则将所述构造序列P'解映射为可靠度排序序列Q'；
    从所述可靠度排序序列Q'序列中读取可靠度值最大的K个元素，得到信息比特序号集合
    Figure PCTCN2018080347-appb-100001
  2. 如权利要求1所述的构造极化码序列的方法，其特征在于，所述构造序列P是根据可靠度排序序列Q和所述速率匹配规则生成的；所述可靠度排序序列Q是对母码序列中每个比特位置的可靠性按照从大到小或者从小到大排列后得到的。
  3. 如权利要求1所述的构造极化码序列的方法，其特征在于，所述信息比特序号集合
    Figure PCTCN2018080347-appb-100002
    的补集
    Figure PCTCN2018080347-appb-100003
    为冻结比特位置集合。
  4. 如权利要求2所述的构造极化码序列的方法，其特征在于，所述构造序列P是根据可靠度排序序列Q和速率匹配规则生成的，包括：
    从后往前逐个从表征速率匹配规则的速率匹配序列中，读取元素RM i，其中，{RM i,0≤i＜N}，并在可靠度排序序列Q中搜索Q j＝RM i；
    将所述可靠度排序序列Q中满足Q j＝RM i的序号i设置为所述构造序列P的元素。
  5. 如权利要求1所述的构造极化码序列的方法，其特征在于，所述长度为N的构造序列P，是根据可靠度排序序列Q和速率匹配规则，经离线计算得到的，计算步骤如下：
    (1)根据速率匹配，得到速率匹配序列{RM i,0≤i＜N}，其中序号i越大，表示对应的比特位置RM i将优先被打孔或缩短；
    (2)根据长度为N＝2 n的可靠度排序序列Q和速率匹配序列{RM i,0≤i＜N}，按照从后往前的顺序逐个读取该速率匹配序列中的元素，并在靠度排序序列Q中搜索满足Q j＝RM i的元素；
    (3)设置P j＝i；
    (4)重复以上步骤，直到读取完所有的速率匹配序列的元素，组成长度为N的构造序列P。
  6. 如权利要求1所述的构造极化码序列的方法，其特征在于，所述根据速率匹配规则将所述构造序列P'解映射为可靠度排序序列Q'，包括：
    采用函数形式或者序列形式将所述构造序列P'解映射为可靠度排序序列Q'。
  7. 一种构造极化码序列的装置，其特征在于，包括：
    存储器，用于存储构造序列P；处理器，用于从长度为N的构造序列P中读取长度为编码码长M的构造序列P'；
    所述处理器还用于根据速率匹配规则，将所述构造序列P'解映射为可靠度排序序列Q'；从所述可靠度排序序列Q'序列中读取可靠度值最大的K个元素，得到信息比特序号集合
    Figure PCTCN2018080347-appb-100004
  8. 如权利要求7所述的构造极化码序列的装置，其特征在于，所述存储器存储的构造序列P是根据可靠度排序序列Q和所述速率匹配规则生成的；所述可靠度排序序列Q是对母码序列中每个比特位置的可靠性按照从大到小或者从小到大排列后得到的。
  9. 如权利要求7所述的构造极化码序列的装置，其特征在于，所述处理器得到的信息比特序号集合
    Figure PCTCN2018080347-appb-100005
    的补集
    Figure PCTCN2018080347-appb-100006
    为冻结比特位置集合。
  10. 如权利要求8所述的构造极化码序列的装置，其特征在于，所述构造序列P，是处理器根据可靠度排序序列Q和速率匹配规则，经离线计算得到的，包括：
    所述处理器根据速率匹配，得到速率匹配序列{RM i,0≤i＜N}，其中序号i越大，表示对应的比特位置RM i将优先被打孔或缩短；
    所述处理器根据长度为N＝2 n的可靠度排序序列Q和速率匹配序列{RM i,0≤i＜N}，按照从后往前的顺序逐个读取该速率匹配序列中的元素，并在靠度排序序列Q中搜索满足Q j＝RM i的元素；
    所述处理器设置P j＝i；
    所述处理器重复以上操作，直到读取完所有的速率匹配序列的元素，组成长度为N的构造序列P。
  11. 如权利要求7所述的构造极化码序列的装置，其特征在于，所述处理器采用函数形式或者序列形式的速率匹配规则将所述构造序列P'解映射为可靠度排序序列Q'。
  12. 如权利要求7至11中任一项所述的构造极化码序列的装置，其特征在于，所述装置为终端或网络侧设备。
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