WO2019001436A1 - 一种Polar码的编码方法及装置 - Google Patents

一种Polar码的编码方法及装置 Download PDF

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Publication number
WO2019001436A1
WO2019001436A1 PCT/CN2018/092943 CN2018092943W WO2019001436A1 WO 2019001436 A1 WO2019001436 A1 WO 2019001436A1 CN 2018092943 W CN2018092943 W CN 2018092943W WO 2019001436 A1 WO2019001436 A1 WO 2019001436A1
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sequence
interleaving
bit sequence
check
bit
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PCT/CN2018/092943
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English (en)
French (fr)
Inventor
黄凌晨
李榕
张华滋
徐晨
戴胜辰
张公正
乔云飞
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华为技术有限公司
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Priority to EP18823331.6A priority Critical patent/EP3637731A4/en
Publication of WO2019001436A1 publication Critical patent/WO2019001436A1/zh
Priority to US16/728,594 priority patent/US11088708B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/1174—Parity-check or generator matrices built from sub-matrices representing known block codes such as, e.g. Hamming codes, e.g. generalized LDPC codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0076—Distributed coding, e.g. network coding, involving channel coding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

Definitions

  • the embodiments of the present invention relate to the field of communications technologies, and in particular, to a method and an apparatus for encoding a Polar code.
  • Cyclic redundancy check (CRC) coding is the most commonly used error checking code in the field of data communication.
  • the feature of CRC coding is that the length of the information field and the check field can be arbitrarily selected. In communication systems, CRC coding is used to detect the correct transmission of data and to control the probability of occurrence of false alarms.
  • FIG. 1 shows a common way of shift register (referred to as register) to implement CRC encoding.
  • the feedback tap of the register is determined by the CRC polynomial [1 0 1 0 1], and the register contents are initialized to preset values.
  • the K information bits are shifted into the register bit by bit from the side, and the feedback tap and the register corresponding state are subjected to a bitwise exclusive OR operation, so that the register state changes.
  • the bit 0 of the number equal to the length of the CRC check is shifted, and then the register state is read, and the register state is used as the CRC check bit, which is appended to the K information bits as the CRC code. word.
  • the transmitting end performs channel coding on the CRC coding code, and the receiving end performs corresponding channel decoding. After the channel decoding ends, the CRC check determines whether the decoding result is successfully decoded.
  • the embodiment of the present invention provides a method and a device for encoding a Polar code, which are used to solve the problem that the decoding process is complicated and the decoding resource is wasted by using the existing CRC coding mode.
  • the position of the check bit is not necessarily located after the information bit to be checked.
  • the position of the check bit in the check bit sequence obtained by the i-th subset is not necessarily located after the information bit position in the i-th subset.
  • each check bit can be verified, and if the check fails, the decoding can be terminated early, and the false alarm probability can be
  • the function of decoding early stop is realized, which helps to avoid waste of decoding resources caused by verification after channel decoding ends, shortens the time used for decoding, and improves the efficiency of decoding.
  • the at least two first bit sequences to be checked are respectively subjected to check coding to obtain at least two check bit sequences, and the union of the at least two first bit sequences to be checked a K information bit, K is a positive integer; interleaving the K information bits and the at least two parity bit sequences to obtain a second bit sequence, or the first partial information bit sequence and Performing an interleaving operation on the first parity bit sequence to obtain a third bit sequence after interleaving; and, a second partial information bit sequence in the entire information bit sequence except the first partial information bit sequence, A second parity bit sequence, and the third parity bit sequence are arranged to obtain the second bit sequence.
  • the second bit sequence is subjected to Polar code encoding.
  • two of the K information bits are to be checked, which are a first partial information bit sequence of length K 1 and a total information bit sequence of length K, K 1 .
  • K 1 and K are both positive integers. That is, K information bits are included in all information bit sequences.
  • the first partial information bit sequence is subjected to check coding to obtain a first parity bit sequence; and the entire information bit sequence is subjected to check coding to obtain a second parity bit sequence.
  • the interleaving sequence S is calculated prior to the interleaving operation.
  • the interleaving operation of the partial information bits of the K information bits and the partial parity bit sequence of the at least two parity bit sequences is implemented by: according to the K The length of the partial information bits in the information bits and the determined check polynomial, the stored interleaving sequence S is read, and the interleaving operation is performed in accordance with the read interleaving sequence S.
  • a method for encoding a Polar code which performs check coding on an empty set bit sequence of length 0 to obtain a first check bit sequence, and performs check coding on K information bits to obtain a second school. Compensating the bit sequence; performing an interleaving operation on the K information bits, the first parity bit sequence, and the second parity bit sequence; performing polarization Polar coding on the sequence after the interleaving operation.
  • each check bit can be verified, and if the check fails, the decoding can be terminated early, and the false alarm probability can be controlled.
  • the function of decoding early stop is realized, which helps to avoid waste of decoding resources caused by verification after channel decoding ends, shortens the time used for decoding, and improves the efficiency of decoding.
  • the first parity bit sequence is an all zero vector.
  • the interleaving sequence S used in the interleaving operation implements J subsequences by implementing the position index value of the element 1 in the intermediate result vector T i in the following manner.
  • P is a submatrix of the system G of the check coding matrix generation, ⁇ represents a bitwise bitwise operation, & represents a bitwise AND operation, and represents a bitwise OR operation.
  • the interleaving sequence S is calculated prior to the interleaving operation.
  • the interleaving operation of the K information bits, the first parity bit sequence and the second parity bit sequence is implemented by: according to the value of the K and the determined The check polynomial is read, the stored interleaving sequence S is read, and the interleaving operation is performed in accordance with the read interleaving sequence S.
  • a method for encoding a Polar code which performs check coding on a first partial information bit sequence of K information bits, and performs an interleaving operation on the coded codeword to obtain a first check code.
  • a word K is a positive integer
  • the first check codeword word implements the first partial information bit sequence and the first check bit sequence by: the first check code sequence, the K information a sequence of the second partial information bit sequence except the first partial information bit sequence is subjected to check coding to obtain a second check code code word, and the second check code code word is implemented by the following manner
  • the first partial information bit sequence, the first parity bit sequence, the second partial information bit sequence, and the second parity bit sequence; the second parity encoded codeword is polarization-Polar encoded.
  • each check bit can be verified, and if the check fails, the decoding can be terminated early, and the false alarm probability can be controlled.
  • the function of decoding early stop is realized, which helps to avoid waste of decoding resources caused by verifying after the end of channel decoding, shortens the time used for decoding, and improves the efficiency of decoding.
  • the interleaving sequence S used in the interleaving operation implements J subsequences by implementing the position index value of the element 1 in the intermediate result vector T i in the following manner.
  • P is a submatrix of the system G of the check coding matrix generation, ⁇ represents a bitwise bitwise operation, & represents a bitwise AND operation, and represents a bitwise OR operation.
  • the interleaving sequence S is calculated prior to the interleaving operation.
  • the first part of the information bits in the K information bits are subjected to check coding, and the coded words are interleaved, and are implemented in the following manner: A part of the information bit sequence is subjected to check coding, and the stored interleaving sequence S is read according to the length of the first partial information bit sequence and the determined check polynomial, and the interleaving operation is performed according to the read interleaving sequence S.
  • a fourth aspect provides a method for encoding a Polar code, which performs check coding on K information bits based on a set check bit length to obtain a first check bit sequence; and according to the set coding parameter, from the first school
  • the second check bit sequence is selected from the bit sequence; the sequence sequenced by the second check bit sequence and the K information bits is subjected to polarization Polar coding.
  • the setting encoding parameter includes at least one parameter or a derived parameter of the at least one parameter: length of the K information bits, mother code length, code length, code rate, path width .
  • a second parity bit sequence with a higher reliability may be selected; or a second parity bit sequence with a lower reliability may be selected; or a specified second parity bit sequence may be selected.
  • the second parity bit sequence is consecutively placed before or after the K information bit positions or at a specified location; or, according to the set cyclic shift value, the second The check bit sequence is continuously placed at a specified position of the K information bits; or the second check bit sequence is interleaved with the K information bits.
  • an encoding apparatus for a Polar code having the function of implementing any of the above-described first aspect and the first aspect of the first aspect.
  • the functions can be implemented by hardware or by hardware implementation of the corresponding software.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the encoding device comprises: an input interface circuit for acquiring information bits of length K; and a logic circuit for performing the first aspect described above And the behavior of the transmitting end in any of the possible designs of the first aspect; the output interface circuit for outputting the Polar encoded bit sequence.
  • the encoding device may be a chip or an integrated circuit.
  • the encoding device when part or all of the function is implemented by software, the encoding device comprises: a memory for storing a program; a processor for executing the program stored by the memory, When the program is executed, the encoding device may implement the method as described in the first aspect and any of the possible designs of the first aspect.
  • the above memory may be a physically separate unit or may be integrated with the processor.
  • the encoding device when some or all of the functions are implemented by software, the encoding device includes a processor.
  • a memory for storing a program is located outside the encoding device, and the processor is connected to the memory through a circuit/wire for reading and executing a program stored in the memory.
  • an encoding apparatus having the functionality to implement any of the possible in-design methods of the second aspect and the second aspect described above.
  • the functions may be implemented by hardware or by corresponding software implemented by hardware.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the encoding device comprises: an input interface circuit for acquiring information bits of length K; and a logic circuit for performing the second aspect described above And the behavior of the transmitting end in any of the possible designs of the second aspect; the output interface circuit for outputting the Polar encoded bit sequence.
  • the encoding device may be a chip or an integrated circuit.
  • the encoding device when part or all of the function is implemented by software, the encoding device comprises: a memory for storing a program; a processor for executing the program stored by the memory, When the program is executed, the encoding device can implement the method described in any of the possible aspects of the second aspect and the second aspect described above.
  • the above memory may be a physically separate unit or may be integrated with the processor.
  • the encoding device when some or all of the functions are implemented by software, the encoding device includes a processor.
  • a memory for storing a program is located outside the encoding device, and the processor is connected to the memory through a circuit/wire for reading and executing a program stored in the memory.
  • an encoding apparatus having the function of implementing any of the possible in-design methods of the third aspect and the third aspect described above.
  • the functions may be implemented by hardware or by corresponding software implemented by hardware.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the encoding device comprises: an input interface circuit for acquiring information bits of length K; and a logic circuit for performing the above third aspect And the behavior of the transmitting end in any of the possible designs of the third aspect; the output interface circuit for outputting the Polar encoded bit sequence.
  • the encoding device may be a chip or an integrated circuit.
  • the encoding device when part or all of the function is implemented by software, the encoding device comprises: a memory for storing a program; a processor for executing the program stored by the memory, When the program is executed, the encoding device can implement the method described in any of the possible aspects of the third aspect and the third aspect described above.
  • the above memory may be a physically separate unit or may be integrated with the processor.
  • the encoding device when some or all of the functions are implemented by software, the encoding device includes a processor.
  • a memory for storing a program is located outside the encoding device, and the processor is connected to the memory through a circuit/wire for reading and executing a program stored in the memory.
  • an encoding apparatus having the function of implementing any of the possible in-design methods of the fourth aspect and the fourth aspect described above.
  • the functions may be implemented by hardware or by corresponding software implemented by hardware.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the encoding device comprises: an input interface circuit for acquiring information bits of length K; and a logic circuit for performing the fourth aspect described above And the behavior of the transmitting end in any of the possible designs of the fourth aspect; the output interface circuit for outputting the Polar encoded bit sequence.
  • the encoding device may be a chip or an integrated circuit.
  • the encoding device when part or all of the function is implemented by software, the encoding device comprises: a memory for storing a program; a processor for executing the program stored by the memory, When the program is executed, the encoding apparatus can implement the method as described in any of the possible aspects of the fourth aspect and the fourth aspect described above.
  • the above memory may be a physically separate unit or may be integrated with the processor.
  • the encoding device when some or all of the functions are implemented by software, the encoding device includes a processor.
  • a memory for storing a program is located outside the encoding device, and the processor is connected to the memory through a circuit/wire for reading and executing a program stored in the memory.
  • a communication system comprising a transmitting end and a receiving end, wherein the transmitting end can perform the method according to any one of the above first to fourth aspects.
  • a tenth aspect a computer storage medium storing a computer program, the computer program comprising the method of any of the first to fourth aspects, the first aspect to the fourth aspect, instruction.
  • a computer program product comprising instructions for causing a computer to perform the methods described in the above aspects when executed on a computer is provided.
  • FIG. 1 is a schematic diagram of a CRC encoding method in the prior art
  • FIG. 2 is a schematic structural diagram of a communication system in an embodiment of the present application.
  • FIG. 3 is a schematic flowchart of a coding method in an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a coding method of a Polar code in an embodiment of the present application.
  • FIG. 5 is a second schematic diagram of a method for encoding a Polar code according to an embodiment of the present application.
  • FIG. 6 is a third schematic diagram of a method for encoding a Polar code according to an embodiment of the present application.
  • FIG. 7 is a fourth schematic diagram of a method for encoding a Polar code according to an embodiment of the present application.
  • FIG. 8 is a fifth schematic diagram of a method for encoding a Polar code according to an embodiment of the present application.
  • FIG. 9 is a sixth schematic diagram of a method for encoding a Polar code according to an embodiment of the present application.
  • FIG. 10a is a seventh schematic diagram of a method for encoding a Polar code according to an embodiment of the present application.
  • FIG. 10b is a schematic diagram of a method for encoding a Polar code according to an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of an apparatus for encoding a Polar code according to an embodiment of the present application.
  • FIG. 12 is a second schematic structural diagram of a device for encoding a Polar code according to an embodiment of the present application.
  • FIG. 13 is a third schematic structural diagram of a device for encoding a Polar code according to an embodiment of the present application.
  • FIG. 14 is a fourth schematic structural diagram of a device for encoding a Polar code according to an embodiment of the present application.
  • 15 is a fifth schematic structural diagram of a device for encoding a Polar code according to an embodiment of the present application.
  • 16 is a sixth structural diagram of a device for encoding a Polar code according to an embodiment of the present application.
  • FIG. 17 is a seventh schematic structural diagram of a device for encoding a Polar code according to an embodiment of the present application.
  • An embodiment of the present application provides a method and an apparatus for encoding a Polar code.
  • the union of the n subsets is all information bits of the K information bits, and the transmitting end performs check coding on the n subsets to obtain n parity bit sequences, wherein the verification and encoding of a subset is obtained.
  • a check bit sequence the sender combines the K information bits with the obtained check bit sequences, and the combined sequence is input to the interleaver for interleaving operation, and the check bits can be interspersed into the K information bits by the interleaving operation.
  • the position of the check bit by the interleaving operation is not necessarily located after the information bit to be checked, for example, the position of the check bit in the check bit sequence obtained by the i-th subset is not necessarily located in the i-th subset After the information bit position.
  • the encoding strategy of the Polar code utilizes a noise-free channel to transmit useful information of the user, and the full-noise channel transmits the agreed information or does not transmit information.
  • the Polar code is also a linear block code whose encoding matrix is G N and the encoding process is among them Is a binary line vector of length N (ie code length); G N is an N ⁇ N matrix, and Defined as the Kronecker product of log 2 N matrices F 2 . Above matrix
  • G N (A) is the set of G N The sub-matrices obtained from those rows corresponding to the index
  • G N (AC) is the set of G N The sub-matrices obtained from those rows corresponding to the index.
  • the encoded output of the Polar code can be simplified to:
  • indicates the number of elements in the collection, and K is the size of the information block.
  • the construction process of the Polar code is a collection
  • the selection process determines the performance of the Polar code.
  • the construction process of the Polar code is generally: determining that there are N polarized channels in total according to the length N of the mother code, respectively corresponding to N rows of the coding matrix, calculating the reliability of the polarized channel, and the first K polarizations with higher reliability.
  • Channel index as a collection Element
  • the index corresponding to the remaining (NK) polarized channels as the index set of fixed bits Elements. set Determine the location of the information bits, the collection The position of the fixed bit is determined.
  • the communication system 200 to which the embodiment of the present application is applied includes a transmitting end 201 and a receiving end 202.
  • the transmitting end 201 may also be referred to as an encoding end, and the receiving end 202 may also be referred to as a decoding end.
  • the transmitting end 201 can be a base station, and the receiving end 202 is a terminal; or the transmitting end 201 is a terminal, and the receiving end 202 is a base station.
  • a base station is a device deployed in a radio access network to provide wireless communication functions to a terminal.
  • the base station may include various forms of macro base stations, micro base stations, relay stations, access points, and the like.
  • the base station may also be another network device having a base station function, and in particular, may also be a terminal serving as a base station function in D2D communication.
  • the terminal may include various handheld devices having wireless communication functions, in-vehicle devices, wearable devices, computing devices, or other processing devices connected to the wireless modem, and various forms of user equipment (UE), mobile stations (mobile) Station, MS), etc.
  • the transmitting end 201 performs check coding and Polar coding on K information bits, where the transmitting end 201 performs segmentation check coding on K information bits, and Interleaving the obtained check codewords, and verifying that the codewords include K information bits and a check bit sequence obtained by segmentation check coding, and the transmitting end 201 sends the coded Polar code to the receiving end 202 to receive End 202 performs decoding and deinterleaving.
  • the method for verifying the encoding by the transmitting end 201 may be performed by using any one of the prior art to verify the encoding method of the Polar code, for example, using an existing CRC encoding method, a hash hash checking encoding method, or the like.
  • the coding method provided by the embodiment of the present application will be described in detail below with reference to FIG.
  • the execution body of the encoding method is taken as an example of the sending end.
  • Step 301 Perform check coding on at least two first bit sequences to be checked to obtain at least two check bit sequences.
  • the union of the at least two first bit sequences to be verified is a sequence of all information bits.
  • the entire information bit sequence is a sequence of all information bits of K information bits.
  • a first bit sequence is subjected to check coding, and a corresponding check bit sequence can be obtained.
  • Step 302 Perform an interleaving operation on all information bit sequences and the at least two check bit sequences to obtain a second bit sequence, or perform an interleaving operation on the first partial information bit sequence and the first parity bit sequence to obtain an interleaved
  • the third bit sequence, the second partial information bit sequence, the second parity bit sequence, and the third parity bit sequence of the entire information bit sequence except the first partial information bit sequence constitute a second bit sequence.
  • Step 303 Perform polarization Polarization on the second bit sequence.
  • the Polar coded information bit set is selected, and the channel corresponding to the information bit set is set as the bit value of the second bit sequence, and then the code word sequence is calculated according to the Polar code coding matrix.
  • the sequence to be decoded is obtained, and the sequence to be decoded is subjected to Polar code decoding. And deinterleaving the decoded sequence.
  • the receiving end may use segment decoding in the decoding process, and verify a part of the information bits obtained by decoding according to a part of the parity bits obtained by decoding, if If the decoding result cannot pass the check, the decoding is stopped immediately, and the feedback decoding fails, otherwise the decoding is continued.
  • FIG. 4 is a schematic diagram of a method for encoding a Polar code according to an embodiment of the present application.
  • the transmitting end performs check coding on the n first bit sequences with n check codes, and correspondingly obtains n check bit sequences.
  • the first bit sequence of length K1 is checked and coded by check code 1
  • the first bit sequence of length K2 is checked and coded by check code 2 to obtain n check bit sequences respectively.
  • the check code may be a check code such as a CRC code or a hash code; and all the information bit sequences and n check bit sequences are arranged by bit collection, and the optional arrangement manner is as follows: according to K information bits, P1, P2 The order of ..., Pn is arranged.
  • An interleaving operation is performed on the aligned bit sequence to obtain a second bit sequence.
  • the interleaving operation may be such that a part of the check bits is located between the information bits. In the embodiment of the present application, after the check bits are not located, the position of the check bits may be arbitrarily placed. Finally, the interleaved second bit sequence is sent to the Polar encoder for encoding.
  • the interleaving operation involved in the embodiments of the present application may be defined by an interleaving sequence.
  • An interleaving sequence is calculated according to the combination matrix of the check matrix of some or all of the check codes, and the combinatorial matrix is exchanged row by column in a certain order, and the order may be a natural order or an order according to column reordering.
  • the row exchange target is that all elements 1 in the column after the swap are located at the top position of the combination matrix; the number of columns of operation is less than or equal to the total number of columns; finally, the interleaving sequence is obtained according to the result of the row exchange.
  • the interleaving sequence S may be calculated in other manners, or the interleaving sequence S may be obtained by looking up the table. It should be noted that the position corresponding to the parity bit in the interleaving sequence is not limited and does not need to be after the information bits it verifies.
  • the first partial information bit sequence of length K 1 is extracted from the K information bits, and optionally, the first K 1 information bits are selected. Based on the first partial information bit sequence of length K 1 and all information bit sequences of length K, the two first bit sequences to be verified described in the above step 301 are obtained. Where K 1 ⁇ K, and K 1 and K are both positive integers.
  • step 302 the transmitting end performs check coding on the first partial information bit sequence to obtain a first check bit sequence; and the transmitting end performs check coding on all information bit sequences to obtain a second check bit sequence.
  • step 303 there may be two interleaving modes, all interleaving and partial interleaving.
  • the manner of all interleaving is: the transmitting end interleaves all information bit sequences, the first parity bit sequence and the second parity bit sequence to obtain a second bit sequence;
  • the partial interleaving manner is: the transmitting end interleaves the first partial information bit sequence and the first parity bit sequence to obtain the third bit sequence after the interleaving, and the transmitting end divides all the information bit sequences by the first partial information bit sequence.
  • the second partial information bit sequence, the second parity bit sequence, and the third parity bit sequence are arranged to obtain a second bit sequence.
  • FIG. 5 it is a coded diagram of the above-described manner of all interleaving.
  • FIG. 6 it is a coded diagram of the above-described partial interleaving.
  • check code is CRC coded as an example, and the specific steps are as follows:
  • the transmitting end uses two CRC codes (CRC1 and CRC2) to check and encode the first partial information bit sequence of length K 1 and all information bit sequences of length K, and the obtained check bit sequences are respectively P1 and P2.
  • the lengths of P1 and P2 are J1 and J2, respectively.
  • the generator polynomial of CRC1 and CRC2 is shown in Table 1.
  • All interleaving as shown in FIG. 5 All information bits of length K, parity bit sequences P1 obtained by CRC1, and parity bit sequence P2 obtained by CRC2 are all input to an interleaver for interleaving.
  • the checksum is obtained CRC1 K 1 information bits and check bits CRC1 arranged P1, to obtain a codeword sequence CW1.
  • CW1 is K 1 information bits
  • the last J1 bits are parity bits P1.
  • the sequence CW1 is interleaved, and the interleaving operation is defined by an interleaving sequence as shown in Table 2.
  • the length of the interleaving sequence is (K 1 + J1), and the interleaving results in CW1'.
  • the remaining (KK 1 ) information bits, the check bits P2 and CW1' are arranged, and the arrangement corresponding to one arrangement is CW1', (K-K1) information bits, and J2 check bits P2, which are obtained.
  • the codewords interleaved in FIG. 5 are Polar coded.
  • the code word CW2 obtained in FIG. 6 is Polar coded.
  • the CRC polynomial is in reverse order, such as CRC polynomial 0x19 with a CRC length of 4 corresponding to x ⁇ 4+x+1.
  • the value of the sequence number less than or equal to K 1 in the interleaving sequence corresponds to the reverse number of the K 1 information bit, for example, the sequence number 1 corresponds to the K 1 information bit, the sequence number 2 corresponds to the (K 1 -1) information bit, and the interleaved sequence
  • the value greater than K 1 corresponds to J1 check bits.
  • the sequence number (K 1 +1) corresponds to the first check bit
  • the sequence number (K 1 +J1) corresponds to the J1 check bit.
  • the transmitting end may perform interleaving after the first part information bit sequence is checked and encoded to obtain the first school.
  • the word and the second part of the information bits are combined in a certain sorting order, and the collected sequence is subjected to check coding to obtain a second check coded code word, and the second check coded code word is Polar coded.
  • the transmitting end uses two CRC codes (CRC1 and CRC2) to check and encode the first partial information bit sequence of length K 1 and all information bit sequences of length K, respectively, and the obtained check bit sequence is respectively P1.
  • P2 P1 and P2 are J1 and J2, respectively.
  • the generator polynomial of CRC1 and CRC2 is shown in Table 1.
  • J1 of parity bits are generated K 1 information bits CRC1 interleaving checksum and CRC1 to give CWl, interleaving sequence defined by the interleaving operation, typically interleaving sequence shown in Table 2.
  • the (K-K1) information bits not checked by CRC1 and CW1 are collected to obtain CW2.
  • the CRC2 check is performed on CW2, and the generated check bits are arranged in CW2 to obtain CW3.
  • the code word CW3 is sent to the Polar encoder for encoding.
  • the sender can also extract the first partial information bit sequence of length K 1 from the K information bits, and extract the length of K 2 .
  • the second partial information bit sequence, K K 1 + K 2 , the first partial information bit sequence and the second partial information bit sequence are complementary, and the union is the entire information bit sequence of the K information bits.
  • the manner of checking, interleaving, and encoding is similar to that of one of the possible implementations described above.
  • the first partial information bit sequence may also intersect with the second partial information bit sequence.
  • the encoding method of the Polar code described in one possible implementation manner described above is applicable to two first bit sequences to be encoded in any case.
  • the transmitting end performs check coding on the null set bit sequence of length 0 to obtain a first check bit sequence (or is distinguished from the above description, where it is recorded as the third check bit. Sequence), the K information bits are checked and encoded to obtain a second parity sequence, and K is a positive integer.
  • the third parity bit sequence is an all zero vector and the length is related to the check code.
  • the transmitting end interleaves all the information bit sequence, the second parity bit sequence and the third parity bit sequence, and performs Polar coding on the sequence after the interleaving operation.
  • FIG. 8 it is a coding diagram in another possible implementation manner described above.
  • the transmitting end uses two CRC codes (CRC1 and CRC2) to check and encode the empty set bit sequence of length 0 and all information bit sequences of length K, respectively.
  • the obtained check bit sequences are respectively
  • the lengths of P1 and P2, P1 and P2 are J1 and J2, respectively.
  • P1 is an all zero vector.
  • the generator polynomial of CRC1 and CRC2 is shown in Table 1;
  • the K bit of information, the check bit sequence P1 obtained by CRC1, and the check bit sequence P2 obtained by CRC2 are sorted and interleaved.
  • the interleaving operation is defined by an interleaving sequence, as shown in Table 3, the length is (K+J2), and the interleaving results in CW1';
  • the check bit sequence P1 obtained by CRC1 is inserted into CW1' to obtain the code word CW2, that is, the check bit of P1 is interspersed in CW1', and the insertion position may be before, after or in the middle of CW1', if inserted into the middle of CW1',
  • the method is that the insertion position corresponds to the position with the lowest reliability among the positions of the subsequent Polar coding (K+J1+J2).
  • the code word CW2 is input to the Polar encoder for encoding.
  • the value of the sequence number is less than or equal to K, and the corresponding number is the reverse number of the K information bits.
  • the sequence number 1 corresponds to the Kth information bit
  • the sequence number 2 corresponds to the (K-1) information bit
  • the sequence number of the interleaved sequence is greater than K.
  • the value corresponds to J2 check bits, for example, the sequence number (K+1) corresponds to the first check bit, and the sequence number (K+J2) corresponds to the J2 check bit.
  • the embodiment of the present application further provides another method for encoding a Polar code.
  • the number of check bits is determined according to the Polar code parameter, and a corpus or subset is selected from all the check bits, and the precoding bits are combined with the information bits to perform Polar coding on the precoded bits.
  • the specific process is as follows.
  • Step 901 Perform check coding on the K information bits based on the set check bit length to obtain a first check bit sequence.
  • Step 902 Select some or all of the check bits from the first check bit sequence according to the set coding parameter to obtain a second check bit sequence.
  • At least one parameter or at least one parameter derived parameter of the coding parameter is set: length of K information bits, mother code length, code length, code rate, and path width.
  • Step 903 Combine the second parity bit sequence with the K information bits.
  • the second parity bit sequence is consecutively placed before or after the K information bit positions or at a specified position; or, according to the set cyclic shift value, the second parity bit sequence is continuously placed in K pieces of information The specified position of the bit; or, the second parity bit sequence is interleaved with the K information bits.
  • Step 904 Perform polarization Polarization on the combined sequence.
  • the encoding method of the CRC is taken as an example, and the encoding method of the Polar code shown in FIG. 9 is further described in detail.
  • the code parameter is a derived parameter determined by the above parameters.
  • FIG. 10a it is a schematic diagram of the encoding method of the Polar code shown in FIG.
  • the transmitting end performs CRC encoding on the K information bit bits of length K to obtain a first parity bit sequence of length Jmax, and selects a second length J according to the coding parameter from the first parity bit sequence of length Jmax.
  • the check bit sequence, J ⁇ Jmax inserts a second check bit sequence of length J into the information bits to obtain a precoded bit sequence of length (K+J), and performs Polar code coding on the precoded bit sequence.
  • the precoding bit sequence of length (K+J) is interleaved, and the interleaved sequence is subjected to Polar code encoding.
  • the number of CRC bits required by the sender to verify the encoding process J is determined by the segmentation function according to the size of (M-K). For example, the specific determination method is shown in Table 4.
  • the number of CRC bits required for the check coding performed by the transmitting end can be flexibly obtained, and only one check code setting is needed to obtain the CRC bit of the Jmax having the longest length, and then an appropriate number of CRC bits are selected.
  • the required J CRC bits are selected from Jmax CRC bits, and the following methods are selected:
  • the position at which the information bits are inserted is determined as follows:
  • J CRC bits are successively placed with a certain position in the information bit sequence as a starting position.
  • a special case is to place J CRC bits consecutively before the information bits of length K or after the information bits of length K.
  • a cyclic shift of the given offset is performed. For example, a certain position in the information bit sequence is used as a starting position, and a certain position in the information bit sequence is determined as a termination position in conjunction with the cyclic shift, and J CRC bits are placed.
  • the interleaving operation uses an interleaving sequence, and the information bits and the CRC bits are interleaved together, and the interleaved CRC bits are interspersed between the information bits.
  • the transmitting end determines the number of check bits according to the encoding parameters, and correspondingly selects the check polynomial to check and encode the K information bits.
  • the obtained parity bits and K information bits together constitute a precoding bit, and the precoding bits are Polar encoded.
  • the at least one parameter of the coding parameter or the derived parameter of the at least one parameter is set: a length of the K information bits, a mother code length, a code length, a code rate, and a path width.
  • the transmitting end determines the number of CRC check bits according to the coding parameters, or the length of the CRC check bit sequence, for example, the number of CRC check bits includes J. 1 , J 2 , ..., Jn, the number of CRC check bits selected by the transmitting end is J, and the transmitting end performs check coding on the K information bits according to the selected number of CRC check bits, and obtains a check bit, and the transmitting end will
  • the J check bits are inserted into K information bits to obtain precoded bits of length (K+J), and the transmitting end performs Polar coding on the precoded bits.
  • the transmitting end interleaves the precoding bits of length (K+J), and performs Polar encoding on the interleaved sequence.
  • the method for determining the number of check bits J required by the transmitting end check encoding process, the method for determining the position of the inserted information bits, and the like are the same as those described in the encoding method of the Polar code shown in FIG. 10a, and the repeated description is not repeated. .
  • the embodiment of the present application further provides an encoding device 1100 for the Polar code, and the encoding device 1100 of the Polar code is used to execute the method shown in FIG.
  • the encoding method of the Polar code, the encoding device 1100 of the Polar code includes:
  • a check unit 1101 configured to perform check coding on at least two first bit sequences to be checked to obtain at least two check bit sequences; and a union of at least two first bit sequences to be verified is K Information bits, K is a positive integer;
  • the interleaving unit 1102 is configured to perform an interleaving operation on the K information bits and the at least two parity bit sequences to obtain a second bit sequence, or perform an interleaving operation on the first partial information bit sequence and the first parity bit sequence to obtain an interlace. a third bit sequence; and arranging the second partial information bit sequence, the second parity bit sequence, and the third parity bit sequence of the entire information bit sequence except the first partial information bit sequence to obtain the first Two bit sequence
  • the coding unit 1103 is configured to perform polarization Polar coding on the second bit sequence.
  • the at least two first bit sequences to be verified include: a first partial information bit sequence of length K 1 , and all information bit sequences of length K, K 1 ⁇ K, and K 1 , K are A positive integer.
  • the checking unit 1101 is specifically configured to: perform check coding on the first partial information bit sequence to obtain a first check bit sequence; and perform check coding on all information bit sequences to obtain a second check bit sequence.
  • the interleaving sequence S used by the interleaving unit 1102 performs an interleaving operation, and the interleaving sequence S includes J sub-sequences, and the i-th sub-sequence includes a position index value of the element 1 and an (K+i) value in the intermediate result vector T i .
  • the interleaving unit 1102 calculates the interleaving sequence S before performing the interleaving operation; or, the interleaving unit 1102 calculates and stores the interleaving sequence S offline; according to the length of the partial information bits in the K information bits and the determined check polynomial, The stored interleaving sequence S is read, and the interleaving operation is performed in accordance with the read interleaving sequence S.
  • an embodiment of the present application further provides an encoding device 1200 for a Polar code, and the encoding device 1200 of the Polar code is used to execute the method of FIG.
  • the step of performing the transmitting end in the compiled code method, the encoding device 1200 of the Polar code includes:
  • a checking unit 1201 configured to perform check coding on an empty set bit sequence of length 0 to obtain a first check bit sequence, and perform check coding on K information bits to obtain a second check bit sequence;
  • the interleaving unit 1202 is configured to perform an interleaving operation on the K information bits, the first parity bit sequence, and the second parity bit sequence.
  • the encoding unit 1203 is configured to perform polarization Polar coding on the sequence after the interleaving operation.
  • the first parity bit sequence is an all zero vector.
  • the interleaving unit 1202 calculates the interleaving sequence S before performing the interleaving operation; or, the interleaving unit 1202 calculates and stores the interleaving sequence S offline, and reads the stored interleaving sequence S according to the value of K and the determined check polynomial. The interleaving operation is performed in accordance with the read interleaving sequence S.
  • the embodiment of the present application further provides an encoding device 1300 for the Polar code, and the encoding device 1300 for the Polar code is used to execute the image encoding device 1300.
  • the encoding method of the Polar code, the encoding device 1300 of the Polar code includes:
  • a checking unit 1301, configured to perform check and encoding on the first part information bit sequence of the K information bits
  • the interleaving unit 1302 is configured to perform an interleaving operation on the coded codeword to obtain a first check codeword, where K is a positive integer, and the first check codeword includes a first part information bit sequence and a first check Bit sequence
  • the checking unit 1301 is further configured to perform check coding to obtain a second check by the first check code sequence, the sequence of the second information bit sequence other than the first part information bit sequence among the K information bits.
  • An encoding codeword, the second parity encoding codeword includes a first partial information bit sequence, a first parity bit sequence, a second partial information bit sequence, and a second parity bit sequence;
  • the encoding unit 1303 is configured to perform polarizationPolar encoding on the second check encoding codeword.
  • the interleaving unit 1302 calculates the interleaving sequence S before performing the interleaving operation; or calculates and stores the interleaving sequence S offline, performs check encoding on the first partial information bit sequence of the K information bits, and according to the length of the first partial information bit sequence And the determined check polynomial, reading the stored interleaving sequence S, and performing the interleaving operation according to the read interleaving sequence S.
  • the embodiment of the present application further provides an encoding device 1400 for a Polar code, including:
  • a checking unit 1401 configured to perform check coding on the K information bits based on the set check bit length to obtain a first check bit sequence
  • the selecting unit 1402 is configured to select a second check bit sequence from the first check bit sequence according to the set encoding parameter.
  • the encoding unit 1403 is configured to perform polarization Polar coding on the sequence obtained by combining the second parity bit sequence and the K information bits.
  • At least one parameter or at least one parameter derived parameter of the coding parameter is set: a length of the K information bits, a mother code length, a code length, a code rate, and a path width.
  • the selecting unit 1402 is specifically configured to: select a second parity bit sequence with a higher reliability; or select a second parity bit sequence with a lower reliability; or select a specified second parity bit sequence. .
  • a merging unit 1404 is further configured to continuously place the second parity bit sequence before or after the K information bit positions or at a specified position; or, according to the set cyclic shift value, the second school The bit sequence is successively placed at a specified position of the K information bits; or the second parity bit sequence is interleaved with the K information bits.
  • an embodiment of the present application further provides an encoding device 1500 for a Polar code, where the encoding device 1500 of the Polar code is used.
  • the encoding method of the Polar code shown in FIG. 3 or FIG. 9 is performed.
  • Some or all of the encoding methods of the Polar code of the foregoing embodiment may be implemented by hardware or by software.
  • the encoding device 1500 of the Polar code includes: an input interface circuit 1501, which is used to acquire K
  • the information circuit 1502 is configured to perform the encoding method of the Polar code shown in FIG. 3 or FIG. 9 .
  • the output interface circuit 1503 is configured to output. Polar encoded bit sequence.
  • the encoding device 1500 of the Polar code may be a chip or an integrated circuit when implemented.
  • the encoding device 1500 of the Polar code includes: a memory 1601 for storing a program; and a processor 1602
  • the program for executing the storage of the memory 1601 when the program is executed, causes the encoding device 1500 of the Polar code to implement the encoding method of the Polar code provided by the above embodiment.
  • the foregoing memory 1601 may be a physically independent unit, or as shown in FIG. 17, the memory 1601 is integrated with the processor 1602.
  • the encoding device 1500 of the Polar code may also include only the processor 1602.
  • the memory 1601 for storing programs is located outside the encoding device 1500 of the Polar code, and the processor 1602 is connected to the memory 1601 through circuits/wires for reading and executing programs stored in the memory 1601.
  • the embodiment of the present application provides a computer storage medium for storing a computer program, where the computer program includes an encoding method for executing the Polar code shown in FIG. 3 or FIG.
  • the embodiment of the present application provides a computer program product including instructions, which when executed on a computer, causes the computer to execute the encoding method of the Polar code shown in FIG. 3 or FIG.
  • the encoding device of the Polar code shown in FIG. 11 to FIG. 15 may also be a system chip.
  • the processor 1602 can be a central processing unit (CPU), a network processor (NP), or a combination of a CPU and an NP.
  • CPU central processing unit
  • NP network processor
  • the processor 1602 can also further include a hardware chip.
  • the hardware chip may be an application specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof.
  • the PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a general array logic (GAL), or any combination thereof.
  • the memory 1601 may include a volatile memory such as a random-access memory (RAM); the memory 1601 may also include a non-volatile memory such as a flash memory (flash) Memory), hard disk drive (HDD) or solid state drive (SSD); the memory 1601 may also include a combination of the above types of memories.
  • RAM random-access memory
  • non-volatile memory such as a flash memory (flash) Memory), hard disk drive (HDD) or solid state drive (SSD); the memory 1601 may also include a combination of the above types of memories.
  • embodiments of the present application can be provided as a method, system, or computer program product.
  • the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment in combination of software and hardware.
  • the application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

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Abstract

一种Polar码的编码方法及装置，用以提供一种新的校验编码方式。该方法为：对所述至少两个待校验的第一比特序列分别进行校验编码以获得至少两个校验比特序列，所述至少两个待校验的第一比特序列的并集为所述K个信息比特，K为正整数；对所述K个信息比特和所述至少两个校验比特序列进行交织操作，或者，将所述第一部分信息比特序列和所述第一校验比特序列进行交织操作以获得交织后的第三比特序列，所述全部信息比特序列中除所述第一部分信息比特序列之外的第二部分信息比特序列、所述第二校验比特序列、和所述第三校验比特序列组成第二比特序列；对所述第二比特序列进行极化Polar编码。

Description

一种Polar码的编码方法及装置
本申请要求在2017年6月27日提交中国专利局、申请号为201710502949.5、发明名称为“一种Polar码的编码方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及通信技术领域，尤其涉及一种Polar码的编码方法及装置。
背景技术
循环冗余校验(cyclic redundancy check，CRC)编码是数据通信领域中最常用的一种查错校验码，CRC编码的特征是信息字段和校验字段的长度可以任意选定。在通信系统中，CRC编码用于检测数据的传输是否正确，以及控制虚警(英文：false alarm)的发生概率。
CRC编码的一种实现方式为移位寄存器形式。图1为一种常用的移位寄存器(简称寄存器)形式实现CRC编码的方式，寄存器的反馈抽头由CRC多项式[1 0 1 0 1]决定，寄存器内容初始化为预设值。编码时，K个信息比特逐比特从一侧移入寄存器，反馈抽头与寄存器对应状态进行比特异或运算，从而寄存器状态发生变化。当所有待编码比特移入寄存器后，再移入与CRC校验长度相等位数的比特0，然后读取寄存器状态，将寄存器状态作为CRC校验比特，附在K个信息比特之后，作为CRC编码码字。发送端对CRC编码编码进行信道编码，接收端进行对应的信道译码，在信道译码结束后，通过CRC校验判断译码结果是否译码成功。
但是，对于顺序译码(即串行译码)的译码方式，如果采用上述传统的CRC编码方式，在信道译码结束后才能进行CRC校验，使得译码过程复杂，占用时间较长，且浪费译码资源。
发明内容
本申请实施例提供一种Polar码的编码方法及装置，用以解决解决采用现有CRC编码方式译码过程复杂从而浪费译码资源的问题。
本申请实施例提供的具体技术方案如下：
第一方面，提供一种Polar码的编码方法，从K个信息比特中取出Ki个信息比特，i＝1～n，n为正整数以获得K个信息比特的n个子集，该n个子集的并集为K个信息比特的全部信息比特，分别对n个子集进行校验编码以获得n个校验比特序列，其中，对一个子集进行校验编码，可以获得一个校验比特序列，将K个信息比特和获得的各个校验比特序列进行合并，将合并后的序列输入交织器进行交织操作，通过交织操作能够将校验比特穿插在K个信息比特之间，其中，通过交织操作校验比特的位置不一定位于被校验的信息比特之后，例如，第i个子集获得的校验比特序列中的校验比特的位置不一定位于第i个子集中的信息比特位置之后。通过上述操作，当接收端采用顺序译码时，通过分段校验，每译码出校验比特，即可进行校验，若校验不通过，可以提前结束译码，在虚警概率可控的基础上，实现了译码早停的功能，有助于避免在信道译码结束后再进行校验造成的译码资源浪费， 缩短了译码所用时长，提高了译码的效率。
在一个可能的设计中，Ki可以满足如下关系：Ki＝Int[K*Ri]+Ci，Int[]为取整操作，可以为四舍五入、向上取整或向下取整；Ri为比例常数，如1/16,1/8,1/4,1/2等；Ci为常数，如Ci＝-2,-1,0,1,2,30,40,50，或与i相关的整数，如Ci＝i,2i,4i等。
在一个可能的设计中，对至少两个待校验的第一比特序列分别进行校验编码以获得至少两个校验比特序列，所述至少两个待校验的第一比特序列的并集为K个信息比特，K为正整数；对所述K个信息比特和所述至少两个校验比特序列进行交织操作以获得第二比特序列，或者，将所述第一部分信息比特序列和所述第一校验比特序列进行交织操作以获得交织后的第三比特序列；以及，将所述全部信息比特序列中除所述第一部分信息比特序列之外的第二部分信息比特序列、所述第二校验比特序列、和所述第三校验比特序列进行排列以获得所述第二比特序列。对第二比特序列进行Polar码编码。
在一个可能的设计中，获取K个信息比特中的两个待校验的第一比特序列，分别为长度为K 1的第一部分信息比特序列，和长度为K的全部信息比特序列，K 1＜K，且K 1、K均为正整数。即全部信息比特序列中包括K个信息比特。
在一个可能的设计中，对所述第一部分信息比特序列进行校验编码以获得第一校验比特序列；以及，对所述全部信息比特序列进行校验编码以获得第二校验比特序列。
在一个可能的设计中，所述交织操作所采用的交织序列S包括J个子序列，第i个所述子序列包括中间结果向量T i中元素为1的位置索引值和(K+i)的值，1≤i≤J，i为整数，T i＝(～M)&(V i)，M＝M︱(V i)，M为掩码向量，V i为校验部分矩阵P的列向量，P为校验编码的系统形式生成矩阵G的子矩阵，～表示逐比特取非运算，&表示逐比特与运算，︱表示逐比特或运算。
在一个可能的设计中，在进行交织操作之前，计算所述交织序列S。
在一个可能的设计中，对所述K个信息比特中的部分信息比特、和所述至少两个校验比特序列中的部分校验比特序列进行交织操作，通过以下方式实现：根据所述K个信息比特中的部分信息比特的长度以及确定的校验多项式，读取存储的所述交织序列S，并按照读取的所述交织序列S进行交织操作。
第二方面，提供一种Polar码的编码方法，对长度为0的空集比特序列进行校验编码以获得第一校验比特序列，以及对K个信息比特进行校验编码以获得第二校验比特序列；对所述K个信息比特、所述第一校验比特序列和所述第二校验比特序列进行交织操作；对交织操作后的序列进行极化Polar编码。当接收端采用顺序译码时，通过分段校验，每译码出校验比特，即可进行校验，若校验不通过，可以提前结束译码，在虚警概率可控的基础上，实现了译码早停的功能，有助于避免在信道译码结束后再进行校验造成的译码资源浪费，缩短了译码所用时长，提高了译码的效率。
在一个可能的设计中，所述第一校验比特序列为全零向量。
在一个可能的设计中，所述交织操作所采用的交织序列S通过以下方式实现J个子序列，第i个所述子序列通过以下方式实现中间结果向量T i中元素为1的位置索引值和(K+i)的值，1≤i≤J，i为整数，T i＝(～M)&(V i)，M＝M︱(V i)，M为掩码向量，V i为校验部分矩阵P的列向量，P为校验编码的系统形式生成矩阵G的子矩阵，～表示逐比特取非运算，&表示逐比特与运算，︱表示逐比特或运算。
在一个可能的设计中，在进行交织操作之前，计算所述交织序列S。
在一个可能的设计中，对所述K个信息比特、所述第一校验比特序列和所述第二校验比特序列进行交织操作，通过以下方式实现：根据所述K的值以及确定的校验多项式，读取存储的所述交织序列S，并按照读取的所述交织序列S进行交织操作。
第三方面，提供一种Polar码的编码方法，对K个信息比特中的第一部分信息比特序列进行校验编码，并对校验编码后的码字进行交织操作以获得第一校验编码码字，K为正整数，所述第一校验编码码字通过以下方式实现所述第一部分信息比特序列和第一校验比特序列；将由所述第一校验编码序列、所述K个信息比特中除所述第一部分信息比特序列之外的第二部分信息比特序列合并后的序列进行校验编码以获得第二校验编码码字，所述第二校验编码码字通过以下方式实现所述第一部分信息比特序列、所述第一校验比特序列、所述第二部分信息比特序列和第二校验比特序列；将所述第二校验编码码字进行极化Polar编码。当接收端采用顺序译码时，通过分段校验，每译码出校验比特，即可进行校验，若校验不通过，可以提前结束译码，在虚警概率可控的基础上，实现了译码早停的功能，有助于避免在信道译码结束后再进行校验造成的译码资源浪费，缩短了译码所用时长，提高了译码的效率
在一个可能的设计中，所述交织操作所采用的交织序列S通过以下方式实现J个子序列，第i个所述子序列通过以下方式实现中间结果向量T i中元素为1的位置索引值和(K+i)的值，1≤i≤J，i为整数，T i＝(～M)&(V i)，M＝M︱(V i)，M为掩码向量，V i为校验部分矩阵P的列向量，P为校验编码的系统形式生成矩阵G的子矩阵，～表示逐比特取非运算，&表示逐比特与运算，︱表示逐比特或运算。
在一个可能的设计中，在进行交织操作之前，计算所述交织序列S。
在一个可能的设计中，对K个信息比特中的第一部分信息比特序列进行校验编码，并对校验编码后的码字进行交织操作，通过以下方式实现：对K个信息比特中的第一部分信息比特序列进行校验编码，并根据第一部分信息比特序列的长度以及确定的校验多项式，读取存储的所述交织序列S，并按照读取的所述交织序列S进行交织操作。
第四方面，提供一种Polar码的编码方法，基于设定校验比特长度对K个信息比特进行校验编码以获得第一校验比特序列；按照设定编码参数，从所述第一校验比特序列中选取第二校验比特序列；将由第二校验比特序列与所述K个信息比特合并后的序列进行极化Polar编码。这样，进行校验编码所需的CRC比特的数量可以灵活获取，只需要一种校验编码设置获得长度最长的Jmax的CRC比特，然后选取合适数量的CRC比特。
在一个可能的设计中，所述设定编码参数以下至少一种参数或所述至少一种参数的衍生参数：所述K个信息比特的长度、母码长度、编码长度、码率、路径宽度。
在一个可能的设计中，可以选取可靠度靠前的第二校验比特序列；或者，选择可靠度靠后的第二校验比特序列；或者，选择指定的第二校验比特序列。
在一个可能的设计中，将所述第二校验比特序列连续地置于所述K个信息比特位置之前或之后或指定位置；或者，按照设定的循环移位值，将所述第二校验比特序列连续地置于所述K个信息比特的指定位置；或者，将所述第二校验比特序列与所述K个信息比特进行交织操作。
第五方面，提供一种Polar码的编码装置，该装置具有实现上述第一方面和第一方面的任一种可能的设计中方法的功能。所述功能可以通过硬件实现，也可以通过硬件执行相 应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。
在一个可能的设计中，当所述功能的部分或全部通过硬件实现时，所述编码装置包括：输入接口电路，用于获取长度为K的信息比特；逻辑电路，用于执行上述第一方面和第一方面的任一种可能的设计中发送端的行为；输出接口电路，用于输出Polar编码后的比特序列。
可选的，所述编码装置可以是芯片或者集成电路。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，所述编码装置包括：存储器，用于存储程序；处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述编码装置可以实现如上述第一方面和第一方面的任一种可能的设计中所述的方法。
可选的，上述存储器可以是物理上独立的单元，也可以与处理器集成在一起。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，所述编码装置包括处理器。用于存储程序的存储器位于所述编码装置之外，处理器通过电路/电线与存储器连接，用于读取并执行所述存储器中存储的程序。
第六方面，提供一种编码装置，该装置具有实现上述第二方面和第二方面的任一种可能的设计中方法的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。
在一个可能的设计中，当所述功能的部分或全部通过硬件实现时，所述编码装置包括：输入接口电路，用于获取长度为K的信息比特；逻辑电路，用于执行上述第二方面和第二方面的任一种可能的设计中发送端的行为；输出接口电路，用于输出Polar编码后的比特序列。
可选的，所述编码装置可以是芯片或者集成电路。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，所述编码装置包括：存储器，用于存储程序；处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述编码装置可以实现如上述第二方面和第二方面的任一种可能的设计中所述的方法。
可选的，上述存储器可以是物理上独立的单元，也可以与处理器集成在一起。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，所述编码装置包括处理器。用于存储程序的存储器位于所述编码装置之外，处理器通过电路/电线与存储器连接，用于读取并执行所述存储器中存储的程序。
第七方面，提供一种编码装置，该装置具有实现上述第三方面和第三方面的任一种可能的设计中方法的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。
在一个可能的设计中，当所述功能的部分或全部通过硬件实现时，所述编码装置包括：输入接口电路，用于获取长度为K的信息比特；逻辑电路，用于执行上述第三方面和第三方面的任一种可能的设计中发送端的行为；输出接口电路，用于输出Polar编码后的比特序列。
可选的，所述编码装置可以是芯片或者集成电路。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，所述编码装置包括：存储器，用于存储程序；处理器，用于执行所述存储器存储的所述程序，当所述程序被执 行时，所述编码装置可以实现如上述第三方面和第三方面的任一种可能的设计中所述的方法。
可选的，上述存储器可以是物理上独立的单元，也可以与处理器集成在一起。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，所述编码装置包括处理器。用于存储程序的存储器位于所述编码装置之外，处理器通过电路/电线与存储器连接，用于读取并执行所述存储器中存储的程序。
第八方面，提供一种编码装置，该装置具有实现上述第四方面和第四方面的任一种可能的设计中方法的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。
在一个可能的设计中，当所述功能的部分或全部通过硬件实现时，所述编码装置包括：输入接口电路，用于获取长度为K的信息比特；逻辑电路，用于执行上述第四方面和第四方面的任一种可能的设计中发送端的行为；输出接口电路，用于输出Polar编码后的比特序列。
可选的，所述编码装置可以是芯片或者集成电路。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，所述编码装置包括：存储器，用于存储程序；处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述编码装置可以实现如上述第四方面和第四方面的任一种可能的设计中所述的方法。
可选的，上述存储器可以是物理上独立的单元，也可以与处理器集成在一起。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，所述编码装置包括处理器。用于存储程序的存储器位于所述编码装置之外，处理器通过电路/电线与存储器连接，用于读取并执行所述存储器中存储的程序。
第九方面，提供了一种通信系统，该系统包括发送端和接收端，所述发送端可以执行如上述第一方面至第四方面任一方面所述的方法。
第十方面，提供了一种计算机存储介质，存储有计算机程序，该计算机程序包括用于执行第一方面至第四方面、第一方面至第四方面的任一可能的实施方式中的方法的指令。
第十一方面，提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述各方面所述的方法。
附图说明
图1为现有技术中CRC编码方式示意图；
图2为本申请实施例中通信系统架构示意图；
图3为本申请实施例中编码方法流程示意图；
图4为本申请实施例中Polar码的编码方法示意图之一；
图5为本申请实施例中Polar码的编码方法示意图之二；
图6为本申请实施例中Polar码的编码方法示意图之三；
图7为本申请实施例中Polar码的编码方法示意图之四；
图8为本申请实施例中Polar码的编码方法示意图之五；
图9为本申请实施例中Polar码的编码方法示意图之六；
图10a为本申请实施例中Polar码的编码方法示意图之七；
图10b为本申请实施例中Polar码的编码方法示意图之八；
图11为本申请实施例中Polar码的编码装置结构示意图之一；
图12为本申请实施例中Polar码的编码装置结构示意图之二；
图13为本申请实施例中Polar码的编码装置结构示意图之三；
图14为本申请实施例中Polar码的编码装置结构示意图之四；
图15为本申请实施例中Polar码的编码装置结构示意图之五；
图16为本申请实施例中Polar码的编码装置结构示意图之六；
图17为本申请实施例中Polar码的编码装置结构示意图之七。
具体实施方式
下面将结合附图，对本申请实施例进行详细描述。
本申请实施例提供一种Polar码的编码方法及装置，发送端从K个信息比特中取出Ki个信息比特，i＝1～n，n为正整数，获得K个信息比特的n个子集，该n个子集的并集为K个信息比特的全部信息比特，发送端分别对n个子集进行校验编码以获得n个校验比特序列，其中，对一个子集进行校验编码，可以获得一个校验比特序列，发送端将K个信息比特和获得的各个校验比特序列进行合并，将合并后的序列输入交织器进行交织操作，通过交织操作能够将校验比特穿插在K个信息比特之间，其中，通过交织操作校验比特的位置不一定位于被校验的信息比特之后，例如，第i个子集获得的校验比特序列中的校验比特的位置不一定位于第i个子集中的信息比特位置之后。通过上述操作，当接收端采用顺序译码时，通过分段校验，每译码出校验比特以及被其检验的信息比特，即可进行校验，若校验不通过，可以提前结束译码，在虚警概率可控的基础上，实现了译码早停的功能，有助于避免在信道译码结束后再进行校验造成的译码资源浪费，缩短了译码所用时长，提高了译码的效率。
为方便对本申请实施例的理解，下面对Polar码作简单介绍。
Polar码的编码策略利用无噪信道传输用户有用的信息，全噪信道传输约定的信息或者不传信息。Polar码也是一种线性块码，其编码矩阵为G N，编码过程为
Figure PCTCN2018092943-appb-000001
其中
Figure PCTCN2018092943-appb-000002
是一个二进制的行矢量，长度为N(即码长)；G N是一个N×N的矩阵，且
Figure PCTCN2018092943-appb-000003
定义为log 2N个矩阵F 2的克罗内克(Kronecker)乘积。上述矩阵
Figure PCTCN2018092943-appb-000004
Polar码的编码过程中，
Figure PCTCN2018092943-appb-000005
中的一部分比特用来携带信息，称为信息比特集合，这些比特的索引的集合记作
Figure PCTCN2018092943-appb-000006
另外的一部分比特设置为接收端和发送端预先约定的固定值，称之为固定比特集合或冻结比特集合(frozen bits)，其索引的集合用
Figure PCTCN2018092943-appb-000007
的补集
Figure PCTCN2018092943-appb-000008
表示。Polar码的编码过程相当于：
Figure PCTCN2018092943-appb-000009
这里，G N(A)是G N中由集合
Figure PCTCN2018092943-appb-000010
中的索引对应的那些行得到的子矩阵，G N(AC)是G N中由集合
Figure PCTCN2018092943-appb-000011
中的索引对应的那些行得到的子矩阵。
Figure PCTCN2018092943-appb-000012
为
Figure PCTCN2018092943-appb-000013
中的信息比特集合，数量为K；
Figure PCTCN2018092943-appb-000014
为
Figure PCTCN2018092943-appb-000015
中的固定比特集合，其数量为(N-K)，是已知比特。这些固定比特通常被设置为0，但是只要接收端和发送端预先约定， 固定比特可以被任意设置。从而，Polar码的编码输出可简化为：
Figure PCTCN2018092943-appb-000016
这里
Figure PCTCN2018092943-appb-000017
为
Figure PCTCN2018092943-appb-000018
中的信息比特集合，
Figure PCTCN2018092943-appb-000019
为长度K的行矢量，即
Figure PCTCN2018092943-appb-000020
|·|表示集合中元素的个数，K为信息块大小，
Figure PCTCN2018092943-appb-000021
是矩阵G N中由集合
Figure PCTCN2018092943-appb-000022
中的索引对应的那些行得到的子矩阵，
Figure PCTCN2018092943-appb-000023
是一个K×N的矩阵。
Polar码的构造过程即集合
Figure PCTCN2018092943-appb-000024
的选取过程，决定了Polar码的性能。Polar码的构造过程通常是，根据母码码长N确定共存在N个极化信道，分别对应编码矩阵的N个行，计算极化信道可靠度，将可靠度较高的前K个极化信道的索引作为集合
Figure PCTCN2018092943-appb-000025
的元素，剩余(N-K)个极化信道对应的索引作为固定比特的索引集合
Figure PCTCN2018092943-appb-000026
的元素。集合
Figure PCTCN2018092943-appb-000027
决定了信息比特的位置，集合
Figure PCTCN2018092943-appb-000028
决定了固定比特的位置。
如图2所示，本申请实施例应用的通信系统200中包括发送端201和接收端202。发送端201也可以称为编码端，接收端202也可以称为译码端。其中，发送端201可以为基站，接收端202为终端；或者，发送端201为终端，接收端202为基站。基站是一种部署在无线接入网中用以为终端提供无线通信功能的装置。基站可以包括各种形式的宏基站，微基站，中继站，接入点等等。可以应用在不同的无线接入技术的系统中，例如长期演进(long term evolution，LTE)系统中，或者，第五代(5th generation，5G)通信系统等更多可能的通信系统中。基站还可以是其他具有基站功能的网络设备，特别地，还可以是D2D通信中担任基站功能的终端。终端可以包括各种具有无线通信功能的手持设备、车载设备、可穿戴设备、计算设备或连接到无线调制解调器的其他处理设备，以及各种形式的用户设备(user equipment，UE)，移动台(mobile station，MS)等。
基于图2所示的通信系统架构，本申请实施例中，发送端201对K个信息比特进行校验编码和Polar编码，其中，发送端201对K个信息比特进行分段校验编码，以及将获得的校验编码码字进行交织，校验编码码字包括K个信息比特和分段校验编码获得的校验比特序列，发送端201将编码后的Polar码发送给接收端202，接收端202进行译码和解交织。
具体地，发送端201进行检验编码的方法可以采用现有技术中的任意一种校验Polar码的编码方法，例如采用现有的CRC编码方式、哈希hash校验编码方式等。
基于图2所示的通信系统架构，下面将结合图3详细介绍一下本申请实施例提供的编码方法。本申请实施例中，以编码方法的执行主体为发送端为例进行介绍。
如图3所示，本申请实施例提供的Polar码的编码方法的具体流程如下所述。
步骤301、对至少两个待校验的第一比特序列分别进行校验编码以获得至少两个校验比特序列。
该至少两个待校验的第一比特序列的并集为全部信息比特序列。该全部信息比特序列为K个信息比特的全部信息比特组成的序列。
其中，对一个第一比特序列进行校验编码，可以获得一个对应的校验比特序列。
步骤302、对全部信息比特序列和该至少两个校验比特序列进行交织操作以获得第二比特序列，或者，将第一部分信息比特序列和第一校验比特序列进行交织操作以获得交织后的第三比特序列，全部信息比特序列中除第一部分信息比特序列之外的第二部分信息比特序列、第二校验比特序列、和第三校验比特序列组成第二比特序列。
步骤303、对第二比特序列进行极化Polar编码。
根据第二比特序列长度，选择Polar编码的信息比特集合，并将与信息比特集合对应 信道设置为第二比特序列的比特值，然后根据Polar码编码矩阵计算得到码字序列。
在接收端或者译码端，获取待译码的序列，对待译码的序列进行Polar码译码。，并对译码后的序列进行解交织操作。
或者，也可以，对顺序译码方式，接收端可以在译码过程中，采用分段译码，根据译码得到的一部分校验比特对译码得到的一部分信息比特进行校验，若已有的译码结果无法通过校验，则立刻停止译码，并反馈译码失败，否则继续译码。
例如，如图4所示为本申请实施例的Polar码的编码方法示意图。
具体地，从K个信息比特中选取出n个子集，n为正整数，第i个子集中包括的信息比特长度为Ki，i＝1、2、……n，获得n个比特序列，记为第一比特序列。其中，Ki可以满足如下关系：Ki＝Int[K*Ri]+Ci，Int[]为取整操作，可以为四舍五入、向上取整或向下取整；Ri为比例常数，如1/16,1/8,1/4,1/2等；Ci为常数，如Ci＝-2,-1,0,1,2,30,40,50，或与i相关的整数，如Ci＝i,2i,4i等。在Polar码编码前，发送端将n个第一比特序列用n个校验码分别进行校验编码，对应获得n个校验比特序列。如，长度为K1的第一比特序列用校验码1进行校验编码，长度为K2的第一比特序列用校验码2进行校验编码以获得的n个校验比特序列分别用P1、P2、…、Pn表示，n个校验比特序列的长度分别为J1、J2、…、Jn，校验比特序列的长度Ji为正整数，i＝1～n。校验码可以为CRC码、Hash码等校验码；通过比特收集，对全部信息比特序列和n个校验比特序列进行排列，可选的排列方式如：按照K个信息比特、P1、P2、…、Pn的顺序进行排列。对排列后的比特序列进行交织操作以获得第二比特序列。交织操作可使得部分校验比特位于信息比特之间，本申请实施例中不限制每个校验比特位于被其校验的信息比特之后，校验比特的位置可以任意放置。最后将交织后的第二比特序列送入Polar编码器进行编码。
本申请实施例涉及的交织操作可由交织序列定义。一种交织序列的计算方式为，根据部分或全部的校验码的校验矩阵的组合矩阵，按一定顺序逐列对组合矩阵进行行交换，该顺序可以是自然顺序或根据列重排序的顺序；对于某一列，行交换的目标为交换后该列中的所有的元素1位于组合矩阵的最靠上的位置；操作的列数小于等于总列数；最后根据行交换的结果获得交织序列。交织序列S包括J个子序列，第i个所述子序列包括中间结果向量T i中元素为1的位置索引值和(K+i)的值，1≤i≤J，i为整数，T i＝(～M)&(V i)，M＝M︱(V i)，M为掩码向量，V i为校验部分矩阵P的列向量，P为校验编码的系统形式生成矩阵G的子矩阵，～表示逐比特取非运算，&表示逐比特与运算，︱表示逐比特或运算。本申请实施例中可以通过其他方式计算交织序列S，也可以通过查表的方式获得交织序列S。需要注意的是，交织序列中校验比特对应的位置没有限定，不需要在其校验的信息比特之后。
在一种可能的实现方式中，从K个信息比特中提取长度为K 1的第一部分信息比特序列，可选的，选取前K 1个信息比特。基于长度为K 1的第一部分信息比特序列和长度为K的全部信息比特序列，获得上述步骤301中所述的两个待校验的第一比特序列。其中，K 1＜K，且K 1、K均为正整数。
步骤302中，发送端对第一部分信息比特序列进行校验编码以获得第一校验比特序列；以及，发送端对全部信息比特序列进行校验编码以获得第二校验比特序列。
步骤303中，可以有两种交织方式，全部交织和部分交织。其中，全部交织的方式为：发送端将全部信息比特序列、第一校验比特序列和第二校验比特序列进行交织操作，获得 第二比特序列；
部分交织的方式为：发送端将第一部分信息比特序列和第一校验比特序列进行交织操作，获得交织后的第三比特序列，以及，发送端将全部信息比特序列中除第一部分信息比特序列之外的第二部分信息比特序列、第二校验比特序列、和第三校验比特序列进行排列，获得第二比特序列。
例如，如图5所示，为上述全部交织的方式的编码示意图。又例如，如图6所示，为上述部分交织的方式的编码示意图。
在图5和图6中，假设校验编码以CRC编码为例，具体步骤为：
一、校验
发送端采用两个CRC码(CRC1和CRC2)分别对长度为K 1的第一部分信息比特序列和长度为K的全部信息比特序列进行校验编码，获得的校验比特序列分别为P1和P2，P1和P2的长度分别为J1和J2。K 1＝Int[K*R]+C，其中，Int[]为取整操作，K为所有信息比特的数量，R和C的可选组合包括{R,C}＝{0.5,0},{0,40}等。其中，J1和J2可以满足一定关系，如J1+J2＝C，J1＝3,4,5,6,7,8等，C为常数，由系统虚警概率要求决定，如C＝19、20等。CRC1和CRC2的生成多项式如表1所示。
二、交织
如图5所示的全部交织：将长度为K的全部信息比特、CRC1获得的校验比特序列P1、CRC2获得的校验比特序列P2全部输入交织器进行交织。
如图6所示的部分交织：对被CRC1校验的K 1个信息比特和CRC1获得的校验比特P1进行排列，得到码字序列CW1。例如，一种排列方式为CW1的前K 1个比特是K 1个信息比特，后J1个比特是校验比特P1。对序列CW1进行交织，交织操作由如表2所示的交织序列定义，交织序列长度为(K 1+J1)，交织后得到CW1’。对剩余的(K-K 1)个信息比特、校验比特P2和CW1’进行排列，一种排列方式对应的排列先后为CW1’、(K-K1)个信息比特、J2个校验比特P2，得到码字CW2。
三、Polar编码
将图5交织后的码字进行Polar编码。
或者，将图6获得的码字CW2进行Polar编码。
表1
Figure PCTCN2018092943-appb-000029
Figure PCTCN2018092943-appb-000030
在表1中，CRC多项式为反序，如CRC长度为4的CRC多项式0x19对应x^4+x+1。
表2
Figure PCTCN2018092943-appb-000031
Figure PCTCN2018092943-appb-000032
Figure PCTCN2018092943-appb-000033
Figure PCTCN2018092943-appb-000034
Figure PCTCN2018092943-appb-000035
Figure PCTCN2018092943-appb-000036
Figure PCTCN2018092943-appb-000037
Figure PCTCN2018092943-appb-000038
Figure PCTCN2018092943-appb-000039
Figure PCTCN2018092943-appb-000040
Figure PCTCN2018092943-appb-000041
Figure PCTCN2018092943-appb-000042
Figure PCTCN2018092943-appb-000043
Figure PCTCN2018092943-appb-000044
Figure PCTCN2018092943-appb-000045
Figure PCTCN2018092943-appb-000046
Figure PCTCN2018092943-appb-000047
Figure PCTCN2018092943-appb-000048
Figure PCTCN2018092943-appb-000049
Figure PCTCN2018092943-appb-000050
Figure PCTCN2018092943-appb-000051
Figure PCTCN2018092943-appb-000052
Figure PCTCN2018092943-appb-000053
Figure PCTCN2018092943-appb-000054
Figure PCTCN2018092943-appb-000055
Figure PCTCN2018092943-appb-000056
表2中列出了CRC长度3,4,5,6,7,8，K1＝32,48,64,30,40,50,60时的交织序列。交织序列中序号小于等于K 1的值，对应的为K 1信息比特的反向编号，如序号1对应第K 1信息比特，序号2对应第(K 1-1)信息比特；对交织序列中序号大于K 1的值，对应J1个校验比特，如序号(K 1+1)对应第1校验比特，序号(K 1+J1)对应第J1校验比特。
可选的，如图7所示，在图6所示的部分交织的Polar码的编码方法的基础上，发送端还可以在第一部分信息比特序列进行校验编码后进行交织，获得第一校验编码码字，将第一校验编码码字与K个信息比特中除第一部分信息比特之外的第二部分信息比特进行比特收集，比特收集的过程可以理解为将第一校验编码码字与第二部分信息比特按照一定排序顺序进行合并，将收集后的序列进行校验编码，获得第二校验编码码字，将第二校验编码码字进行Polar编码。具体地，发送端采用两个CRC码(CRC1和CRC2)分别对长度为K 1的第一部分信息比特序列和长度为K的全部信息比特序列进行校验编码，获得的校验比特序列分别为P1和P2，P1和P2的长度分别为J1和J2。K 1＝Int[K*R]+C，其中，Int[]为取整操作，K为所有信息比特的数量，R和C的可选组合包括{R,C}＝{0.5,0},{0,40}等。其中，J1和J2可以满足一定关系，如J1+J2＝C，J1＝3,4,5,6,7,8等，C为常数，由系统虚警概率要求决定，如C＝19、20等。CRC1和CRC2的生成多项式如表1所示。对被CRC1校验的K 1个信息比特和CRC1产生的J1个校验比特进行交织，得到CW1，交织操作由交织序列定义，典型交织序列如表2所示。收集未被CRC1校验的(K-K1)个信息比特和CW1，得到CW2。对CW2进行CRC2校验，产生的校验比特与CW2进行排列得到CW3。将码字CW3送入Polar编码器进行编码。
上述一种可能的实现方式只是本申请实施例的一种举例，可以理解的是，发送端还可以从K个信息比特提取长度为K 1的第一部分信息比特序列，以及提取长度为K 2的第二部分信息比特序列，K＝K 1+K 2，第一部分信息比特序列和第二部分信息比特序列互补，且并集为K个信息比特的全部信息比特序列。校验、交织和编码的方式与上述一种可能的实现方式描述方式类似，可选的，第一部分信息比特序列还可以与第二部分信息比特序列存在交集。总之，上述一种可能的实现方式所描述的Polar码的编码方法适用于任意情形下的两个待编码的第一比特序列。
在另一种可能的实现方式中，发送端对长度为0的空集比特序列进行校验编码以获得第一校验比特序列(或者为与上述描述区分，此处记为第三校验比特序列)，对K个信息比特进行校验编码以获得第二校验比特序列，K为正整数。第三校验比特序列为全零向量，长度与校验码相关。发送端将全部信息比特序列、第二校验比特序列和第三校验比特序列进行交织操作，对交织操作后的序列进行Polar编码。
例如，如图8所示，为上述另一种可能的实现方式中的编码示意图。
(一)、校验
在Polar码编码前，发送端采用两个CRC码(CRC1和CRC2)分别对长度为0的空集比特序列和长度为K的全部信息比特序列进行校验编码，获得的校验比特序列分别为P1和P2，P1和P2的长度分别为J1和J2。P1为全零向量。J1和J2满足一定关系，如J1+J2＝C，J2＝16,17,18,19等，其中C为常数，由系统虚警概率要求决定，如C＝19、20、21、22等，CRC1和CRC2的生成多项式如表1所示；
(二)、交织
对K个信息比特、CRC1获得的校验比特序列P1、CRC2获得的校验比特序列P2进行排序和交织。
对K个信息比特和校验比特序列P2进行排列，得到码字序列CW1，一种排列方式为CW1的前K个比特是K个信息比特，后J2个比特是校验比特P2；
对码字CW1进行交织，交织操作由交织序列定义，交织序列如表3所示，长度为(K+J2)，交织后得到CW1’；
将CRC1获得的校验比特序列P1插入CW1’，得到码字CW2，即将P1的校验比特穿插在CW1’中，插入位置可以是CW1’之前、之后或中间，若插入到CW1’中间，一种方法是插入位置对应后续Polar编码时(K+J1+J2)个位置中可靠度最低的位置。
(三)、编码
将码字CW2输入Polar编码器进行编码。
表3
Figure PCTCN2018092943-appb-000057
Figure PCTCN2018092943-appb-000058
Figure PCTCN2018092943-appb-000059
Figure PCTCN2018092943-appb-000060
Figure PCTCN2018092943-appb-000061
Figure PCTCN2018092943-appb-000062
Figure PCTCN2018092943-appb-000063
Figure PCTCN2018092943-appb-000064
Figure PCTCN2018092943-appb-000065
Figure PCTCN2018092943-appb-000066
Figure PCTCN2018092943-appb-000067
Figure PCTCN2018092943-appb-000068
Figure PCTCN2018092943-appb-000069
Figure PCTCN2018092943-appb-000070
Figure PCTCN2018092943-appb-000071
Figure PCTCN2018092943-appb-000072
Figure PCTCN2018092943-appb-000073
Figure PCTCN2018092943-appb-000074
Figure PCTCN2018092943-appb-000075
Figure PCTCN2018092943-appb-000076
Figure PCTCN2018092943-appb-000077
Figure PCTCN2018092943-appb-000078
Figure PCTCN2018092943-appb-000079
Figure PCTCN2018092943-appb-000080
Figure PCTCN2018092943-appb-000081
Figure PCTCN2018092943-appb-000082
Figure PCTCN2018092943-appb-000083
Figure PCTCN2018092943-appb-000084
Figure PCTCN2018092943-appb-000085
Figure PCTCN2018092943-appb-000086
Figure PCTCN2018092943-appb-000087
Figure PCTCN2018092943-appb-000088
Figure PCTCN2018092943-appb-000089
Figure PCTCN2018092943-appb-000090
Figure PCTCN2018092943-appb-000091
Figure PCTCN2018092943-appb-000092
Figure PCTCN2018092943-appb-000093
Figure PCTCN2018092943-appb-000094
Figure PCTCN2018092943-appb-000095
Figure PCTCN2018092943-appb-000096
Figure PCTCN2018092943-appb-000097
Figure PCTCN2018092943-appb-000098
Figure PCTCN2018092943-appb-000099
Figure PCTCN2018092943-appb-000100
Figure PCTCN2018092943-appb-000101
Figure PCTCN2018092943-appb-000102
Figure PCTCN2018092943-appb-000103
Figure PCTCN2018092943-appb-000104
Figure PCTCN2018092943-appb-000105
Figure PCTCN2018092943-appb-000106
Figure PCTCN2018092943-appb-000107
Figure PCTCN2018092943-appb-000108
Figure PCTCN2018092943-appb-000109
Figure PCTCN2018092943-appb-000110
表3中列出了CRC长度19,18,17,16，K＝80,100,120时的交织序列。交织序列中序号小于等于K的值，对应的为K信息比特的反向编号，如序号1对应第K信息比特，序号2对应第(K-1)信息比特；对交织序列中序号大于K的值，对应J2个校验比特，如序号(K+1)对应第1校验比特，序号(K+J2)对应第J2校验比特。
基于同一发明构思，如图9所示，本申请实施例还提供了另一种Polar码的编码方法。根据Polar码参数确定校验比特数量，并从所有校验比特中选取全集或子集，与信息比特一起组成预编码比特，对预编码比特进行Polar编码。具体过程如下所述。
步骤901、基于设定校验比特长度对K个信息比特进行校验编码以获得第一校验比特序列；
步骤902、按照设定编码参数，从第一校验比特序列中选取部分或全部校验比特，获得第二校验比特序列。
其中，设定编码参数以下至少一种参数或至少一种参数的衍生参数：K个信息比特的长度、母码长度、编码长度、码率、路径宽度。
具体地，选取可靠度靠前的部分校验比特，获得第二校验比特序列；或者，发送端选择可靠度靠后的部分校验比特，获得第二校验比特序列；或者，发送端选择指定的部分校验比特，获得第二校验比特序列。
步骤903、将第二校验比特序列与K个信息比特进行合并。
其中，将第二校验比特序列连续地置于K个信息比特位置之前或之后或指定位置；或者，按照设定的循环移位值，将第二校验比特序列连续地置于K个信息比特的指定位置；或者，发将第二校验比特序列与K个信息比特进行交织操作。
步骤904、对合并后的序列进行极化Polar编码。
下面以编码方式为CRC编码为例，对图9所示的Polar码的编码方法进一步详细说明。
在固定CRC多项式长度Jmax时，针对不同的码参数，从Jmax中选取不同的CRC比特数量J作为预编码比特参与Polar编码。
其中码参数可以包含以下至少一种：信息比特长度K，编码长度M，码率R＝K/M， 母码长度N，与译码侧约定的路径宽度(即List大小)L。或者，码参数为由上述参数确定的衍生参数。
如图10a所示，为图9所示的Polar码的编码方法的简要示意图。发送端对长度为K的K个信息比特比特进行CRC编码以获得长度为Jmax的第一校验比特序列，从长度为Jmax的第一校验比特序列中根据编码参数选取长度为J的第二校验比特序列，J＜Jmax，将长度为J的第二校验比特序列插入信息比特中以获得长度为(K+J)的预编码比特序列，对预编码比特序列进行Polar码编码。可选的，对长度为(K+J)的预编码比特序列进行交织，对交织后的序列进行Polar码编码。
具体地，发送端校验编码过程所需校验比特数量J可以为J＝J ref+J’，其中J ref为满足虚警概率要求的CRC比特数量，可选的，
Figure PCTCN2018092943-appb-000111
其中，integer为各种取整函数，比如上取整、下取整、四舍五入；scale(J ref)为J ref的函数，可为4*J ref+β。
或者，发送端校验编码过程所需CRC比特数量J根据(M-K)的大小，由分段函数确定。例如，具体确定方式如表4所示。
表4
M-K 0～256 256～512 512～1024 …
J ref+J’ J ref+0 J ref+1 J ref+2 …
可见，随着(M-K)的值越大，所需CRC比特的数量越大。
这样，发送端进行校验编码所需的CRC比特的数量可以灵活获取，只需要一种校验编码设置获得长度最长的Jmax的CRC比特，然后选取合适数量的CRC比特。
所需J个CRC比特从Jmax个CRC比特中选取，有如下选取方法：
选取Jmax个CRC比特中的J个最低位比特，或者，选取Jmax个CRC比特中的J个最高位比特，或者，选取Jmax个CRC比特中指定的J个位置的比特，J个位置由向量(i 1,i 2,…,i j)指定。
具体地，插入信息比特的位置有如下确定方式：
(1)连续放置
以信息比特序列中某个位置为起始位置，连续放置J个CRC比特。特殊情况为将J个CRC比特连续放置在长度为K的信息比特之前，或者，放在长度为K的信息比特之后。
(2)循环连续放置
在连续放置的基础上，再进行给定偏移的循环移位。例如，以信息比特序列中某个位置为起始位置，结合循环移位确定信息比特序列中某个位置为终止位置，放置J个CRC比特。
(3)分散放置
若对长度为(K+J)的预编码比特序列进行交织，交织操作采用交织序列，对信息比特和CRC比特一起做交织，交织后的CRC比特散布在信息比特之间。
其中，可以只将部分CRC比特和信息比特一起做交织操作。也可以按一定比例，直接将CRC比特散布在信息比特之间，信息比特不参与交织。
基于图9或图10a所示的Polar码的编码方法，一种可能的设计中，发送端根据编码参数确定校验比特的数量，并相应地选取校验多项式对K个信息比特进行校验编码以获得的校验比特和K个信息比特共同组成预编码比特，对预编码比特进行Polar编码。其中， 设定编码参数以下至少一种参数或所述至少一种参数的衍生参数：所述K个信息比特的长度、母码长度、编码长度、码率、路径宽度。具体地，以校验编码为CRC编码为例，如图10b所示，发送端根据编码参数确定CRC校验比特数量，或者称为CRC校验比特序列的长度，例如CRC校验比特数量包括J 1、J 2、……、Jn，发送端选择CRC校验比特数量为J，发送端根据选择的CRC校验比特数量，对K个信息比特进行校验编码，获得校验比特，发送端将J个校验比特插入K个信息比特以获得长度为(K+J)的预编码比特，发送端对预编码比特进行Polar编码。可选的，发送端将长度为(K+J)的预编码比特进行交织，对交织后的序列进行Polar编码。其中，发送端校验编码过程所需校验比特数量J的确定方法、插入信息比特的位置的确定方法等与图10a所示的Polar码的编码方法中描述方法相同，重复之处不再赘述。
基于图3所示Polar码的编码方法的同一发明构思，如图11所示，本申请实施例中还提供一种Polar码的编码装置1100，Polar码的编码装置1100用于执行图3所示Polar码的编码方法，Polar码的编码装置1100包括：
校验单元1101，用于对至少两个待校验的第一比特序列分别进行校验编码以获得至少两个校验比特序列；至少两个待校验的第一比特序列的并集为K个信息比特，K为正整数；
交织单元1102，用于对K个信息比特和至少两个校验比特序列进行交织操作以获得第二比特序列，或者，将第一部分信息比特序列和第一校验比特序列进行交织操作以获得交织后的第三比特序列；以及，将全部信息比特序列中除第一部分信息比特序列之外的第二部分信息比特序列、第二校验比特序列、和第三校验比特序列进行排列以获得第二比特序列；
编码单元1103，用于对第二比特序列进行极化Polar编码。
可选的，至少两个待校验的第一比特序列包括：长度为K 1的第一部分信息比特序列，和长度为K的全部信息比特序列，K 1＜K，且K 1、K均为正整数。
可选的，校验单元1101具体用于：对第一部分信息比特序列进行校验编码以获得第一校验比特序列；以及对全部信息比特序列进行校验编码以获得第二校验比特序列。
可选的，交织单元1102采用的交织序列S进行交织操作，交织序列S包括J个子序列，第i个子序列包括中间结果向量T i中元素为1的位置索引值和(K+i)的值，1≤i≤J，i为整数，T i＝(～M)&(V i)，M＝M︱(V i)，M为掩码向量，V i为校验部分矩阵P的列向量，P为校验编码的系统形式生成矩阵G的子矩阵，～表示逐比特取非运算，&表示逐比特与运算，︱表示逐比特或运算。
可选的，交织单元1102在进行交织操作之前，计算交织序列S；或者，交织单元1102离线计算并存储交织序列S；根据K个信息比特中的部分信息比特的长度以及确定的校验多项式，读取存储的交织序列S，并按照读取的交织序列S进行交织操作。
基于上述图3所示Polar码的编码方法的同一发明构思，如图12所示，本申请实施例中还提供一种Polar码的编码装置1200，Polar码的编码装置1200用于执行图3所示的编译码方法中发送端执行的步骤，Polar码的编码装置1200包括：
校验单元1201，用于对长度为0的空集比特序列进行校验编码以获得第一校验比特序列，以及对K个信息比特进行校验编码以获得第二校验比特序列；
交织单元1202，用于对K个信息比特、第一校验比特序列和第二校验比特序列进行交织操作；
编码单元1203，用于对交织操作后的序列进行极化Polar编码。
可选的，第一校验比特序列为全零向量。
可选的，交织单元1202进行交织操作所采用的交织序列S包括J个子序列，第i个子序列包括中间结果向量T i中元素为1的位置索引值和(K+i)的值，1≤i≤J，i为整数，T i＝(～M)&(V i)，M＝M︱(V i)，M为掩码向量，V i为校验部分矩阵P的列向量，P为校验编码的系统形式生成矩阵G的子矩阵，～表示逐比特取非运算，&表示逐比特与运算，︱表示逐比特或运算。
可选的，交织单元1202在进行交织操作之前，计算交织序列S；或者，交织单元1202离线计算并存储交织序列S，根据K的值以及确定的校验多项式，读取存储的交织序列S，并按照读取的交织序列S进行交织操作。
基于上述图3所示Polar码的编码方法的同一发明构思，如图13所示，本申请实施例中还提供一种Polar码的编码装置1300，Polar码的编码装置1300用于执行图3所示的Polar码的编码方法，Polar码的编码装置1300包括：
校验单元1301，用于对K个信息比特中的第一部分信息比特序列进行校验编码；
交织单元1302，用于对校验编码后的码字进行交织操作以获得第一校验编码码字，K为正整数，第一校验编码码字包括第一部分信息比特序列和第一校验比特序列；
校验单元1301，还用于将由第一校验编码序列、K个信息比特中除第一部分信息比特序列之外的第二部分信息比特序列合并后的序列进行校验编码以获得第二校验编码码字，第二校验编码码字包括第一部分信息比特序列、第一校验比特序列、第二部分信息比特序列和第二校验比特序列；
编码单元1303，用于将第二校验编码码字进行极化Polar编码。
可选的，交织单元1302进行交织操作所采用的交织序列S包括J个子序列，第i个子序列包括中间结果向量T i中元素为1的位置索引值和(K+i)的值，1≤i≤J，i为整数，T i＝(～M)&(V i)，M＝M︱(V i)，M为掩码向量，V i为校验部分矩阵P的列向量，P为校验编码的系统形式生成矩阵G的子矩阵，～表示逐比特取非运算，&表示逐比特与运算，︱表示逐比特或运算。
交织单元1302在进行交织操作之前，计算交织序列S；或者，离线计算并存储交织序列S，对K个信息比特中的第一部分信息比特序列进行校验编码，并根据第一部分信息比特序列的长度以及确定的校验多项式，读取存储的交织序列S，并按照读取的交织序列S进行交织操作。
基于图9的Polar码的编码方法的同一发明构思，如图14所示，本申请实施例还提供一种Polar码的编码装置1400，包括：
校验单元1401，用于基于设定校验比特长度对K个信息比特进行校验编码以获得第一校验比特序列；
选取单元1402，用于按照设定编码参数，从第一校验比特序列中选取第二校验比特序列；
编码单元1403，用于将由第二校验比特序列与K个信息比特合并后的序列进行极化Polar编码。
可选的，设定编码参数以下至少一种参数或至少一种参数的衍生参数：K个信息比特的长度、母码长度、编码长度、码率、路径宽度。
可选的，选取单元1402具体用于：选取可靠度靠前的第二校验比特序列；或者，选择可靠度靠后的第二校验比特序列；或者，选择指定的第二校验比特序列。
可选的，还包括合并单元1404，用于将第二校验比特序列连续地置于K个信息比特位置之前或之后或指定位置；或者，按照设定的循环移位值，将第二校验比特序列连续地置于K个信息比特的指定位置；或者，将第二校验比特序列与K个信息比特进行交织操作。
基于图3或图9所示的Polar码的编码方法的同一发明构思，如图15所示，本申请实施例中还提供一种Polar码的编码装置1500，该Polar码的编码装置1500用于执行图3或图9所示的Polar码的编码方法。上述实施例的Polar码的编码方法中的部分或全部可以通过硬件来实现也可以通过软件来实现，当通过硬件实现时，Polar码的编码装置1500包括：输入接口电路1501，用于获取K个信息比特；逻辑电路1502，用于执行上述图3或图9所示的Polar码的编码方法，具体请见前面方法实施例中的描述，此处不再赘述；输出接口电路1503，用于输出Polar编码后的比特序列。
可选的，Polar码的编码装置1500在具体实现时可以是芯片或者集成电路。
可选的，当上述实施例的Polar码的编码方法中的部分或全部通过软件来实现时，如图16所示，Polar码的编码装置1500包括：存储器1601，用于存储程序；处理器1602，用于执行存储器1601存储的程序，当程序被执行时，使得Polar码的编码装置1500可以实现上述实施例提供的Polar码的编码方法。
可选的，上述存储器1601可以是物理上独立的单元，也可以如图17所示，存储器1601与处理器1602集成在一起。
可选的，当上述实施例的Polar码的编码方法中的部分或全部通过软件实现时，Polar码的编码装置1500也可以只包括处理器1602。用于存储程序的存储器1601位于Polar码的编码装置1500之外，处理器1602通过电路/电线与存储器1601连接，用于读取并执行存储器1601中存储的程序。
本申请实施例提供了一种计算机存储介质，用于存储计算机程序，该计算机程序包括用于执行图3或图9所示的Polar码的编码方法。
本申请实施例提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行图3或图9所示的Polar码的编码方法。
本申请实施例图11～图15所示的Polar码的编码装置还可以是一种系统芯片。
处理器1602可以是中央处理器(central processing unit，CPU)，网络处理器(network processor，NP)或者CPU和NP的组合。
处理器1602还可以进一步包括硬件芯片。上述硬件芯片可以是专用集成电路(appJication-specific integrated circuit，ASIC)，可编程逻辑器件(programmable logic device，PLD)或其组合。上述PLD可以是复杂可编程逻辑器件(complex programmable logic device，CPLD)，现场可编程逻辑门阵列(field-programmable gate array，FPGA)，通用阵列逻辑(generic array logic,GAL)或其任意组合。
存储器1601可以包括易失性存储器(volatile memory)，例如随机存取存储器(random-access memory，RAM)；存储器1601也可以包括非易失性存储器(non-volatile memory)，例如快闪存储器(flash memory)，硬盘(hard disk drive，HDD)或固态硬盘(soJid-state drive，SSD)；存储器1601还可以包括上述种类的存储器的组合。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产 品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的精神和范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (26)

  1. 一种极化Polar码的编码方法，其特征在于，包括：
    对至少两个待校验的第一比特序列分别进行校验编码以获得至少两个校验比特序列，所述至少两个待校验的第一比特序列的并集为K个信息比特，K为正整数；
    对所述K个信息比特和所述至少两个校验比特序列进行交织操作以获得第二比特序列，或者，将所述第一部分信息比特序列和所述第一校验比特序列进行交织操作以获得交织后的第三比特序列，所述全部信息比特序列中除所述第一部分信息比特序列之外的第二部分信息比特序列、所述第二校验比特序列、和所述第三校验比特序列组成第二比特序列；
    对所述第二比特序列进行极化Polar编码。
  2. 如权利要求1所述的方法，其特征在于，所述至少两个待校验的第一比特序列包括：
    长度为K 1的第一部分信息比特序列，和长度为K的全部信息比特序列，K 1＜K，且K 1、K均为正整数。
  3. 如权利要求2所述的方法，其特征在于，所述对所述至少两个待校验的第一比特序列分别进行校验以获得至少两个校验比特序列，包括：
    对所述第一部分信息比特序列进行校验编码以获得第一校验比特序列；以及
    对所述全部信息比特序列进行校验编码以获得第二校验比特序列。
  4. 如权利要求1～3任一项所述的方法，其特征在于，所述交织操作所采用的交织序列S包括J个子序列，第i个所述子序列包括中间结果向量T i中元素为1的位置索引值和(K+i)的值，1≤i≤J，i为整数，T i＝(～M)&(V i)，M＝M︱(V i)，M为掩码向量，V i为校验部分矩阵P的列向量，P为校验编码的系统形式生成矩阵G的子矩阵，～表示逐比特取非运算，&表示逐比特与运算，︱表示逐比特或运算。
  5. 如权利要求4所述的方法，其特征在于，在进行交织操作之前，计算所述交织序列S。
  6. 如权利要求4或5所述的方法，其特征在于，所述对所述K个信息比特中的部分信息比特、和所述至少两个校验比特序列中的部分校验比特序列进行交织操作，包括：
    根据所述K个信息比特中的部分信息比特的长度以及确定的校验多项式，读取存储的所述交织序列S，并按照读取的所述交织序列S进行交织操作。
  7. 一种极化Polar码的编码方法，其特征在于，包括：
    对长度为0的空集比特序列进行校验编码以获得第一校验比特序列，以及对K个信息比特进行校验编码以获得第二校验比特序列；
    对所述K个信息比特、所述第一校验比特序列和所述第二校验比特序列进行交织操作；
    对交织操作后的序列进行极化Polar编码。
  8. 如权利要求7所述的方法，其特征在于，所述第一校验比特序列为全零向量。
  9. 如权利要求7或8所述的方法，其特征在于，所述交织操作所采用的交织序列S包括J个子序列，第i个所述子序列包括中间结果向量T i中元素为1的位置索引值和(K+i)的值，1≤i≤J，i为整数，T i＝(～M)&(V i)，M＝M︱(V i)，M为掩码向量，V i为校验部分矩阵P的列向量，P为校验编码的系统形式生成矩阵G的子矩阵，～表示逐比特取非运算，&表示逐比特与运算，︱表示逐比特或运算。
  10. 如权利要求9所述的方法，其特征在于，在进行交织操作之前，计算所述交织序列S。
  11. 如权利要求9或10所述的方法，其特征在于，所述对所述K个信息比特、所述第一校验比特序列和所述第二校验比特序列进行交织操作，包括：
    根据所述K的值以及确定的校验多项式，读取存储的所述交织序列S，并按照读取的所述交织序列S进行交织操作。
  12. 一种极化Polar码的编码装置，其特征在于，包括：
    校验单元，用于对至少两个待校验的第一比特序列分别进行校验编码以获得至少两个校验比特序列，所述至少两个待校验的第一比特序列的并集为K个信息比特，K为正整数；
    交织单元，用于对所述K个信息比特和所述至少两个校验比特序列进行交织操作以获得第二比特序列，或者，将所述第一部分信息比特序列和所述第一校验比特序列进行交织操作以获得交织后的第三比特序列；以及，所述全部信息比特序列中除所述第一部分信息比特序列之外的第二部分信息比特序列、所述第二校验比特序列、和所述第三校验比特序列组成所述第二比特序列；
    编码单元，用于对所述第二比特序列进行极化Polar编码。
  13. 如权利要求12所述的装置，其特征在于，所述至少两个待校验的第一比特序列包括：
    长度为K 1的第一部分信息比特序列，和长度为K的全部信息比特序列，K 1＜K，且K 1、K均为正整数。
  14. 如权利要求13所述的装置，其特征在于，所述校验单元具体用于：
    对所述第一部分信息比特序列进行校验编码以获得第一校验比特序列；以及
    对所述全部信息比特序列进行校验编码以获得第二校验比特序列。
  15. 如权利要求12～14任一项所述的装置，其特征在于，所述交织单元进行交织操作所采用的交织序列S包括J个子序列，第i个所述子序列包括中间结果向量T i中元素为1的位置索引值和(K+i)的值，1≤i≤J，i为整数，T i＝(～M)&(V i)，M＝M︱(V i)，M为掩码向量，V i为校验部分矩阵P的列向量，P为校验编码的系统形式生成矩阵G的子矩阵，～表示逐比特取非运算，&表示逐比特与运算，︱表示逐比特或运算。
  16. 如权利要求15所述的装置，其特征在于，所述交织单元还用于：
    在进行交织操作之前，计算所述交织序列S。
  17. 如权利要求15或16所述的装置，其特征在于，所述交织单元具体用于：根据所述K个信息比特中的部分信息比特的长度以及确定的校验多项式，读取存储的所述交织序列S，并按照读取的所述交织序列S进行交织操作。
  18. 一种极化Polar码的编码装置，其特征在于，包括：
    校验单元，用于对长度为0的空集比特序列进行校验编码以获得第一校验比特序列，以及对K个信息比特进行校验编码以获得第二校验比特序列；
    交织单元，用于对所述K个信息比特、所述第一校验比特序列和所述第二校验比特序列进行交织操作；
    编码单元，用于对交织操作后的序列进行极化Polar编码。
  19. 如权利要求18所述的装置，其特征在于，所述第一校验比特序列为全零向量。
  20. 如权利要求18或19所述的装置，其特征在于，所述交织单元进行交织操作所采 用的交织序列S包括J个子序列，第i个所述子序列包括中间结果向量T i中元素为1的位置索引值和(K+i)的值，1≤i≤J，i为整数，T i＝(～M)&(V i)，M＝M︱(V i)，M为掩码向量，V i为校验部分矩阵P的列向量，P为校验编码的系统形式生成矩阵G的子矩阵，～表示逐比特取非运算，&表示逐比特与运算，︱表示逐比特或运算。
  21. 如权利要求20所述的装置，其特征在于，所述交织单元还用于：
    发送端在进行交织操作之前，计算所述交织序列S。
  22. 如权利要求20或21所述的装置，其特征在于，所述交织单元具体用于：
    根据所述K的值以及确定的校验多项式，读取存储的所述交织序列S，并按照读取的所述交织序列S进行交织操作。
  23. 一种极化Polar码的编码装置，其特征在于，包括处理器和存储器；其中，所述存储器中存储一组程序，所述处理器用于调用所述存储器中存储的程序，当所述程序被执行时，使得所述处理器执行如权利要求1～6或7-11中任一项所述的方法。
  24. 如权利要求23所述的装置，其特征在于，所述装置为芯片或集成电路。
  25. 一种计算机存储介质，其特征在于，存储有计算机程序，所述计算机程序包括用于执行如权利要求1～6或7-11中任一项所述的方法的指令。
  26. 一种包含指令的计算机程序产品，其特征在于，当所述计算机程序产品在计算机上运行时，使得计算机执行如权利要求1～6或7-11中任一项所述的方法。
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