WO2017054164A1 - 极化码的编译码方法及其装置 - Google Patents
极化码的编译码方法及其装置 Download PDFInfo
- Publication number
- WO2017054164A1 WO2017054164A1 PCT/CN2015/091202 CN2015091202W WO2017054164A1 WO 2017054164 A1 WO2017054164 A1 WO 2017054164A1 CN 2015091202 W CN2015091202 W CN 2015091202W WO 2017054164 A1 WO2017054164 A1 WO 2017054164A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- decoding
- bits
- bit
- group
- crc
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
Definitions
- the present invention relates to communication technologies, and in particular, to a coding and decoding method for a polarization code and an apparatus therefor.
- FEC Forward Error Correction
- Polar code (hereinafter referred to as Polar code) is a kind of FEC technology. It is a channel coding method proposed by Erdal Arikan in 2007. It is based on Binary Discrete Memoryless Channel (BDMC). This coding method can theoretically reach the Shannon limit and has a low coding code complexity.
- SC decoding algorithm is the most common decoding algorithm for Polar codes. However, for medium and long codes, SC decoding performance is not ideal.
- SC List sequence sequential deletion
- CRC Cyclic Redundancy Check
- the SCL+CRC algorithm performs path splitting after each SC decoding, allowing the Lmax strip decoding result path, and selecting a path capable of passing the CRC check and having the largest probability product from the Lmax strip decoding result path.
- the decoding result is used as a decoding output, thereby significantly improving the decoding accuracy.
- the existing SCL+CRC decoding algorithm has a slow decoding speed and a large delay, which cannot meet the high-efficiency processing requirements.
- Embodiments of the present invention provide a coding and decoding method for a polarization code and a device thereof to improve decoding speed.
- an embodiment of the present invention provides a method for encoding a polarization code, including:
- the information bits are sequentially divided into M groups of information bits according to the position in the codeword, where M is an integer greater than or equal to 2;
- the bit generated by the bit, the CRC check bit added by the mth information bit is generated according to the first group information bit to the m-1th information bit and the mth information bit to which the CRC check bit is added, 2 ⁇ m ⁇ M;
- the information bits to be transmitted and the frozen bits are polarization coded to obtain a codeword and transmitted.
- the information bits are sequentially divided into M groups of information bits according to the position in the codeword, including:
- the information bits are equally divided into M groups in order of position in the code word to obtain M sets of information bits.
- the pair of M information bits are respectively added with a cyclic redundancy check code CRC check bit, including:
- the CRC check bits are respectively appended to the tail of each group of information bits in the M group of information bits.
- an embodiment of the present invention provides a method for decoding a polarization code, including:
- the decoding process includes: receiving the bits in the m-1th group
- the SCL decoding process of the L paths is performed, and the decoding results of the L paths are respectively subjected to CRC check together with the final decoding results of the received bits of the 1st to the m-2th groups, and if the L paths are decoded If there is a path that can pass the CRC check, the SCL decoding process is started on the mth received bit; otherwise, the L is doubled, and the SCL decoding process is restarted from the first group until L reaches the upper limit of the path number. L max and m reaches M.
- the SCL decoding process is performed on the M group of received bits, and the final decoding result corresponding to the M group of received bits is combined with the frozen bit and output, including:
- the optimal decoding result in the decoding result that is to be verified is used as a final decoding result corresponding to the mth group receiving bit.
- the decoding result of the path with the largest node probability product in the decoding result of each path is used as the final decoding result corresponding to the mth group receiving bit, and executing S607;
- the method before performing the SCL decoding process on the M group of received bits, the method further includes:
- the L max is adjusted based on the reception speed of the current information bits and/or the remaining space of the reception buffer.
- an embodiment of the present invention provides an encoding device, including:
- a grouping module configured to divide the information bits into M groups of information bits according to the position in the codeword, where M is an integer greater than or equal to 2;
- an encoding processing module configured to respectively add a cyclic redundancy check code CRC check bit to the M group information bits to obtain information bits to be sent, wherein the CRC check bits attached to the first group information bits are based on the first group information
- the bit generated by the bit, the CRC check bit added by the mth information bit is generated according to the first group information bit to the m-1th information bit and the mth information bit to which the CRC check bit is added, 2 ⁇ m ⁇ M;
- a code sending module configured to perform polarization coding on the information bits to be sent and the frozen bits, obtain a codeword, and send the codeword.
- the grouping module is specifically configured to divide the information bits into M groups according to the position order in the codeword, to obtain M groups of information bits.
- an embodiment of the present invention provides an encoding device, including: a packetizer, and M CRCs. a generator and an encoder; wherein a packetizer is coupled to an input of the M CRC generators, an output of the mth CRC generator and the encoder and the m+1th to Mth CRC generators The input is connected, and the output of the Mth CRC generator is connected to the encoder, where M is an integer greater than or equal to 2;
- the packetizer is configured to divide the information bits into M groups of information bits according to the position in the codeword;
- the M CRC generators are configured to respectively add a cyclic redundancy check code CRC check bit to the M group information bits to obtain information bits to be transmitted, wherein the CRC check bits attached to the first group information bits are based on The CRC check bits added by the mth information bits generated by the first group of information bits are generated based on the first group information bits to the m-1th information bits and the mth information bits to which the CRC check bits are added. , 2 ⁇ m ⁇ M;
- the encoder is configured to perform polarization coding on the information bits to be sent and the frozen bits to obtain a codeword and send the same.
- an embodiment of the present invention provides a decoding device, including:
- a packet module configured to receive a codeword, where the codeword includes a received bit and a frozen bit; extracting a received bit from the codeword, and dividing the received bit into M sets of received bits according to a position in a codeword , wherein each group of received bits includes a cyclic redundancy check code CRC check bit, and M is an integer greater than or equal to 2;
- a decoding processing module configured to perform SCL decoding processing on the M groups of received bits, and combine and output the final decoding result corresponding to the M groups of received bits, where the decoding processing includes:
- the m-1th group receives the SCL decoding process of the L paths, and performs the CRC check on the decoding results of the L paths together with the final decoding results of the 1st to m-2th received bits, respectively. If there is a path capable of passing the CRC check in the decoding result of the L paths, the SCL decoding process is started on the mth received bit; otherwise, the L is doubled, and the SCL decoding process is restarted from the first group. Until L reaches the upper limit of the path number L max and m reaches M.
- the decoding processing module is specifically configured to:
- the optimal decoding result in the decoding result that is to be verified is used as a final decoding result corresponding to the mth group receiving bit.
- the decoding result of the path with the largest node probability product in the decoding result of each path is used as the final decoding result corresponding to the mth group receiving bit, and executing S607;
- an embodiment of the present invention provides a decoding apparatus, including: a packetizer, an SCL decoder, M CRC checkers, a controller, and a memory; wherein the packetizer and the SCL decoder Connecting, the mth output of the SCL decoder is connected to the m+1th to Mth CRC checkers, the memory and the controller and the SCL decoder, the controller and the M CRC checkers are connected to the SCL decoder, where M is an integer greater than or equal to 2;
- the packetizer is configured to receive a codeword, where the codeword includes a received bit and a frozen bit; extract a received bit from the codeword, and divide the received bit into M groups according to a position in a codeword Receiving bits, wherein each group of received bits includes a CRC check bit;
- the SCL decoder is configured to perform SCL decoding processing on the M groups of received bits, and send the decoding processing result to the CRC checker for CRC check;
- the M CRC checkers are configured to perform a CRC check on the decoded result of the M sets of received bits to obtain a check result
- the controller is configured to determine a final decoding result of each group of received bits according to the check result, and store the final decoding result into the memory, and obtain a decoding result of all received bits After that, the final decoding result corresponding to the M group receiving bits is combined with the frozen bit and output;
- the memory is configured to store a final decoding result of each group of received bits determined by the controller, and feed back a final decoding result of each group of received bits to the SCL checker;
- the SCL decoding process and the CRC check process include: performing SCL decoding processing on the L-th path of the m-1th received bit, and decoding the result of each L path and the first The final decoding result of the received bits of the m-2th group is performed together with the CRC check. If there is a path that can pass the CRC check in the decoding result of the L paths, the SCL decoding process of the mth received bits is started. Otherwise, L is doubled, and SCL decoding processing is resumed from the first group until L reaches the upper limit of the path number L max and m reaches M.
- the SCL decoding process and the CRC check process specifically include:
- the optimal decoding result in the decoding result that is to be verified is used as a final decoding result corresponding to the mth group receiving bit.
- the decoding result of the path with the largest node probability product in the decoding result of each path is used as the final decoding result corresponding to the mth group receiving bit, and executing S607;
- the information bits to be transmitted at the encoding end are segment-encoded, and the received information bits are segment-decoded at the decoding end, and in the SCL decoding process, the split path is adaptively adjusted, as opposed to In the prior art, the decoding time is significantly reduced, the decoding speed is fast, the delay is low, and the decoding speed of 2-M times can be improved.
- the coding end when the coding end generates the CRC check bit for the mth information bit, the information bits of the first to m-1 groups are all introduced together for CRC calculation, thereby ensuring the information bits of each group in the segment coding.
- the embodiment of the present invention can also dynamically adjust the path number upper limit L max , avoiding idle or waste of the decoding device, and reasonably allocating system resources; further, the decoding capability of the embodiment of the present invention and the traditional SCL+CRC decoder Quite, the decoding ability is not lossless.
- 1 is a schematic diagram of encoding processing of an existing polarization code SCL+CRC;
- FIG. 2 is a flow chart of an embodiment of a method for encoding a polarization code according to the present invention
- FIG. 3 is a schematic structural diagram of an encoding apparatus used in the method embodiment shown in FIG. 2;
- FIG. 5 is a schematic structural diagram of a decoding device for a polarization code according to the present invention.
- FIG. 6 is a flowchart of an embodiment of a method for decoding a polarization code according to the present invention.
- FIG. 7 is a schematic diagram of processing state transition of a controller in the decoding device shown in FIG. 5;
- FIG. 8 is a schematic diagram of comparison between a decoding process and an existing SCL decoding process according to an embodiment of the present invention.
- FIG. 9 is a schematic structural diagram of an embodiment of an encoding device according to the present invention.
- FIG. 10 is a schematic structural diagram of an embodiment of a decoding device according to the present invention.
- the embodiment of the invention is directed to the encoding and decoding process of the Polar code.
- the Polar code is based on the channel polarization theory. After the channel is polarized, part of the channel tends to be a noiseless channel, and another part of the channel tends to a full noise channel. Based on this phenomenon, when the Polar code is encoded, the information bits to be transmitted can be transmitted on the noiseless channel, and the frozen bits can be transmitted on the full noise channel. Therefore, when the code length N tends to At infinity, the system capacity can reach the Shannon limit.
- the encoding of the Polar code is also referred to as G N coset encoding.
- the Polar code is a linear block code whose coding formula is: Vector Is the information bit to be transmitted, and G N is an N-order generation matrix. Is the encoded codeword.
- FIG. 1 is a schematic diagram of encoding processing of SCL+CRC of a conventional polarization code.
- the encoder is input to the Polar code (2048, 1024) for encoding, and the encoded 2048 bits are output.
- the SCL decoder first performs SC decoding processing on the received 2048 bits, outputs L paths, and then performs CRC check on the L paths respectively, and selects to satisfy the CRC check, and the probability The largest path of the product is used as the decoded output.
- the SCL+CRC algorithm performs path splitting after performing SC decoding on the complete information bits, and has reached the set upper limit L max by finding the path or path number that can pass the CRC check.
- FIG. 2 is a flowchart of an embodiment of a method for encoding a polarization code according to the present invention
- FIG. 3 is a schematic structural diagram of an encoding device used in the method embodiment shown in FIG. 2, as shown in FIGS. 2 and 3, the coding method of this embodiment is shown in FIG. include:
- the information bits are sequentially divided into M groups of information bits according to the position in the codeword; wherein M is an integer greater than or equal to 2;
- the encoding device may include, for example, M CRC generators and a Polar encoder, and the Polar encoder is finally encoded to obtain N-bit bits including K-bit information bits and NK-bit freeze bits. Freezing bits
- the encoding device needs to add a CRC check bit to the original information bits to form.
- the encoding device may divide the original information bits into M groups according to the position order of the original information bits in the codeword, and the original information bits of each group are n 1 , n 2 , . . .
- n M bits the first group
- the Polar encoder can use the G N coset to encode the N bits. Encoding, eventually forming an N-bit codeword
- each group of information bits may be different in the M group information bits.
- each group of information bits may also be divided into M according to the position order. Information bits of equal length for each group obtained after grouping.
- the CRC check bits when the CRC check bits are respectively added to the M group information bits, the CRC check bits may be preferably added to the tails of the respective sets of information bits in the M sets of information bits.
- the encoding process of the embodiment of the present invention performs packet encoding on the original information bits to be sent, and when generating the CRC check bits of the current group information bits, it is necessary to refer to the information bits of the previous groups and the calibration.
- the bits are checked so that the information bits of each group are not isolated during the grouping process, and the correlation between the information bits is ensured.
- the first step likelihood ratio calculation.
- the likelihood ratio of each received signal y i on the channel is obtained.
- ⁇ is a parameter related to the signal-to-noise ratio of the channel.
- the second step the path splits.
- the current decoding path can be split into two, ie with For frozen bits
- the path splitting is not performed, and the number of paths is kept unchanged.
- the third step calculating the probability that each node on the path obtained by the split is 0 and is 1.
- Step 4 Determine whether the number of paths obtained by the current split exceeds the preset number of surviving paths L. If not, perform the second step and the third step, continue the path splitting and the probability calculation of each node, and if so, calculate the current The probabilistic product of each path obtained by splitting, and selecting the path with the largest L product of the probability, and continuing to perform the second and third steps based on the selected path until the path splitting process of all nodes is completed.
- L 4, All are frozen bits, no path splitting is required, and they are all known to the decoding end, so the probability of these three nodes is 1, for In other words, it is an information bit, split into two paths, which can be calculated separately using equations (2) and (3).
- Probability for In other words, it does not need path splitting for frozen bits and is known to the decoding end. Therefore, the probability of the node is 1, and the path is still 2, and does not exceed L, and can continue to split. for In other words, it is an information bit, and continues to split to get 4 paths, which can be calculated separately using equations (2) and (3). with The probability, at this time, the path is 4, does not exceed L, can continue to split.
- the four paths with the largest probability product can be selected from the eight paths, and the remaining four paths are discarded.
- the information bits Continue to split the path and still get 8 paths, which can be calculated separately using equations (2) and (3). with The probability, and the probability product of the eight paths needs to be calculated by formula (4), and then the four paths with the largest probability product are selected from the eight paths, and the remaining four paths are discarded.
- the path splitting of all nodes is completed, and L surviving paths are obtained.
- the fifth step is to select the probability product from the L surviving paths.
- the decoded result on the largest path is used as the final decoded output.
- the fifth step is to perform CRC check on the decoding results on the L surviving paths, and use the decoding result of the CRC check as the final decoding output, or When a plurality of paths pass the CRC check, the decoding result that maximizes the probability product in the path through which the CRC check passes is used as the final decoded output.
- FIG. 5 is a schematic structural diagram of a decoding apparatus for a polarization code according to the present invention.
- the decoding apparatus may include an SCL decoder, M CRC checkers, a controller, and a memory.
- the SCL decoder is configured to perform SCL decoding on the M groups of received bits respectively, and the M CRC checkers respectively correspond to the decoding results of each group in the SCL decoder, and perform CRC check on the decoding results of each group respectively.
- the controller is responsible for centralized control of the entire decoding process. When it is determined that there is a decoding result of the CRC check, the decoding result may be stored in the memory. After completing the decoding of each group, the controller may be stored according to each of the memories. Group decoding results and freezing codewords to generate the final complete translation Code results and output.
- the decoding device can know in advance which positions on the received codeword are information bits, which locations are frozen bits, and the transmission position of the CRC check bits of the encoding device can be known in advance, and the encoding device pair can also be known in advance.
- the original information bits are grouped into groups of M groups. Therefore, the decoding device may group the K received bits except the NK freeze bits among the received N bits according to the packet division manner of the encoding device, to obtain M sets of received bits, and each set of received bits includes The received bits corresponding to the original information bits and the corresponding CRC check bits. That is, as shown in FIG. 5, each set of received bits obtained by the decoding device is K 1 , K 2 , . . .
- FIG. 6 is a flowchart of a method for decoding a polarization code according to the present invention
- FIG. 7 is a schematic diagram of a process state transition of a controller in the decoding device shown in FIG. 5, which is shown in FIG. 5 to FIG.
- the decoding method may extract the received bit from the codeword, and divide the received bit into M sets of received bits according to the position in the codeword, wherein each group receives The bits all include the CRC check bits generated by the encoding device shown in FIG.
- the decoding device can perform SCL decoding processing on the M sets of received bits, wherein the m-1th group receives The bit performs the SCL decoding process of the L paths, and performs the CRC check on the decoding result of each L path together with the final decoding result of the first to m-2th received bits, respectively, if the L path is translated. If there is a path in the code result that can pass the CRC check, the SCL decoding process is started on the mth received bit; otherwise, the L is doubled, and the SCL decoding process is restarted from the first group until the L reaches the number of paths. The upper limit L max and m reaches M.
- the decoding method in this embodiment may include:
- the decoding process starts from one path splitting of the first group of received bits, and the upper limit of the number of paths can be set to L s .
- the value L s of L max can be dynamically adjusted, for example, dynamically adjusted according to the reception speed of the current information bits and/or the remaining space of the buffer before decoding of a codeword begins.
- the upper limit Lmax of the number of paths allowed in the decoding of the next codeword can be calculated according to the remaining space of the current input buffer and stored in the controller.
- D is the number of remaining spaces of the buffer
- t is the interval time of inputting channel information of adjacent codewords
- T max (2L 0 -1) KT 0 .
- L 0 is the number of path splits
- K is the number of bits to be decoded
- T 0 is the time required to split one bit. Therefore, in order to ensure that the buffer does not overflow, T max ⁇ Dt is required. So L max is the maximum that satisfies this condition:
- S604 Perform CRC check on the decoding results of the L paths, and obtain a CRC check result corresponding to the decoding result of each path.
- the decoding result of each path and the first to complete decoding are required.
- the decoding result of the received bits of the m-1 group is subjected to CRC check, and a CRC check result corresponding to the decoding result of the L paths is obtained.
- the optimal decoding result in the decoding result that is to be verified is used as a final decoding result corresponding to the mth group receiving bit.
- the decoding result of the path with the largest node probability product in the decoding result of each path is used as the final decoding result corresponding to the mth group receiving bit, and executing S607;
- the decoding process sequentially performs SCL decoding on the M sets of received bits in order from 1 to M.
- SCL decoding process for each set of received bits, reference may be made to the previously described SCL decoding process.
- the controller includes a state machine of ML max +1 states, except for the last state, each state depends on two parameters m and L, where the state (L, m) lasts for K m L clocks.
- the SCL decoder can receive bits for the first group. Decoding processing in which the number of paths L is 1 is performed. Therefore, the SCL decoding algorithm can obtain one path through path splitting, and the decoding result on the path It is sent to the CRC checker 1 for CRC check, and the CRC check result CRC#1 of the decoded result is obtained.
- the memory can feed back the final decoded result of the first set of received bits to the SCL decoder, so that the SCL decoder can finalize the first set of received bits.
- the code result is used as a reference for performing CRC check on the decoding result of the second group of received bits.
- the decoding device can perform SCL decoding on the second set of received bits.
- the SCL decoder can perform path splitting on the second group of received bits to obtain one path, and the decoding result on the path And the final decoding result of the first set of received bits Both are sent to the CRC checker 2 for CRC check, and the decoding result with the path is obtained.
- the controller can output the decoding result of the path to the memory, and the memory can store the final decoding result of the second group of received bits, and control
- the SCL decoder When decoding the third group of received bits, the SCL decoder can obtain the final decoding result of the first group of received bits and the final decoding result of the second group of received bits, so that the SCL decoder can The final decoding result of one set of received bits and the final decoded result of the second set of received bits are used as a reference for performing CRC check on the decoding result of the third set of received bits.
- the decoding device can perform SCL decoding on the third set of received bits.
- the SCL decoder can perform path splitting on the third group of received bits to obtain one path, and the decoding result on the path Final decoding result of the first set of received bits And the final decoding result of the first set of received bits Both are sent to the CRC checker 3 for CRC check, and the decoding result with the path is obtained.
- the SCL decoding process in which the number of paths L is 1 is performed, and if the decoding result of the path also passes the CRC check, the final decoding result of all the information bits can be obtained.
- the controller can therefore control the SCL decoder to re-receive the first set of bits Perform path splitting to get 2 paths, and the decoding results of these 2 paths Both are sent to the CRC checker 1 for CRC check, and the CRC check results of the decoding results of the two paths are respectively obtained, and the two CRC check results are sent to the controller to determine whether the check is passed or not. check.
- the controller may perform the optimal decoding result in the decoding result that passes the check. Output to the memory, the memory can store the final decoded result of the first set of received bits. It should be noted that if the decoding result of only one path passes the check, the decoding result of the path is the optimal decoding result. If the decoding results of the two paths pass the verification, the controller may From the decoding results of the two paths, the decoding result with the highest probability product of each node is selected as the optimal decoding result.
- the controller can therefore control the SCL decoder to re-receive the first set of bits Perform path splitting to get 4 paths, and the decoding results of these 4 paths Both are sent to the CRC checker 1 for CRC check, and the CRC check results of the decoding results of the four paths are respectively obtained, and the subsequent processing is similar to the processing of the above two paths, and so on.
- the SCL decoding process is resumed from the first group of received bits.
- L max may be a predetermined value, based on the system requirements for complexity and performance requirements, the threshold survivor paths provided, in general, when L ⁇ L max, can be found Verify the optimal path passed.
- the present embodiment can select the decoding result with the highest probability product of each node from the L max split path to output to the memory.
- FIG. 8 is a schematic diagram of a comparison between a decoding process and an existing SCL decoding process according to an embodiment of the present invention, as shown in FIG. 8 , wherein a thick line characterizes a decoding process in the decoding process of the embodiment of the present invention.
- Existing SCL decoding process It can be seen from the process shown in FIG. 8 that the embodiment of the present invention performs segmentation coding on the information bits to be transmitted at the encoding end, and performs segmentation decoding on the received information bits at the decoding end, and in the SCL decoding process.
- the decoding time is significantly reduced, the decoding speed is fast, the delay is low, and the decoding speed of 2-M times can be improved.
- the information bits of the first to m-1 groups are all introduced together for CRC calculation, thereby ensuring the information bits of each group in the segment coding.
- the CRC check bit is generated by the decoding end for the m-th group decoding result
- the decoded results of the first to m-1 groups that have been decoded are also introduced into the CRC calculation to ensure the decoding result. Relevance and accuracy.
- the embodiment of the present invention can also dynamically adjust the path number upper limit L max , avoiding idle or waste of the decoding device, and reasonably allocating system resources; further, the decoding capability of the embodiment of the present invention and the traditional SCL+CRC decoder Quite, the decoding ability is not lossless.
- FIG. 9 is a schematic structural diagram of an embodiment of an encoding device according to the present invention. As shown in FIG. 9, the encoding device of this embodiment may include:
- a grouping module 91 configured to divide the information bits into M groups of information bits according to the position in the codeword, where M is an integer greater than or equal to 2;
- the encoding processing module 92 is configured to add a cyclic redundancy check code CRC check bit to the M group information bits to obtain information bits to be transmitted, wherein the CRC check bits attached to the first group information bits are according to the first group.
- the information bits are generated, and the CRC check bits added by the mth information bits are generated according to the first group information bits to the m-1th information bits and the mth information bits to which the CRC check bits are added, 2 ⁇ m ⁇ M;
- the code sending module 93 is configured to perform polarization coding on the information bits to be sent and the frozen bits to obtain a codeword and send the codeword.
- the grouping module 91 is specifically configured to divide the information bits into M groups according to the position order in the codeword to obtain M groups of information bits.
- the present invention also provides an implementation of a hardware structure of an encoding device, as shown in FIG. 3, which includes: a packetizer, M CRC generators, and an encoder; wherein, the input of the packetizer and the M CRC generators Connecting, the output of the mth CRC generator is connected to the encoder and the input of the m+1th to the Mth CRC generator, and the output of the Mth CRC generator is connected to the encoder, where M is An integer greater than or equal to 2;
- a packetizer configured to divide information bits into M groups of information bits according to a position in the codeword
- M CRC generators for respectively adding a cyclic redundancy check code CRC check bit to the M group information bits to obtain information bits to be transmitted, wherein the CRC check bits attached to the first group information bits are according to the first
- the CRC check bit added by the mth information bit is generated according to the first group information bit to the m-1th information bit and the mth information bit to which the CRC check bit is added, 2 ⁇ m ⁇ M;
- an encoder configured to perform polarization coding on the information bits to be sent and the frozen bits to obtain a codeword and send the same.
- the coding device of this embodiment may be used to perform the operations performed by the foregoing coding end, and the principle and technical effects thereof are similar, and details are not described herein again.
- FIG. 10 is a schematic structural diagram of an embodiment of a decoding device according to the present invention. As shown in FIG. 10, the decoding device in this embodiment may include:
- a grouping module 10 configured to receive a codeword, where the codeword includes a received bit and a frozen bit; extract a received bit from the codeword, and divide the received bit into M group receiving according to a position in a codeword a bit, wherein each group of received bits includes a cyclic redundancy check code CRC check bit, and M is an integer greater than or equal to 2;
- the decoding processing module 11 is configured to perform SCL decoding processing on the M sets of received bits, and combine and output the final decoding result corresponding to the M sets of received bits, and the frozen bit is included; wherein the decoding process includes: Performing SCL decoding processing on the L-th path of the m-1th received bit, and performing CRC check on the decoding result of each L-path together with the final decoding result of the first to m-th set of received bits, respectively If there is a path capable of passing the CRC check in the decoding result of the L paths, the SCL decoding process is started on the mth received bit; otherwise, the L is doubled, and the SCL decoding is resumed from the first group. Processing until L reaches the upper limit of the path number L max and m reaches M.
- the decoding processing module 11 is specifically configured to:
- the optimal decoding result in the decoding result that is to be verified is used as a final decoding result corresponding to the mth group receiving bit.
- the decoding result of the path with the largest node probability product in the decoding result of each path is used as the final decoding result corresponding to the mth group receiving bit, and executing S607;
- the present invention further provides a hardware structure implementation of a decoding device, as shown in FIG. 5, the decoding device may include: a packetizer, an SCL decoder, M CRC checkers, a controller, and a memory; wherein the packetizer is coupled to the SCL decoder, the mth output of the SCL decoder is coupled to the m+1th to Mth CRC checkers, the memory and controller, and the SCL decoder, the controller M CRC checkers are connected to the SCL decoder, where M is an integer greater than or equal to 2;
- a packetizer for receiving a codeword, the codeword comprising a received bit and a frozen bit; extracting a received bit from the codeword, and dividing the received bit into M sets of received bits according to a position in a codeword , wherein each group of received bits includes a CRC check bit;
- An SCL decoder configured to perform SCL decoding processing on the M groups of received bits, and send the decoding processing result to the CRC checker for CRC check;
- a controller configured to determine a final decoding result of each group of received bits according to the verification result, and store the final decoding result into the memory, and receive the M group after obtaining the decoding result of all the received bits The final decoding result corresponding to the bit is combined with the frozen bit and output;
- a memory for storing a final decoding result of each group of received bits determined by the controller, and feeding back a final decoding result of each group of received bits to the SCL checker;
- the SCL decoding process and the CRC check process include: performing SCL decoding processing on the L-th path of the m-1th received bit, and decoding the result of each L path with the first to the first The final decoding result of the received bits of the m-2 group is performed together with the CRC check. If there is a path that can pass the CRC check in the decoding result of the L paths, the SCL decoding process is started on the mth received bit; otherwise The L is doubled, and the SCL decoding process is restarted from the first group until L reaches the upper limit of the path number L max and m reaches M.
- the foregoing SCL decoding process and the CRC check process specifically include:
- the optimal decoding result in the decoding result that is to be verified is used as a final decoding result corresponding to the mth group receiving bit.
- the decoding result of the path with the largest node probability product in the decoding result of each path is used as the final decoding result corresponding to the mth group receiving bit, and executing S607;
- the decoding device of this embodiment may be used to perform the operations performed by the above-mentioned decoding end, and the principle and technical effects thereof are similar, and details are not described herein again.
- the foregoing program may be stored in a computer readable storage medium, and when executed, the program includes the steps of the foregoing method embodiment; and the foregoing storage medium includes: ROM, RAM A variety of media that can store program code, such as a disk or a disc.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Error Detection And Correction (AREA)
Abstract
本发明实施例提供一种极化码的编译码方法及其装置。极化码的译码方法,包括:接收码字,所述码字包含接收比特和冻结比特;从所述码字中提取接收比特,并对所述接收比特按照在码字中的位置顺序划分成M组接收比特,其中,各组接收比特均包含循环冗余校验码CRC校验比特,M为大于等于2的整数;对所述M组接收比特进行SCL译码处理,并将M组接收比特对应的最终译码结果与冻结比特进行组合并输出;其中,所述译码处理包括:对第m-1组接收比特进行L条路径的SCL译码处理,并对各L条路径的译码结果分别与第1至第m-2组接收比特的最终译码结果一同进行CRC校验,若L条路径的译码结果中存在能够通过CRC校验的路径,则开始对第m组接收比特进行SCL译码处理;否则对L翻倍,并从第1组开始重新进行SCL译码处理,直到L达到路径数上限Lmax且m达到M。
Description
本发明涉及通信技术,尤其涉及一种极化码的编译码方法及其装置。
前向纠错(Forward Error Correction,以下简称:FEC)技术是通信系统的一个关键技术,可以通过牺牲一定的传输带宽来大幅提升系统性能。
极化码(以下简称:Polar码)是FEC技术的一种,是由Erdal Arikan于2007年提出的一种信道编码方法,在二进制离散无记忆信道(Binary Discrete Memoryless Channel,以下简称:BDMC)下,这种编码方法理论上可以达到香农极限,并且具有较低的编译码复杂度。连续删除(Successive Cancellation,以下简称:SC)译码算法是针对于Polar码最常见的译码算法。但针对中长码,SC译码性能并不理想。为解决这一问题,现有技术在SC译码算法基础上,提出了序列连续删除(SC List,以下简称:SCL)+循环冗余校验码(Cyclic Redundancy Check,以下简称:CRC)译码算法。SCL+CRC算法是在每一次的SC译码之后,进行路径分裂,允许有Lmax条译码结果路径,从这Lmax条译码结果路径中选出能够通过CRC校验且概率乘积最大的一条路径上的译码结果作为译码输出,从而显著提高译码准确度。
但是,现有的SCL+CRC译码算法,其译码速度慢,延时大,无法满足高效的处理需求。
发明内容
本发明实施例提供一种极化码的编译码方法及其装置,以提高译码速度。
第一方面,本发明实施例提供一种极化码的编码方法,包括:
将信息比特按照在码字中的位置顺序划分成M组信息比特,其中M为大于等于2的整数;
对M组信息比特分别附加循环冗余校验码CRC校验比特,得到待发送信息比特,其中,第1组信息比特所附加的CRC校验比特是根据第1组信息
比特生成的,第m组信息比特所附加的CRC校验比特是根据附加有CRC校验比特的第1组信息比特至第m-1组信息比特以及第m组信息比特生成的,2≤m≤M;
对所述待发送信息比特和冻结比特进行极化编码,得到码字并发送。
可选的,所述将信息比特按照在码字中的位置顺序划分成M组信息比特,包括:
将信息比特按照在码字中的位置顺序等分成M组,得到M组信息比特。
可选的,所述对M组信息比特分别附加循环冗余校验码CRC校验比特,包括:
将所述CRC校验比特分别附加在M组信息比特中各组信息比特的尾部。
第二方面,本发明实施例提供一种极化码的译码方法,包括:
接收码字,所述码字包含接收比特和冻结比特;
从所述码字中提取接收比特,并对所述接收比特按照在码字中的位置顺序划分成M组接收比特,其中,各组接收比特均包含循环冗余校验码CRC校验比特,M为大于等于2的整数;
对所述M组接收比特进行SCL译码处理,并将M组接收比特对应的最终译码结果与冻结比特进行组合并输出;其中,所述译码处理包括:对第m-1组接收比特进行L条路径的SCL译码处理,并对各L条路径的译码结果分别与第1至第m-2组接收比特的最终译码结果一同进行CRC校验,若L条路径的译码结果中存在能够通过CRC校验的路径,则开始对第m组接收比特进行SCL译码处理;否则对L翻倍,并从第1组开始重新进行SCL译码处理,直到L达到路径数上限Lmax且m达到M。
可选的,所述对所述M组接收比特进行SCL译码处理,并将M组接收比特对应的最终译码结果与冻结比特进行组合并输出,包括:
S601、初始化处理,其中,L=1,Lmax=Ls;
S602、令m=1;
S603、对第m组接收比特进行SCL译码,得到L条路径的译码结果;
S604、对L条路径的译码结果分别进行CRC校验,得到与各条路径的译码结果对应的CRC校验结果,其中,对第m组接收比特的L条路径的译码结果进行CRC校验时,将各条路径的译码结果与已经完成译码的
第1~m-1组接收比特的译码结果一起进行CRC校验,得到与L条路径的译码结果分别对应的CRC校验结果;
S605、根据各CRC校验结果,判断各条路径的译码结果中是否存在至少一条路径的译码结果通过校验;若是,则执行S606,否则执行S610;
S606、将通过校验的译码结果中最优的译码结果作为第m组接收比特对应的最终译码结果;
S607、判断m是否等于M,若是,则执行S609,否则执行S608;
S608、令m=m+1,并执行S603;
S609、将M组接收比特对应的最终译码结果与冻结比特进行组合并输出;
S610、判断L是否等于Lmax,若是,则执行S611,否则执行S612;
S611、将各条路径的译码结果中节点概率乘积最大的路径的译码结果作为第m组接收比特对应的最终译码结果,并执行S607;
S612、令L=2L,并执行S602。
可选的,所述对所述M组接收比特进行SCL译码处理之前,还包括:
根据当前信息比特的接收速度和/或接收缓冲器的剩余空间,对所述Lmax进行调整。
第三方面,本发明实施例提供一种编码设备,包括:
分组模块,用于将信息比特按照在码字中的位置顺序划分成M组信息比特,其中M为大于等于2的整数;
编码处理模块,用于对M组信息比特分别附加循环冗余校验码CRC校验比特,得到待发送信息比特,其中,第1组信息比特所附加的CRC校验比特是根据第1组信息比特生成的,第m组信息比特所附加的CRC校验比特是根据附加有CRC校验比特的第1组信息比特至第m-1组信息比特以及第m组信息比特生成的,2≤m≤M;
编码发送模块,用于对所述待发送信息比特和冻结比特进行极化编码,得到码字并发送。
可选的,所述分组模块,具体用于将信息比特按照在码字中的位置顺序等分成M组,得到M组信息比特。
第四方面,本发明实施例提供一种编码设备,包括:分组器、M个CRC
生成器以及编码器;其中,分组器与所述M个CRC生成器的输入端连接,第m个CRC生成器的输出端与所述编码器和第m+1至第M个CRC生成器的输入端连接,第M个CRC生成器的输出端与所述编码器连接,其中M为大于等于2的整数;
所述分组器,用于将信息比特按照在码字中的位置顺序划分成M组信息比特;
所述M个CRC生成器,用于对M组信息比特分别附加循环冗余校验码CRC校验比特,得到待发送信息比特,其中,第1组信息比特所附加的CRC校验比特是根据第1组信息比特生成的,第m组信息比特所附加的CRC校验比特是根据附加有CRC校验比特的第1组信息比特至第m-1组信息比特以及第m组信息比特生成的,2≤m≤M;
所述编码器,用于对所述待发送信息比特和冻结比特进行极化编码,得到码字并发送。
第五方面,本发明实施例提供一种译码设备,包括:
分组模块,用于接收码字,所述码字包含接收比特和冻结比特;从所述码字中提取接收比特,并对所述接收比特按照在码字中的位置顺序划分成M组接收比特,其中,各组接收比特均包含循环冗余校验码CRC校验比特,M为大于等于2的整数;
译码处理模块,用于对所述M组接收比特进行SCL译码处理,并将M组接收比特对应的最终译码结果与冻结比特进行组合并输出;其中,所述译码处理包括:对第m-1组接收比特进行L条路径的SCL译码处理,并对各L条路径的译码结果分别与第1至第m-2组接收比特的最终译码结果一同进行CRC校验,若L条路径的译码结果中存在能够通过CRC校验的路径,则开始对第m组接收比特进行SCL译码处理;否则对L翻倍,并从第1组开始重新进行SCL译码处理,直到L达到路径数上限Lmax且m达到M。
可选的,所述译码处理模块,具体用于:
S601、初始化处理,其中,L=1,Lmax=Ls;
S602、令m=1;
S603、对第m组接收比特进行SCL译码,得到L条路径的译码结果;
S604、对L条路径的译码结果分别进行CRC校验,得到与各条路径
的译码结果对应的CRC校验结果,其中,对第m组接收比特的L条路径的译码结果进行CRC校验时,将各条路径的译码结果与已经完成译码的第1~m-1组接收比特的译码结果一起进行CRC校验,得到与L条路径的译码结果分别对应的CRC校验结果;
S605、根据各CRC校验结果,判断各条路径的译码结果中是否存在至少一条路径的译码结果通过校验;若是,则执行S606,否则执行S610;
S606、将通过校验的译码结果中最优的译码结果作为第m组接收比特对应的最终译码结果;
S607、判断m是否等于M,若是,则执行S609,否则执行S608;
S608、令m=m+1,并执行S603;
S609、将M组接收比特对应的最终译码结果与冻结比特进行组合并输出;
S610、判断L是否等于Lmax,若是,则执行S611,否则执行S612;
S611、将各条路径的译码结果中节点概率乘积最大的路径的译码结果作为第m组接收比特对应的最终译码结果,并执行S607;
S612、令L=2L,并执行S602。
第六方面,本发明实施例提供一种译码设备,包括:分组器、SCL译码器、M个CRC校验器、控制器以及存储器;其中,所述分组器与所述SCL译码器连接,所述SCL译码器的第m路输出与第m+1至第M个CRC校验器连接,所述存储器与所述控制器和所述SCL译码器,所述控制器与所述M个CRC校验器和所述SCL译码器连接,其中M为大于等于2的整数;
所述分组器,用于接收码字,所述码字包含接收比特和冻结比特;从所述码字中提取接收比特,并对所述接收比特按照在码字中的位置顺序划分成M组接收比特,其中,各组接收比特均包含CRC校验比特;
所述SCL译码器,用于对所述M组接收比特分别进行SCL译码处理,并将译码处理结果对应发送给CRC校验器进行CRC校验;
所述M个CRC校验器,用于分别对所述M组接收比特的译码结果进行CRC校验得到校验结果;
所述控制器,用于根据所述校验结果确定各组接收比特的最终译码结果,并将最终译码结果存储到所述存储器中,并且在得到全部接收比特的译码结
果之后将M组接收比特对应的最终译码结果与冻结比特进行组合并输出;
所述存储器,用于存储控制器确定的各组接收比特的最终译码结果,并将各组接收比特的最终译码结果反馈给所述SCL校验器;
其中,所述SCL译码处理和所述CRC校验处理,包括:对第m-1组接收比特进行L条路径的SCL译码处理,并对各L条路径的译码结果分别与第1至第m-2组接收比特的最终译码结果一同进行CRC校验,若L条路径的译码结果中存在能够通过CRC校验的路径,则开始对第m组接收比特进行SCL译码处理;否则对L翻倍,并从第1组开始重新进行SCL译码处理,直到L达到路径数上限Lmax且m达到M。
可选的,所述SCL译码处理和所述CRC校验处理,具体包括:
S601、初始化处理,其中,L=1,Lmax=Ls;
S602、令m=1;
S603、对第m组接收比特进行SCL译码,得到L条路径的译码结果;
S604、对L条路径的译码结果分别进行CRC校验,得到与各条路径的译码结果对应的CRC校验结果,其中,对第m组接收比特的L条路径的译码结果进行CRC校验时,将各条路径的译码结果与已经完成译码的第1~m-1组接收比特的译码结果一起进行CRC校验,得到与L条路径的译码结果分别对应的CRC校验结果;
S605、根据各CRC校验结果,判断各条路径的译码结果中是否存在至少一条路径的译码结果通过校验;若是,则执行S606,否则执行S610;
S606、将通过校验的译码结果中最优的译码结果作为第m组接收比特对应的最终译码结果;
S607、判断m是否等于M,若是,则执行S609,否则执行S608;
S608、令m=m+1,并执行S603;
S609、将M组接收比特对应的最终译码结果与冻结比特进行组合并输出;
S610、判断L是否等于Lmax,若是,则执行S611,否则执行S612;
S611、将各条路径的译码结果中节点概率乘积最大的路径的译码结果作为第m组接收比特对应的最终译码结果,并执行S607;
S612、令L=2L,并执行S602。
本发明实施例通过在编码端对待发送的信息比特进行分段编码,在译码端对接收到的信息比特进行分段译码,且在SCL译码过程中,分裂路径自适应调整,相对于现有技术来说,其译码时间显著减小,译码速度快,延时低,可以提高2-M倍的译码速度。而且,本发明实施例在编码端对第m组信息比特生成CRC校验比特时,将第1~m-1组信息比特均引入一同进行CRC计算,保证了分段编码中各组信息比特的关联性,在译码端对第m组译码结果生成CRC校验比特时,同样将已经译码得到的第1~m-1组译码结果均引入一同进行CRC计算,保证了译码结果的关联性和准确性。另外,本发明实施例还可以动态调整路径数量上限Lmax,避免了译码设备闲置或浪费,合理分配系统资源;此外,本发明实施例的译码能力与传统的SCL+CRC器译码器相当,译码能力无损。
图1为现有极化码的SCL+CRC的编码处理示意图;
图2为本发明极化码的编码方法实施例的流程图;
图3为图2所示方法实施例所采用的编码设备的结构示意图;
图4为N=8的Polar码路径分裂过程的示意图;
图5为本发明中极化码的译码设备的结构示意图;
图6为本发明极化码的译码方法实施例的流程图;
图7为图5所示译码设备中控制器的处理状态迁移示意图;
图8为本发明实施例的译码处理过程和现有SCL译码处理过程的对比示意图;
图9为本发明编码设备实施例的结构示意图;
图10为本发明译码设备实施例的结构示意图。
本发明实施例针对Polar码的编译码处理。Polar码是基于信道极化理论完成的,将信道极化以后,一部分信道趋于无噪信道,另外一部分信道趋于全噪信道。基于这个现象,Polar码在进行编码时,可以将要传送的信息比特放在无噪信道上传输,而在全噪信道上传输冻结比特。因此,当码长N趋于
无穷大时,系统容量可以达到香农极限。
Polar码的编码又称为GN陪集编码。Polar码的码字长度N被严格定义为2的幂次方,即对于任意n≥0都有N=2n。Polar码是线性分组码,其编码公式为:式中,向量是所需传送的信息比特,GN是N阶次的生成矩阵,是编码后的码字。
图1为现有极化码的SCL+CRC的编码处理示意图,如图1所示,以Polar码长2048,码率R=0.5为例,其信息比特为1024bits,经过16bits的CRC校验编码以后,与1008bits的冻结比特一起,输到Polar码(2048,1024)编码器进行编码,输出编码后的2048比特。在译码端,SCL译码器首先会对接收到的这2048个比特进行SC译码处理,输出L条路径,然后分别对这L条路径进行CRC校验,选满足CRC校验,且概率积最大的路径做为译码输出。
由图1可以看出,SCL+CRC算法是在对完整的信息比特进行一次SC译码之后,进行路径分裂,并在已经找到能够通过CRC校验的路径或者路径数达到所设定上限Lmax时结束译码,也即允许有Lmax条路径进行后续的操作,从中选出能够通过CRC校验,并且概率乘积最大的一条路径,作为译码输出。因此,对于一次SC译码来说,该算法需要基于全部信息比特进行路径分裂并判断各路径中是否存在通过CRC校验的路径,若不存在,则需要增大输出的路径数L,再进行一次SC译码过程,直到路径数量L达到最大值Lmax。该过程处理复杂,耗时较长。
图2为本发明极化码的编码方法实施例的流程图,图3为图2所示方法实施例所采用的编码设备的结构示意图,如图2和3所示,本实施例的编码方法包括:
S201、将信息比特按照在码字中的位置顺序划分成M组信息比特;其中M为大于等于2的整数;
S202、对M组信息比特分别附加循环冗余校验码CRC校验比特,得到待发送信息比特,其中,第1组信息比特所附加的CRC校验比特是根据第1组信息比特生成的,第m组信息比特所附加的CRC校验比特是根据附加有CRC校验比特的第1组信息比特至第m-1组信息比特以及第m组信息比特生成的,2≤m≤M;
S203、对所述待发送信息比特和冻结比特进行极化编码,得到码字并发
送。
结合图3具体来说,编码设备例如可以包括M个CRC生成器和一个Polar编码器,Polar编码器最终要编码得到N位比特,其中包含K位信息比特和N-K位冻结比特。冻结比特对于译码端来说,其发送内容以及在码字中的位置均是已知的。针对K位信息比特来说,编码设备需要对原始信息比特附加CRC校验比特来形成。具体来说,编码设备可以按照原始信息比特在码字中的位置顺序将原始信息比特划分成M组,每一组的原始信息比特为n1,n2,…,nM位,第一组原始信息比特为经过CRC生成器1校验以后变成第二组原始信息比特为第二组原始信息比特与第一组的CRC校验输出共同作为CRC生成器2的输入,CRC校验后的比特为以此类推,第m组(1≤m≤M)包含nm个原始信息比特和rm个校验比特,其末位比特的位置为km,所以kM=K。
由上述过程可知,第m组的校验比特为:
基于所需生成的校验比特位数,本领域技术人员可以对M个CRC生成器进行设计,此处不再赘述。
需要说明的是,在上述编码过程中,M组信息比特中,各组信息比特的长度可以是不相同的,优选的,各组信息比特的也可以是将全部信息比特按照位置顺序等分成M组后得到的各组等长的信息比特。
另外,在对M组信息比特分别附加CRC校验比特时,可以优选地将CRC校验比特分别附加在M组信息比特中各组信息比特的尾部。
由上述编码过程可知,本发明实施例的编码过程是对待发送的原始信息比特进行分组编码,并且,在生成当前组信息比特的CRC校验比特时,需要参考其之前各组的信息比特以及校验比特,从而在分组的过程中,不会对各组的信息比特进行隔离,保证了信息比特之间的相关性。
下面详细介绍,在上述编码过程的基础上,译码端的具体译码过程。在对该译码过程进行说明之前,首先对SCL译码算法进行说明。发送信号在
经过信道传输后,译码端从信道上接收的信号为针对该可以进行如下译码处理过程:
第一步:似然比计算。
第二步:路径分裂。
在具体的分裂过程中,可以预先设定幸存路径条数L的值。例如,对图4所给出的4位信息比特的Polar码路径分裂来说,最多可分裂得到24=16条路径,路径分裂到时,将得到4条分裂路径;路径分裂到时,将得到8条路径;路径分裂到时,将得到16条路径。
第三步:计算分裂得到的路径上各节点为0和为1的概率。
该节点为0和为1的概率分别采用下述公式(2)和公式(3)计算得到:
第四步:确定当前分裂得到的路径数是否超过预设幸存路径数L,若未超过,则执行第二步和第三步,继续进行路径分裂和各节点概率计算,若超过,则计算当前分裂得到的各路径的概率乘积,并从中选择L条概率乘积最大的路径,并基于所选择的路径继续执行第二步和第三步,直到完成全部节点的路径分裂过程。
以L=4举例来说,均为冻结比特,无需路径分裂且对于译码端来
说其均为已知,因此这3个节点的概率均为1,对于来说,其为信息比特,分裂成2条路径,可以采用公式(2)和(3)分别计算和的概率,对于来说,其为冻结比特无需路径分裂且对于译码端来说其均为已知,因此该节点的概率为1,且路径依然为2条,未超过L,可以继续分裂。对于来说,其为信息比特,继续分裂得到4条路径,可以采用公式(2)和(3)分别计算和的概率,此时路径为4条,未超过L,可以继续分裂。对来说,其为信息比特,继续分裂得到8条路径,可以采用公式(2)和(3)分别计算和的概率,而且,因为此时的路径数超过了L,需要通过计算这8条路径的概率乘积。概率乘积具体可以采用公式(4)计算得到:
其中,b∈{0,1}。
然后,可以从这8条路径中选择出概率乘积最大的4条路径,并丢弃剩余的4条路径。在所选择的这4条路径的基础上,对信息比特继续进行路径分裂,依然得到8条路径,可以采用公式(2)和(3)分别计算和的概率,并且需要采用公式(4)计算这8条路径的概率乘积,进而从这8条路径中选择出概率乘积最大的4条路径,并丢弃剩余的4条路径。至此,即完成了全部节点的路径分裂,并且得到了L条幸存路径。
而对于SCL+CRC译码算法来说,第五步是对L条幸存路径上的译码结果均进行CRC校验,将CRC校验通过的译码结果作为最终的译码输出,或者在有多条路径均通过CRC校验时,将CRC校验通过的路径中概率乘积最大的译码结果作为最终的译码输出。
图5为本发明中极化码的译码设备的结构示意图,如图5所示,该译码设备可以包括SCL译码器、M个CRC校验器、控制器以及存储器。其中,SCL译码器用于对M组接收比特分别进行SCL译码,M个CRC校验器分别与SCL译码器中各组译码结果对应,对各组的译码结果分别进行CRC校验,控制器负责整个译码过程的集中控制,在确定存在CRC校验通过的译码结果时,可以将该译码结果存入存储器,在完成各组译码之后,可以根据存储器中存储的各组译码结果以及冻结码字,生成最终的完整译
码结果并进行输出。
译码设备可以预先获知接收的码字上哪些位置传输的是信息比特,哪些位置传输的是冻结比特,也可以预先获知编码设备的CRC校验比特的传输位置,而且还可以预先获知编码设备对原始信息比特进行M组的分组划分方式。因此,译码设备可以按照编码设备的分组划分方式,对接收到的N个比特位中除N-K个冻结比特之外的K个接收比特进行分组,得到M组接收比特,每组接收比特中包含原始信息比特对应的接收比特以及相应的CRC校验比特。即如图5中所示,译码设备划分得到的每一组接收比特为K1,K2,…,KM位,第1组接收比特为经过SCL译码以后变成第2组接收比特为经过SCL译码以后变成以此类推,第m组接收比特为经过SCL译码以后变成第M组接收比特为经过SCL译码以后变成其中Km为第m组包含的比特数,K1=k1,Km=km-km-1。
图6为本发明极化码的译码方法实施例的流程图,图7为图5所示译码设备中控制器的处理状态迁移示意图,结合图5~图7所示,本实施例的译码方法在接收到包含接收比特和冻结比特的码字后,可以从码字中提取接收比特,并对接收比特按照在码字中的位置顺序划分成M组接收比特,其中,各组接收比特均包含图2所示编码设备所生成的CRC校验比特,M为大于等于2的整数;然后译码设备可以对M组接收比特进行SCL译码处理,其中,对第m-1组接收比特进行L条路径的SCL译码处理,并对各L条路径的译码结果分别与第1至第m-2组接收比特的最终译码结果一同进行CRC校验,若L条路径的译码结果中存在能够通过CRC校验的路径,则开始对第m组接收比特进行SCL译码处理;否则对L翻倍,并从第1组开始重新进行SCL译码处理,直到L达到路径数上限Lmax且m达到M。
具体的,本实施例的译码方法可以包括:
S601、初始化处理,其中,L=1,Lmax=Ls。
S602、令m=1。
具体来说,译码处理过程均是从对第1组接收比特进行1条路径分裂开始的,路径数上限可以设定为Ls。
优选的,Lmax的取值Ls可以动态地调整,例如在对一个码字译码开始前,可以根据当前信息比特的接收速度和/或缓冲器的剩余空间动态地调整。在一个码字译码结束,下一个码字译码开始之前,根据当前输入缓冲器的剩余空间可以计算出下一个码字译码时所允许的路径数上限Lmax,并存入控制器。假设D为缓冲器剩余空间数,t为相邻码字信道信息输入的间隔时间,那么所允许的路径数上限Lmax应满足条件使译码过程中缓冲器不会溢出。根据前面的译码过程分析,译码过程理论上可能占用的最长时间与传统自适应SCL相同,即Tmax=(2L0-1)KT0。其中,L0为路径分裂个数,K为待译码的比特数,T0为分裂一个比特所需的时间。因此,为了保证缓冲器不会溢出,要求Tmax<Dt。所以Lmax为满足该条件的最大值即:
S603、对第m组接收比特进行SCL译码,得到L条路径的译码结果。
S604、对L条路径的译码结果分别进行CRC校验,得到与各条路径的译码结果对应的CRC校验结果。
其中,与图2所示编码过程对应的,对第m组接收比特的L条路径的译码结果进行CRC校验时,需要将各条路径的译码结果与已经完成译码的第1~m-1组接收比特的译码结果一起进行CRC校验,得到与L条路径的译码结果分别对应的CRC校验结果。
S605、根据各CRC校验结果,判断各条路径的译码结果中是否存在至少一条路径的译码结果通过校验;若是,则执行S606,否则执行S610;
S606、将通过校验的译码结果中最优的译码结果作为第m组接收比特对应的最终译码结果;
S607、判断m是否等于M,若是,则执行S609,否则执行S608。
S608、令m=m+1,并执行S603。
S609、将M组接收比特对应的最终译码结果与冻结比特进行组合并输出。
S610、判断L是否等于Lmax,若是,则执行S611,否则执行S612;
S611、将各条路径的译码结果中节点概率乘积最大的路径的译码结果作为第m组接收比特对应的最终译码结果,并执行S607;
S612、令L=2L,并执行S602。
结合图5和图7具体来说,译码过程是对M组接收比特按照从1至M的顺序依次进行SCL译码。对于每组接收比特的SCL译码过程,其可以参考前述已说明的SCL译码过程。
控制器包括MLmax+1个状态的状态机,除了最后一个状态外,每个状态取决于两个参数m和L,其中状态(L,m)持续KmL个时钟。
从(L=1,m=1)这一初始状态开始,SCL译码器可以对第1组接收比特进行路径数L为1的译码处理,因此,SCL译码算法可以经过路径分裂得到1条路径,该条路径上的译码结果被送入CRC校验器1进行CRC校验,得到该译码结果的CRC校验结果CRC#1,该CRC校验结果CRC#1被送入控制器中判决是通过校验还是没通过校验,例如CRC#1=1则表征通过校验,CRC#1=0则表征未通过校验。
若CRC#1=1校验通过,则控制器可以将该路径的译码结果输出给存储器,存储器即可存储该第1组接收比特的最终译码结果。在此基础上,控制器可以将状态迁移至(L=1,m=2),即开始对第2组接收比特进行SCL译码处理。在对第2组接收比特进行译码处理时,存储器可以将第1组接收比特的最终译码结果再反馈给SCL译码器,从而使得SCL译码器可以将第1组接收比特的最终译码结果作为对第2组接收比特的译码结果进行CRC校验时的参考。具体来说,译码设备可以对第2组接收比特进行SCL译码。也即SCL译码器可以对第2组接收比特进行路径分裂得到1条路径,该条路径上的译码结果以及第1组接收比特的最终译码结果均被送入CRC校验器2进行CRC校验,得到与该路径的译码结果对应的CRC校验结果CRC#2,该CRC校验结果CRC#2被送入控制器中判决是通过校验还是没通过校验,例如CRC#2=1则表征通过校验,CRC#2=0则表征未通过校验。若第2组接收比特进行路径数L为1的SCL译码处理也通过了CRC校验,则控制器可以将该路径的译码结果输出给存储器,存储器即可存储该第2组接收比特的最终译码结果,控制器可以将状态迁移至(L=1,m=3),即开始对第3组接收比特进行SCL译码处理。在对第3组接收比特进行译码处理时,SCL译码器可以获得第1组接收比特的最终译码结果和第2组接收比特的最终译码结果,从而使得SCL译码器可以将第1组接收比特的最
终译码结果和第2组接收比特的最终译码结果作为对第3组接收比特的译码结果进行CRC校验时的参考。具体来说,译码设备可以对第3组接收比特进行SCL译码。也即SCL译码器可以对第3组接收比特进行路径分裂得到1条路径,该条路径上的译码结果第1组接收比特的最终译码结果以及第1组接收比特的最终译码结果均被送入CRC校验器3进行CRC校验,得到与该路径的译码结果对应的CRC校验结果CRC#3,该CRC校验结果CRC#3被送入控制器中判决是通过校验还是没通过校验,例如CRC#3=1则表征通过校验,CRC#3=0则表征未通过校验,依次类推。最快的处理过程是,在L=1的情况下,控制器可以一直将状态迁移至(L=1,m=M),即开始对第M组接收比特进行路径数L为1的SCL译码处理,若该路径的译码结果也通过了CRC校验,则可以得到全部信息比特的最终译码结果。
若CRC#1=0校验不通过,且此时路径数L未达到路径数上限Lmax,则控制器可以将路径数L翻倍,即调整为L=2,此时控制器的状态迁移至(L=2,m=1)。控制器因此可以控制SCL译码器重新对第1组接收比特进行路径分裂,得到2条路径,这2条路径的译码结果均被送入CRC校验器1进行CRC校验,分别得到2条路径的译码结果的CRC校验结果,该2个CRC校验结果被送入控制器中判决是通过校验还是没通过校验。
针对状态(L=2,m=1),若2条路径中有至少1条路径的译码结果校验通过,则控制器可以将该校验通过的译码结果中的最优译码结果输出给存储器,存储器即可存储该第1组接收比特的最终译码结果。需要说明的是,若只有1条路径的译码结果通过校验,则该条路径的译码结果就是最优译码结果,若2条路径的译码结果均通过校验,则控制器可以从这2条路径的译码结果中选出各节点概率乘积最高的译码结果作为最优译码结果。之后,控制器的状态即可迁移至(L=2,m=2),从而可以对第2组接收比特进行路径数为2的SCL译码处理。在得到2条路径上的译码结果之后,这2条路径上的译码结果可以分别与第1组接收比特的最终译码结果一同被送入CRC校验器2进行CRC校验,得
到与2条路径的译码结果分别对应的CRC校验结果CRC#2,该2条路径的CRC校验结果CRC#2被送入控制器中判决是通过校验还是没通过校验,例如CRC#2=1则表征通过校验,CRC#2=0则表征未通过校验。若第2组接收比特进行路径数L为2的译码结果中至少有1条路径的译码结果也通过了CRC校验,则控制器可以存储第2组接收比特的最终译码结果,并且可以将状态迁移至(L=2,m=3),即开始对第3组接收比特进行SCL译码处理,依次类推,控制器可以将状态迁移至(L=2,m=M),即开始对第M组接收比特进行路径数L为2的SCL译码处理,若也通过了CRC校验,就可以得到全部信息比特的最终译码结果。
针对状态(L=2,m=1),若2条路径的译码结果均未通过CRC校验且路径数L未达到路径数上限Lmax,则控制器可以将路径数L再翻倍,即调整为L=4,此时控制器的状态迁移至(L=4,m=1)。控制器因此可以控制SCL译码器重新对第1组接收比特进行路径分裂,得到4条路径,这4条路径的译码结果均被送入CRC校验器1进行CRC校验,分别得到4条路径的译码结果的CRC校验结果,后续的处理过程与前述对2条路径的处理过程是类似的,以此类推。
综上,以L=L0<Lmax为例来说:
对于状态(L=L0,m=1),若这L0条路径中至少有1条路径的译码结果通过了CRC校验,则控制器的状态从(L=L0,m=1)迁移至(L=L0,m=2),若L0条路径的译码结果均未通过CRC校验,则控制器的状态从(L=L0,m=2)迁移至(L=2L0,m=1)从第1组接收比特重新开始SCL译码处理。
对于状态(L=L0,m=2),若这L0条路径中至少有1条路径的译码结果通过了CRC校验,则控制器的状态从(L=L0,m=2)迁移至(L=L0,m=3),若L0条路径的译码结果均未通过CRC校验且L0≠Lmax,则控制器的状态从(L=L0,m=3)迁移至(L=2L0,m=1)。
以此类推,最慢的处理过程是,控制器需要遍历全部状态,在L=Lmax,m=M后,结束译码处理过程。
需要说明的是,Lmax可以是预设值,是根据系统对复杂度的需求以及
对性能的需求,设置的幸存路径的门限值,一般情况下,在L≤Lmax时,均可以找到校验通过的最优路径。但也存在直到L=Lmax时也无法找到校验通过路径的极端情况。对这种极端情况,本实施例可以从Lmax条分裂路径中选择各节点概率乘积最高的译码结果输出给存储器。
下面再举例对上述译码过程所需时间进行说明。
假设预先可以获知L=L0时才能够找到正确路径。那么在译码过程中:
L=1<L0且m=1时CRC#1=0(不能通过校验),此时L→2并重新从第m=1组开始译码。用T0表示分裂一个比特所需要的时间,那么此过程需要时间T(1,1)=K1T0。
L=2<L0且m=1时CRC#1=0(仍不能通过校验),此时L→4并重新从第m=1组开始译码。此过程需要时间T(2,1)=2K1T0。
L=L0且m=1时CRC#1=1(能通过校验),此时L不变并开始第m=2组译码。此过程需要时间T(L0,1)=L0K1T0。
L=L0且m=2时CRC#2=1(能通过校验),此时L不变并开始第m=3组译码。此过程需要时间T(L0,2)=L0K2T0。
L=L0且m=m时CRC#2=1(能通过校验),此时L不变并开始第m=m+1组译码。此过程需要时间T(L0,m)=L0KmT0。
L=L0且m=M时CRC#M=1(能通过校验),此时结束译码,可以输出译码结果。此过程需要时间T(L0,M)=L0KMT0。
整个译码过程所需总时间为:
若M组信息比特平均划分,即Ki=K/M,那么译码总时间为:
特殊情况,在L<L0时,有很小的可能CRC#1=1(能通过校验),那么L不变并对第2、3、4……组译码,直到第m组满足CRC#m=0(不能通过校验),此时L→2L并重新从第1组开始译码,此过程需要时间T(L,0)+T(L,1)+…+T(L,m)=LkmT0。
综上,图8为本发明实施例的译码处理过程和现有SCL译码处理过程的对比示意图,如图8所示,其中粗线条表征本发明实施例的译码处理过程中,虚线条表征现有SCL译码处理过程。由该图8所示过程可知,本发
明实施例通过在编码端对待发送的信息比特进行分段编码,在译码端对接收到的信息比特进行分段译码,且在SCL译码过程中,分裂路径自适应调整,相对于现有技术来说,其译码时间显著减小,译码速度快,延时低,可以提高2-M倍的译码速度。而且,本发明实施例在编码端对第m组信息比特生成CRC校验比特时,将第1~m-1组信息比特均引入一同进行CRC计算,保证了分段编码中各组信息比特的关联性,在译码端对第m组译码结果生成CRC校验比特时,同样将已经译码得到的第1~m-1组译码结果均引入一同进行CRC计算,保证了译码结果的关联性和准确性。另外,本发明实施例还可以动态调整路径数量上限Lmax,避免了译码设备闲置或浪费,合理分配系统资源;此外,本发明实施例的译码能力与传统的SCL+CRC器译码器相当,译码能力无损。
图9为本发明编码设备实施例的结构示意图,如图9所示,本实施例的编码设备可以包括:
分组模块91,用于将信息比特按照在码字中的位置顺序划分成M组信息比特,其中M为大于等于2的整数;
编码处理模块92,用于对M组信息比特分别附加循环冗余校验码CRC校验比特,得到待发送信息比特,其中,第1组信息比特所附加的CRC校验比特是根据第1组信息比特生成的,第m组信息比特所附加的CRC校验比特是根据附加有CRC校验比特的第1组信息比特至第m-1组信息比特以及第m组信息比特生成的,2≤m≤M;
编码发送模块93,用于对所述待发送信息比特和冻结比特进行极化编码,得到码字并发送。
可选的,分组模块91,具体用于将信息比特按照在码字中的位置顺序等分成M组,得到M组信息比特。
本发明还提供一种编码设备的硬件结构实现,该硬件结构图如3所示,其包括:分组器、M个CRC生成器以及编码器;其中,分组器与M个CRC生成器的输入端连接,第m个CRC生成器的输出端与编码器和第m+1至第M个CRC生成器的输入端连接,第M个CRC生成器的输出端与所述编码器连接,其中M为大于等于2的整数;
分组器,用于将信息比特按照在码字中的位置顺序划分成M组信息比特;
M个CRC生成器,用于对M组信息比特分别附加循环冗余校验码CRC校验比特,得到待发送信息比特,其中,第1组信息比特所附加的CRC校验比特是根据第1组信息比特生成的,第m组信息比特所附加的CRC校验比特是根据附加有CRC校验比特的第1组信息比特至第m-1组信息比特以及第m组信息比特生成的,2≤m≤M;
编码器,用于对所述待发送信息比特和冻结比特进行极化编码,得到码字并发送。
本实施例的编码设备可以用于执行上述编码端所执行的操作,其原理和技术效果类似,此处不再赘述。
图10为本发明译码设备实施例的结构示意图,如图10所示,本实施例的译码设备可以包括:
分组模块10,用于接收码字,所述码字包含接收比特和冻结比特;从所述码字中提取接收比特,并对所述接收比特按照在码字中的位置顺序划分成M组接收比特,其中,各组接收比特均包含循环冗余校验码CRC校验比特,M为大于等于2的整数;
译码处理模块11,用于对所述M组接收比特进行SCL译码处理,并将M组接收比特对应的最终译码结果与冻结比特进行组合并输出;其中,所述译码处理包括:对第m-1组接收比特进行L条路径的SCL译码处理,并对各L条路径的译码结果分别与第1至第m-2组接收比特的最终译码结果一同进行CRC校验,若L条路径的译码结果中存在能够通过CRC校验的路径,则开始对第m组接收比特进行SCL译码处理;否则对L翻倍,并从第1组开始重新进行SCL译码处理,直到L达到路径数上限Lmax且m达到M。
可选的,译码处理模块11,具体用于:
S601、初始化处理,其中,L=1,Lmax=Ls;
S602、令m=1;
S603、对第m组接收比特进行SCL译码,得到L条路径的译码结果;
S604、对L条路径的译码结果分别进行CRC校验,得到与各条路径的译码结果对应的CRC校验结果,其中,对第m组接收比特的L条路径的译码结果进行CRC校验时,将各条路径的译码结果与已经完成译码的第1~m-1组接收比特的译码结果一起进行CRC校验,得到与L条路径的
译码结果分别对应的CRC校验结果;
S605、根据各CRC校验结果,判断各条路径的译码结果中是否存在至少一条路径的译码结果通过校验;若是,则执行S606,否则执行S610;
S606、将通过校验的译码结果中最优的译码结果作为第m组接收比特对应的最终译码结果;
S607、判断m是否等于M,若是,则执行S609,否则执行S608;
S608、令m=m+1,并执行S603;
S609、将M组接收比特对应的最终译码结果与冻结比特进行组合并输出;
S610、判断L是否等于Lmax,若是,则执行S611,否则执行S612;
S611、将各条路径的译码结果中节点概率乘积最大的路径的译码结果作为第m组接收比特对应的最终译码结果,并执行S607;
S612、令L=2L,并执行S602。
另外,本发明还提供一种译码设备的硬件结构实现,该硬件结构图如5所示,该译码设备可以包括:分组器、SCL译码器、M个CRC校验器、控制器以及存储器;其中,分组器与SCL译码器连接,SCL译码器的第m路输出与第m+1至第M个CRC校验器连接,存储器与控制器和SCL译码器,控制器与M个CRC校验器和SCL译码器连接,其中M为大于等于2的整数;
分组器,用于接收码字,所述码字包含接收比特和冻结比特;从所述码字中提取接收比特,并对所述接收比特按照在码字中的位置顺序划分成M组接收比特,其中,各组接收比特均包含CRC校验比特;
SCL译码器,用于对所述M组接收比特分别进行SCL译码处理,并将译码处理结果对应发送给CRC校验器进行CRC校验;
M个CRC校验器,用于分别对所述M组接收比特的译码结果进行CRC校验得到校验结果;
控制器,用于根据所述校验结果确定各组接收比特的最终译码结果,并将最终译码结果存储到所述存储器中,并且在得到全部接收比特的译码结果之后将M组接收比特对应的最终译码结果与冻结比特进行组合并输出;
存储器,用于存储控制器确定的各组接收比特的最终译码结果,并将各组接收比特的最终译码结果反馈给所述SCL校验器;
其中,SCL译码处理和所述CRC校验处理,包括:对第m-1组接收比特进行L条路径的SCL译码处理,并对各L条路径的译码结果分别与第1至第m-2组接收比特的最终译码结果一同进行CRC校验,若L条路径的译码结果中存在能够通过CRC校验的路径,则开始对第m组接收比特进行SCL译码处理;否则对L翻倍,并从第1组开始重新进行SCL译码处理,直到L达到路径数上限Lmax且m达到M。
优选的,上述SCL译码处理和所述CRC校验处理,具体包括:
S601、初始化处理,其中,L=1,Lmax=Ls;
S602、令m=1;
S603、对第m组接收比特进行SCL译码,得到L条路径的译码结果;
S604、对L条路径的译码结果分别进行CRC校验,得到与各条路径的译码结果对应的CRC校验结果,其中,对第m组接收比特的L条路径的译码结果进行CRC校验时,将各条路径的译码结果与已经完成译码的第1~m-1组接收比特的译码结果一起进行CRC校验,得到与L条路径的译码结果分别对应的CRC校验结果;
S605、根据各CRC校验结果,判断各条路径的译码结果中是否存在至少一条路径的译码结果通过校验;若是,则执行S606,否则执行S610;
S606、将通过校验的译码结果中最优的译码结果作为第m组接收比特对应的最终译码结果;
S607、判断m是否等于M,若是,则执行S609,否则执行S608;
S608、令m=m+1,并执行S603;
S609、将M组接收比特对应的最终译码结果与冻结比特进行组合并输出;
S610、判断L是否等于Lmax,若是,则执行S611,否则执行S612;
S611、将各条路径的译码结果中节点概率乘积最大的路径的译码结果作为第m组接收比特对应的最终译码结果,并执行S607;
S612、令L=2L,并执行S602。
本实施例的译码设备可以用于执行上述译码端所执行的操作,其原理和技术效果类似,此处不再赘述。
本领域普通技术人员可以理解:实现上述方法实施例的全部或部分步骤
可以通过程序指令相关的硬件来完成,前述的程序可以存储于一计算机可读取存储介质中,该程序在执行时,执行包括上述方法实施例的步骤;而前述的存储介质包括:ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
最后应说明的是:以上各实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述各实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。
Claims (13)
- 一种极化码的编码方法,其特征在于,包括:将信息比特按照在码字中的位置顺序划分成M组信息比特,其中M为大于等于2的整数;对M组信息比特分别附加循环冗余校验码CRC校验比特,得到待发送信息比特,其中,第1组信息比特所附加的CRC校验比特是根据第1组信息比特生成的,第m组信息比特所附加的CRC校验比特是根据附加有CRC校验比特的第1组信息比特至第m-1组信息比特以及第m组信息比特生成的,2≤m≤M;对所述待发送信息比特和冻结比特进行极化编码,得到码字并发送。
- 根据权利要求1所述的方法,其特征在于,所述将信息比特按照在码字中的位置顺序划分成M组信息比特,包括:将信息比特按照在码字中的位置顺序等分成M组,得到M组信息比特。
- 根据权利要求1或2所述的方法,其特征在于,所述对M组信息比特分别附加循环冗余校验码CRC校验比特,包括:将所述CRC校验比特分别附加在M组信息比特中各组信息比特的尾部。
- 一种极化码的译码方法,其特征在于,包括:接收码字,所述码字包含接收比特和冻结比特;从所述码字中提取接收比特,并对所述接收比特按照在码字中的位置顺序划分成M组接收比特,其中,各组接收比特均包含循环冗余校验码CRC校验比特,M为大于等于2的整数;对所述M组接收比特进行SCL译码处理,并将M组接收比特对应的最终译码结果与冻结比特进行组合并输出;其中,所述译码处理包括:对第m-1组接收比特进行L条路径的SCL译码处理,并对各L条路径的译码结果分别与第1至第m-2组接收比特的最终译码结果一同进行CRC校验,若L条路径的译码结果中存在能够通过CRC校验的路径,则开始对第m组接收比特进行SCL译码处理;否则对L翻倍,并从第1组开始重新进行SCL译码处理,直到L达到路径数上限Lmax且m达到M。
- 根据权利要求4所述的方法,其特征在于,所述对所述M组接收比特进行SCL译码处理,并将M组接收比特对应的最终译码结果与冻结比特 进行组合并输出,包括:S601、初始化处理,其中,L=1,Lmax=Ls;S602、令m=1;S603、对第m组接收比特进行SCL译码,得到L条路径的译码结果;S604、对L条路径的译码结果分别进行CRC校验,得到与各条路径的译码结果对应的CRC校验结果,其中,对第m组接收比特的L条路径的译码结果进行CRC校验时,将各条路径的译码结果与已经完成译码的第1~m-1组接收比特的译码结果一起进行CRC校验,得到与L条路径的译码结果分别对应的CRC校验结果;S605、根据各CRC校验结果,判断各条路径的译码结果中是否存在至少一条路径的译码结果通过校验;若是,则执行S606,否则执行S610;S606、将通过校验的译码结果中最优的译码结果作为第m组接收比特对应的最终译码结果;S607、判断m是否等于M,若是,则执行S609,否则执行S608;S608、令m=m+1,并执行S603;S609、将M组接收比特对应的最终译码结果与冻结比特进行组合并输出;S610、判断L是否等于Lmax,若是,则执行S611,否则执行S612;S611、将各条路径的译码结果中节点概率乘积最大的路径的译码结果作为第m组接收比特对应的最终译码结果,并执行S607;S612、令L=2L,并执行S602。
- 根据权利要求4或5所述的方法,其特征在于,所述对所述M组接收比特进行SCL译码处理之前,还包括:根据当前信息比特的接收速度和/或接收缓冲器的剩余空间,对所述Lmax进行调整。
- 一种编码设备,其特征在于,包括:分组模块,用于将信息比特按照在码字中的位置顺序划分成M组信息比特,其中M为大于等于2的整数;编码处理模块,用于对M组信息比特分别附加循环冗余校验码CRC校验比特,得到待发送信息比特,其中,第1组信息比特所附加的CRC校验比 特是根据第1组信息比特生成的,第m组信息比特所附加的CRC校验比特是根据附加有CRC校验比特的第1组信息比特至第m-1组信息比特以及第m组信息比特生成的,2≤m≤M;编码发送模块,用于对所述待发送信息比特和冻结比特进行极化编码,得到码字并发送。
- 根据权利要求7所述的设备,其特征在于,所述分组模块,具体用于将信息比特按照在码字中的位置顺序等分成M组,得到M组信息比特。
- 一种编码设备,其特征在于,包括:分组器、M个CRC生成器以及编码器;其中,分组器与所述M个CRC生成器的输入端连接,第m个CRC生成器的输出端与所述编码器和第m+1至第M个CRC生成器的输入端连接,第M个CRC生成器的输出端与所述编码器连接,其中M为大于等于2的整数;所述分组器,用于将信息比特按照在码字中的位置顺序划分成M组信息比特;所述M个CRC生成器,用于对M组信息比特分别附加循环冗余校验码CRC校验比特,得到待发送信息比特,其中,第1组信息比特所附加的CRC校验比特是根据第1组信息比特生成的,第m组信息比特所附加的CRC校验比特是根据附加有CRC校验比特的第1组信息比特至第m-1组信息比特以及第m组信息比特生成的,2≤m≤M;所述编码器,用于对所述待发送信息比特和冻结比特进行极化编码,得到码字并发送。
- 一种译码设备,其特征在于,包括:分组模块,用于接收码字,所述码字包含接收比特和冻结比特;从所述码字中提取接收比特,并对所述接收比特按照在码字中的位置顺序划分成M组接收比特,其中,各组接收比特均包含循环冗余校验码CRC校验比特,M为大于等于2的整数;译码处理模块,用于对所述M组接收比特进行SCL译码处理,并将M组接收比特对应的最终译码结果与冻结比特进行组合并输出;其中,所述译码处理包括:对第m-1组接收比特进行L条路径的SCL译码处理,并对各L条路径的译码结果分别与第1至第m-2组接收比特的最终译码结果一同进行 CRC校验,若L条路径的译码结果中存在能够通过CRC校验的路径,则开始对第m组接收比特进行SCL译码处理;否则对L翻倍,并从第1组开始重新进行SCL译码处理,直到L达到路径数上限Lmax且m达到M。
- 根据权利要求10所述的设备,其特征在于,所述译码处理模块,具体用于:S601、初始化处理,其中,L=1,Lmax=Ls;S602、令m=1;S603、对第m组接收比特进行SCL译码,得到L条路径的译码结果;S604、对L条路径的译码结果分别进行CRC校验,得到与各条路径的译码结果对应的CRC校验结果,其中,对第m组接收比特的L条路径的译码结果进行CRC校验时,将各条路径的译码结果与已经完成译码的第1~m-1组接收比特的译码结果一起进行CRC校验,得到与L条路径的译码结果分别对应的CRC校验结果;S605、根据各CRC校验结果,判断各条路径的译码结果中是否存在至少一条路径的译码结果通过校验;若是,则执行S606,否则执行S610;S606、将通过校验的译码结果中最优的译码结果作为第m组接收比特对应的最终译码结果;S607、判断m是否等于M,若是,则执行S609,否则执行S608;S608、令m=m+1,并执行S603;S609、将M组接收比特对应的最终译码结果与冻结比特进行组合并输出;S610、判断L是否等于Lmax,若是,则执行S611,否则执行S612;S611、将各条路径的译码结果中节点概率乘积最大的路径的译码结果作为第m组接收比特对应的最终译码结果,并执行S607;S612、令L=2L,并执行S602。
- 一种译码设备,其特征在于,包括:分组器、SCL译码器、M个CRC校验器、控制器以及存储器;其中,所述分组器与所述SCL译码器连接,所述SCL译码器的第m路输出与第m+1至第M个CRC校验器连接,所述存储器与所述控制器和所述SCL译码器,所述控制器与所述M个CRC校验器和所述SCL译码器连接,其中M为大于等于2的整数;所述分组器,用于接收码字,所述码字包含接收比特和冻结比特;从所述码字中提取接收比特,并对所述接收比特按照在码字中的位置顺序划分成M组接收比特,其中,各组接收比特均包含CRC校验比特;所述SCL译码器,用于对所述M组接收比特分别进行SCL译码处理,并将译码处理结果对应发送给CRC校验器进行CRC校验;所述M个CRC校验器,用于分别对所述M组接收比特的译码结果进行CRC校验得到校验结果;所述控制器,用于根据所述校验结果确定各组接收比特的最终译码结果,并将最终译码结果存储到所述存储器中,并且在得到全部接收比特的译码结果之后将M组接收比特对应的最终译码结果与冻结比特进行组合并输出;所述存储器,用于存储控制器确定的各组接收比特的最终译码结果,并将各组接收比特的最终译码结果反馈给所述SCL校验器;其中,所述SCL译码处理和所述CRC校验处理,包括:对第m-1组接收比特进行L条路径的SCL译码处理,并对各L条路径的译码结果分别与第1至第m-2组接收比特的最终译码结果一同进行CRC校验,若L条路径的译码结果中存在能够通过CRC校验的路径,则开始对第m组接收比特进行SCL译码处理;否则对L翻倍,并从第1组开始重新进行SCL译码处理,直到L达到路径数上限Lmax且m达到M。
- 根据权利要求12所述的设备,其特征在于,所述SCL译码处理和所述CRC校验处理,具体包括:S601、初始化处理,其中,L=1,Lmax=Ls;S602、令m=1;S603、对第m组接收比特进行SCL译码,得到L条路径的译码结果;S604、对L条路径的译码结果分别进行CRC校验,得到与各条路径的译码结果对应的CRC校验结果,其中,对第m组接收比特的L条路径的译码结果进行CRC校验时,将各条路径的译码结果与已经完成译码的第1~m-1组接收比特的译码结果一起进行CRC校验,得到与L条路径的译码结果分别对应的CRC校验结果;S605、根据各CRC校验结果,判断各条路径的译码结果中是否存在至少一条路径的译码结果通过校验;若是,则执行S606,否则执行S610;S606、将通过校验的译码结果中最优的译码结果作为第m组接收比特对应的最终译码结果;S607、判断m是否等于M,若是,则执行S609,否则执行S608;S608、令m=m+1,并执行S603;S609、将M组接收比特对应的最终译码结果与冻结比特进行组合并输出;S610、判断L是否等于Lmax,若是,则执行S611,否则执行S612;S611、将各条路径的译码结果中节点概率乘积最大的路径的译码结果作为第m组接收比特对应的最终译码结果,并执行S607;S612、令L=2L,并执行S602。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2015/091202 WO2017054164A1 (zh) | 2015-09-30 | 2015-09-30 | 极化码的编译码方法及其装置 |
CN201580083408.2A CN108292967B (zh) | 2015-09-30 | 2015-09-30 | 极化码的编译码方法及其装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2015/091202 WO2017054164A1 (zh) | 2015-09-30 | 2015-09-30 | 极化码的编译码方法及其装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2017054164A1 true WO2017054164A1 (zh) | 2017-04-06 |
Family
ID=58422545
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2015/091202 WO2017054164A1 (zh) | 2015-09-30 | 2015-09-30 | 极化码的编译码方法及其装置 |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN108292967B (zh) |
WO (1) | WO2017054164A1 (zh) |
Cited By (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108768411A (zh) * | 2018-07-09 | 2018-11-06 | 中国计量大学 | 基于scl的极化码低复杂度分段译码器设计 |
WO2018201409A1 (en) * | 2017-05-04 | 2018-11-08 | Nokia Technologies Oy | Coding apparatus for polar codes |
WO2018201404A1 (en) * | 2017-05-04 | 2018-11-08 | Qualcomm Incorporated | Polar codes for uplink control information |
WO2018214101A1 (en) * | 2017-05-25 | 2018-11-29 | Qualcomm Incorporated | False alarm rate suppression for polar codes |
CN108988873A (zh) * | 2017-05-31 | 2018-12-11 | 华为技术有限公司 | 一种Polar码处理方法、译码器和终端 |
WO2018227604A1 (en) * | 2017-06-16 | 2018-12-20 | Huawei Technologies Co., Ltd. | Methods and apparatus for polar encoding |
CN109150383A (zh) * | 2017-06-27 | 2019-01-04 | 华为技术有限公司 | 一种Polar码的编码方法及装置 |
CN109412607A (zh) * | 2017-08-16 | 2019-03-01 | 深圳市海思半导体有限公司 | 译码方法及装置 |
WO2019047544A1 (zh) * | 2017-09-08 | 2019-03-14 | 华为技术有限公司 | 编码方法及装置 |
CN109660264A (zh) * | 2018-12-03 | 2019-04-19 | 中国人民解放军陆军工程大学 | 高性能极化码译码算法 |
CN110601700A (zh) * | 2019-08-09 | 2019-12-20 | 中国地质大学(武汉) | 一种适用于极化码串行抵消列表译码算法的硬件排序器 |
CN110741576A (zh) * | 2017-06-01 | 2020-01-31 | 高通股份有限公司 | 针对低等待时间解码和减小的虚警率的具有多种格式的极性码构造 |
CN110785937A (zh) * | 2017-06-26 | 2020-02-11 | 上海诺基亚贝尔股份有限公司 | Crc和极化码传输方案 |
CN110868224A (zh) * | 2019-11-26 | 2020-03-06 | 华南理工大学 | 一种基于模4和分段校验辅助的极化码编译码方法 |
US10594439B2 (en) | 2017-09-08 | 2020-03-17 | Huawei Technologies Co., Ltd. | Channel encoding method and apparatus in wireless communications to output a polar encoded bit sequence |
CN111262595A (zh) * | 2018-11-30 | 2020-06-09 | 中兴通讯股份有限公司 | 一种极化码译码方法及装置、多级译码器、存储介质 |
CN111435838A (zh) * | 2019-01-14 | 2020-07-21 | 华为技术有限公司 | 译码方法、装置及设备 |
CN112332864A (zh) * | 2020-12-03 | 2021-02-05 | 北京壹思达惟信息技术有限公司 | 一种自适应有序移动剪枝列表的极化码译码方法及系统 |
CN114142873A (zh) * | 2021-10-12 | 2022-03-04 | 北京邮电大学 | 一种极化码译码方法及装置 |
US11296724B2 (en) | 2017-09-08 | 2022-04-05 | Huawei Technologies Co., Ltd. | Encoding method and apparatus |
CN114978497A (zh) * | 2022-05-17 | 2022-08-30 | 中国人民解放军国防科技大学 | 面向量子密钥分发的追加冻结比特信息协调方法及装置 |
US12052031B2 (en) | 2017-05-04 | 2024-07-30 | Qualcomm Incorporated | Polar codes for uplink control information |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111628782B (zh) * | 2020-07-03 | 2022-08-09 | 中山大学 | 一种分段翻转连续对消列表法的极化码译码方法及装置 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103281166A (zh) * | 2013-05-15 | 2013-09-04 | 北京邮电大学 | 一种基于极化码的混合自动重传请求传输方法 |
CN103825669A (zh) * | 2012-11-16 | 2014-05-28 | 华为技术有限公司 | 数据处理的方法和装置 |
CN104219019A (zh) * | 2013-05-31 | 2014-12-17 | 华为技术有限公司 | 编码方法及编码设备 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101496182B1 (ko) * | 2013-12-16 | 2015-03-09 | 성균관대학교산학협력단 | 최소거리가 확장된 극 부호 생성 방법 및 장치 |
-
2015
- 2015-09-30 WO PCT/CN2015/091202 patent/WO2017054164A1/zh active Application Filing
- 2015-09-30 CN CN201580083408.2A patent/CN108292967B/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103825669A (zh) * | 2012-11-16 | 2014-05-28 | 华为技术有限公司 | 数据处理的方法和装置 |
CN103281166A (zh) * | 2013-05-15 | 2013-09-04 | 北京邮电大学 | 一种基于极化码的混合自动重传请求传输方法 |
CN104219019A (zh) * | 2013-05-31 | 2014-12-17 | 华为技术有限公司 | 编码方法及编码设备 |
Cited By (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110582955A (zh) * | 2017-05-04 | 2019-12-17 | 上海诺基亚贝尔股份有限公司 | 用于极化码的编码装置 |
WO2018201409A1 (en) * | 2017-05-04 | 2018-11-08 | Nokia Technologies Oy | Coding apparatus for polar codes |
WO2018201404A1 (en) * | 2017-05-04 | 2018-11-08 | Qualcomm Incorporated | Polar codes for uplink control information |
WO2018201753A1 (en) | 2017-05-04 | 2018-11-08 | Qualcomm Incorporated | Polar codes for uplink control information |
EP3619850A4 (en) * | 2017-05-04 | 2021-01-27 | QUALCOMM Incorporated | POLAR CODES FOR UPRIGHT LINK ORDERING INFORMATION |
JP7195273B2 (ja) | 2017-05-04 | 2022-12-23 | クアルコム,インコーポレイテッド | アップリンク制御情報用のポーラ符号 |
JP2020520141A (ja) * | 2017-05-04 | 2020-07-02 | クアルコム,インコーポレイテッド | アップリンク制御情報用のポーラ符号 |
US12052031B2 (en) | 2017-05-04 | 2024-07-30 | Qualcomm Incorporated | Polar codes for uplink control information |
CN110582958A (zh) * | 2017-05-04 | 2019-12-17 | 高通股份有限公司 | 用于上行链路控制信息的极化码 |
WO2018214101A1 (en) * | 2017-05-25 | 2018-11-29 | Qualcomm Incorporated | False alarm rate suppression for polar codes |
CN108988873A (zh) * | 2017-05-31 | 2018-12-11 | 华为技术有限公司 | 一种Polar码处理方法、译码器和终端 |
CN110741576A (zh) * | 2017-06-01 | 2020-01-31 | 高通股份有限公司 | 针对低等待时间解码和减小的虚警率的具有多种格式的极性码构造 |
CN110663189A (zh) * | 2017-06-16 | 2020-01-07 | 华为技术有限公司 | 用于极化编码的方法和装置 |
US10826532B2 (en) | 2017-06-16 | 2020-11-03 | Huawei Technologies Co., Ltd. | Methods and apparatus for polar encoding |
CN110663189B (zh) * | 2017-06-16 | 2021-11-19 | 华为技术有限公司 | 用于极化编码的方法和装置 |
WO2018227604A1 (en) * | 2017-06-16 | 2018-12-20 | Huawei Technologies Co., Ltd. | Methods and apparatus for polar encoding |
CN110785937A (zh) * | 2017-06-26 | 2020-02-11 | 上海诺基亚贝尔股份有限公司 | Crc和极化码传输方案 |
CN110785937B (zh) * | 2017-06-26 | 2023-08-25 | 上海诺基亚贝尔股份有限公司 | Crc和极化码传输方案 |
CN109150383A (zh) * | 2017-06-27 | 2019-01-04 | 华为技术有限公司 | 一种Polar码的编码方法及装置 |
US11088708B2 (en) | 2017-06-27 | 2021-08-10 | Huawei Technologies Co., Ltd. | Polar code encoding method and apparatus |
CN109412607A (zh) * | 2017-08-16 | 2019-03-01 | 深圳市海思半导体有限公司 | 译码方法及装置 |
CN109412607B (zh) * | 2017-08-16 | 2022-08-26 | 深圳市海思半导体有限公司 | 译码方法及装置 |
RU2728527C1 (ru) * | 2017-09-08 | 2020-07-30 | Хуавей Текнолоджиз Ко., Лтд. | Способ и устройство кодирования |
US10594439B2 (en) | 2017-09-08 | 2020-03-17 | Huawei Technologies Co., Ltd. | Channel encoding method and apparatus in wireless communications to output a polar encoded bit sequence |
WO2019047544A1 (zh) * | 2017-09-08 | 2019-03-14 | 华为技术有限公司 | 编码方法及装置 |
US11502780B2 (en) | 2017-09-08 | 2022-11-15 | Huawei Technologies Co., Ltd. | Channel decoding method and apparatus in wireless communications |
US11025366B2 (en) | 2017-09-08 | 2021-06-01 | Huawei Technologies Co., Ltd. | Channel encoding method and apparatus in wireless communications |
US11296724B2 (en) | 2017-09-08 | 2022-04-05 | Huawei Technologies Co., Ltd. | Encoding method and apparatus |
CN108768411A (zh) * | 2018-07-09 | 2018-11-06 | 中国计量大学 | 基于scl的极化码低复杂度分段译码器设计 |
CN111262595A (zh) * | 2018-11-30 | 2020-06-09 | 中兴通讯股份有限公司 | 一种极化码译码方法及装置、多级译码器、存储介质 |
CN109660264A (zh) * | 2018-12-03 | 2019-04-19 | 中国人民解放军陆军工程大学 | 高性能极化码译码算法 |
CN109660264B (zh) * | 2018-12-03 | 2023-05-05 | 中国人民解放军陆军工程大学 | 高性能极化码译码算法 |
CN111435838B (zh) * | 2019-01-14 | 2022-06-14 | 华为技术有限公司 | 译码方法、装置及设备 |
CN111435838A (zh) * | 2019-01-14 | 2020-07-21 | 华为技术有限公司 | 译码方法、装置及设备 |
CN110601700B (zh) * | 2019-08-09 | 2021-05-04 | 中国地质大学(武汉) | 一种适用于极化码串行抵消列表译码算法的硬件排序器 |
CN110601700A (zh) * | 2019-08-09 | 2019-12-20 | 中国地质大学(武汉) | 一种适用于极化码串行抵消列表译码算法的硬件排序器 |
CN110868224B (zh) * | 2019-11-26 | 2023-03-21 | 华南理工大学 | 一种基于模4和分段校验辅助的极化码编译码方法 |
CN110868224A (zh) * | 2019-11-26 | 2020-03-06 | 华南理工大学 | 一种基于模4和分段校验辅助的极化码编译码方法 |
CN112332864A (zh) * | 2020-12-03 | 2021-02-05 | 北京壹思达惟信息技术有限公司 | 一种自适应有序移动剪枝列表的极化码译码方法及系统 |
CN112332864B (zh) * | 2020-12-03 | 2023-09-08 | 北京壹思达惟信息技术有限公司 | 一种自适应有序移动剪枝列表的极化码译码方法及系统 |
CN114142873A (zh) * | 2021-10-12 | 2022-03-04 | 北京邮电大学 | 一种极化码译码方法及装置 |
CN114978497A (zh) * | 2022-05-17 | 2022-08-30 | 中国人民解放军国防科技大学 | 面向量子密钥分发的追加冻结比特信息协调方法及装置 |
Also Published As
Publication number | Publication date |
---|---|
CN108292967A (zh) | 2018-07-17 |
CN108292967B (zh) | 2020-07-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2017054164A1 (zh) | 极化码的编译码方法及其装置 | |
US11595055B2 (en) | Methods and apparatus to parallelize data decompression | |
US10312947B2 (en) | Concatenated and sliding-window polar coding | |
Hashemi et al. | Partitioned successive-cancellation list decoding of polar codes | |
WO2021000531A1 (zh) | 一种基于llr的分段翻转极化码译码方法和智能终端 | |
CN107370560B (zh) | 一种极化码的编码和速率匹配方法、装置及设备 | |
EP3364542A1 (en) | Error correction coding method based on cascading of polar codes and repetition codes or multi-bit parity check codes | |
CN111541517B (zh) | 一种列表极化码传播译码方法 | |
CN109660264A (zh) | 高性能极化码译码算法 | |
WO2018133215A1 (zh) | 基于lsc-crc译码的分段极化码编译码方法及系统 | |
WO2014173133A1 (zh) | 极性码的译码方法和译码装置 | |
WO2014059780A1 (zh) | 一种编译码的方法、装置及系统 | |
CN108574561A (zh) | 极化码编码的方法和装置 | |
WO2020108586A1 (zh) | 一种极化码译码方法及装置、多级译码器、存储介质 | |
JP2001036417A (ja) | 誤り訂正符号化装置、方法及び媒体、並びに誤り訂正符号復号装置、方法及び媒体 | |
CN109768846B (zh) | 基于二核三核混合极化码的凿孔方法、系统、装置及介质 | |
Liu et al. | Improved polar SCL decoding by exploiting the error correction capability of CRC | |
WO2018179246A1 (en) | Check bit concatenated polar codes | |
US20180278268A1 (en) | Method for generating a sequence for a pola code and medium therefor and method and apparatus for transmitting data using thereof | |
CN110661533B (zh) | 优化译码器存储极化码译码性能的方法 | |
US20110258522A1 (en) | Encoding apparatus, decoding apparatus, and encoding and decoding system | |
WO2014180301A1 (zh) | 极性Polar码的译码方法和装置 | |
WO2016015288A1 (zh) | 译码方法和译码器 | |
CN111446973B (zh) | 基于多翻转比特集合的极化码置信传播译码方法 | |
KR102111678B1 (ko) | 인터리버를 이용한 극 부호 장치, 극 부호의 반복 복호 장치 및 이를 이용한 부호 방법과 복호 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 15905076 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 15905076 Country of ref document: EP Kind code of ref document: A1 |