WO2016172940A1 - 极性码的译码方法和译码装置 - Google Patents

极性码的译码方法和译码装置 Download PDF

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WO2016172940A1
WO2016172940A1 PCT/CN2015/078033 CN2015078033W WO2016172940A1 WO 2016172940 A1 WO2016172940 A1 WO 2016172940A1 CN 2015078033 W CN2015078033 W CN 2015078033W WO 2016172940 A1 WO2016172940 A1 WO 2016172940A1
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path
bit
candidate path
paths
candidate
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PCT/CN2015/078033
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English (en)
French (fr)
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崔志英
范有喆
李斌
沈晖
金杰
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华为技术有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes

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  • Embodiments of the present invention relate to the field of codecs and, more particularly, to a decoding method and a decoding apparatus for a Polar code (polar code).
  • polar code polar code
  • the Polar code is a good code that has been proven to achieve Shannon capacity and has low codec complexity.
  • B N is a transposed matrix, such as a bit reversal matrix.
  • A is the information (Information) bit set index
  • G N is a sub-matrix obtained from G N.
  • a C is the G N.
  • the decoding of the Polar code can be decoded by SC (successive-cancellation).
  • SC uccessive-cancellation
  • SC decoding O(Nlog 2 N). Although SC decoding can achieve good performance with a long code length N, it approaches the Shannon limit. However, when N is short or medium, the performance of the SC decoding of the Polar code does not exceed the performance of the Turbo code and the LDPC (Low-density Parity-check) code, and the decoding performance needs to be further improved.
  • SC decoding it is a bit-by-bit sequential decoding. After each bit is decoded, it is used for hard decoding and then used for subsequent bit decoding. This may cause error propagation, resulting in degradation of decoding performance.
  • List decoding preserves multiple candidate paths to achieve decoding performance that approximates maximum likelihood.
  • SC-List decoding is obtained by combining SC decoding and List decoding.
  • Path splitting every time if Is an information bit, which splits the current decoding path into two paths: one path And a path
  • a predefined threshold which may be referred to as a list size or search width
  • L the least reliable path is discarded, and only the L most reliable paths (which may be referred to as surviving paths or reserved paths) are retained; And update the probability values on all paths.
  • L is a positive integer
  • the L most reliable paths constitute a set of reliable paths (which can be called a set of surviving paths).
  • the bit estimation sequence corresponding to the decoding path having the largest path metric value in the reliable path set is determined as the decoding result of the polarity code.
  • the existing SC-List decoding uses a fixed number of surviving path numbers L, and the decoding complexity is O (L ⁇ N ⁇ log 2 N). Specifically, the existing SC-List decoding selects L paths from the 2L path according to the path metric value PM, wherein one path corresponds to one PM value, 2L paths correspond to 2L PM values, and the existing decoder will 2L.
  • the PM values are arranged from small to large, and the path corresponding to the smallest L PM values (reliable path) is selected to continue decoding, and so on, to obtain the final L reliable path.
  • Embodiments of the present invention provide a decoding method and a decoding apparatus for a polar code, which can improve decoding efficiency.
  • a method for decoding a polarity code including: determining a path metric value PM of each candidate path in a candidate path set of an ith bit of the polarity code, where The candidate path set of the i-th bit is extended by the L-preserved path of the i-th bit The number of the candidate paths is less than or equal to 2L, where L is a preset list size; comparing the PMs of all the paths in the candidate path set with the acceptance threshold and the rejection threshold of the i-th bit, according to the comparison result The candidate path set determines L paths as the reserved path of the i-th bit.
  • the path metric value PM of each candidate path in the candidate path set of the ith bit of the polarity code is determined to include:
  • a hard decision value indicating the lth reserved path of the i-1th bit a path metric indicating the lth reserved path of the i-1th bit, a path metric indicating a first candidate path corresponding to a lth reserved path of the i-1th bit in the i-th bit, a path metric indicating a second candidate path corresponding to a lth reserved path of the i-1th bit in the i-th bit, Indicates the log likelihood value of the i-th bit of the l-th path in the polar code, l ⁇ [1, L].
  • the method before comparing the PM of all the paths in the candidate path set with the acceptance threshold and the rejection threshold of the ith bit, the method further includes: The PMs of all the paths in the candidate path set determine the acceptance threshold and the rejection threshold of the i-th bit.
  • determining, by the PM of all paths in the candidate path set, an acceptance threshold and a rejection threshold of the i-th bit including: all the candidate path set The median in the middle, determined as the acceptance threshold, all in the candidate path set One of the plurality of PMs greater than the median is determined to be the rejection threshold.
  • all of the candidate path sets are included One of the plurality of PMs greater than the median is determined as the rejection threshold, including: all of the candidate path sets The maximum or second largest value in the determination is determined as the rejection threshold.
  • any one of the first to the fourth possible implementation manners in the fifth possible implementation manner, are respectively different from the first Comparing the acceptance threshold of the i bits with the rejection threshold, determining L paths as the reserved path of the i th bit from the candidate path set according to the comparison result, including: the PM in the candidate path set is less than or equal to the acceptance threshold Candidate path as the reserved path of the ith bit And a first subset of the set, the candidate path in the set of candidate path sets being greater than the acceptance threshold and less than or equal to the rejection threshold as the second subset of the reserved path set of the i-th bit.
  • a decoding apparatus for a polar code including: a first determining unit, configured to determine a path metric value PM of each candidate path in a candidate path set of an i-th bit of the polar code
  • the candidate path set of the i-th bit is obtained by extending the L-preserved path of the i-th bit, the number of the candidate path is less than or equal to 2L, and L is a preset list size; the second determining unit, And comparing the PMs of all the paths in the candidate path set with the acceptance threshold and the rejection threshold of the ith bit, and determining L paths from the candidate path set as the reserved path of the ith bit according to the comparison result.
  • the first determining unit determines, according to the following formula, a PM of each candidate path in the candidate path set of the ith bit of the polarity code:
  • a hard decision value indicating the lth reserved path of the i-1th bit a path metric indicating the lth reserved path of the i-1th bit, a path metric indicating a first candidate path corresponding to a lth reserved path of the i-1th bit in the i-th bit, a path metric indicating a second candidate path corresponding to a lth reserved path of the i-1th bit in the i-th bit, Indicates the log likelihood value of the i-th bit of the l-th path in the polar code, l ⁇ [1, L].
  • the method further includes:
  • a third determining unit configured to determine, according to the PMs of all the paths in the candidate path set, an acceptance threshold and a rejection threshold of the i-th bit.
  • the third determining unit The median in the middle, determined as the acceptance threshold, all in the candidate path set One of the plurality of PMs greater than the median is determined to be the rejection threshold.
  • the third determining unit The maximum or second largest value in the determination is determined as the rejection threshold.
  • the second determining unit the candidate path The candidate path in the set is less than or equal to the candidate path that accepts the threshold as the first subset of the reserved path set of the i-th bit, and the candidate path in the set of candidate path sets is greater than the candidate path that accepts the threshold and is less than or equal to the rejection threshold.
  • a second subset of the set of reserved paths of the ith bit is less than or equal to the candidate path that accepts the threshold as the first subset of the reserved path set of the i-th bit.
  • the embodiment of the present invention compares the PMs of all paths in the candidate path set of the i-th bit with the acceptance threshold and the rejection threshold, and determines L paths as the i-th bit from the candidate path set according to the comparison result.
  • the path is reserved; it is not necessary to sort the PMs of all paths, which avoids a large amount of hardware resources and time resources consumed by the sorting operation, and improves the decoding efficiency.
  • FIG. 1 is a schematic block diagram of a wireless communication system in accordance with an embodiment of the present invention.
  • FIG. 2 is a schematic flow chart of a method of decoding a polar code according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a decoding code tree of a polarization code having a code length of 4, in accordance with one embodiment of the present invention.
  • FIG. 4 is a schematic block diagram of path selection in a method of decoding a polarization code according to an embodiment of the present invention.
  • FIG. 5 is a schematic block diagram of path selection in a method of decoding a polarization code according to another embodiment of the present invention.
  • FIG. 6 is a schematic diagram showing simulation results on a FER performance of a decoding method and a prior art decoding method according to an embodiment of the present invention.
  • Figure 7 is a schematic block diagram of a decoding apparatus for a polar code in accordance with one embodiment of the present invention.
  • FIG. 8 is a schematic block diagram of a decoding apparatus of a polar code according to another embodiment of the present invention.
  • GSM Global System of Mobile communication
  • CDMA Code Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access
  • GPRS General Packet Radio Service
  • LTE Long Term Evolution
  • FDD Frequency Division Duplex
  • TDD Time Division Duplex
  • UMTS Universal Mobile Telecommunication System
  • FIG. 1 illustrates a wireless communication system 100 in accordance with various embodiments described herein.
  • System 100 includes a base station 102 that can include multiple antenna groups.
  • one antenna group may include antennas 104 and 106
  • another antenna group may include antennas 108 and 110
  • additional groups may include antennas 112 and 114.
  • Two antennas are shown for each antenna group, however more or fewer antennas may be used for each group.
  • Base station 102 can additionally include a transmitter chain and a receiver chain, as will be understood by those of ordinary skill in the art, which can include multiple components associated with signal transmission and reception (e.g., processor, modulator, multiplexer, demodulation) , demultiplexer or antenna, etc.).
  • Base station 102 can communicate with one or more access terminals, such as access terminal 116 and access terminal 122. However, it will be appreciated that base station 102 can communicate with substantially any number of access terminals similar to access terminals 116 and 122. Access terminals 116 and 122 can be, for example, cellular telephones, smart phones, portable computers, handheld communication devices, handheld computing devices, satellite radios, global positioning systems, PDAs, and/or any other for communicating over wireless communication system 100. Suitable for equipment. As shown, access terminal 116 is in communication with antennas 112 and 114, with antennas 112 and 114 transmitting information to access terminal 116 over forward link 118 and receiving information from access terminal 116 over reverse link 120.
  • access terminal 116 is in communication with antennas 112 and 114, with antennas 112 and 114 transmitting information to access terminal 116 over forward link 118 and receiving information from access terminal 116 over reverse link 120.
  • access terminal 122 is in communication with antennas 104 and 106, wherein antennas 104 and 106 transmit information to access terminal 122 over forward link 124 and receive information from access terminal 122 over reverse link 126.
  • FDD Frequency Division Duplex
  • the forward link 118 can utilize different frequency bands than those used by the reverse link 120, and the forward link 124 can be utilized and reversed. Different frequency bands used by link 126.
  • the forward chain Path 118 and reverse link 120 may use a common frequency band, and forward link 124 and reverse link 126 may use a common frequency band.
  • Each set of antennas and/or regions designed for communication is referred to as a sector of base station 102.
  • the antenna group can be designed to communicate with access terminals in sectors of the coverage area of base station 102.
  • the transmit antennas of base station 102 may utilize beamforming to improve the signal to noise ratio for forward links 118 and 124 of access terminals 116 and 122.
  • the base station 102 transmits to the randomly dispersed access terminals 116 and 122 in the relevant coverage area by the base station as compared to all of the access terminals transmitted by the base station, the mobile devices in the adjacent cells are subject to Less interference.
  • base station 102, access terminal 116, and/or access terminal 122 may be transmitting wireless communication devices and/or receiving wireless communication devices.
  • the transmitting wireless communication device can encode the data for transmission.
  • the transmitting wireless communication device can have (eg, generate, obtain, store in memory, etc.) a certain number of information bits to be transmitted over the channel to the receiving wireless communication device.
  • Such information bits may be included in a transport block (or multiple transport blocks) of data that may be segmented to produce a plurality of code blocks.
  • the transmitting wireless communication device can encode each code block using a polar code encoder (not shown) to improve the reliability of data transmission, thereby ensuring communication quality.
  • FIG. 2 is a schematic flow chart of a method of decoding a polar code according to an embodiment of the present invention.
  • the decoding method shown in FIG. 2 can be performed by a decoding device.
  • the decoding method shown in FIG. 2 includes:
  • the PM of each candidate path in the candidate path set of the i-th bit is determined, and the candidate is selected.
  • the PMs of all paths in the path set are compared with the acceptance threshold and the rejection threshold, and the surviving path (which may be referred to as a reliable path or a reserved path) and the deleted path are determined from the candidate path set according to the comparison result, and the surviving path is obtained.
  • the number of paths of the surviving path is L
  • the number of paths of the deleted path is L.
  • the reliable path is the final L reliable path of the polarity code, and N is the number of polar code bits.
  • the final L reliable paths are obtained, and the bit estimation sequence corresponding to the decoding path having the largest path metric in the final L reliable path set is determined as the polarity. The decoding result of the code.
  • the embodiment of the present invention compares the PMs of all the paths in the candidate path set of the i-th bit with the acceptance threshold and the rejection threshold, and determines L paths as the reserved path of the i-th bit from the candidate path set according to the comparison result; It is not necessary to size the PMs of all paths, which avoids a large amount of hardware resources and time resources consumed by the sorting operation, and improves the decoding efficiency.
  • the ordering of 2L PM values requires more hardware resources and delay.
  • 2L PM values are compared in parallel with two thresholds AT and RT. Therefore, path selection requires only 4L comparison operations and these comparison operations can be performed in parallel. Therefore, path selection based on threshold comparison requires only one comparator delay. Therefore, obtaining AT and RT does not introduce additional delay. Therefore, the path selection scheme based on the threshold comparison can greatly reduce the delay of the list decoder.
  • a polarity code with a code length of N may correspond to a binary decoding code tree composed of N layer edges, where the i-th layer of the decoding code tree corresponds to the polarity code.
  • the i-th bit in the absence of a frozen bit, except for the leaf node (the last bit), each node in the decoding code tree has two successor nodes, which are related to the node and the two successor nodes of the node. The two sides of the union are marked as 0 and 1, respectively.
  • the value of the freeze bit is a preset value, for example, 0, there is only one successor node among the nodes corresponding to the freeze bit.
  • All edges are divided into N layers according to the distance from the node that is associated with the root node to the root node, the layer closest to the root node is the first layer, and the node associated with the leaf node is the Nth layer, for example, 3 is a decoding code tree of a polar code having a code length of 4, wherein there are no nodes of frozen bits in the decoding tree, and the decoding code tree has 4 layers.
  • the i-th bit corresponds to the i-th layer of the decoding code tree, hereinafter, the i-th layer and the i-th bit Bits can mean the same thing.
  • the pruning is performed, that is, the reserved path is selected from the candidate path set, and the candidate path of the i-th bit is selected.
  • the number is less than L, there is no need to perform branching, and all candidate paths are used as reserved paths.
  • Each subsequent path in the 2L subsequent path is a shortest path composed of a node from the root node to the i-th layer in the decoding code tree, and the operation of deleting the candidate path may be referred to as a pruning operation, but the present invention is not limited thereto. this.
  • the i-th bit in the polarity code corresponding to the i-th layer may be described as an information bit.
  • the decoding method in the embodiment of the present invention may use only one bit to adopt the method described in FIG. 1, and other bits are decoded by using the prior art;
  • the method of the present invention is not limited by the embodiment of the present invention.
  • the ith bit in the embodiment of the present invention may be one of N bits in the polarity code.
  • the value of i may be one or more of M to N, and i may also traverse.
  • the value of the candidate path of the Mth bit is greater than L, and the embodiment of the present invention is not limited thereto.
  • a polar code decoding process with a code length of N can be considered to be searched in a binary tree of depth N.
  • Two branches output by the node of depth i correspond to two possible values of information bits u i , labeled "0" and "1", respectively.
  • the corresponding node has only one subtree in the binary tree.
  • a path from the root node to the leaf node represents a possible transmitted codeword, namely (u 0 , u 1 , u 2 , ..., u N-1 ).
  • the list decoder is a breadth-first search. When searching for depth i, it retains at most L optimal nodes, corresponding to the path decoded by L parts, recorded as At the end of decoding, it can output L possible decoding results, thereby improving the error correction performance of the polar code.
  • the list decoder decodes u i+1 bits
  • the decision for this bit is always a preset value (ie "0"). Therefore, the L partial decoding path is updated as follows:
  • the decision for this bit may be "0" or "1". Therefore, L strip decoding paths can generate 2L possible partial decoding paths
  • the list decoder only selects the optimal L strips among the 2L paths, and then continues the decoding operation. Among them, the path selection is based on the path value PM.
  • the PM of each candidate path in the candidate path set of the ith bit of the polarity code is determined according to the following formula,
  • a hard decision value indicating the lth reserved path of the i-1th bit a path metric indicating the lth reserved path of the i-1th bit, a path metric indicating a first candidate path corresponding to a lth reserved path of the i-1th layer in the i-th bit, a path metric indicating a second candidate path corresponding to the lth reserved path of the i-1th layer in the i-th layer, Indicates the log likelihood value of the i-th bit of the l-th path in the polar code, l ⁇ [1, L].
  • the reliable path of the first bit is a likelihood function value of the first information bit in the polar code, for example,
  • the PM values of the L paths p 0 , p 1 , . . . , p L-1 of the u i bit are in turn In the u i+1 bit, the LLR of the bit code output by the polar code decoder is The decoding path extended by the lth path is Or 1.
  • the PM value of the 2L partial decoding path of the corresponding u i+1 bit is updated as follows:
  • the PMs of all the paths in the candidate path set are compared with the acceptance threshold and the rejection threshold, the L paths are determined as the reliable path set of the layer from the candidate path set according to the comparison result;
  • the PM sorts the size, avoids the consumption of a large amount of hardware resources and time resources due to the sorting operation, and improves the decoding efficiency.
  • the acceptance threshold and the rejection threshold in the embodiment of the present invention may be obtained in advance, may be determined according to the PM, or determined according to other manners. That is, before 220, the method of the embodiment of the present invention may further include acquiring an acceptance threshold and a rejection threshold.
  • the method of the embodiment of the present invention further includes determining an acceptance threshold and rejection of the i-th layer according to the PMs of all the paths in the candidate path set. Threshold.
  • the acceptance threshold and the rejection threshold are obtained, including determining the acceptance threshold and the rejection threshold of the i-th layer according to the PMs of all the paths in the candidate path set.
  • the Accept Threshold (AT) and the Reject Threshold (RT) may both be referred to as a pruning threshold.
  • these operations may be performed simultaneously with the LLR in which the polar code decoder calculates the information bits, and therefore, obtaining AT and RT in the embodiment of the present invention does not introduce additional time. Delay.
  • the PMs of all the paths in the candidate path set are compared with the acceptance threshold and the rejection threshold, the L paths are determined as the reliable path set of the layer from the candidate path set according to the comparison result;
  • the PM sorts the size, avoids the consumption of a large amount of hardware resources and time resources due to the sorting operation, and improves the decoding efficiency.
  • determining, according to the PMs of all the paths in the candidate path set, the acceptance threshold and the rejection threshold of the i-th layer include:
  • the median in the middle is determined to be the acceptance threshold.
  • One of the plurality of PMs greater than the median is determined to be the rejection threshold.
  • the median of the path values of the L reliable paths of the i-1th layer is determined as the acceptance threshold of the i-th layer, and the path values of the L reliable paths of the i-1th layer are greater than the median
  • One of the plurality of PMs in the number is determined as the rejection threshold of the i-th layer.
  • all of the candidate path sets can be The maximum or second largest value in the determination is determined as the rejection threshold.
  • the maximum value or the second largest value of the path values of the L reliable paths of the i-1th layer may be determined as the rejection threshold.
  • the method for determining the AT and RT values can be obtained.
  • the LLR of the i-th information bit can be calculated by the polar code decoder while determining the AT and RT values. Therefore, the AT and the RT are obtained in the embodiment of the present invention. No additional delays will be introduced.
  • the PMs of all the paths in the candidate path set are compared with the acceptance threshold and the rejection threshold, the L paths are determined as the reliable path set of the layer from the candidate path set according to the comparison result; The PM sorts the size, avoids the consumption of a large amount of hardware resources and time resources due to the sorting operation, and improves the decoding efficiency.
  • the candidate path in the candidate path set is less than or equal to the candidate path that accepts the threshold as the first subset of the reserved path set of the i-th bit, and the candidate path set is included in the candidate path set.
  • the PM is larger than the candidate path that accepts the threshold and is less than or equal to the rejection threshold as the second subset of the set of reserved paths of the i-th bit.
  • the second subset is a collection of paths other than the first subset of the set of reliable paths.
  • the embodiment of the present invention proposes a path selection scheme based on threshold comparison:
  • a path selection scheme based on threshold comparison is described in FIG.
  • the first region of FIG. 4 at least the best eight paths are selected by comparison with the threshold of the AT, wherein the first region corresponds to the first subset.
  • the worst few paths are excluded by comparison with the threshold of RT.
  • the paths are randomly selected to obtain an optimal path (corresponding to the second subset) of the 16 optimal paths except the first region.
  • the random selection path does not guarantee that the optimal 16 paths are always selected compared to the conventional method of precise ordering. Therefore, performance loss will be introduced.
  • RT PM L-2 .
  • this can increase the number of paths that are excluded, thereby reducing the chance of randomly selecting paths. Therefore, a path selection scheme based on threshold comparison will introduce minimal performance loss.
  • the embodiment of the present invention compares the PMs of all the paths in the candidate path set of the i-th bit with the acceptance threshold and the rejection threshold, and determines L paths as the reserved path of the i-th bit from the candidate path set according to the comparison result; It is not necessary to size the PMs of all paths, which avoids a large amount of hardware resources and time resources consumed by the sorting operation, and improves the decoding efficiency.
  • the existing sorting decoder 1 calculates the PM by using Equation 1.1 and sorts 2L PMs, and selects the smallest L path decoding among the PM values.
  • the existing sorting decoder 2 calculates the PM by using Equation 1.2 and sorts 2L PMs.
  • the decoder of the embodiment of the present invention is a decoder based on the threshold comparison of the embodiment of the present invention, wherein the rejection threshold is PM15, and the decoder 2 of the embodiment of the present invention is based on the example of the present invention.
  • the threshold comparison decoder, wherein the rejection threshold is PM14, as can be seen from FIG. 6, the performance of the path selection scheme based on the threshold comparison in the embodiment of the present invention is basically the same as that of the existing sequencing decoder, that is, The performance loss introduced by the present invention is almost negligible.
  • the present invention determines L paths as the reserved path of the ith bit from the candidate path set according to the comparison result; it is not necessary to size the PMs of all the paths, and avoids consumption due to the sorting operation. A large amount of hardware resources and time resources improve the decoding efficiency.
  • the decoding method of the polar code of the embodiment of the present invention is described in detail above with reference to FIG. 1 to FIG. 6.
  • the decoding apparatus of the polar code according to the embodiment of the present invention will be described below with reference to FIGS. 7 to 8.
  • FIG. 7 is a schematic block diagram of a decoding apparatus for a polar code in accordance with one embodiment of the present invention.
  • the decoding apparatus 700 shown in FIG. 7 includes a first determining unit 710 and a second determining unit 720.
  • the first determining unit 710 is configured to determine a path metric value PM of each candidate path in the candidate path set of the ith bit of the polarity code, where the candidate path set of the ith bit is by the i-1
  • the L-bits of the bits are extended, and the number of candidate paths is less than or equal to 2L, and L is a preset list size.
  • the second determining unit 720 is configured to compare the PMs of all the paths in the candidate path set with the acceptance threshold and the rejection threshold of the ith bit, and determine the L paths as the reservation of the ith bit from the candidate path set according to the comparison result. path.
  • the embodiment of the present invention compares the PMs of all the paths in the candidate path set of the i-th bit with the acceptance threshold and the rejection threshold, and determines L paths as the reserved path of the i-th bit from the candidate path set according to the comparison result; It is not necessary to size the PMs of all paths, which avoids a large amount of hardware resources and time resources consumed by the sorting operation, and improves the decoding efficiency.
  • the first determining unit 710 determines, according to the following formula, the PM of each candidate path in the candidate path set of the ith bit of the polarity code:
  • a hard decision value indicating the lth reserved path of the i-1th bit a path metric indicating the lth reserved path of the i-1th bit, a path metric indicating a first candidate path corresponding to a lth reserved path of the i-1th bit in the i-th bit, a path metric indicating a second candidate path corresponding to a lth reserved path of the i-1th bit in the i-th bit, Indicates the log likelihood value of the i-th bit of the l-th path in the polar code, l ⁇ [1, L].
  • the decoding apparatus 700 further includes a third determining unit, specifically, a third determining unit, configured to determine an acceptance threshold and a rejection of the ith bit according to the PMs of all paths in the candidate path set. Threshold.
  • the third determining unit will all in the candidate path set
  • the median in the middle, determined to accept the threshold, will be in the candidate path set
  • One of the plurality of PMs greater than the median is determined to be the rejection threshold.
  • the third determining unit will retain all of the path set The maximum or second largest value in the determination is determined as the rejection threshold.
  • the second determining unit 720 the candidate path in the candidate path set is less than or equal to the candidate path that accepts the threshold as the first subset of the reserved path set of the i-th bit, and the candidate path set is set.
  • the PM in the middle is larger than the candidate path that accepts the threshold and is less than or equal to the rejection threshold as the second subset of the reserved path set of the i-th bit.
  • the decoding apparatus 700 of the polar code shown in FIG. 7 can implement the processes involved in the decoding apparatus in the decoding method of the polar code shown in FIG. 1 to FIG. 6, and the translation shown in FIG.
  • the code device 700 For the specific functions of the code device 700, reference may be made to the various processes performed by the decoding device in FIGS. 1 to 6. To avoid repetition, details are not described herein again.
  • FIG. 8 is a schematic block diagram of a decoding apparatus of a polar code according to another embodiment of the present invention.
  • the decoding apparatus 800 shown in FIG. 8 includes a processor 810, a memory 820, and a bus system 830.
  • the processor 810 is configured to determine, by the bus system 830, the code stored in the memory 820, the path metric value PM of each candidate path in the candidate path set of the ith bit of the polarity code, where, i
  • the candidate path set of the bits is obtained by extending the L-preserved path of the i-1th bit, and the number of the candidate paths is less than or equal to 2L, where L is a preset list size;
  • the PMs of all the paths in the candidate path set are compared with the acceptance threshold and the rejection threshold of the i-th bit, and the L paths are determined as the reserved path of the i-th bit from the candidate path set according to the comparison result.
  • the embodiment of the present invention compares the PMs of all the paths in the candidate path set of the i-th bit with the acceptance threshold and the rejection threshold, and determines L paths as the reserved path of the i-th bit from the candidate path set according to the comparison result; It is not necessary to size the PMs of all paths, which avoids a large amount of hardware resources and time resources consumed by the sorting operation, and improves the decoding efficiency.
  • Processor 810 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the foregoing method may be completed by an integrated logic circuit of hardware in the processor 810 or an instruction in a form of software.
  • the processor 810 may be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a Field Programmable Gate Array (FPGA), or the like. Programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA Field Programmable Gate Array
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like. Knot The steps of the method disclosed in the embodiments of the present invention may be directly implemented by the hardware decoding processor, or may be performed by a combination of hardware and software modules in the decoding processor.
  • the software module can be located in a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable read only memory or an electrically erasable programmable memory, a register, etc. In the storage medium.
  • the storage medium is located in the memory 820.
  • the processor 810 reads the information in the memory 820 and completes the steps of the foregoing method in combination with hardware.
  • the bus system 830 may include a power bus, a control bus, and a status signal bus in addition to the data bus. Wait. However, for clarity of description, various buses are labeled as bus system 830 in the figure.
  • the processor 810 determines, according to the following formula, the PM of each candidate path in the candidate path set of the ith bit of the polarity code,
  • a hard decision value indicating the lth reserved path of the i-1th bit a path metric indicating the lth reserved path of the i-1th bit, a path metric indicating a first candidate path corresponding to a lth reserved path of the i-1th bit in the i-th bit, a path metric indicating a second candidate path corresponding to a lth reserved path of the i-1th bit in the i-th bit, Indicates the log likelihood value of the i-th bit of the l-th path in the polar code, l ⁇ [1, L].
  • the processor 810 will all of the reliable path sets The median in the middle, determined to accept the threshold, will be in the reliable path set One of the plurality of PMs greater than the median is determined to be the rejection threshold.
  • the processor 810 determines an acceptance threshold and a rejection threshold of the i-th bit according to the PMs of all paths in the candidate path set.
  • the processor 810 will all of the candidate path sets.
  • the median in the middle, determined to accept the threshold, will be in the candidate path set
  • One of the plurality of PMs greater than the median is determined to be the rejection threshold.
  • the processor 810 will all of the candidate path sets The maximum or second largest value in the determination is determined as the rejection threshold.
  • the processor 810 the candidate path in the candidate path set is less than or equal to the candidate path that accepts the threshold as the first subset of the reserved path set of the i-th bit, where the candidate path set is The PM is larger than the candidate path that accepts the threshold and is less than or equal to the rejection threshold. A second subset of the set of reserved paths of the i-th bit.
  • the decoding apparatus 800 of the polar code shown in FIG. 8 corresponds to the decoding apparatus 700 shown in FIG. 7, and can implement the embodiment of the decoding method of the polar code shown in FIG. 1 to FIG.
  • the specific functions of the decoding apparatus 800 shown in FIG. 8 can refer to the various processes performed by the decoding apparatus in FIGS. 1 to 6. To avoid repetition, details are not described herein again.
  • system and “network” are used interchangeably herein.
  • the term “and/or” in this context is merely an association describing the associated object, indicating that there may be three relationships, for example, A and / or B, which may indicate that A exists separately, and both A and B exist, respectively. B these three situations.
  • the character "/" in this article generally indicates that the contextual object is an "or" relationship.
  • B corresponding to A means that B is associated with A, and B can be determined according to A.
  • determining B from A does not mean that B is only determined based on A, and that B can also be determined based on A and/or other information.
  • the disclosed systems, devices, and The method can be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of cells is only a logical function division.
  • multiple units or components may be combined or integrated. Go to another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, or an electrical, mechanical or other form of connection.
  • the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiments of the present invention.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another.
  • a storage medium may be any available media that can be accessed by a computer.
  • computer readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage media or other magnetic storage device, or can be used for carrying or storing in the form of an instruction or data structure.
  • connection may suitably be a computer readable medium.
  • the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave
  • coaxial cable , fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, wireless, and microwave are included in the fixing of the associated media.
  • a disk and a disc include a compact disc (CD), a laser disc, a compact disc, a digital versatile disc (DVD), a floppy disk, and a Blu-ray disc, wherein the disc is usually magnetically copied, and the disc is The laser is used to optically replicate the data. Combinations of the above should also be included within the scope of the computer readable media.

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Abstract

本发明实施例提供了一种极性码的译码方法和译码装置，该方法包括确定极性码的第i个比特的候选路径集合中的每一条候选路径的路径度量值PM，其中，第i个比特的候选路径集合由第i-1个比特的L条保留路径扩展得到，候选路径的数量小于或等于2L，L为预设的列表大小；将候选路径集合中所有路径的PM与第i个比特的接受门限和拒绝门限做比较，根据比较结果从候选路径集合确定出L条路径作为第i个比特的保留路径。本发明实施例无需对所有路径的PM进行大小排序，避免了因排序运算而消耗大量的硬件资源和时间资源，提高了译码效率。

Description

极性码的译码方法和译码装置 技术领域
本发明实施例涉及编解码领域，并且更具体地，涉及Polar码（极性码）的译码方法和译码装置。
背景技术
通信系统通常采用信道编码提高数据传输的可靠性，保证通信的质量。Polar码是已被证明可以取得香农容量且具有低编译码复杂度的好码。Polar码是一种线性块码。其生成矩阵为GN.，其编码过程为
Figure PCTCN2015078033-appb-000001
这里
Figure PCTCN2015078033-appb-000002
码长N=2n，n≥0。
这里
Figure PCTCN2015078033-appb-000003
BN是转置矩阵，例如比特反转（bit reversal）矩阵。
Figure PCTCN2015078033-appb-000004
是F的克罗内克幂（Kronecker power），定义为
Figure PCTCN2015078033-appb-000005
Polar码用陪集码可以表示为
Figure PCTCN2015078033-appb-000006
其编码过程为：
Figure PCTCN2015078033-appb-000007
这里A为信息（information）比特索引的集合，GN.(A)是GN.中由集合A中的索引对应的那些行得到的子矩阵，GN.(AC)是GN.中由集合AC中的索引对应的那些行得到的子矩阵。
Figure PCTCN2015078033-appb-000008
是冻结（frozen）比特，其数量为(N-K)，是已知比特。为了简单，这些冻结比特可以设为0。
Polar码的译码可以用SC（successive-cancellation，连续消除）译码，其过程如下：
考虑一种Polar码，其参数为
Figure PCTCN2015078033-appb-000009
SC译码中，依次计算如下条件似然函数：
Figure PCTCN2015078033-appb-000010
如果
Figure PCTCN2015078033-appb-000011
如下作判决：
Figure PCTCN2015078033-appb-000012
如果
Figure PCTCN2015078033-appb-000013
简单令
Figure PCTCN2015078033-appb-000014
上述公式中，
Figure PCTCN2015078033-appb-000015
表示比特ui的判决值。
SC译码的复杂度为O(Nlog2N)。虽然SC译码在码长N很长的情况下能够取得好的性能，逼近香农限。但是当N较短或者中等长度的时候，Polar 码的SC译码的性能没有超过Turbo码和LDPC（Low-density Parity-check，低密度奇偶校验）码的性能，需要进一步提高译码性能。
在SC译码中是逐比特顺序译码，在译完每个比特之后是进行硬判后给后续比特译码使用，这样有可能存在错误传播，导致译码性能下降。List（列表）译码保留多条候选路径能够取得逼近最大似然的译码性能。SC译码和List译码结合就得到SC-List译码。
Polar码的SC-List译码的过程简述如下：
路径分裂：每次如果
Figure PCTCN2015078033-appb-000016
是信息比特（information bit），则将当前的译码路径分裂成两条路径：一条路径
Figure PCTCN2015078033-appb-000017
的和一条路径
Figure PCTCN2015078033-appb-000018
当总的路径数超出预定义的门限（可称为列表大小或搜索宽度）L的时候，丢弃最不可靠的路径，仅保持L条最可靠的路径（可称为幸存路径或保留路径）；并且更新所有路径上的概率值。L是正整数，L条最可靠的路径构成可靠路径集合（可称为幸存路径集合）。最终将可靠路径集合中具有最大路径度量值的译码路径对应的比特估计序列确定为所述极性码的译码结果。
无路径分裂：如果
Figure PCTCN2015078033-appb-000019
是冻结比特，则所有译码路径并不分裂，设
Figure PCTCN2015078033-appb-000020
保持路径数不变并且更新所有路径的概率值。
现有的SC-List译码采用固定数目的幸存路径数L，译码的复杂度为O(L×N×log2N)。具体地，现有SC-List译码的根据路径度量值PM从2L路径中选择出L个路径，其中一条路径对应一个PM值，2L条路径对应2L个PM值，现有解码器将2L个PM值由小到大排列，并将最小的L个PM值对应的路径（可靠路径）被选中继续进行解码，以此类推，获得最终的L条可靠路径。
然而，现有技术中对2L条路径的排序运算会消耗大量的硬件资源和时间资源，译码效率低。
发明内容
本发明实施例提供了一种极性码的译码方法和译码装置，该方法能够提高译码效率。
第一方面，提供了一种极性码的译码方法，其特征在于，包括：确定该极性码的第i个比特的候选路径集合中的每一条候选路径的路径度量值PM，其中，该第i个比特的候选路径集合由第i-1个比特的L条保留路径扩展得 到，该候选路径的数量小于或等于2L，L为预设的列表大小；将该候选路径集合中所有路径的PM与该第i个比特的接受门限和拒绝门限做比较，根据比较结果从该候选路径集合确定出L条路径作为该第i个比特的保留路径。
结合第一方面，在第一种实现方式中，该确定该极性码的第i个比特的候选路径集合中的每一条候选路径的路径度量值PM，包括：
根据以下公式确定该极性码的第i个比特的候选路径集合中的每一条候选路径的PM，
Figure PCTCN2015078033-appb-000021
Figure PCTCN2015078033-appb-000022
其他
其中，
Figure PCTCN2015078033-appb-000023
表示第i-1个比特的第l保留路径的硬判决值，
Figure PCTCN2015078033-appb-000024
表示第i-1个比特的第l保留路径的路径度量值，
Figure PCTCN2015078033-appb-000025
表示第i个比特中与第i-1个比特的第l保留路径对应的第一候选路径的路径度量值，
Figure PCTCN2015078033-appb-000026
表示第i个比特中与第i-1个比特的第l保留路径对应的第二候选路径的路径度量值，
Figure PCTCN2015078033-appb-000027
表示该极性码中第l路径第i个比特的对数似然值，l∈[1，L]。
结合第一种可能的实现方式，在第二种实现方式中，在将该候选路径集合中所有路径的PM分别与该第i个比特的接受门限和拒绝门限做比较，之前，还包括：根据该候选路径集合中所有路径的PM确定该第i个比特的接受门限和拒绝门限。
结合第二种可能的实现方式，在第三种实现方式中，该根据该候选路径集合中所有路径的PM确定该第i个比特的接受门限和拒绝门限，包括：将该候选路径集合中所有
Figure PCTCN2015078033-appb-000028
中的中位数，确定为该接受门限，将该候选路径集合中所有
Figure PCTCN2015078033-appb-000029
中大于该中位数中的多个PM中的一个确定为该拒绝门限。
结合第三种可能的实现方式，在第四种实现方式中，该将该候选路径集合中所有
Figure PCTCN2015078033-appb-000030
中大于该中位数中的多个PM中的一个确定为该拒绝门限，包括：将该候选路径集合中所有
Figure PCTCN2015078033-appb-000031
中的最大值或第二大值确定为该拒绝门限。
结合第一方面、第一至第四种可以的实现方式中的任一种可能的实现方式，在第五种可能的实现方式中，该将该候选路径集合中所有路径的PM分别与该第i个比特的接受门限和拒绝门限做比较，根据比较结果从该候选路径集合确定出L条路径作为该第i个比特的保留路径，包括：将该候选路径集合中的PM小于或等于接受门限的候选路径作为该第i个比特的保留路径 集合的第一子集，将该述候选路径集合中的PM大于接受门限且小于或等于拒绝门限的候选路径作为该第i个比特的保留路径集合的第二子集。
第二方面，提供了一种极性码的译码装置，包括：第一确定单元，用于确定该极性码的第i个比特的候选路径集合中的每一条候选路径的路径度量值PM，其中，该第i个比特的候选路径集合由第i-1个比特的L条保留路径扩展得到，该候选路径的数量小于或等于2L，L为预设的列表大小；第二确定单元，用于将该候选路径集合中所有路径的PM分别与该第i个比特的接受门限和拒绝门限做比较，根据比较结果从该候选路径集合确定出L条路径作为该第i个比特的保留路径。
结合第二方面，在第一种实现方式中，该第一确定单元根据以下公式确定该极性码的第i个比特的候选路径集合中的每一条候选路径的PM：
Figure PCTCN2015078033-appb-000032
Figure PCTCN2015078033-appb-000033
其他
其中，
Figure PCTCN2015078033-appb-000034
表示第i-1个比特的第l保留路径的硬判决值，
Figure PCTCN2015078033-appb-000035
表示第i-1个比特的第l保留路径的路径度量值，
Figure PCTCN2015078033-appb-000036
表示第i个比特中与第i-1个比特的第l保留路径对应的第一候选路径的路径度量值，
Figure PCTCN2015078033-appb-000037
表示第i个比特中与第i-1个比特的第l保留路径对应的第二候选路径的路径度量值，
Figure PCTCN2015078033-appb-000038
表示该极性码中第l路径第i个比特的对数似然值，l∈[1，L]。
结合第二方面的第一种可能的实现方式，在第二种实现方式中，还包括：
第三确定单元，用于根据该候选路径集合中所有路径的PM确定该第i个比特的接受门限和拒绝门限。
结合第二方面的第二种可能的实现方式，在第三种实现方式中，该第三确定单元将该候选路径集合中所有
Figure PCTCN2015078033-appb-000039
中的中位数，确定为该接受门限，将该候选路径集合中所有
Figure PCTCN2015078033-appb-000040
中大于该中位数中的多个PM中的一个确定为该拒绝门限。
结合第二方面的第三种可能的实现方式，在第四种实现方式中，该第三确定单元将该保留路径集合中所有
Figure PCTCN2015078033-appb-000041
中的最大值或第二大值确定为该拒绝门限。
结合第二方面、第二方面的第一至第四种可以的实现方式中的任一种可能的实现方式，在第五种可能的实现方式中，该第二确定单元将该候选路径 集合中的PM小于或等于接受门限的候选路径作为该第i个比特的保留路径集合的第一子集，将该述候选路径集合中的PM大于接受门限且小于或等于拒绝门限的候选路径作为该第i个比特的保留路径集合的第二子集。
基于上述技术方案，本发明实施例通过将第i比特的候选路径集合中所有路径的PM与接受门限和拒绝门限做比较，根据比较结果从候选路径集合确定出L条路径作为该第i比特的保留路径；无需对所有路径的PM进行大小排序，避免了因排序运算而消耗大量的硬件资源和时间资源，提高了译码效率。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明一个实施例的无线通信系统示意框图。
图2是根据本发明一个实施例的极性码的译码方法的示意性流程图。
图3是根据本发明一个实施例的码长为4的极化码的译码码树示意图。
图4是根据本发明一个实施例的极化码的译码方法中的路径选择示意框图。
图5是根据本发明另一实施例的极化码的译码方法中的路径选择示意框图。
图6是根据本发明一个实施例的译码方法与现有技术的译码方法在FER性能上仿真结果示意图。
图7是根据本发明一个实施例的极性码的译码装置的示意框图。
图8是根据本发明另一实施例的极性码的译码装置的示意框图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例可应用于各种通信系统，因此，下面的描述不限制于特定通信系统。全球移动通讯（Global System of Mobile communication，简称“GSM”）系统、码分多址（Code Division Multiple Access，简称“CDMA”）系统、宽带码分多址（Wideband Code Division Multiple Access，简称“WCDMA”）系统、通用分组无线业务（General Packet Radio Service，简称“GPRS”）、长期演进（Long Term Evolution，简称“LTE”）系统、LTE频分双工（Frequency Division Duplex，简称“FDD”）系统、LTE时分双工（Time Division Duplex，简称“TDD”）、通用移动通信系统（Universal Mobile Telecommunication System，简称“UMTS”）等。在上述的系统中的基站或者终端使用传统Turbo码、LDPC码编码处理的信息或者数据都可以使用本实施例中的Polar码编码。
图1示出了根据本文所述的各个实施例的无线通信系统100。系统100包括基站102，后者可包括多个天线组。例如，一个天线组可包括天线104和106，另一个天线组可包括天线108和110，附加组可包括天线112和114。对于每个天线组示出了2个天线，然而可对于每个组使用更多或更少的天线。基站102可附加地包括发射机链和接收机链，本领域普通技术人员可以理解，它们均可包括与信号发送和接收相关的多个部件（例如处理器、调制器、复用器、解调器、解复用器或天线等）。
基站102可以与一个或多个接入终端（例如接入终端116和接入终端122）通信。然而，可以理解，基站102可以与类似于接入终端116和122的基本上任意数目的接入终端通信。接入终端116和122可以是例如蜂窝电话、智能电话、便携式电脑、手持通信设备、手持计算设备、卫星无线电装置、全球定位系统、PDA和/或用于在无线通信系统100上通信的任意其它适合设备。如图所示，接入终端116与天线112和114通信，其中天线112和114通过前向链路118向接入终端116发送信息，并通过反向链路120从接入终端116接收信息。此外，接入终端122与天线104和106通信，其中天线104和106通过前向链路124向接入终端122发送信息，并通过反向链路126从接入终端122接收信息。在频分双工（Frequency Division Duplex，简称为“FDD”）系统中，例如，前向链路118可利用与反向链路120所使用的不同频带，前向链路124可利用与反向链路126所使用的不同频带。此外，在时分双工（Time Division Duplex，简称为“TDD”）系统中，前向链 路118和反向链路120可使用共同频带，前向链路124和反向链路126可使用共同频带。
被设计用于通信的每组天线和/或区域称为基站102的扇区。例如，可将天线组设计为与基站102覆盖区域的扇区中的接入终端通信。在通过前向链路118和124的通信中，基站102的发射天线可利用波束成形来改善针对接入终端116和122的前向链路118和124的信噪比。此外，与基站通过单个天线向它所有的接入终端发送相比，在基站102利用波束成形向相关覆盖区域中随机分散的接入终端116和122发送时，相邻小区中的移动设备会受到较少的干扰。
在给定时间，基站102、接入终端116和/或接入终端122可以是发送无线通信装置和/或接收无线通信装置。当发送数据时，发送无线通信装置可对数据进行编码以用于传输。具体地，发送无线通信装置可具有（例如生成、获得、在存储器中保存等）要通过信道发送至接收无线通信装置的一定数目的信息比特。这种信息比特可包含在数据的传输块（或多个传输块）中，其可被分段以产生多个码块。此外，发送无线通信装置可使用极性码编码器（未示出）来对每个码块编码，以提高数据传输的可靠性，进而保证通信质量。
图2是根据本发明一个实施例的极性码的译码方法的示意性流程图。如图2所示的译码方法可以由译码装置执行，具体的，如图2所示的译码方法，包括：
210，确定极性码的第i个比特的候选路径集合中的每一条候选路径的路径度量值PM，其中，第i个比特的候选路径集合由第i-1个比特的L条保留路径扩展得到，候选路径的数量小于或等于2L，L为预设的列表大小。
220，将候选路径集合中所有路径的PM与第i个比特的接受门限和拒绝门限做比较，根据比较结果从候选路径集合确定出L条路径作为第i个比特的保留路径。
具体而言，在极性码的译码过程中，在译码路径扩展到极性码的第i个比特时，确定第i个比特的候选路径集合中的每一条候选路径的PM，将候选路径集合中所有路径的PM与接受门限和拒绝门限做比较，根据比较结果从从候选路径集合中确定第i个比特的幸存路径（可称为可靠路径或保留路径）和删除路径，将幸存路径进行路径分裂（扩展）且将删除路径删除。其中，幸存路径的路径数量为L，删除路径的路径数量为L，应理解，在i＜N时， 可以将第i个比特的L条可靠路径的后继的路径（具有2L个）组成的集合确定为第i+1层的候选路径集合，或者在i＝N时，将第i个比特的L条可靠路径作为极性码的的最终的L个可靠路径，N为极性码比特的个数。换句话说，在译码完所有比特后，得到最终的L条可靠路径，并将该最终的L条可靠路径集合中具有最大路径度量值的译码路径对应的比特估计序列确定为该极性码的译码结果。
因此，本发明实施例通过将第i比特的候选路径集合中所有路径的PM与接受门限和拒绝门限做比较，根据比较结果从候选路径集合确定出L条路径作为该第i比特的保留路径；无需对所有路径的PM进行大小排序，避免了因排序运算而消耗大量的硬件资源和时间资源，提高了译码效率。
进一步地，现有技术中，从硬件实现的角度，对2L个PM值的排序需要较多的硬件资源和时延。例如，当采用双调排序（Bitonic）算法排序2L个PM值时，它将需要执行0.5L*(1+log2L)*(2+log2L)个比较运算。而且排序的时延长达0.5*(1+log2L)*(2+log2L)个比较器的延迟。而本发明实施例采用的门限比较需要非常少的硬件资源和运算时间。在基于门限比较的路径选择方案中，2L个PM值被并行的与两个门限AT和RT进行比较。因此，路径选择只需要4L个比较运算且这些比较运算可以被并行执行。因此，基于门限比较的路径选择只需要一个比较器的延迟。因此，获得AT与RT不会引入额外的时延。因此，基于门限比较的路径选择方案可以极大地减少列表解码器的时延。
应理解，在本发明实施例中，一个码长为N的极性码可以对应一个由N层边构成的二叉译码码树，其中，译码码树的第i层，对应极性码的第i位，在不存在冻结比特的情况下，除叶子节点（最后一位）外，译码码树中各节点均有2条后继节点，与该节点和该节点的两个后继节点相关联的两条边分别被标记为0和1。当存在冻结比特时，由于冻结比特的取值为一个预设的值，例如为0，所以冻结比特对应的节点中只有一个后继节点。所有的边根据与其相关联的、远离根节点的那个节点到根节点的距离被分为N层，最靠近根节点的为第1层，与叶子节点相关联的为第N层，例如，图3所示是一个码长为4的极性码的译码码树，其中，该译码树中不存在冻结比特的节点，该译码码树共有4层。
还应理解，第i比特位对应译码码树的第i层，在下文中，第i层与第i 比特可以表示相同的意思。
应注意，在本发明实施例中，第i个比特的候选路径的个数大于L时，才进行剪枝，即从候选路径集合中选出保留路径，在第i个比特的候选路径的个数小于L时，无需进行减枝，将所有的候选路径均作为保留路径。2L条后继路径中的每一条后继路径为译码码树上从根节点到第i层的一个节点构成的最短路径，删除候选路径的操作可以被称为剪枝操作，但本发明并不限于此。
上述本发明实施例中可以以第i层对应的极性码中的第i位均为信息比特位来说明的，当第i位为冻结比特位时，则所有译码路径并不分裂，保持路径数不变即可。还应理解，作为另一个实施例，本发明实施例中的译码方法可以只有一个比特采用图1所描述的方法，其他比特的译码采用现有技术；也可以多个比特采用图1所描述的方法，本发明实施例并不对此做限定。换句话说，本发明实施例中的第i个比特可以为极性码中的N个比特中的一个，例如，i的取值可以为M至N中的一个或多个，i也可以遍历取值M至N，其中，第M个比特的候选路径的条数大于L，本发明实施例并不限于此。
例如，码长为N的极性码解码过程可以被视为在一个深度为N的二叉树中进行搜索。由深度为i的节点输出的两枝对应于信息位ui的两个可能值，分别标记为“0”和“1”。特别地，对于frozen位，由于其总是取一个预设的值（例如“0”），对应的节点在二叉树中仅有一个子树。因此，在这样的二叉树中，由根节点到叶子节点的一条径表示一个可能的发送码字，即(u0，u1，u2，…，uN-1)。列表解码器是一个广度优先的搜索。在搜索深度i时，它最多保留L个最优的节点，对应于L条部分解码的路径，记作
Figure PCTCN2015078033-appb-000042
Figure PCTCN2015078033-appb-000043
在解码结束时，它可以输出L条可能的解码结果，从而提高极性码的纠错性能。
假设列表解码器解码ui+1位时，在ui位处的L条径pl(l=0,1,...,L-1)已经得到。当ui+1是frozen位时，对于该位的判决总是预设值（即“0”）。因此，L条部分解码路径更新如下：
Figure PCTCN2015078033-appb-000044
Figure PCTCN2015078033-appb-000045
当ui+1是信息位时，对于该位的判决可能为“0”或“1”。因此，L条解码路径可以产生2L条可能的部分解码路径
Figure PCTCN2015078033-appb-000046
Figure PCTCN2015078033-appb-000047
 为了控制搜索的复杂度，列表解码器仅在2L条路径中选择最优的L条后，再继续进行解码运算。其中，路径选择的依据是路径值PM。
可选地，作为另一实施例，在210中，根据以下公式确定极性码的第i个比特的候选路径集合中的每一条候选路径的PM，
Figure PCTCN2015078033-appb-000048
Figure PCTCN2015078033-appb-000049
其他
其中，
Figure PCTCN2015078033-appb-000050
表示第i-1个比特的第l保留路径的硬判决值，
Figure PCTCN2015078033-appb-000051
表示第i-1个比特的第l保留路径的路径度量值，
Figure PCTCN2015078033-appb-000052
表示第i个比特中与第i-1层的第l保留路径对应的第一候选路径的路径度量值，
Figure PCTCN2015078033-appb-000053
表示第i层中与第i-1层的第l保留路径对应的第二候选路径的路径度量值，
Figure PCTCN2015078033-appb-000054
表示极性码中第l路径第i比特的对数似然值，l∈[1，L]。
其中，第1比特的可靠路径为极性码中第一个信息位的似然函数值，例如，
Figure PCTCN2015078033-appb-000055
例如，假设ui位的L条路径p0,p1,…,pL-1的PM值依次是
Figure PCTCN2015078033-appb-000056
Figure PCTCN2015078033-appb-000057
在ui+1位，极性码解码器输出的关于该位的LLR为
Figure PCTCN2015078033-appb-000058
Figure PCTCN2015078033-appb-000059
由第l条路径扩展的解码路径为
Figure PCTCN2015078033-appb-000060
Figure PCTCN2015078033-appb-000061
或1。对应的ui+1位的2L条部分解码路径的PM值更新如下：
Figure PCTCN2015078033-appb-000062
在硬件实现中，上式变形如下，
Figure PCTCN2015078033-appb-000063
Figure PCTCN2015078033-appb-000064
其他  （1.2）
其中δ(x)＝0.5*(1-sign(x))。
由于传统的极性码列表解码器，当2L个PM值由上式更新后，它们被由小到大排列，最小的L个PM值对应的径被选中继续进行解码。但是，这样的排序运算会消耗大量的硬件资源和时间资源，而且，对于每一个信息位都要进行上述排序运算，照成大量的硬件资源和时间资源的消耗。基于此，本发明实施例提出了基于门限比较的路径选择。具体地，本发明实施例将候选路径集合中所有路径的PM与接受门限和拒绝门限做比较，根据比较结果从候选路径集合确定出L条路径作为该层的可靠路径集合；在i＜N时，将第i层的L条可靠路径的后继的路径组成的集合确定为第i+1层的候选路径集合，或者在i＝N时，将第i层的L条可靠路径作为极性码的的最终的L 个可靠路径。
因此，本发明实施例由于将候选路径集合中所有路径的PM与接受门限和拒绝门限做比较，根据比较结果从候选路径集合确定出L条路径作为该层的可靠路径集合；无需对所有路径的PM进行大小排序，避免了因排序运算而消耗大量的硬件资源和时间资源，提高了译码效率。
应理解，本发明实施例中的接受门限和拒绝门限可以是预先获得的，也可是根据PM确定的，或者根据其它方式确定的。也就是说，在220之前，本发明实施例方法还可以包括获取接受门限和拒绝门限。
具体地，当接受门限和拒绝门限由PM确定时，作为另一实施例，在220之前，本发明实施例方法还包括，根据候选路径集合中所有路径的PM确定第i层的接受门限和拒绝门限。换句话说，获取接受门限和拒绝门限，包括根据候选路径集合中所有路径的PM确定第i层的接受门限和拒绝门限。
应理解，接受门限（Accept Threshold，AT）和拒绝门限（Reject Threshold，RT）可以均称为剪枝门限。
应注意，为了获得第i信息位的AT和RT值，相应的PM值需要从L个PM值中获得。在本发明实施例中，这些运算（确定AT和RT值）可以与极性码解码器计算该信息位的LLR同时进行，因此，在本发明实施例中获得AT与RT不会引入额外的时延。因此，本发明实施例由于将候选路径集合中所有路径的PM与接受门限和拒绝门限做比较，根据比较结果从候选路径集合确定出L条路径作为该层的可靠路径集合；无需对所有路径的PM进行大小排序，避免了因排序运算而消耗大量的硬件资源和时间资源，提高了译码效率。
进一步地，作为另一实施例，根据候选路径集合中所有路径的PM确定第i层的接受门限和拒绝门限包括：
将候选路径集合中所有
Figure PCTCN2015078033-appb-000065
中的中位数，确定为接受门限，
将候选路径集合中所有
Figure PCTCN2015078033-appb-000066
中大于中位数中的多个PM中的一个确定为拒绝门限。
换句话说，将第i-1层的L个可靠路径的路径值中的中位数确定为第i层的接受门限，将第i-1层的L个可靠路径的路径值中大于中位数中的多个PM中的一个确定为第i层的拒绝门限。
进一步地，根据本发明实施例，可以将候选路径集合中所有
Figure PCTCN2015078033-appb-000067
中的最 大值或第二大值确定为拒绝门限。
换句话说，根据本发明实施例，可以将第i-1层的L个可靠路径的路径值中的最大值或第二大值确定为拒绝门限。
具体而言，从上述计算PM的公式可以看出，产生的2L条路径的PM可以被平均分为两组
Figure PCTCN2015078033-appb-000068
和
Figure PCTCN2015078033-appb-000069
Figure PCTCN2015078033-appb-000070
不失一般性，设
Figure PCTCN2015078033-appb-000071
那么，可以构造两个门限：接受门限（AT）和拒绝门限（RT）。其中，AT=PML/2（第i-1层的L个可靠路径的路径值中的中位数），RT=PML-1（第i-1层的L个可靠路径的路径值中最大值）。它们具有如下性质：
1，在2L个PM值里，至少有L个值大于等于AT。因为，两个PM组中后半部分的值均大于AT。同时，在2L个PM值里，至少有L/2个值小于等于AT，它们是第一个PM组中的前L/2个。
2，在2L个PM值里，至少有L个值小于等于RT，它们是第一个组中所有的PM值。
由上述确定AT和RT值的方法可以得到，本发明实施例中可以在极性码解码器计算第i信息位的LLR同时确定AT和RT值，因此，在本发明实施例中获得AT与RT不会引入额外的时延。并且，本发明实施例由于将候选路径集合中所有路径的PM与接受门限和拒绝门限做比较，根据比较结果从候选路径集合确定出L条路径作为该层的可靠路径集合；无需对所有路径的PM进行大小排序，避免了因排序运算而消耗大量的硬件资源和时间资源，提高了译码效率。
可选地，作为另一实施例，在220中，将候选路径集合中的PM小于或等于接受门限的候选路径作为第i个比特的保留路径集合的第一子集，将述候选路径集合中的PM大于接受门限且小于或等于拒绝门限的候选路径作为第i个比特的保留路径集合的第二子集。
应理解，第二子集为可靠路径集合中除第一子集之外的路径的集合。
具体而言，根据以上AT和RT的性质，本发明实施例提出了基于门限比较的路径选择方案：
当2L条路径的PM值生成后，与AT和RT分别进行比较。AS={l|PMl<AT},CS={l|AT≤PMl≤RT}。AS对应的路径必在被保留的L个路径（可靠路径）里且L/2≤|AS|≤L。对于剩余的(L-|AS|)条路径，它们被随机 地从CS中选出。
举例来说，当L=16，基于门限比较的路径选择方案被描述在图4中。如图4中第一区域所示，通过与AT的门限比较，至少最好的8条路径被选出，其中第一区域对应上述第一子集。如图4中第二区域所示，通过与RT的门限比较，最差的几条路径被排除。对于剩下的第三区域所示路径，路径被随机的选出以得到16条最优路径除第一区域外的最优的路径（对应第二子集）。从图4中可以看出，与精确排序的传统方法相比，随机选择路径不能保证始终选出最优的16条路径。因此，将引入性能损失。
为了减小因随机选择路径而引起的性能损失，可以适当地减少RT的值，例如RT=PML-2。如图5所示，这样可以增加被排除的路径数量，从而减小随机选择路径的机会。因此，基于门限比较的路径选择方案将引入极小的性能损失。
因此，本发明实施例通过将第i比特的候选路径集合中所有路径的PM与接受门限和拒绝门限做比较，根据比较结果从候选路径集合确定出L条路径作为该第i比特的保留路径；无需对所有路径的PM进行大小排序，避免了因排序运算而消耗大量的硬件资源和时间资源，提高了译码效率。
图6是本发明实施例的仿真实验结果示意图，具体地，图6示出了在MatLab中进行的数值仿真实验结果。其中，极性码长N=2048，码率1/2的极性码通过BPSK调制，在AWGN信道中传输。16位的循环冗余校验码被加入polar码的信息位。图6比较了L=16时，现有排序解码器和本发明实施例提出的基于门限的解码器的性能曲线图。其中现有排序解码器1采用公式1.1计算PM并将2L个PM排序，选择PM值中最小的L个路径译码，现有排序解码器2采用公式1.2计算PM并将2L个PM排序，选择PM值中最小的L个路径译码，本发明实施例的解码器1为基于本发明实施例门限比较的解码器，其中，拒绝门限为PM15，本发明实施例的解码器2基于本发明实例例门限比较的解码器，其中，拒绝门限为PM14，从图6中可以看出，本发明实施例中基于门限比较的路径选择方案的性能与现有排序解码器的性能基本一样，也就说本发明引入的性能损失几乎可以忽略。并且，本发明实施在保持性能的基础上，根据比较结果从候选路径集合确定出L条路径作为该第i比特的保留路径；无需对所有路径的PM进行大小排序，避免了因排序运算而消耗大量的硬件资源和时间资源，提高了译码效率。
上文中结合图1至图6详细描述了本发明实施例的极性码的译码方法，下面将结合图7至图8描述本发明实施例的极性码的译码装置。
图7是根据本发明一个实施例的极性码的译码装置的示意框图。如图7所示的译码装置700包括：第一确定单元710和第二确定单元720。
具体地，第一确定单元710用于确定极性码的第i个比特的候选路径集合中的每一条候选路径的路径度量值PM，其中，第i个比特的候选路径集合由第i-1个比特的L条保留路径扩展得到，候选路径的数量小于或等于2L，L为预设的列表大小。第二确定单元720用于将候选路径集合中所有路径的PM分别与第i个比特的接受门限和拒绝门限做比较，根据比较结果从候选路径集合确定出L条路径作为第i个比特的保留路径。
因此，本发明实施例通过将第i比特的候选路径集合中所有路径的PM与接受门限和拒绝门限做比较，根据比较结果从候选路径集合确定出L条路径作为该第i比特的保留路径；无需对所有路径的PM进行大小排序，避免了因排序运算而消耗大量的硬件资源和时间资源，提高了译码效率。
可选地，作为另一实施例，第一确定单元710根据以下公式确定极性码的第i个比特的候选路径集合中的每一条候选路径的PM：
Figure PCTCN2015078033-appb-000072
Figure PCTCN2015078033-appb-000073
其他
其中，
Figure PCTCN2015078033-appb-000074
表示第i-1个比特的第l保留路径的硬判决值，
Figure PCTCN2015078033-appb-000075
表示第i-1个比特的第l保留路径的路径度量值，
Figure PCTCN2015078033-appb-000076
表示第i个比特中与第i-1个比特的第l保留路径对应的第一候选路径的路径度量值，
Figure PCTCN2015078033-appb-000077
表示第i个比特中与第i-1个比特的第l保留路径对应的第二候选路径的路径度量值，表示极性码中第l路径第i个比特的对数似然值，l∈[1，L]。
可选地，作为另一实施例，译码装置700还包括第三确定单元，具体地，第三确定单元，用于根据候选路径集合中所有路径的PM确定第i个比特的接受门限和拒绝门限。
可选地，作为另一实施例第三确定单元将候选路径集合中所有
Figure PCTCN2015078033-appb-000079
中的中位数，确定为接受门限，将候选路径集合中所有
Figure PCTCN2015078033-appb-000080
中大于中位数中的多个PM中的一个确定为拒绝门限。
进一步地，作为另一实施例，第三确定单元将保留路径集合中所有
Figure PCTCN2015078033-appb-000081
中的最大值或第二大值确定为拒绝门限。
可选地，作为另一实施例，第二确定单元720将候选路径集合中的PM小于或等于接受门限的候选路径作为第i个比特的保留路径集合的第一子集，将述候选路径集合中的PM大于接受门限且小于或等于拒绝门限的候选路径作为第i个比特的保留路径集合的第二子集。
应理解，图7所示的极性码的译码装置700能够实现图1至图6所示的极性码的译码方法实施例中涉及译码装置的各个过程，图7所示的译码装置700的具体功能可参照图1至6中由译码装置完成的各个过程，为避免重复，此处不再赘述。
图8是根据本发明另一实施例的极性码的译码装置的示意框图。如图8所示的译码装置800包括：处理器810、存储器820和总线系统830。
具体地，处理器810用于通过总线系统830调用存储在存储器820中的代码，确定极性码的第i个比特的候选路径集合中的每一条候选路径的路径度量值PM，其中，第i个比特的候选路径集合由第i-1个比特的L条保留路径扩展得到，候选路径的数量小于或等于2L，L为预设的列表大小；
将候选路径集合中所有路径的PM与第i个比特的接受门限和拒绝门限做比较，根据比较结果从候选路径集合确定出L条路径作为第i个比特的保留路径。
因此，本发明实施例通过将第i比特的候选路径集合中所有路径的PM与接受门限和拒绝门限做比较，根据比较结果从候选路径集合确定出L条路径作为该第i比特的保留路径；无需对所有路径的PM进行大小排序，避免了因排序运算而消耗大量的硬件资源和时间资源，提高了译码效率。
上述本发明实施例揭示的方法可以应用于处理器810中，或者由处理器810实现。处理器810可能是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法的各步骤可以通过处理器810中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器810可以是通用处理器、数字信号处理器（Digital Signal Processor，DSP）、专用集成电路（Application Specific Integrated Circuit，ASIC）、现成可编程门阵列（Field Programmable Gate Array，FPGA）或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本发明实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结 合本发明实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存取存储器（Random Access Memory，RAM）、闪存、只读存储器（Read-Only Memory，ROM）、可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器820，处理器810读取存储器820中的信息，结合其硬件完成上述方法的步骤，该总线系统830除包括数据总线之外，还可以包括电源总线、控制总线和状态信号总线等。但是为了清楚说明起见，在图中将各种总线都标为总线系统830。
可选地，作为另一实施例，处理器810根据以下公式确定极性码的第i个比特的候选路径集合中的每一条候选路径的PM，
Figure PCTCN2015078033-appb-000082
Figure PCTCN2015078033-appb-000083
其他
其中，
Figure PCTCN2015078033-appb-000084
表示第i-1个比特的第l保留路径的硬判决值，
Figure PCTCN2015078033-appb-000085
表示第i-1个比特的第l保留路径的路径度量值，
Figure PCTCN2015078033-appb-000086
表示第i个比特中与第i-1个比特的第l保留路径对应的第一候选路径的路径度量值，
Figure PCTCN2015078033-appb-000087
表示第i个比特中与第i-1个比特的第l保留路径对应的第二候选路径的路径度量值，
Figure PCTCN2015078033-appb-000088
表示极性码中第l路径第i个比特的对数似然值，l∈[1，L]。
可选地，作为另一实施例，处理器810将可靠路径集合中所有
Figure PCTCN2015078033-appb-000089
中的中位数，确定为接受门限，将可靠路径集合中所有
Figure PCTCN2015078033-appb-000090
的中大于中位数中的多个PM中的一个确定为拒绝门限。
可选地，作为另一实施例，处理器810根据候选路径集合中所有路径的PM确定第i个比特的接受门限和拒绝门限。
具体地，作为另一实施例，处理器810将候选路径集合中所有
Figure PCTCN2015078033-appb-000091
中的中位数，确定为接受门限，将候选路径集合中所有
Figure PCTCN2015078033-appb-000092
的中大于中位数中的多个PM中的一个确定为拒绝门限。
进一步地，作为另一实施例，处理器810将将候选路径集合中所有
Figure PCTCN2015078033-appb-000093
中的最大值或第二大值确定为拒绝门限。
可选地，作为另一实施例，处理器810将候选路径集合中的PM小于或等于接受门限的候选路径作为第i个比特的保留路径集合的第一子集，将述候选路径集合中的PM大于接受门限且小于或等于拒绝门限的候选路径作为 第i个比特的保留路径集合的第二子集。
应理解，图8所示的极性码的译码装置800与图7所示的译码装置700相对应，能够实现图1至图6所示的极性码的译码方法实施例中涉及译码装置的各个过程，图8所示的译码装置800的具体功能可参照图1至6中由译码装置完成的各个过程，为避免重复，此处不再赘述。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本发明的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本发明的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本发明实施例的实施过程构成任何限定。
另外，本文中术语“系统”和“网络”在本文中常被可互换使用。本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
应理解，在本发明实施例中，“与A相应的B”表示B与A相关联，根据A可以确定B。但还应理解，根据A确定B并不意味着仅仅根据A确定B，还可以根据A和/或其它信息确定B。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和 方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、装置或单元的间接耦合或通信连接，也可以是电的，机械的或其它的形式连接。
作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本发明实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以是两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到本发明可以用硬件实现，或固件实现，或它们的组合方式来实现。当使用软件实现时，可以将上述功能存储在计算机可读介质中或作为计算机可读介质上的一个或多个指令或代码进行传输。计算机可读介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是计算机能够存取的任何可用介质。以此为例但不限于：计算机可读介质可以包括RAM、ROM、EEPROM、CD-ROM或其他光盘存储、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质。此外。任何连接可以适当的成为计算机可读介质。例如，如果软件是使用同轴电缆、光纤光缆、双绞线、数字用户线（DSL）或者诸如红外线、无线电和微波之类的无线技术从网站、服务器或者其他远程源传输的，那么同轴电缆、光纤光缆、双绞线、DSL或者诸如红外线、无线和微波之类的无线技术包括在所属介质的定影中。如本发明所使用的，盘（Disk）和碟（disc）包括压缩光碟（CD）、激光碟、光碟、数字通用光碟（DVD）、软盘和蓝光光碟，其中盘通常磁性的复制数据，而碟则用激光来光学的复制数据。上面的组合也应当包括在计算机可读介质的保护范围之内。
总之，以上所述仅为本发明技术方案的较佳实施例而已，并非用于限定本发明的保护范围。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (12)

  1. 一种极性码的译码方法，其特征在于，包括：
    确定所述极性码的第i个比特的候选路径集合中的每一条候选路径的路径度量值PM，其中，所述第i个比特的候选路径集合由第i-1个比特的L条保留路径扩展得到，所述候选路径的数量小于或等于2L，L为预设的列表大小；
    将所述候选路径集合中所有路径的PM与所述第i个比特的接受门限和拒绝门限做比较，根据比较结果从所述候选路径集合确定出L条路径作为所述第i个比特的保留路径。
  2. 根据权利要求1所述的译码方法，其特征在于，所述确定所述极性码的第i个比特的候选路径集合中的每一条候选路径的路径度量值PM，包括：
    根据以下公式确定所述极性码的第i个比特的候选路径集合中的每一条候选路径的PM，
    Figure PCTCN2015078033-appb-100001
    Figure PCTCN2015078033-appb-100002
    其他
    其中，
    Figure PCTCN2015078033-appb-100003
    表示第i-1个比特的第l保留路径的硬判决值，
    Figure PCTCN2015078033-appb-100004
    表示第i-1个比特的第l保留路径的路径度量值，
    Figure PCTCN2015078033-appb-100005
    表示第i个比特中与第i-1个比特的第l保留路径对应的第一候选路径的路径度量值，
    Figure PCTCN2015078033-appb-100006
    表示第i个比特中与第i-1个比特的第l保留路径对应的第二候选路径的路径度量值，
    Figure PCTCN2015078033-appb-100007
    表示所述极性码中第l路径第i个比特的对数似然值，l∈[1，L]。
  3. 根据权利要求2所述的译码方法，其特征在于，在将所述候选路径集合中所有路径的PM分别与所述第i个比特的接受门限和拒绝门限做比较，之前，还包括：
    根据所述候选路径集合中所有路径的PM确定所述第i个比特的接受门限和拒绝门限。
  4. 根据权利要求3所述的译码方法，其特征在于，所述根据所述候选路径集合中所有路径的PM确定所述第i个比特的接受门限和拒绝门限，包括：
    将所述候选路径集合中所有
    Figure PCTCN2015078033-appb-100008
    中的中位数，确定为所述接受门限，
    将所述候选路径集合中所有
    Figure PCTCN2015078033-appb-100009
    中大于所述中位数中的多个PM中的一个确定为所述拒绝门限。
  5. 根据权利要求4所述的译码方法，其特征在于，所述将所述候选路径集合中所有
    Figure PCTCN2015078033-appb-100010
    中大于所述中位数中的多个PM中的一个确定为所述拒绝门限，包括：
    将所述候选路径集合中所有
    Figure PCTCN2015078033-appb-100011
    中的最大值或第二大值确定为所述拒绝门限。
  6. 根据权利要求1至5中任一项所述的译码方法，其特征在于，
    所述将所述候选路径集合中所有路径的PM分别与所述第i个比特的接受门限和拒绝门限做比较，根据比较结果从所述候选路径集合确定出L条路径作为所述第i个比特的保留路径，包括：
    将所述候选路径集合中的PM小于或等于接受门限的候选路径作为所述第i个比特的保留路径集合的第一子集，
    将所述述候选路径集合中的PM大于接受门限且小于或等于拒绝门限的候选路径作为所述第i个比特的保留路径集合的第二子集。
  7. 一种极性码的译码装置，其特征在于，包括：
    第一确定单元，用于确定所述极性码的第i个比特的候选路径集合中的每一条候选路径的路径度量值PM，其中，所述第i个比特的候选路径集合由第i-1个比特的L条保留路径扩展得到，所述候选路径的数量小于或等于2L，L为预设的列表大小；
    第二确定单元，用于将所述候选路径集合中所有路径的PM分别与所述第i个比特的接受门限和拒绝门限做比较，根据比较结果从所述候选路径集合确定出L条路径作为所述第i个比特的保留路径。
  8. 根据权利要求7所述的译码装置，其特征在于，
    所述第一确定单元根据以下公式确定所述极性码的第i个比特的候选路径集合中的每一条候选路径的PM：
    Figure PCTCN2015078033-appb-100012
    Figure PCTCN2015078033-appb-100013
    其他
    其中，
    Figure PCTCN2015078033-appb-100014
    表示第i-1个比特的第l保留路径的硬判决值，
    Figure PCTCN2015078033-appb-100015
    表示第i-1个比特的第l保留路径的路径度量值，
    Figure PCTCN2015078033-appb-100016
    表示第i个比特中与第i-1个比特的第l保留路径对应的第一候选路径的 路径度量值，
    Figure PCTCN2015078033-appb-100017
    表示第i个比特中与第i-1个比特的第l保留路径对应的第二候选路径的路径度量值，
    Figure PCTCN2015078033-appb-100018
    表示所述极性码中第l路径第i个比特的对数似然值，l∈[1，L]。
  9. 根据权利要求8所述的译码装置，其特征在于，还包括：
    第三确定单元，用于根据所述候选路径集合中所有路径的PM确定所述第i个比特的接受门限和拒绝门限。
  10. 根据权利要求9所述的译码装置，其特征在于，
    所述第三确定单元将所述候选路径集合中所有
    Figure PCTCN2015078033-appb-100019
    中的中位数，确定为所述接受门限，将所述候选路径集合中所有
    Figure PCTCN2015078033-appb-100020
    中大于所述中位数中的多个PM中的一个确定为所述拒绝门限。
  11. 根据权利要求10所述的译码装置，其特征在于，所述第三确定单元将所述保留路径集合中所有
    Figure PCTCN2015078033-appb-100021
    中的最大值或第二大值确定为所述拒绝门限。
  12. 根据权利要求7至11中任一项所述的译码装置，其特征在于，
    所述第二确定单元将所述候选路径集合中的PM小于或等于接受门限的候选路径作为所述第i个比特的保留路径集合的第一子集，将所述述候选路径集合中的PM大于接受门限且小于或等于拒绝门限的候选路径作为所述第i个比特的保留路径集合的第二子集。
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