WO2018137635A1 - Polar码编译码方法及装置 - Google Patents

Polar码编译码方法及装置 Download PDF

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WO2018137635A1
WO2018137635A1 PCT/CN2018/073908 CN2018073908W WO2018137635A1 WO 2018137635 A1 WO2018137635 A1 WO 2018137635A1 CN 2018073908 W CN2018073908 W CN 2018073908W WO 2018137635 A1 WO2018137635 A1 WO 2018137635A1
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crc
bit
bits
information
check
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PCT/CN2018/073908
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English (en)
French (fr)
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张公正
张华滋
乔云飞
李榕
王俊
王桂杰
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华为技术有限公司
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Priority to EP18745275.0A priority Critical patent/EP3562071B1/en
Publication of WO2018137635A1 publication Critical patent/WO2018137635A1/zh
Priority to US16/519,988 priority patent/US11025278B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615—Use of computational or mathematical techniques
    • H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H04L69/324—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC

Definitions

  • Embodiments of the present invention relate to the field of wireless communications, and in particular, to a Polar code encoding and decoding method and apparatus.
  • Polar code (Polar codes) proposed by Turkish professor Arikan is the first good code that theoretically proves to reach Shannon's capacity and has low coding and decoding complexity.
  • the Polar code is a linear block code whose coding matrix is G N and the encoding process is among them Is a binary line vector with a length of N (ie, the length of the mother code); G N is an N ⁇ N matrix, and Defined as the Kronecker product of log 2 N matrices F 2 .
  • G N. (A) is a sub-matrix obtained from those rows corresponding to the index in the set A in G N.
  • G N (A C ) is obtained from the rows corresponding to the indexes in the set A C in G N . Submatrix.
  • the encoded output of the Polar code can be simplified to: Is a K ⁇ N matrix.
  • the construction process of the Polar code is a collection
  • the selection process determines the performance of the Polar code.
  • the construction process of the Polar code is generally: determining that there are N polarized channels in total according to the length N of the mother code, respectively corresponding to N rows of the coding matrix, calculating the reliability of the polarized channel, and the first K polarizations with higher reliability.
  • the index of the channel is the element of set A, and the index corresponding to the remaining (NK) polarized channels is used as the index set of fixed bits.
  • Set A determines the position of the information bits, the set The position of the fixed bit is determined.
  • the Polar code can use a serial cancellation (English: Successive Cancellation, SC) decoding algorithm, and sequentially decodes from the first bit.
  • the Serial Cancellation List (SCL) decoding algorithm is an improvement of the SC decoding algorithm, and multiple candidate decoding results are retained in the decoding process.
  • SCL regards the decoding process as a path search process, that is, the path is extended by using the first bit as the root node, and the path is evaluated by a metric value, which is dynamically updated according to a predetermined rule as the path is expanded. .
  • the extension decoding the next bit
  • the L candidate paths with the best path metric in the current layer are retained until the last layer is extended (the last bit is decoded).
  • the path with the best metric value among the L candidate paths is output as the decoding output.
  • the SCL decoding algorithm can obtain maximum likelihood decoding performance.
  • the CA-Polar code is a Polar code of a CRC (Cyclic Redundancy Check), which is referred to as a CA-Polar code.
  • the MPEG is encoded by the CRC, and the encoded bits are mapped into the information bits.
  • the CA-SCL (CRC-Aided Successive Cancellation List) decoding algorithm is used for decoding, that is, the candidate path through which the CRC passes is selected as the decoding output among the L candidate paths outputted by the SCL decoding. If the correct path is deleted at the intermediate node of the CA-SCL decoding because the metric value is poor, the subsequent CRC check cannot improve the performance of the SCL decoding.
  • the embodiment of the present application provides a Polar code encoding method, an encoding device, a decoding method, and a decoding device, which can further improve the performance of the CA-Polar code.
  • a Polar coding method including:
  • Determining at least one of the frozen bits as a check freeze bit the value of the check freeze bit being determined by a value of P information bits that meet a preset condition in the information bits before the check freeze bit, P An integer greater than or equal to 1;
  • Polar coding is performed on the information bits, the check freeze bits, and other freeze bits other than the check freeze bits.
  • an encoding apparatus including:
  • An acquiring unit configured to obtain, according to a reliability order of the polarization channel, a location of the information bit and the frozen bit, where the reliability of the polarization channel corresponding to the information bit is higher than the reliability of the polarization channel corresponding to the frozen bit;
  • a CRC coding unit configured to perform cyclic redundancy check CRC coding on the information block, and map the CRC encoded bit to the information bit;
  • a determining unit configured to determine at least one bit of the frozen bit as a check freeze bit, where the value of the check freeze bit is P information bit that meets a preset condition in the information bit before the check freeze bit The value determines that P is an integer greater than or equal to 1;
  • a Polar coding unit configured to perform Polar coding on the information bits, the check freeze bits, and other freeze bits other than the check freeze bits.
  • an encoding apparatus including:
  • a processor configured to execute the program stored by the memory, when the program is executed, the processor is configured to obtain information bits and locations of freeze bits according to reliability ranking of the polarized channels, where the information bits correspond to The reliability of the polarized channel is higher than the reliability of the polarized channel corresponding to the frozen bit, performing cyclic redundancy check CRC coding on the information block, mapping the CRC encoded bit to the information bit, and determining the At least one of the frozen bits is used as a check freeze bit, and the value of the check freeze bit is determined by a value of P information bits that meet a preset condition in the information bits before the check freeze bit, and P is greater than or equal to An integer of 1; Polar coding of the information bits, the check freeze bits, and other freeze bits other than the check freeze bits.
  • an encoding apparatus including:
  • At least one input terminal for receiving information blocks
  • a signal processor configured to obtain information bits and locations of freeze bits according to reliability ranking of the polarized channels, where the reliability of the polarized channels corresponding to the information bits is higher than the reliability of the polarized channels corresponding to the frozen bits, Performing cyclic redundancy check CRC coding on the information block, mapping CRC encoded bits to the information bits, determining at least one bit of the frozen bits as a check freeze bit, and the value of the check freeze bit is determined by Determining, in the information bits before the freeze bit, the value of the P information bits that meet the preset condition, P is an integer greater than or equal to 1; freezing the information bit, the check freeze bit, and the checksum Other frozen bits other than bits are Polar encoded;
  • At least one output for outputting a coded block obtained by the signal processor At least one output for outputting a coded block obtained by the signal processor.
  • a Polar decoding method including:
  • the serially canceled list SCL decoding algorithm is used to decode the to-be-decoded bits in order, and output L candidate paths with optimal metric values, and the decoding result of each candidate path includes information blocks and cyclic redundancy check.
  • a CRC bit wherein, the value of the check freeze bit in each path is determined by a value obtained by decoding P information bits that meet a preset condition in the information bits before the check freeze bit, and P is greater than or equal to 1 Integer
  • the L candidate path is subjected to CRC check, and the information block in the first candidate path through which the CRC check passes is used as a decoding output.
  • a decoding apparatus including:
  • An acquiring unit configured to acquire a position of the information bit and the frozen bit in the bit to be decoded, and determine at least one bit of the frozen bit as a check freeze bit;
  • a decoding unit configured to sequentially decode the to-be-decoded bits by using a serial cancellation list SCL decoding algorithm, and output L candidate paths with optimal metric values, where the decoding result of each candidate path includes an information block And a cyclic redundancy check CRC bit; wherein, the value of the check freeze bit in each path is determined by a value obtained by decoding P information bits that meet a preset condition in the information bits before the check freeze bit , P is an integer greater than or equal to 1;
  • a CRC check unit configured to perform a CRC check on the L candidate paths starting from a candidate path with an optimal metric value
  • an output unit configured to use the information block in the first candidate path through which the CRC check passes as a decoding output.
  • a decoding apparatus including:
  • a processor configured to execute the program stored by the memory, when the program is executed, the processor is configured to acquire a position of an information bit and a frozen bit in a bit to be decoded, and determine at least one of the frozen bits
  • One bit is used as a check freeze bit; the bit to be decoded is sequentially decoded by using a serial offset list SCL decoding algorithm, and L candidate paths with the best metric value are output, and the decoding result of each candidate path includes An information block and a cyclic redundancy check CRC bit, wherein a value of the check freeze bit in each path is obtained by decoding P information bits that meet a preset condition among information bits before the check freeze bit The value is determined, P is an integer greater than or equal to 1; starting from the candidate path with the best metric value, performing CRC check on the L candidate paths, and using the information block in the first candidate path through which the CRC check is used as a translation Code output.
  • a decoding apparatus including:
  • At least one input terminal for receiving bit information to be decoded
  • a signal processor configured to acquire a position of the information bit and the frozen bit in the bit to be decoded, determine at least one bit of the frozen bit as a check freeze bit; use the serial offset list SCL decoding algorithm to sequentially The bit to be decoded is decoded, and the L candidate paths with the best metric value are output, and the decoding result of each candidate path includes an information block and a cyclic redundancy check CRC bit, wherein the check freeze in each path is frozen.
  • the value of the bit is determined by a value obtained by decoding the P information bits that meet the preset condition in the information bits before the check frozen bit, and P is an integer greater than or equal to 1; starting from the candidate path with the best metric value, Performing a CRC check on the L candidate paths;
  • At least one output terminal is used for decoding the information block in the first candidate path through which the CRC check passes.
  • the sequence numbers of the P information bits are the same as the value of the sequence modulo Q of the check freeze bit, and Q is an integer greater than or equal to 1.
  • the Q is a prime or an odd number.
  • the Q is 3, 5, 7, or 9.
  • the P information bits that meet the preset condition are information bits that are randomly determined from all information bits before the check freeze bit. .
  • a random number is generated by using a random seed for each information bit preceding the check freeze bit, if the random number The number is less than the preset threshold T, and the information bit participates in determining the value of the check freeze bit.
  • the random seed generates a random number uniformly distributed between 0 and 1, and T is a value greater than 0 and less than 1.
  • the threshold T is a value equal to or equal to 1/3 or 1/5.
  • the P information bits are information bits corresponding to the sequence number of the check freeze bit, the same as the sequence number Q or the modulo M, and the Q and the M are not mutually The same prime number or odd number; or the sequence number of the P information bits is an odd number or a prime number; or the P information bits include: a serial number modulo Q1, a modulo Q2, ..., or a modulo Qh of the sequence and the check frozen bit
  • the information bits have the same value, h is an integer greater than or equal to 2, and Q1, Q2, ..., Qh are integers greater than or equal to 1 and different from each other.
  • modulo When it is determined by modulo which information bits participate in determining the value of the check frozen bit, it may be modulo by a number, for example 5, or two or more numbers at the same time, for example, the parity block with the checksum 3. Information bits corresponding to all sequence numbers of the same value of modulo 5 or modulo 7 are used to determine the value of the check freeze bit.
  • the one information bit is the one that is closest to the check freeze bit, and the sequence number of the check freeze bit is the same as the one
  • the difference between the sequence numbers of the information bits is not equal to the integer power of 2.
  • all the frozen bits are check freeze bits; if the information bits satisfying the preset condition are not present before the check freeze bits, Then the check freeze bit remains as a freeze bit and is set to a fixed value.
  • the number of 1s in the vector obtained by adding the bit vector of the bit is larger than the number of 1 in the coding matrix corresponding to the row vector of any of the information bits.
  • the information bits and the frozen bits are ordered according to a natural order of the polarized channels.
  • the shift register is used to select p information bits.
  • performing cyclic redundancy check on the information block CRC coding includes any one of the following :
  • CRC-encoded bits include an information block and K CRC CRC bits, where K CRC is a preset fixed CRC length;
  • CRC encoded bits include information blocks and (K CRC + K' CRC ) CRC bits, where K CRC is a preset fixed CRC Length, K' CRC is the extra CRC length; or
  • the first-level CRC-encoded bit includes an information block and K CRC CRC bits, and the first-level CRC-encoded bit is used as an overall block.
  • the second-level CRC encoding to obtain a second-level CRC-encoded bit including an information block, K CRC first-level CRC bits, and K' CRC second-level CRC bits Where K CRC is a fixed CRC length set in advance, and K' CRC is an extra CRC length;
  • K CRC , K CRC , and K' CRC are integers greater than zero.
  • the CRC encoding After the latter bits are mapped to the information bits, the CRC bits and the location of the information block include any of the following:
  • the CRC bits are arranged after the information block;
  • the CRC bits are placed before the information block; or
  • CRC bits are arranged between blocks of information
  • the CRC bits are divided into a plurality of segments, each segment being located anywhere between the information blocks, before the information block, or after the information block.
  • the metric value is a path value PM.
  • the decoded output is either determined to be a decoding failure.
  • a ninth aspect of the present application is directed to a computer readable storage medium having instructions stored therein that, when executed on a computer, cause the computer to perform the various aspects or various possible implementations described above The encoding method or decoding method.
  • Yet another aspect of the present application provides a computer program product comprising instructions which, when executed on a computer, cause the computer to perform the encoding method or the decoding method described in the above aspects or various possible implementations.
  • Yet another aspect of the present application provides a computer program that, when executed on a computer, causes the computer to perform the encoding method or the decoding method described in the above aspects or various possible implementations.
  • some or all of the frozen bits are determined as the check freeze bits from the frozen bits of the Polar code, and the values of the check freeze bits are determined by the values of the previous information bits.
  • the check freeze bit is related to the previous information bit. If the previous information bit is decoded incorrectly, the value of the check freeze bit calculated according to the information is more likely to be inconsistent with the LLR received by the check freeze bit.
  • the metric value of the path is deteriorated, so that the error path is more likely to be deleted when the metric values of the candidate path are sorted, thereby improving the performance of the CA-SCL decoding.
  • FIG. 1 is a schematic diagram of a basic flow of a wireless communication transmitting end and a receiving end;
  • 2a is a schematic diagram of path expansion and metric calculation in the case where the LLR of the current bit is greater than 0 in the embodiment of the present application;
  • 2b is a schematic diagram showing path extension and metric calculation in the case where the LLR of the current bit is less than 0 in the embodiment of the present application;
  • FIG. 3 is a schematic diagram of a path extension and PM value update of SCL decoding
  • FIG. 4 is a schematic diagram of a process of CA-Polar coding
  • Figure 5 is a schematic illustration of a CA-Polar configuration
  • FIG. 6 is a schematic diagram of an encoding process provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of an encoding apparatus provided by an implementation of the present application.
  • FIG. 8 is a schematic flowchart diagram of an encoding method provided by an implementation of the present application.
  • FIG. 9 is a schematic diagram of a CA-Polar structure provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of relationship between each dynamic check bit and its previous information bits in the embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of still another encoding apparatus provided by the implementation of the present application.
  • FIG. 12 is a schematic structural diagram of still another encoding apparatus provided by the implementation of the present application.
  • FIG. 13 is a schematic structural diagram of a decoding apparatus provided by an implementation of the present application.
  • 15 is a schematic diagram of path extension and path value update of SCL decoding provided by an embodiment of the present application.
  • 16 is a performance simulation result of a compiled code method provided by the implementation of the present application and a conventional CA-Polar;
  • 17 is a schematic structural diagram of still another decoding apparatus provided by the implementation of the present application.
  • FIG. 18 is a schematic structural diagram of still another decoding apparatus provided by the implementation of the present application.
  • Figure 19 is a Polar coding matrix having a mother code length of 32;
  • FIG. 20 is a schematic diagram of a principle of a segmented CRC coding according to an embodiment of the present application.
  • FIG. 21 is a schematic flowchart of still another coding method according to an embodiment of the present application.
  • FIG. 22 is a schematic diagram showing the positional relationship between a CRC bit and an information block in a CRC encoded bit according to an embodiment of the present application.
  • the technical solution of the embodiment of the present application can be applied to a 5G communication system or a future communication system, and can also be applied to other various wireless communication systems, such as a Global System of Mobile communication (GSM) system, and code division multiple access (CDMA, Code Division Multiple Access system, Wideband Code Division Multiple Access (WCDMA) system, General Packet Radio Service (GPRS), Long Term Evolution (LTE) system, LTE Frequency Division Duplex (FDD) system, LTE Time Division Duplex (TDD), Universal Mobile Telecommunication System (UMTS), and the like.
  • GSM Global System of Mobile communication
  • CDMA Code Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access
  • GPRS General Packet Radio Service
  • LTE Long Term Evolution
  • FDD Frequency Division Duplex
  • TDD Time Division Duplex
  • UMTS Universal Mobile Telecommunication System
  • FIG. 1 is a basic flow of wireless communication.
  • the source is sequentially transmitted after source coding, channel coding, and digital modulation.
  • digital demodulation, channel decoding, and source decoding are sequentially outputted to the sink.
  • the channel codec can use a Polar code, and in channel decoding, SC decoding and SCL decoding can be used.
  • the SCL decoding algorithm is an improvement on the SC decoding algorithm. Multiple candidate paths are reserved in the decoding process, and finally a path is selected as the decoding result according to the metric value of each candidate path.
  • the metric value of the l- th path, PM l (i), that is, the path value (English: path metric, PM) is the metric value when decoding to the ith bit, as shown in formula (1) (setting LLR> The value corresponding to 0 is 0, and the value corresponding to LLR ⁇ 0 is 1):
  • LLR(i) is the log-likelihood ratio (LLR) of the current bit.
  • the value corresponding to the LLR may be 0 or 1, for example, when LLR ⁇ 0, the corresponding value is 1, and when LLR>0, the corresponding value is 0.
  • the PM is unchanged; if the value corresponding to the LLR of the current bit (0 or 1) is inconsistent with the decision result, the PM increases the penalty value
  • each path is expanded into two paths, a total of 2L paths are extended, and L is the number of candidate paths that need to be reserved.
  • the decision result of each node is 0 and 1, respectively, and the PM of each path is calculated according to the above formula, and then the extended path is sorted according to the PM, the L paths with the smallest PM are reserved, and the remaining L paths are deleted, also called a clipping. branch. If the current bit is a frozen bit, the corresponding node in each path does not expand, directly determines the corresponding known fixed value, and calculates the PM of each path according to formula (1).
  • the following describes the value corresponding to 1 when LLR ⁇ 0, and the value corresponding to 0 when LLR>0.
  • the LLR(i) of the current decoding bit is greater than 0 (the corresponding value is 0)
  • the current bit is an information bit in the path extension process
  • two paths need to be extended.
  • the result of the decision is inconsistent with the value corresponding to the LLR (indicated by "x" in Fig.
  • PM(i) PM(i-1) +
  • the known fixed value is 0 and the LLR corresponding value is also 1, the known fixed value does not match the value corresponding to the LLR.
  • PM(i) PM(i-1)+
  • ; if the known fixed value is 1, the known fixed value is consistent with the value corresponding to the LLR, PM(i) PM (i-1).
  • Fig. 2(a) and Fig. 2(b) by retaining the path with the smallest PM value at each expansion, two candidate paths L1 and L2 as indicated by the arrows are finally obtained.
  • the final PM value of the path L1 is 0.0, and the PM value of the other path L2 is finally 0.2. Therefore, the 0.0 path L1 with a small PM is selected as the decoding output, and the value of the decoded information bits is 0011.
  • CA-Polar Polar Code Cascading CRC (Cyclic Redundancy Check), referred to as CA-Polar
  • CA-SCL CRC-Aided Successive Cancellation List
  • CA-Polar code construction process assuming that the information block size is K info , the CRC length is K crc , and the mother code length of the Polar code is N, it is necessary to select K info + K crc from the N polarized channels. As the information bits, the rest are used as frozen bits.
  • the CA-Polar encoding process is as shown in FIG. 4, which first performs CRC encoding on the information block, then maps the CRC encoded bit to the position of the information bit, and places a fixed value agreed by the transmitting end and the receiving end at the position of the frozen bit, and then Then perform Polar coding to obtain a CA-Polar coding block.
  • the information block and the CRC bits are unknown, and decoding is performed according to the normal SCL decoding process.
  • L candidate decoding results are obtained, and the decoding result includes an information block and a CRC bit.
  • the CRC is checked for each candidate result. If the check passes, the information block of the path is used as the decoding output. If the CRC check fails, the information block of the path with the smallest PM is obtained. As the decoding output, it is also possible to directly indicate the decoding failure.
  • the CRC bits are treated as information bits, and the CRC bits are used to assist in selecting the path at the end of SCL decoding. But at the intermediate node of SCL, the correct path may be deleted because of the larger PM.
  • a check freeze bit is added in the CA-Polar, and the value of the check freeze bit is determined by the value of the information bit in front of it, that is, the previous information bit is verified by using the check freeze bit. It is used to assist CA-Polar's SCL decoding, improve the probability of deleting the wrong path at the intermediate node, and improve the performance of CA-Polar.
  • the check freeze bit here is referred to with respect to the original freeze bit, indicating that a portion of the original freeze bit is selected for placing a value associated with the information bit, that is, the freeze bit is used to verify the bit before. At least one information bit.
  • the check freeze bit can also be called a parity bit or a parity freeze bit.
  • such frozen bits may also be called dynamic freeze bits.
  • the parameters of the information block size and code length are different each time, and such dynamic freeze bit positions may change, and may not always be fixed at a certain position.
  • the corresponding remaining frozen bits can be called static freeze bits. For convenience of description, the following is collectively referred to as a check freeze bit.
  • the encoding process includes:
  • CRC coding According to the CA-Polar construction algorithm, a highly reliable polarization channel is selected as the information bit, the information block is CRC-coded, and the coded bits are mapped to information bits;
  • Polar coding Polar coding the information bits, the check frozen bits and the remaining frozen bits to obtain a Polar coded block
  • the SCL decoding algorithm is used for decoding, and the check frozen bit is treated as a frozen bit without path expansion, but the value of the frozen bit is verified by the value and check of the information bit obtained by the previous decoding.
  • the equation is determined; after the SCL decoding is completed, L candidate paths are obtained, and the path through which the CRC check passes is selected from the candidate paths by the CRC as the decoding output.
  • the CRC can be used to select the decoding result from the candidate path, or can be used for error detection to determine whether the decoding result is correct or not.
  • the check freeze bit Since the value of the check freeze bit is determined by the value of the information bit obtained by the previous decoding and the check equation, once the previously decoded information bit is incorrect, the check freeze bit passes when the check freeze bit is decoded.
  • the value of the calculated information bit and the value corresponding to the received LLR may increase.
  • the PM value is added according to the calculation of the above formula (1).
  • the absolute value of the bit LLR thereby increasing the PM value of the path, which is more likely to be deleted during subsequent decoding.
  • the encoding device 700 shown in FIG. 7 can perform an encoding method. As shown in FIG. 7, the encoding method of the embodiment of the present application may include the following process:
  • the obtaining unit 701 obtains the position of the information bit and the frozen bit according to the reliability order of the polarized channel, and the reliability of the polarized channel corresponding to the information bit is higher than the reliability of the polarized channel corresponding to the frozen bit. Specifically, the obtaining unit 701 sorts the reliability of the polarized channels, and selects K info + K crc as the most reliable information bits, K info is the size of the information block to be encoded, and K crc is the number of CRC bits. The remaining polarized channels act as freeze bits.
  • the CRC encoding unit 702 performs CRC encoding on the information block to obtain K info + K crc CRC encoded bits, which are mapped to information bits.
  • the determining unit 703 determines that at least one bit is determined as the check frozen bit from the frozen bits determined in step 801, and the value of the frozen bit is verified by the P information bits that meet the preset condition in the information bits before the check frozen bit The value determines that P is an integer greater than or equal to one.
  • the check freeze bit indicates that the value of the bit is related to the value of other bits.
  • the information bits of other bits are selected, rather than frozen bits.
  • the term "check freeze bit" is used to distinguish from existing freeze bits (fixed bits), and may have other names, such as dynamic freeze bits, parity bits, and the like.
  • the reliability of the first few polarized channels with the lowest sequence number is the lowest, so usually the first few polarized channels of the Polar code are used as frozen bits, that is, usually exist before the first information bit.
  • One or more freeze bits If the check freeze bit is used to check the information bits before it, the first freeze bits have no information bits before, so they cannot be used as check freeze bits.
  • the value of the frozen bit other than the check frozen bit is set to a fixed value known to the transceiver, 0 or 1.
  • the Polar encoding unit 704 performs Arikan Polar encoding on the information bits, the check frozen bits, and other frozen bits other than the check frozen bits to obtain a coded block.
  • the coded block obtained by coding may also be called a code sequence, an code code word, and the like.
  • the check freeze bit of the present application is selected from the frozen bit, and the frozen bit is in the order of the polarized channel, and the polarization channel reliability is lower than the information bit.
  • the Polar code constructed by the embodiment of the present application, the information block and the CRC bit are distributed together on the most reliable polarization channel, and the parity bit (check bit) is distributed in the pole with reliability lower than the information bit.
  • the check freeze bits are interspersed in the information block and the CRC bits.
  • the introduction of the check freeze bit not only has no loss to the performance of the existing CA-Polar, but also improves the accuracy of the decoding.
  • step 803 at least one of the frozen bits is determined as a check frozen bit, and all the frozen bits may be used as check freeze bits, but if there is no information bit before the check freeze bit (for example, FIG. 9 After sorting according to the natural order (coding order) of the polarized channel, if there is no information bit before the first check frozen bit, the check frozen bit is processed in the original manner, and remains as a frozen bit, and is set as the transceiver end. Known fixed values. It is also possible to select partial freeze bits as check freeze bits according to certain conditions, instead of all the default freeze check bits.
  • Each frozen bit refers to its previous information bits.
  • the check frozen bit can refer to its previous information bit or multiple information bits. That is to say, the value of the check freeze bit can be determined by one of its preceding information bits or a plurality of information bits.
  • a check equation (check function) can be constructed according to the same rules. Since the objects of the channel coding process are 0 and 1, the parity information can be used when the previous information bits are checked by the check freeze bit. For example, if a certain frozen bit checks (references) its previous one information bit, the value of the information bit is assigned to the check frozen bit at the encoding end. If one of the two information bits before the parity check bit is checked, the value obtained by binary addition (exclusive OR) of the values of the two information bits is assigned to the check freeze bit.
  • the P information bits that meet the preset conditions can be determined in a plurality of ways.
  • the information bits participating in determining the value of the frozen bit may be selected based on an agreed value Q, which is an integer greater than one.
  • Q an integer greater than one.
  • the information bit of the same number as the value of the check freeze bit number modulo Q is used as the information bit participating in the check freeze bit check.
  • Q 5
  • polarization channels U 18 determines a parity bit frozen
  • the value of Q mentioned here can be determined according to parameters such as the length of the mother code. For example, the longer the code length, the larger the value of Q can be.
  • Q can also be agreed to be a prime number or an odd number, for example, Q can be 3, 5, 7, or 9.
  • the information bits participating in the check can be read through the shift register. If Q is a prime number, it is implemented using a prime shift register.
  • the P information bits that meet the preset condition may also be agreed to be all the information bits whose odd number or odd number before the frozen bit is verified.
  • the P pieces of information may also be determined by selecting a information bit whose sequence number is the same as the value of the sequence number modulo Q1, the modulo Q2, ..., or the modulo Qh of the check freeze bit, and participates in determining the value of the check freeze bit, h For an integer greater than or equal to 2, Q1, Q2, ..., Qh are integers greater than or equal to 1 and different from each other.
  • a number can be used to modulo, for example, 5, or two or more numbers can be used to freeze the check at the same time.
  • the sequence number of the information bits before the bit is modulo to determine P information bits. For example, information bits corresponding to all the numbers of the same value as the check frozen block modulo 3, modulo 5 or modulo 7 are used to determine the value of the check freeze bit.
  • the P information bits that meet the preset conditions can be determined in a random manner, that is, the check equation for each frozen bit can be randomly constructed.
  • a random number is generated according to the agreed random seed to determine whether each information bit before a certain check freeze bit participates in the check of each check freeze bit.
  • a uniformly distributed number between (0, 1) according to an agreed random seed may be a decimal or a fraction, and may only produce a number greater than 0 and less than 1, or may include a number of 0 or 1 itself.
  • a random number is generated by a random seed for each of the preceding information bits, and if the random number is less than the threshold T, the information bit participates in determining the value of the check frozen bit, if the number If the threshold T is greater than or equal to, the information bit does not participate in determining the value of the check freeze bit. Both ends of the transceiver use the same random seed to generate the same random number, thus ensuring that the configuration of the compiled code is consistent.
  • the value of T is a number greater than 0 and less than 1, and can be set, for example, to a number equal to or stipulated by 1/3 or 1/5.
  • the threshold T determines the probability that the information bits participate in the check and the complexity of each check equation. Here, the larger T is, the higher the probability that the information bits participate in the check, and the more complicated the check equation of each check freeze bit is.
  • a single-bit check equation is constructed, and each check freeze bit is only used to check a certain information bit in front of it, that is, the value of each check freeze bit is determined only by the value of a certain information bit preceding the freeze bit. Due to the structure of the Arikan Polar core, verifying information bits at 2 m apart may not provide performance gain. Therefore, in the case of single-bit check, the information bits that are closest to the check freeze bit and whose distance is not equal to 2 m can be selected as the information bits participating in determining the value of the check freeze bit, where m is greater than or equal to 0. The integer. According to the natural ordering of the polarized channels, the selected one information bit is the nearest to the check frozen bit, and the difference between the sequence number of the check frozen bit and the sequence number of the one information bit is not equal to 2 integer times. power
  • Selecting P information bits that meet the preset condition may select an information bit with an increased code distance of the polarization channel of the check frozen bit.
  • the performance of the check freeze bit on the performance of the Polar is mainly due to the increase of the code distance of the Polar code.
  • the code weight of the Arikan Polar code can be calculated as the number of 1s in the row (also called the row vector) of the coding matrix in which each information bit is located. For example, the encoding matrix G 32 of the Polar code having a mother code length of 32 is as shown in FIG.
  • the line of the coding matrix in which the 15th bit U 15 is located is:
  • R 15 [1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
  • R 18 [1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
  • R 15 +R 18 [0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
  • the row vector obtained by R 15 + R 18 has a number of 1 of 10, that is, the check equation can increase the code weight from 8 to 10.
  • a check equation with an improved code weight effect can improve the performance of the Polar code. Relative to a certain frozen bit, if there is at least one information bit before it, the condition that the row of the coding matrix in which it is located is added to the row of the coding matrix in which the check frozen bit is located is satisfied. If the number of 1 is greater than the number of 1s in the row vector of the coding matrix in which the information bits are located, the check freeze bit that satisfies the condition may be referred to as a valid check freeze bit. Therefore, the information bits before a certain check freeze bit can be used to determine whether the check freeze bit is valid.
  • the P information bits that meet the preset condition may be information bits that meet the condition.
  • the P information bits that meet the preset condition may be information bits that meet the condition.
  • the principle of determining the freeze bit is to select a valid check freeze bit that satisfies the above conditions.
  • a valid check freeze bit can be searched for each information bit, and then a check equation can be constructed; for each frozen bit, it can be processed as a check freeze bit first, and for each check freeze bit, search
  • the valid information bits before it, and then construct the check equation for example, for a certain check frozen bit, search for 3 valid information bits before it, can participate in the determination of the check frozen bit, or use
  • the method of single-bit verification, or random seed determination, or the method of serial number mode Q is determined.
  • the method for performing CRC coding on an information block may be in a plurality of different manners, correspondingly, in the decoding method involved in the embodiment of FIG.
  • the CRC checksum decoding output is also different. The following three methods of CRC coding and corresponding verification methods are listed.
  • (i) Single CRC block coding A CRC encoding is performed on the information block of K info length to obtain CRC coded bits, including information blocks and K CRC CRC bits, and then mapping the coded bits to information bits.
  • the K CRC CRC bits are used to select the decoding result from the candidate path, and also to judge whether the decoding result is correct or not, that is, error detection.
  • Segmented CRC coding dividing the information block into a plurality of segments, performing CRC encoding on each segment of the information block, and then mapping each encoded coded bit to the information bit position;
  • the CRC check is performed separately for segmentation, which can be used to select the decoding result, or to perform error detection at the same time.
  • segmentation check can be performed when performing CRC check on multiple candidate decoding paths of SCL. For example, as shown in FIG. 20, assuming that the information block is divided into two segments, the CRC is also divided into two segments, and the structure of the information block and the CRC bits is roughly [I1 C1 I2 C2], where I1 and I2 are divided into two segments.
  • Information bit segments, C1 and C2 refer to a CRC segment that is segmented into two segments, where C1 is used to verify I1 and C2 is used to verify I2 or [I1, I2].
  • C1 and C2 are used to verify I2 or [I1, I2].
  • I1 and C2 do not need to be verified again, which saves the verification time.
  • the CRC check representing the path passes.
  • the information block and the CRC bits are divided into two segments. In practical applications, the number of segments can be arbitrarily set.
  • K' CRC bits are additionally selected for CRC coding, ie the total CRC bits include (K CRC +K' CRC ).
  • the information block is subjected to overall CRC encoding, including information blocks and (K CRC + K' CRC ) CRC bits, and then the encoded bits are mapped to information bit positions; wherein K' CRC is an extra CRC length, Adding the CRC length to the existing CRC length can compensate for the error detection performance degradation caused by SCL decoding.
  • the size of the added CRC length can vary depending on the size of the List.
  • the (K CRC + K' CRC ) CRC bits can be used to select the decoding result from the candidate path, and can also be used for error detection.
  • the coded bits are mapped to information bits.
  • One of the CRC bits can be agreed to use for picking paths, ie error correction, and the other for error detection.
  • the decoding result is first selected from a plurality of candidate paths by using an error correction CRC bit, and the decoding result includes an information block and an error detection CRC bit. Then, the error detection CRC bit is used for error detection on the decoding result.
  • K CRC is the base CRC bit.
  • the K CRC of the PBCH in LTE is defined as 16 bits
  • the transport data block in the PDSCH is defined as 24 bits, where the base bits can be indicated by the system MAC layer.
  • the base CRC bits may be defined as other lengths in different communication systems.
  • the K' CRC is an extra CRC bit.
  • the check capability of a shorter length CRC bit is lower than that of a longer CRC.
  • the length of the extra CRC bits can also be determined according to other rules during implementation, and is not limited to the calculation method here.
  • FIG. 21 is a schematic flowchart diagram of still another encoding method provided by an embodiment of the present application, and the method may be performed by the decoding apparatus shown in FIG. 7, FIG. 11, or FIG.
  • the method includes:
  • This step can be performed by the fetch unit 701 of FIG. 7, the processor 1102 of FIG. 11, or the signal processor 1202 of FIG.
  • the information bit, the frozen bit, and the position of the check frozen bit are obtained according to the target code length M, the mother code length N, and the information bit number K.
  • the top K bits that can be the highest height are selected as information bits, and the remaining bits are frozen bits, and the position of the check bits is determined from the frozen bits according to the method described above.
  • K K info +K crc .
  • K info is the size of the information block
  • K crc is the number of CRC bits (also arguably the length of the CRC block).
  • Step 2102 Perform CRC encoding on the information block. This step can be performed by the CRC encoding unit 701 of FIG. 7, the processor 1102 of FIG. 11, or the signal processor 1202 of FIG.
  • the input of the CRC code is the sequence a 0 , a 1 , a 2 ,..., a A-1
  • the check bit generated after CRC coding is
  • the encoded output sequence of the CRC is b 0 , b 1 , ..., b B-1 .
  • the sequence obtained by CRC coding satisfies the formula (2).
  • Step 2105 may be performed by a rate matching unit (not shown) in the encoding device of FIG. 7, processor 1102 of FIG. 11, or signal processor 1202 of FIG.
  • step 2101 If the CRC encoding is performed by adopting an extra CRC bit, before step 2101, step 2100 is further included to obtain an additional CRC length.
  • Step 2101 can be performed by the acquisition unit 701 of FIG. 7, the processor 1102 of FIG. 11, or the signal processor 1202 of FIG.
  • the processing of the decoding result is different for the decoding method involved in the embodiment of FIG.
  • the information block and the CRC bit are mapped to the information bits
  • a certain interleaving can be performed.
  • the decoding result of the SCL is first deinterleaved during decoding, and then the path selection and error detection are performed by the CRC check.
  • the CRC-encoded bits include information blocks and CRC bits, and the information blocks and CRC bits can be ordered to be mapped to the positions of the information bits in the following four manners.
  • the CRC bits referred to herein include a single CRC block, a CRC slice, an extra CRC bit, and a base CRC bit involved in the CRC coding aspect of (i)(ii)(iii) above.
  • the CRC bit is located after the information block as shown in Fig. 22 (1).
  • the CRC bit is located before the information block as shown in Fig. 22 (2).
  • the CRC bits are located between the information blocks as shown in Fig. 22 (3).
  • the CRC bit is divided into a plurality of segments, each segment being located anywhere between the information blocks, before the information block, or after the information block, as shown in Fig. 22 (4).
  • the present application provides another encoding apparatus 1100 that can implement the encoding method of the present application.
  • the encoding device 1100 includes:
  • the processor 1102 is configured to execute the program stored by the memory, and when the program is executed, execute the encoding method shown in FIG. 8.
  • the method includes: obtaining information bits and locations of frozen bits according to reliability ranking of the polarized channels, where the reliability of the polarized channels corresponding to the information bits is higher than the reliability of the polarized channels corresponding to the frozen bits, Performing cyclic redundancy check CRC coding on the information block, mapping CRC encoded bits to the information bits, determining at least one bit of the frozen bits as a check freeze bit, and the value of the check freeze bit is determined by Determining, in the information bits before the freeze bit, the value of the P information bits that meet the preset condition, P is an integer greater than or equal to 1; freezing the information bit, the check freeze bit, and the checksum Other frozen bits other than bits are Polar encoded.
  • the processor Since the encoding method has been described in the foregoing method embodiments, the processor is only used to execute the encoding method according to the program. Therefore, for a detailed description of the encoding method, refer to the relevant parts of the corresponding embodiment of FIG. 8 and FIG. Let me repeat.
  • the memory 1101 can be a physically separate unit or can be integrated with the processor 1102.
  • the encoding apparatus of FIG. 11 may further include a transmitter (not shown) for transmitting a coded block obtained by the processor 1102 by performing Polar encoding on the information bits and the check freeze bits.
  • the present application provides another encoding apparatus 1200 that can implement the encoding method of the present application.
  • the encoding device 1200 includes:
  • the signal processor 1202 is configured to obtain, according to the reliability ranking of the polarized channel, the location of the information bit and the frozen bit, where the reliability of the polarized channel corresponding to the information bit is higher than the reliability of the polarized channel corresponding to the frozen bit Performing cyclic redundancy check CRC coding on the information block, mapping the CRC encoded bits to the information bits, determining at least one bit of the frozen bits as a check frozen bit, and the value of the check frozen bit Determining, by the value of P information bits that meet a preset condition among the information bits before the check freeze bit, P is an integer greater than or equal to 1; for the information bit, the check freeze bit, and the checksum Freezing bits other than frozen bits for Polar encoding;
  • At least one output (outPut) 1203 is used to output the coded block obtained by the signal processor 1202.
  • the signal processor 1202 may be implemented by hardware, for example, a baseband processor, a processing circuit, an encoder, or an encoding circuit.
  • the signal processor 1202 is only used to perform the encoding method. Therefore, for a detailed description of the encoding method, refer to the relevant parts of the corresponding embodiment of FIG. 8 and FIG. Let me repeat.
  • the encoding apparatus of FIG. 12 may further include a transmitter (not shown) for transmitting the encoded block of the output (outPut) 1203.
  • the encoding device in this application may be any device having wireless communication capabilities, such as an access point, a site, a user equipment, a base station, and the like.
  • the decoding device 1300 shown in FIG. 13 can be used to perform the decoding method of the present application. As shown in Figure 14, the decoding process includes the following process:
  • the obtaining unit 1301 obtains the position of the information bit and the frozen bit according to the reliability order of the polarization channel, and the reliability of the polarization channel corresponding to the information bit is higher than the reliability of the polarization channel corresponding to the frozen bit. Specifically, the obtaining unit 1301 sorts the reliability of the polarized channels, and selects K info + K crc as the most reliable information bits, K info is the size of the information block, and K crc is the number of CRC bits. The remaining polarized channels act as freeze bits. The obtaining unit 1301 determines at least one of the frozen bits as a check freeze bit.
  • the serially canceled list SCL decoding algorithm sequentially decodes the to-be-decoded bits, and outputs L candidate paths, where the value of the check frozen bits of each path is determined by the check frozen bits.
  • the value of the P information bits in the previous information bits that meet the preset condition is determined, and P is an integer greater than or equal to 1.
  • the configuration of the position of the check freeze bit, the information bit for determining its value, and the check equation are the same as those of the code side.
  • the decoding unit 1302 sequentially decodes the to-be-decoded bits by using a serial offset list SCL decoding algorithm, and outputs L candidate paths with optimal metric values, and the decoding result of each candidate path includes information blocks and loops. Redundancy check CRC bits.
  • the CRC bits are decoded as information bits, which are unknown bits, and path expansion is required in the decoding process. Since the value of the check freeze bit is determined by the information bit and the check equation in front of it, the decoding of the check freeze bit is the same as the original freeze bit, and is decoded as a known bit, and is not decoded during the decoding process.
  • the path extension is performed, except that the decoding result of the value of the frozen bit is determined by the information bits and the check equation that have been previously decoded.
  • the CRC check unit 1303 performs CRC check on the L candidate paths in order from the candidate path with the best metric value.
  • the CRC check unit 1303 can perform a CRC check on all L candidate paths to obtain a result of a check pass or a check failure. After the candidate path passed by the first CRC check is also obtained, the remaining candidate paths are no longer verified.
  • the information block in the first candidate path through which the CRC check passes is used as a decoding output.
  • the output unit 1304 selects the first candidate path passed by the CRC check as a decoding result, and the information block corresponding to the information bit serves as the output of the current decoding.
  • the calculation of the PM value is calculated by the formula (1), and by retaining the path with the smallest PM value at each expansion, two candidate paths L1 and L2 as indicated by the arrows are obtained. The final PM value of path L1 is 0.3, and the PM value of the other path L2 is finally 0.2.
  • the CRC check is performed first from the path L2 with the smallest PM (the metric value is optimal), and if the check passes, L2 is selected as the decoded output.
  • L2 path check fails, continue to verify the L1 path. If the check passes, select L1 as the decode output. If both L1 and L2 check fail, the L2 path with the smaller PM (the best metric value) can be selected as the decoding result output. If both L1 and L2 are not verified, it can be confirmed that the decoding failed.
  • the i-th bit indicated in the figure is a check freeze bit
  • two arrows 1501 indicate that the value of the check freeze bit is determined by the i-th bit (information bit). It can be seen that when decoding the i-th bit, path expansion is not required, and the value of the i-th bit is determined by the value of the i-th bit in the path, so the value of the check-free bit in the path L1 Is 0, and the value of the check freeze bit in L2 is 1.
  • the difference between Fig. 15 and Fig. 3 is that the i-th bit corresponds to the freeze bit in Fig. 3, and the check freeze bit is corresponding in Fig. 15.
  • Fig. 15 the i-th bit corresponds to the freeze bit in Fig. 3
  • the check freeze bit is corresponding in Fig. 15.
  • FIG. 15 assumes that the LLR(i) of the check freeze bits of the L1 and L2 paths is less than 0, assuming that the value corresponding to LLR(i) is less than 0 is 1, and the decoding result of the i bits in the L1 path is 0 and LLR.
  • the results of (i) are inconsistent.
  • assumed to be 0.3.
  • Figure 16 is a comparison of the performance of the solution of the present application with the conventional CA-Polar under the AWGN channel.
  • the conventional CA-Polar except for the information bits, the remaining polarized channels are freeze bits, and are set to all zeros.
  • the scheme of the present application adopts that all the freeze bits are check freeze bits, and the value of the check freeze bit is determined by selecting the information bits of the same sequence number as the check freeze bit number modulo 5.
  • the technical solution of the present application has a performance gain of between 0.2 dB and 0.3 dB with respect to the conventional CA-Polar. The lower the code rate, the larger the gain, because at low bit rates, more polarized channels can be used as check freeze bits, and the probability that the correct path remains during SCL decoding is higher.
  • the decoding apparatus 1700 shown in FIG. 17 can also be used to perform a decoding method.
  • the decoding apparatus 1700 includes:
  • a memory 1701 configured to store a program
  • the processor 1702 is configured to execute the program stored in the memory, and when the program is executed, execute the decoding method shown in FIG. 14.
  • the method includes: obtaining a position of an information bit and a frozen bit in a bit to be decoded, determining at least one bit of the frozen bit as a check freeze bit; and sequentially performing the to-be-translated by using a serial offset list SCL decoding algorithm
  • the code bits are decoded, and the L candidate paths with the best metric value are output, and the decoding result of each candidate path includes an information block and a cyclic redundancy check CRC bit, wherein the check freeze bits in each path
  • the value is determined by a value obtained by decoding the P information bits that meet the preset condition in the information bits before the check freeze bit, and P is an integer greater than or equal to 1; starting from the candidate path with the best metric value,
  • the L candidate paths perform CRC check, and the information block in the first candidate path through which the CRC check passes is used as a decode
  • the path with the best metric value can be selected as the decoding output, and the decoding failure can also be confirmed.
  • the memory 1701 may be a physically separate unit or may be integrated with the processor 1702.
  • the decoding apparatus of Figure 17 may further comprise a receiver (not shown) for receiving the coded block transmitted by the encoding means, for the decoding means, the bit to be decoded or the bit sequence to be decoded .
  • the present application provides another decoding apparatus 1800 that can implement the encoding method of the present application.
  • the decoding device 1800 includes:
  • At least one input (180) for receiving bit information to be decoded At least one input (180) for receiving bit information to be decoded
  • a signal processor 1802 configured to acquire a position of the information bit and the frozen bit in the bit to be decoded, determine at least one bit of the frozen bit as a check freeze bit; use a serial offset list SCL decoding algorithm to sequentially Decoding the decoded bits for decoding, and outputting L candidate paths with the best metric value, and the decoding result of each candidate path includes an information block and a cyclic redundancy check CRC bit, wherein the check in each path
  • the value of the frozen bit is determined by a value obtained by decoding the P information bits that meet the preset condition in the information bits before the check frozen bit, and P is an integer greater than or equal to 1; starting from the candidate path with the best metric value, Performing a CRC check on the L candidate paths;
  • At least one output 1803 is used for decoding the information block in the first candidate path through which the CRC check passes.
  • the signal processor 1802 may be implemented by hardware, for example, a baseband processor, a processing circuit, a decoder, or a decoding circuit.
  • the decoding apparatus of Figure 18 may further comprise a receiver (not shown) for receiving the coded block transmitted by the encoding means, for the decoding means, the bit to be decoded or the bit sequence to be decoded .
  • the decoding device of the embodiment of the present application may be any device having a wireless communication function, such as an access point, a site, a user equipment, a base station, and the like.
  • serial cancellation list SCL decoding algorithm in the embodiment of the present application includes other SCL-like decoding algorithms that sequentially decode, provide multiple candidate paths, or an improved algorithm for the SCL decoding algorithm.
  • the encoding device or the decoding device in the embodiment of the present application may be separate devices in actual use; or may be integrated devices for transmitting information to be sent after being encoded, or receiving information. Perform decoding.
  • the unit and method processes of the examples described in the embodiments of the present application can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the solution. The skilled person can use different methods for each particular application to implement the described functionality.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division, and the actual implementation may have another division manner.
  • multiple units or components may be combined or integrated into another system. Some of the steps in the method can be ignored or not executed.
  • the coupling or direct coupling or communication connection of the various units to one another may be achieved through some interfaces, which may be in electrical, mechanical or other form.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above embodiments it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof.
  • software it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions.
  • the computer program instructions When the computer program instructions are loaded and executed on a computer, the processes or functions described in accordance with embodiments of the present invention are generated in whole or in part.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • the computer instructions can be stored in or transmitted by a computer readable storage medium.
  • the computer instructions can be from a website site, computer, server or data center to another website site by wire (eg, coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (eg, infrared, wireless, microwave, etc.) Transfer from a computer, server, or data center.
  • wire eg, coaxial cable, fiber optic, digital subscriber line (DSL)
  • wireless eg, infrared, wireless, microwave, etc.
  • the computer readable storage medium can be any available media that can be accessed by a computer or a server, data center, or equivalent data storage device that includes one or more available media.
  • the usable medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape, a USB flash drive, a ROM, a RAM, etc.), an optical medium (eg, a CD, a DVD, etc.), or a semiconductor medium (eg, a solid state hard disk Solid State Disk (SSD) ))Wait.
  • a magnetic medium eg, a floppy disk, a hard disk, a magnetic tape, a USB flash drive, a ROM, a RAM, etc.
  • an optical medium eg, a CD, a DVD, etc.
  • a semiconductor medium eg, a solid state hard disk Solid State Disk (SSD)

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Abstract

本申请实施例提供一种Polar编码方法，该方法包括：根据极化信道的可靠度排序获取信息比特和冻结比特的位置，所述信息比特对应的极化信道的可靠度高于所述冻结比特对应的极化信道的可靠度；对信息块进行循环冗余校验CRC编码，将CRC编码后的比特映射到所述信息比特；确定所述冻结比特中的至少一个比特作为校验冻结比特，所述校验冻结比特的值由所述校验冻结比特之前的信息比特中符合预设条件的P个信息比特的值确定，P为大于等于1的整数；对所述信息比特、所述校验冻结比特和所述校验冻结比特以外的其他冻结比特进行Polar编码。该编码方法能够进一步提高CA-Polar码的性能。

Description

Polar码编译码方法及装置
本申请要求于2017年01月26日提交中国专利局、申请号为201710061829.6、申请名称为“Polar码编译码方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明实施例涉及无线通信领域，更具体地，涉及Polar码编译码方法及装置。
背景技术
通信系统通常采用信道编码提高数据传输的可靠性，以保证通信的质量。土耳其教授Arikan提出的极化码(英文：Polar codes)是第一个理论上证明可以达到香农容量且具有低编译码复杂度的好码。Polar码是一种线性块码，其编码矩阵为G N，编码过程为
Figure PCTCN2018073908-appb-000001
其中
Figure PCTCN2018073908-appb-000002
是一个二进制的行矢量，长度为N(即母码长度)；G N是一个N×N的矩阵，且
Figure PCTCN2018073908-appb-000003
定义为log 2N个矩阵F 2的克罗内克(Kronecker)乘积。
上述矩阵
Figure PCTCN2018073908-appb-000004
传统Polar码的编码过程中，
Figure PCTCN2018073908-appb-000005
中的一部分比特用来携带信息，称为信息比特，这些比特的索引的集合记作
Figure PCTCN2018073908-appb-000006
另外的一部分比特设置为收发端预先约定的固定值，称之为固定比特或冻结比特(frozen bits)，其索引的集合用
Figure PCTCN2018073908-appb-000007
的补集
Figure PCTCN2018073908-appb-000008
表示。Polar码的编码过程相当于：
Figure PCTCN2018073908-appb-000009
这里，G N.(A)是G N.中由集合A中的索引对应的那些行得到的子矩阵，G N(A C)是G N中由集合A C中的索引对应的那些行得到的子矩阵。
Figure PCTCN2018073908-appb-000010
为
Figure PCTCN2018073908-appb-000011
中的信息比特集合，信息比特个数为K；
Figure PCTCN2018073908-appb-000012
为
Figure PCTCN2018073908-appb-000013
中的冻结比特集合，冻结比特个数为(N-K)，是已知比特。这些冻结比特的值通常被设置为0，但是只要收发端预先约定，固定比特可以被任意设置。固定比特设置为0时，Polar码的编码输出可简化为：
Figure PCTCN2018073908-appb-000014
是一个K×N的矩阵。
Polar码的构造过程即集合
Figure PCTCN2018073908-appb-000015
的选取过程，决定了Polar码的性能。Polar码的构造过程通常是，根据母码码长N确定共存在N个极化信道，分别对应编码矩阵的N个行，计算极化信道可靠度，将可靠度较高的前K个极化信道的索引作为集合A的元素，剩余(N-K)个极化信道对应的索引作为固定比特的索引集合
Figure PCTCN2018073908-appb-000016
的元素。集合A决定了信息比特的位置，集合
Figure PCTCN2018073908-appb-000017
决定了固定比特的位置。
在译码端，Polar码可以采用串行抵消(英文：Successive Cancellation,简称SC)译码算法，从第1个比特开始顺序译码。串行抵消列表(英文Successive Cancellation List,简称SCL)译码算法是对SC译码算法的改进，在译码过程中保留多个候选译码结果。SCL把译码过程看成一个路径搜索过程，即以第1个比特作为 根结点进行路径扩展，采用一个度量值对该路径进行评估，该度量值随着路径的扩展按照预定的规则动态更新。每一次扩展(译码下一个比特)时，保留当前层中具有最优路径度量的L条候选路径，直到扩展到最后一层(译码最后一个比特)。最终输出L条候选路径中度量值最优的路径作为译码输出。SCL译码算法可以获得最大似然译码性能。
为了提高Polar码的性能，现有技术对Polar码进行改进，提出了CA-Polar码。CA-Polar码是级联CRC(英文：Cyclic Redundancy Check，循环冗余校验)的Polar码，简称CA-Polar码。通过对信息块进行CRC编码，再将编码后的比特映射到信息比特中。相应的，译码的时候采用CA-SCL(CRC-Aided Successive Cancellation List)译码算法进行译码，即在SCL译码输出的L条候选路径中选择CRC通过的候选路径作为译码输出。如果在CA-SCL译码的中间节点，正确路径因为度量值较差而被删除，则后续的CRC校验无法提升SCL译码的性能。
发明内容
本申请实施例提供Polar码编码方法及编码装置、译码方法及译码装置，能够进一步提高CA-Polar码的性能。
第一方面，提供一种Polar编码方法，包括：
根据极化信道的可靠度排序获取信息比特和冻结比特的位置，所述信息比特对应的极化信道的可靠度高于所述冻结比特对应的极化信道的可靠度；
对信息块进行循环冗余校验CRC编码，将CRC编码后的比特映射到所述信息比特；
确定所述冻结比特中的至少一个比特作为校验冻结比特，所述校验冻结比特的值由所述校验冻结比特之前的信息比特中符合预设条件的P个信息比特的值确定，P为大于等于1的整数；
对所述信息比特、所述校验冻结比特和所述校验冻结比特以外的其他冻结比特进行Polar编码。
第二方面，提供一种编码装置，包括：
获取单元，用于根据极化信道的可靠度排序获取信息比特和冻结比特的位置，所述信息比特对应的极化信道的可靠度高于所述冻结比特对应的极化信道的可靠度；
CRC编码单元，用于对信息块进行循环冗余校验CRC编码，将CRC编码后的比特映射到所述信息比特；
确定单元，用于确定所述冻结比特中的至少一个比特作为校验冻结比特，所述校验冻结比特的值由所述校验冻结比特之前的信息比特中符合预设条件的P个信息比特的值确定，P为大于等于1的整数；
Polar编码单元，用于对所述信息比特、所述校验冻结比特和所述校验冻结比特以外的其他冻结比特进行Polar编码。
第三方面，提供一种编码装置，包括：
存储器，用于存储程序；
处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于根据极化信道的可靠度排序获取信息比特和冻结比特的位置，所述信息比特对应的极化信道的可靠度高于所述冻结比特对应的极化信道的可靠度，对信息块进行循环冗余校验CRC编码，将CRC编码后的比特映射到所述信息比特，确定所述冻结比特中的至少一个比特作为校验冻结比特，所述校验冻结比特的值由所述校验冻结比特之前的信息比特中符合预设条件的P个信息比特的值确定，P为大于等于1的整数；对所述信息比特、所述校验冻结比特和所述校验冻结比特以外的其他冻结比特进行Polar编码。
第四方面，提供一种编码装置，包括：
至少一个输入端，用于接收信息块；
信号处理器，用于根据极化信道的可靠度排序获取信息比特和冻结比特的位置，所述信息比特对应的极化信道的可靠度高于所述冻结比特对应的极化信道的可靠度，对信息块进行循环冗余校验CRC编码，将CRC编码后的比特映射到所述信息比特，确定所述冻结比特中的至少一个比特作为校验冻结比特，所述校验冻结比特的值由所述校验冻结比特之前的信息比特中符合预设条件的P个信息比特的值确定，P为大于等于1的整数；对所述信息比特、所述校验冻结比特和所述校验冻结比特以外的其他冻结比特进行Polar编码；
至少一个输出端，用于输出信号处理器得到的编码块。
第五方面，提供一种Polar译码方法，包括：
获取待译码比特中信息比特和冻结比特的位置,确定所述冻结比特中的至少一个比特作为校验冻结比特；
采用串行抵消列表SCL译码算法按顺序对所述待译码比特进行译码，输出度量值最优的L条候选路径，每条候选路径的译码结果包括信息块和循环冗余校验CRC比特；其中，各个路径中的所述校验冻结比特的值由所述校验冻结比特之前的信息比特中符合预设条件的P个信息比特译码得到的值确定，P为大于等于1的整数；
从度量值最优的候选路径开始，对所述L条候选路径进行CRC校验，将CRC校验通过的第一个候选路径中的信息块作为译码输出。
第六方面，提供一种译码装置，包括：
获取单元，用于获取待译码比特中信息比特和冻结比特的位置，确定所述冻结比特中的至少一个比特作为校验冻结比特；
译码单元，用于采用串行抵消列表SCL译码算法按顺序对所述待译码比特进行译码，输出度量值最优的L条候选路径，每条候选路径的译码结果包括信息块和循环冗余校验CRC比特；其中，各个路径中的所述校验冻结比特的值由所述校验冻结比特之前的信息比特中符合预设条件的P个信息比特译码得到的值确定，P为大于等于1的整数；
CRC校验单元，用于从度量值最优的候选路径开始，对所述L条候选路径进行CRC校验；
输出单元，用于将CRC校验通过的第一个候选路径中的信息块作为译码输出。
第七方面，提供一种译码装置，包括：
存储器，用于存储程序；
处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于获取待译码比特中信息比特和冻结比特的位置，确定所述冻结比特中的至少一个比特作为校验冻结比特；采用串行抵消列表SCL译码算法按顺序对所述待译码比特进行译码，输出度量值最优的L条候选路径，每条候选路径的译码结果包括信息块和循环冗余校验CRC比特，其中，各个路径中的所述校验冻结比特的值由所述校验冻结比特之前的信息比特中符合预设条件的P个信息比特译码得到的值确定，P为大于等于1的整数；从度量值最优的候选路径开始，对所述L条候选路径进行CRC校验，将CRC校验通过的第一个候选路径中的信息块作为译码输出。
第八方面、提供一种译码装置，包括：
至少一个输入端，用于接收待译码比特信息；
信号处理器，用于获取待译码比特中信息比特和冻结比特的位置，确定所述冻结比特中的至少一个比特作为校验冻结比特；采用串行抵消列表SCL译码算法按顺序对所述待译码比特进行译码，输出度量值最优的L条候选路径，每条候选路径的译码结果包括信息块和循环冗余校验CRC比特，其中，各个路径中的所述校验冻结比特的值由所述校验冻结比特之前的信息比特中符合预设条件的P个信息比特译码得到的值确定，P为大于等于1的整数；；从度量值最优的候选路径开始，对所述L条候选路径进行CRC校验；
至少一个输出端，用于将CRC校验通过的第一个候选路径中的信息块作为译码输出。
结合以上所有方面，在第一种可能的实现方式中，所述P个信息比特的序号是与所述校验冻结比特的序号模Q的值相同，Q为大于等于1的整数。
结合第一种可能的实现方式，在第一种可能的实现方式中，所述Q为质数或奇数。
结合第一种或第二种可能的实现方式，在第三种可能的实现方式中，所述Q为3、5、7或9。
结合第一种可能的实现方式，在第四种可能的实现方式中，所述符合预设条件的P个信息比特是从所述该校验冻结比特之前的所有信息比特中随机确定的信息比特。
结合第四种可能的实现方式，在第五种可能的实现方式中，对于每一个校验冻结比特，对该校验冻结比特前面的每一个信息比特采用随机种子产生一个随机数，如果该随机数小于预设的门限T，则该信息比特参与确定该校验冻结比特的值。
结合第五种可能的实现方式，在第六种可能的实现方式中，所述随机种子产生0到1之间均匀分布的随机数，T为大于0小于1的值。
结合第六种可能的实现方式，在第七种可能的实现方式中，所述门限T为约等于或等于1/3或1/5的数值。
结合以上所有方面，在第八种可能的实现方式中，所述P个信息比特是与所述校验冻结比特的序号模Q或模M相同的序号对应的信息比特，Q、M为互不相同的质数或奇数；或者所述P个信息比特的序号是奇数或者质数；或者所述P个信息比特包括：序号与所述校验冻结比特的序号模Q1、模Q2、…、或模Qh的值相同的信息比特，h为大于等于2的整数，Q1、Q2、…、Qh分别为大于等于1且互不相同的整数。在通过取模确定哪些信息比特参与确定校验冻结比特的值时，可以用一个数来取模，例如5，也可以同时用两个数或更多的数，例如将与校验冻结比特模3、模5或模7相同的值的所有序号对应的信息比特都用于确定该校验冻结比特的值。
结合以上所有方面，在第九种可能的实现方式中，所述P＝1。
结合第九种可能的实现方式，在第十种可能的实现方式中，所述1个信息比特为距所述校验冻结比特最近的、且所述校验冻结比特的序号与所述1个信息比特的序号的之差不等于2的整数次幂。
结合以上所有方面或所有可能的实现方式，在第十一种可能的实现方式中，所有的冻结比特为校验冻结比特；若校验冻结比特之前不存在满足所述预设条件的信息比特，则该校验冻结比特保留为冻结比特并设置为固定的值。
结合以上所有方面或所有可能的实现方式，在第十二种可能的实现方式中，所述编码矩阵中对应P个信息比特中任一信息比特的行向量与编码矩阵中对应所述校验冻结比特的行向量相加得到的向量中1的个数大于编码矩阵中对应所述任一信息比特的行向量的1的个数。
结合以上所有方面或所有可能的实现方式，在第十三种可能的实现方式中，所述信息比特和所述冻结比特按照极化信道的自然序排序。
结合以上第一、二、三或八种可能的实现方式，在第十四种可能的实现方式中，采用移位寄存器选取p个信息比特。
结合以上第一、第二、第三、第四方面或其可能的实现方式，在第十五种可能的实现方式中，对信息块进行循环冗余校验CRC编码包括以下中的任意一种：
对信息块进行CRC编码，得到CRC编码后的比特，所述CRC编码后的比特包括信息块和K CRC个CRC比特，其中，K CRC为预先设置的固定CRC长度；或
将所述信息块分成多个片段，分别对所述信息块的每个片段进行CRC编码，得到CRC编码后的比特，所述CRC编码后的比特包括信息块和K CRC个CRC比特，K CRC为预先设置的固定CRC长度或者为固定CRC长度加上额外CRC长度后的长度；或
对所述信息块进行整体CRC编码，得到CRC编码后的比特，所述CRC编码后的比特包括信息块和(K CRC+K’ CRC)个CRC比特，其中，K CRC为预先设置的固定CRC长度，K’ CRC为额外的CRC长度；或
对信息块进行第一级CRC编码，得到CRC编码后的比特，所述第一级CRC编码后的比特包括信息块和K CRC个CRC比特，将第一级CRC编码后的比特作为一个整体块，进行第二级CRC编码，得到第二级CRC编码后的比特，所述第二级CRC编码后的比特包括信息块、K CRC个第一级CRC比特和K’ CRC个第二级CRC比特，其中，K CRC为预先设置 的固定CRC长度，K’ CRC为额外CRC长度；
其中，K CRC、K CRC、K’ CRC为大于0的整数。
结合第十五种可能的实现方式中，在第十六种可能的实现方式中，K’ CRC根据SCL译码的候选路径数L确定。例如，K’ CRC＝Log 2(L)，那么L＝8时，K’ CRC＝3。
结合以上第一、第二、第三、第四方面或对应的可能的实现方式、第十五种、第十六种可能的实现方式，在第十七种可能的实现方式中，将CRC编码后的比特映射到所述信息比特后，CRC比特与信息块的位置包括以下中的任意一种：
CRC比特排在信息块之后；或
CRC比特排在信息块之前；或
CRC比特排在信息块之间；或
CRC比特分成多个片段，每个片段位于信息块之间、信息块之前或者信息块之后中的任意位置。
结合第五至第八方面的任意方面，在第十七种可能的实现方式中，所述度量值为路径值PM。
结合第五至第八方面的任意方面，在第十八种可能的实现方式中，若L条候选路径的CRC校验均未通过，L条候选路径中度量值最优的路径的信息块作为译码输出或者确定为译码失败。
本申请的第九方面提了供一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述各方面或各种可能的实现方式所述的编码方法或译码方法。
本申请的又一方面提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述各方面或各种可能的实现方式所述的编码方法或译码方法。
本申请的又一方面提供了一种计算机程序，当其在计算机上运行时，使得计算机执行上述各方面或各种可能的实现方式所述的编码方法或译码方法。
本申请实施例从Polar码的冻结比特中，确定部分或者全部冻结比特作为校验冻结比特，这些校验冻结比特的值由其之前的信息比特的值确定。校验冻结比特由于与前面的信息比特相关，如果前面的信息比特译码有错，根据该信息计算得到的校验冻结比特的值与校验冻结比特接收到的LLR不符的可能性更大，使得该路径的度量值变劣，从而在候选路径的度量值排序时更可能把该错误路径删除，提高了CA-SCL译码的性能。
附图说明
图1是无线通信发送端和接收端的基本流程示意图；
图2a是本申请实施例中当前比特的LLR大于0的情况下，路径扩展及度量值计算示意图；
图2b是本申请实施例中当前比特的LLR小于0情况下，路径扩展及度量值计算示 意图；
图3是SCL译码的一种路径扩展和PM值更新的示意图；
图4是CA-Polar编码的过程示意图；
图5是CA-Polar构造的示意图；
图6是本申请实施例提供的编码过程示意图；
图7是本申请实施提供的一种编码装置的结构示意图；
图8是本申请实施提供的一种编码方法的流程示意图；
图9是本申请实施例提供的一种CA-Polar构造的示意图；
图10是本申请实施例的各个动态校验比特与其之前信息比特的校验关系示意图；
图11是本申请实施提供的又一种编码装置的结构示意图；
图12是本申请实施提供的又一种编码装置的结构示意图；
图13是本申请实施提供的一种译码装置的结构示意图；
图14是本申请实施提供的一种译码方法的流程示意图；
图15是本申请实施例提供的SCL译码的一种路径扩展和路径值更新的示意图；
图16是本申请实施提供的编译码方法与传统CA-Polar的性能仿真结果；
图17是本申请实施提供的又一种译码装置的结构示意图；
图18是本申请实施提供的又一种译码装置的结构示意图；
图19是母码长度为32的Polar编码矩阵；
图20是本申请实施例分段式CRC编码的原理示意图；
图21是本申请实施例提供的又一种编码方法的流程示意图；
图22是本申请实施例CRC编码后的比特中，CRC比特与信息块的位置关系示意图。
具体实施方式
本申请实施例的技术方案可以应用5G通信系统或未来的通信系统，也可以用于其他各种无线通信系统，例如：全球移动通讯(GSM，Global System of Mobile communication)系统、码分多址(CDMA，Code Division Multiple Access)系统、宽带码分多址(WCDMA，Wideband Code Division Multiple Access)系统、通用分组无线业务(GPRS，General Packet Radio Service)、长期演进(LTE，Long Term Evolution)系统、LTE频分双工(FDD，Frequency Division Duplex)系统、LTE时分双工(TDD，Time Division Duplex)、通用移动通信系统(UMTS，Universal Mobile Telecommunication System)等。
图1是无线通信的基本流程，在发送端，信源依次经过信源编码、信道编码、数字调制后发出。在接收端，依次经过数字解调、信道译码、信源解码输出信宿。信道编解码可以采用Polar码，而在信道解码的时候，可以采用SC译码以及SCL译码。SCL译码算法是对SC译码算法的改进，在译码过程中保留多个候选路径，最后根据每个候选路径的度量值选择一个路径作为译码结果。
第l条路径的度量值PM l(i)，即路径值(英文：path metric，简称PM)在译码到第i个比 特时的度量值的如公式(1)所示(设定LLR>0对应的值为0，LLR<0对应的值为1)：
Figure PCTCN2018073908-appb-000018
其中，LLR(i)是当前比特的对数似然比(英文：Log-likelihood Ratio，简称LLR)。LLR对应的值可以是0也可以是1，例如，当LLR<0时对应的值为1，当LLR>0时对应的值为0。当然，在实际应用时也可以采用其它的方式，例如将LLR<0对应的值设置为0，将LLR>0对应的值设置为1。LLR＝0时，可以认为其对应的值是0也可以认为其对应的值是1，在实际应用时可以根据需要进行设置。如果当前比特的LLR对应的值与判决结果一致，PM不变；如果当前比特的LLR对应的值(0或1)与判决结果不一致，PM增加惩罚值|LLR(i)|，即惩罚值为当前比特的LLR的绝对值。从PM的计算公式可以看出，PM越小，表示该路径对应的码字与接收信号越近，代表该路径的度量值越优，因此最后可以输出PM最小的路径作为译码结果。公式(1)中如果当前比特的LLR对应的值(0或1)与判决结果不一致，PM也可以改为减去惩罚值|LLR(i)|，即PMl(i)＝PM l(i-1)-|LLR(i)|，相应的，选择最优度量值的路径即表示选择PM最大的路径。本申请以公式(1)为例进行描述。
在SCL译码过程，如果当前比特是信息比特，每条路径会扩展成2条路径，总共扩展出2L条路径，L是最终需要保留的候选路径个数。每个节点的判决结果分别为0和1，并根据上式计算各路径的PM，然后对扩展后的路径根据PM进行排序，保留PM最小的L条路径，删除其余L条路径，也叫做剪枝。如果当前比特是冻结比特，各条路径中的相应节点不进行扩展，直接判决为相应的已知的固定值，并根据式(1)计算各路径的PM。
为方便描述，下面都以LLR<0时对应的值为1，LLR>0时对应的值为0作为例子进行描述。如图2(a)所示，若当前译码比特的LLR(i)大于0(对应的值为0)，在路径扩展过程中，若当前比特是信息比特，则需要扩展两条路径，若判决结果也为0，则判决结果与LLR对应的值一致(图2(a)中以“√”表示)，此种情况下PM(i)＝PM(i-1)；若判决结果为1，则判决结果与LLR对应的值不一致(图2(a)中以“x”表示)，此种情况下PM(i)＝PM(i-1)+|LLR(i)|。若当前比特是冻结比特，则对路径不进行扩展，按照已知的固定值计算PM，若已知的固定值是0，LLR对应的值也为0，则该已知的固定值与LLR对应的值一致，此种情况下PM(i)＝PM(i-1)；若已知的固定值是1，则该已知的固定值与LLR对应的值不一致，此种情况下PM(i)＝PM(i-1)+|LLR(i)|。如图2(b)所示，若当前译码比特的LLR(i)小于0(对应的值为1)，在路径扩展过程中，若当前比特是信息比特，则需要扩展两条路径，若判决结果为0，则判决结果与LLR对应的值不一致，此种情况下 PM(i)＝PM(i-1)+|LLR(i)|；若判决结果为1，则判决结果与LLR对应的值一致，此种情况下PM(i)＝PM(i-1)。若当前比特是冻结比特，不进行扩展，按照已知的固定值计算PM，若已知的固定值是0，LLR对应的值也为1，则该已知的固定值与LLR对应的值不一致，PM(i)＝PM(i-1)+|LLR(i)|；若已知的固定值是1，则该已知的固定值与与LLR对应的值一致，PM(i)＝PM(i-1)。
图3是SCL译码算法List＝2的示例,在译码过程中保留2个候选路径。通常前面的几个比特是冻结比特，设置为固定的值，如0。因此实际上从第一个信息比特开始译码。图2(a)和图2(b)中通过在每次扩展的时候，保留PM值最小的路径，最后得到如箭头所示的两条候选路径L1和L2。路径L1最终的PM值为0.0，另一条路径L2的PM值最终为0.2，因此选择PM较小的0.0那条路径L1作为译码输出，译码得到的信息比特的值为0011。对Polar码级联CRC(Cyclic Redundancy Check，循环冗余校验)，简称CA-Polar，并通过CRC校验在SCL译码输出的候选路径中选择CRC通过的路径作为译码输出，CA-SCL(CRC-Aided Successive Cancellation List)译码算法，能显著提高Polar码的性能。
CA-Polar码构造过程：假设信息块大小为K info，CRC长度为K crc，Polar编码的母码码长为N，则需要从N个极化信道中选择K info+K crc个可靠度最高的作为信息比特，其余的作为冻结比特。CA-Polar编码过程如图4所示，先对信息块进行CRC编码，然后将CRC编码后的比特映射到信息比特的位置，在冻结比特的位置放置发送端和接收端约定的固定值，然后再进行Polar编码，得到CA-Polar的编码块。SCL译码过程中，信息块和CRC比特均未知，按照正常的SCL译码过程进行译码。在SCL译码结束后，得到L个候选译码结果，译码结果中包括信息块和CRC比特。从PM最小的路径开始，对每个候选结果进行CRC校验，如果校验通过，则将该路径的信息块作为译码输出；如果CRC校验均未通过，将PM最小的路径的信息块作为译码输出，或者也可以直接指示译码失败。
如图5所示，在CA-Polar的编译码过程中，CRC比特均作为信息比特处理，在SCL译码结束时CRC比特用于辅助选择路径。但是在SCL的中间节点，正确路径可能因为PM较大被删除。
本申请实施例在CA-Polar中加入校验冻结比特，该校验冻结比特的值由其前面的信息比特的值确定，也就是说，利用该校验冻结比特对前面的信息比特进行校验，用于辅助CA-Polar的SCL译码，在中间节点提高删除错误路径的概率，提高CA-Polar的性能。这里的校验冻结比特是相对于原来的冻结比特称呼的，表示原来的冻结比特中会有一部分被选出来用于放置与信息比特有关联的值，也就是该冻结比特用于校验其之前的至少一个信息比特。校验冻结比特也可以叫做奇偶校验比特或者奇偶校验冻结比特。在一些实施例中，这样的冻结比特也可以叫做动态冻结比特，每次发送的信息块大小、码长等参数不同，这样的动态冻结比特位置会改变，并不一定总是固定在某个位置，相应的其余的冻结比特可以叫做静态冻结比特。为了便于描述，以下统一称作校验冻结比特。
如图6所示，编码过程包括：
(1)CRC编码：根据CA-Polar的构造算法，选择可靠度高的极化信道作为信息比特，对信息块进行CRC编码，将编码后的比特映射到信息比特；
(2)校验冻结比特编码：从剩下的极化信道中确定校验冻结比特，构造校验方程，根据信息比特的值和校验方程计算校验冻结比特的值；其余的冻结比特放置约定的固定值；
(3)Polar编码：对信息比特、校验冻结比特和其余的冻结比特进行Polar编码，得到Polar编码块；
接收端译码时，采用SCL译码算法进行译码，将校验冻结比特作为冻结比特处理，不进行路径扩展，但校验冻结比特的值由前面译码得到的信息比特的值及校验方程确定；SCL译码结束后，得到L条候选路径，用CRC从候选路径中选择CRC校验通过的路径作为译码输出。译码时，该CRC既可以用于从候选路径中挑选译码结果，也可以用于检错即判断译码结果正确与否。
由于校验冻结比特的值由前面译码得到的信息比特的值及校验方程确定，一旦前面译码的信息比特有误，那么在译码该校验冻结比特时，该校验冻结比特通过信息比特计算得到的值与接收的LLR对应的值不一致性的可能增大，相应的在计算该条路径的PM值时，根据前述公式(1)的计算，PM值会加上该校验冻结比特LLR的绝对值，从而加大了该路径的PM值，该路径在后续译码过程中被删除的可能性加大。
如图7所示的编码装置700可以执行编码方法。如图7所示，本申请实施例的编码方法可以包括以下过程：
801、获取信息比特和冻结比特的位置。
获取单元701根据极化信道的可靠度排序获取信息比特和冻结比特的位置，所述信息比特对应的极化信道的可靠度高于所述冻结比特对应的极化信道的可靠度。具体的，获取单元701根据极化信道的可靠度排序，从中选择K info+K crc个最可靠的作为信息比特，K info是待编码信息块的大小，K crc是CRC比特的个数。剩余的极化信道作为冻结比特。
802、对信息块进行循环冗余校验CRC编码，将CRC编码后的比特映射到所述信息比特。
CRC编码单元702对信息块进行CRC编码，得到K info+K crc个CRC编码比特，将其映射到信息比特。
803、确定所述冻结比特中的至少一个比特作为校验冻结比特，所述校验冻结比特的值由该校验冻结比特之前的信息比特中符合预设条件的P个信息比特的值确定，P为大于等于1的整数。
确定单元703确定从步骤801所确定的冻结比特中，确定至少一个比特作为校验冻结比特，校验冻结比特的值由该校验冻结比特之前的信息比特中符合预设条件的P个信息比特的值确定，P为大于等于1的整数。这里所说的校验冻结比特，表示该比特的值与其他比特的值有关。在本申请的一个实施例中，其他比特选择的信息比特，而非冻结比特。“校验冻结比特”的称呼是为了与现有的冻结比特(固定比特)做区 分，还可以有其他的名称，比如动态冻结比特、奇偶校验比特等。由于Polar码的特性，通常序号最小的前几个极化信道可靠度是最低的，因而通常Polar码的前几个极化信道是作为冻结比特的，也就是在第一个信息比特之前通常存在一个或者多个冻结比特，如果校验冻结比特是用于校验其之前的信息比特，那么最初的这些冻结比特之前没有信息比特，所以不能用于作为校验冻结比特。校验冻结比特以外的其他冻结比特的值，设置为收发端已知的固定值，0或者1。
804、对所述信息比特、校验冻结比特和所述校验冻结比特以外的其他冻结比特进行Polar编码。
Polar编码单元704对信息比特、校验冻结比特和所述校验冻结比特以外的其他冻结比特进行Arikan Polar编码，得到编码块。编码得到的编码块也可以叫做编码序列、编码码字等。
本申请的校验冻结比特，选自于冻结比特，而冻结比特在极化信道的排序中，极化信道可靠度低于信息比特。如图9所示，本申请实施例构造的Polar码，信息块和CRC比特一起分布在最可靠的极化信道上，校验冻结比特(校验比特)分布在可靠度低于信息比特的极化信道上；如果按照自然序排列，则校验冻结比特散布在信息块和CRC比特中。校验冻结比特的引入，对现有CA-Polar的性能不但没有损失，还能提升译码的准确率。
步骤803中，确定冻结比特中的至少一个比特作为校验冻结比特的方式，可以是所有的冻结比特都作为校验冻结比特，但是如果某一个校验冻结比特之前没有信息比特(例如图9所示的按照极化信道自然序(编码顺序)排序后，第一个校验冻结比特之前没有信息比特，则该校验冻结比特按照原有的方式处理，仍保留为冻结比特，设为收发端已知的固定值。也可以按照一定的条件选择部分冻结比特作为校验冻结比特，而不是默认所有的都是校验冻结比特。
每个冻结比特去参考其之前的信息比特，如图10所示，校验冻结比特可以参考其之前的一个信息比特或者多个信息比特。也就是说，校验冻结比特的值可以由其前面的一个信息比特或者多个信息比特确定。在编译码端可以根据相同的规则，构造校验方程(校验函数)。因为信道编码处理的对象是0和1，所以当用校验冻结比特校验其之前的信息比特的时候，可以用奇偶校验的方式。例如，某个冻结比特校验(参考)其之前的1个信息比特，则在编码端的时候将该信息比特的值赋给该校验冻结比特。如果某个校验冻结比特校验之前的2个信息比特，则将该2个信息比特的值进行二进制相加(异或)后的值赋给该校验冻结比特。
符合预设条件的P个信息比特可以通过多个方式确定。在一个实施例中，可以基于一个约定的数值Q来选择参与确定冻结比特的值的信息比特，Q是大于1的整数。例如选择某个校验冻结比特之前、与该校验冻结比特序号模Q的值相同的序号的信息比特，作为参与该校验冻结比特校验的信息比特。例如Q＝5，假设极化信道U 18确定为一个校验冻结比特，则处于极化信道U 13、U 8、U 3的信息比特作为参与确定U 18的值的信息比特，即U 18＝U 3+U 8+U 13，如果U 3不是信息比特，则不参与校验，校验方程变为U 18＝U 8+U 13； 如果U 13、U 8、U 3都不是信息比特，则校验方程变为U 18＝0，U 18仍保留为冻结比特。由于Polar码SC顺序译码的特点，校验冻结比特用于校验其前面的信息比特。因此，在第一个信息比特之前的冻结比特没有信息比特可以校验，那仍保留为冻结比特。这里所说的Q的取值，可以根据母码码长等参数确定。例如，码长越长，Q的取值可以取大一些。Q也可以约定为是质数或者奇数，例如Q可以为3、5、7、或9等。在硬件实现的时候，可以通过移位寄存器读取参与校验的信息比特。如果Q是质数，则采用质数移位寄存器实现。校验方程也可以采用组合的方案，例如选择与该校验冻结比特序号模Q或模M的值相同的序号的信息比特参与校验。若例如，Q＝5，M＝7，则U18＝U 3+U 8+U 13+U 11+U 4。同样的，如果通过该校验方程选定的比特不是信息比特，则该信息比特不参与确定该校验冻结比特的值。作为另一个可选的方式，符合预设条件的P个信息比特，也可以约定为校验冻结比特之前的序号为奇数或者质数的所有信息比特。所述P个信息也可以通过以下方式确定：选择序号与所述校验冻结比特的序号模Q1、模Q2、…、或模Qh的值相同的信息比特参与确定校验冻结比特的值，h为大于等于2的整数，Q1、Q2、…、Qh分别为大于等于1且互不相同的整数。也就是说，在通过取模确定哪些信息比特参与确定校验冻结比特的值时，可以用一个数来取模，例如5，也可以同时用两个数或更多的数分别对校验冻结比特之前的信息比特的序号进行取模来确定P个信息比特。例如将与校验冻结比特模3、模5或模7相同的值的所有序号对应的信息比特都用于确定该校验冻结比特的值。
在一个实施例中，符合预设条件的P个信息比特可以通过随机的方式确定，也就是说可以随机构造每个冻结比特的校验方程。例如根据约定的随机种子产生随机数，来确定某校验冻结比特之前的各信息比特是否参与各校验冻结比特的校验。例如，根据约定的随机种子产生(0，1)之间均匀分布的数，可以是小数或分数，可以只产生大于0小于1的数，也可以包括0或1本身的数。对于每一个校验冻结比特，对其前面的每一个信息比特，通过随机种子产生一个随机数，如果该随机数小于门限T，则该信息比特参与确定该校验冻结比特的值，如果该数大于等于门限T，则该信息比特不参与确定该校验冻结比特的值。收发两端采用相同的随机种子，就可以产生相同的随机数，从而保证编译码的配置是一致的。T取值为大于0小于1的数，例如可以设置为等于或者约定于1/3或1/5的数。门限T决定了信息比特参与校验的概率和各校验方程的复杂度。这里T越大，信息比特参与校验的概率越高，各校验冻结比特的校验方程越复杂。
符合预设条件的P个信息比特，可以简单设置为1个信息比特，即P＝1。构造单比特校验方程，各校验冻结比特只用于校验其前面的某一个信息比特，即各校验冻结比特的值只由该冻结比特前面的某个信息比特的值确定。由于Arikan Polar内核的结构性，校验相距2 m位置的信息比特可能不能带来性能增益。因此单比特校验时，可以选择位于校验冻结比特之前，距其最近的且距离不等于2 m的信息比特，作为参与确定该校验冻结比特的值的信息比特，这里m为大于等于0的整数。按照极化信道的自然排序，所选择的1个信息比特为距该校验冻结比特最近的、且该校验冻结比特的序号与这1个信息比特的序号的之差不等于2的整数次幂
选择符合预设条件的P个信息比特，可以选择对该校验冻结比特的极化信道的码距有提升的信息比特。校验冻结比特对Polar性能的提升，主要来自对Polar码码距的提高。Arikan Polar码的码重可以计算为各信息比特所在的编码矩阵的行(又称行向量)中1的个数。例如，母码长度为32的Polar码的编码矩阵G 32如图19所示。
第15个比特U 15所在的编码矩阵的行是：
R 15＝[1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
R 15中共有8个1，即其码重为8。假设U 15如果对应的极化信道为信息比特，且是信息比特中码重最小的，则此Polar码的最小码距即是8。如果用U 18去校验该信息比特，校验方程为U 18＝U 15，其中U 18所在的编码矩阵的行为：
R 18＝[1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
根据二进制的特点，该校验方程等效于U 15+U 18＝0。对应到Polar编码，冻结比特的编码相当于U 15*R 15+U 18*R 18＝U 15*(R 15+R 18)。也就是说，对于U 18的冻结比特，等效的编码为：
R 15+R 18＝[0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
R 15+R 18得到的行向量，1的个数为10，也就是该校验方程能够将码重从8提高为10。具有提高码重效果的校验方程能提高Polar码性能。相对于某个冻结比特而言，在其之前若存在至少一个信息比特，满足这样的条件：其所在的编码矩阵的行与该校验冻结比特所在的编码矩阵的行相加后得到的行向量1的个数大于该信息比特所在的编码矩阵的行向量中1的个数，则可以将满足该条件的该校验冻结比特称为有效校验冻结比特。因此，某一校验冻结比特之前的信息比特可以用于确定该校验冻结比特是否有效。相应的，符合预设条件的P个信息比特可以是符合该条件的信息比特。在通过前面的方法获得P个信息比特之后，只选择P个信息比特中满足该条件的比特参与确定对应的校验冻结比特的值，若没有信息比特满足条件，则该校验冻结比特无效，该校验冻结比特仍然保留为做冻结比特，其设置为已知的固定值。
本申请实施例中，并非一定要选择所有冻结比特作为校验冻结比特，也可以仅仅选择部分冻结比特作为校验冻结比特。那么校验冻结比特的确定原则是可以是选出满足上述条件的有效校验冻结比特。实现的时候，可以针对每个信息比特搜索有效的校验冻结比特，然后构造校验方程；也可以针对每个冻结比特，先作为校验冻结比特处理，针对每个校验冻结比特，去搜索在其之前的有效的信息比特，然后构造校验方程，例如针对某个校验冻结比特，搜索到在其之前的有3个有效信息比特，可以全部参与校验冻结比特的确定，也可以采用单比特校验的方式，或者随机种子确定，或者序号模Q的方式确定。
本申请图6及图8的实施例中的编码方法中，对信息块进行CRC编码的方法可以用多种不同的方式，相应的，对于图14的实施例中涉及到的译码方法中的CRC校验和译码输出也不同。以下列举三种方式CRC编码及相应的校验方法。
(i)、单一CRC块编码：对K info长的信息块进行一次CRC编码，得到CRC编码比特，包括信息块和K CRC个CRC比特，然后将编码后的比特映射到信息比特。译码时， K CRC个CRC比特既用于从候选路径中挑选译码结果，也用于译码结果正确与否的判断，即检错。
(ii)、分段式CRC编码：将信息块分成多个片段，对信息块的每段分别进行CRC编码，然后将编码后的每段编码比特映射到信息比特位置；译码时，在各分段分别进行CRC校验，可以用于挑选译码结果，也可以同时实现检错。采用该方法的好处是，是在对SCL的多个候选译码路径进行CRC校验时，可以进行分段校验。例如，如图20所示，假设信息块被分成两段，CRC也被分成两段，信息块和CRC比特的结构大致为[I1 C1 I2 C2],其中I1和I2是指被分成两段的信息比特片段，C1和C2是指被成两段分段的CRC片段，其中C1用于校验I1，C2用于校验I2或者[I1,I2]。在译码端进行CRC校验时，若发现I1未被校验通过，则I2就无需再校验，节省了校验时间。当C1、C2全部校验通过，则代表该条路径的CRC校验通过。此处举例的是信息块和CRC比特均分成两段的例子，在实际应用中，具体分成多少段可以任意设置。
(iii)、多级CRC编码：除了方式(i)(ii)中所述的K CRC个CRC比特之外，还另外选择K’ CRC个比特进行CRC编码，即总的CRC比特包括(K CRC+K’ CRC)个。
CRC编码时，对信息块进行整体CRC编码，包括信息块和(K CRC+K’ CRC)个CRC比特，然后将编码后的比特映射到信息比特位置；其中K’ CRC是额外的CRC长度，在现有的CRC长度上添加该CRC长度，可以弥补SCL译码导致的检错性能下降。添加的CRC长度大小可以根据List大小变化。译码时，该(K CRC+K’ CRC)个CRC比特可以用于从候选路径中挑选译码结果，也可以用于检错。
另一个实施方式中，CRC编码时，先对信息块进行第一级CRC编码，得到K CRC个CRC比特，将编码后的比特作为一个整体块，进行第二级CRC编码，得到额外K’ CRC个CRC比特，再次编码后的比特映射到信息比特。可以约定其中一种CRC比特用于挑选路径，即纠错，另一个用于检错。译码时，先用纠错CRC比特从多个候选路径中选择译码结果，译码结果包含信息块和检错CRC比特。然后对译码结果用检错CRC比特进行检错。
在多级CRC编码中，K CRC为基础CRC比特。例如LTE中PBCH的K CRC定义为16比特，而在PDSCH中的传输数据块定义为24比特，这里的基础比特可以由系统MAC层指示。在不同的通信系统里对基础CRC比特可能会定义为其他长度。这里的K’ CRC是额外CRC比特，例如当Polar码采用SCL译码时，list的值越大，代表所选取的路径L越多，从L个候选路径中选出通过CRC校验通过的作为正确的译码结果。通常，长度较短的CRC比特的校验能力比长度较长的CRC的检错能力要低。因此，当List越大时，同等的CRC长度不能达到较好的检错性能。所以当List越大时，可以适当增加额外CRC比特的长度。例如，List＝8时，表示选出L＝8条候选路径，可以确定K’ CRC＝log 2(L)＝3。类似的，List＝16时，K’ CRC＝4。实现时也可以根据其他规则确定额外CRC比特的长度，不用局限于于这里的计算方式。
图21是本申请实施例提供的又一种编码方法的流程示意图，该方法可以由图7、图11或图12所示的译码装置执行。该方法包括：
2101：获取信息比特、冻结比特和校验冻结比特的位置，该步骤可以由图7的获取 单元701、图11的处理器1102或图12的信号处理器1202执行。
根据目标码长M、母码长度N、信息比特个数K获取信息比特、冻结比特和校验冻结比特的位置。例如，根据极化信道可靠度的排序，选取可高度最高的前K个比特作为信息比特，剩余的作为冻结比特，并从冻结比特中按照上面描述的方法确定校验比特的位置。这里K＝K info+K crc。K info是信息块的大小，K crc是CRC比特的个数(也可以说是CRC块的长度)。
2102：对信息块进行CRC编码。该步骤可以由图7的CRC编码单元701、图11的处理器1102或图12的信号处理器1202执行。
假设A＝K info,B＝K info+K crc，CRC编码的输入是序列a 0，a 1，a 2，...，a A-1，CRC编码后生成的校验比特是
Figure PCTCN2018073908-appb-000019
CRC的编码后输出序列是b 0，b 1，...，b B-1。CRC编码得到的序列满足公式(2)。
Figure PCTCN2018073908-appb-000020
2103：设置信息比特、冻结比特和校验冻结比特的值，得到待编码序列c 0，c 1，c 2，...，c c-1，C＝N(母码长度)。序列c 0，c 1，c 2，...，c c-1的值由以下公式(3)表示，该步骤可以由图7的确定单元703、图11的处理器1102或图12的信号处理器1202执行。
Figure PCTCN2018073908-appb-000021
2104：Arikan Polar编码，输出的编码序列为d 0，d 1，d 2，...，d D-1，其中D＝N。Polar编码的计算过程可以由以下公式(4)表示。该步骤可以由图7的Polar编码单元704执行。
Figure PCTCN2018073908-appb-000022
可选的，该方法还可以包括步骤2105：对编码序列进行速率匹配，输出速率匹配后的编码序列e 0，e 1，...，e E-1，E＝M。若目标码长与母码长度不相同，则对2104得到的编码序列进行速率匹配，例如通过重复、缩短或者打孔的方法进行速率匹配。当母码长度N小于目标码长M时，可以将编码序列重复(M-N)个比特，得到目标码长M的编码序列。若母码长度N大于目标码长M，可以通过打孔或者缩短(N-M)个比特，得到目标码长M的编码序列，打孔或者缩短的的方案可以预先设置好。步骤2105可以由图7的编码装置中的速率匹配单元(图中未示出)、图11的处理器1102或图12的信号处理器1202执行。
若采用CRC编码采用的是额外CRC比特的方式，则在步骤2101之前，还包括步骤2100、获取额外CRC长度。根据实际编码的情况，确定额外CRC长度J’，K crc＝J+J’，J为固定CRC长度(基础CRC长度)。步骤2101可以由图7中的获取单元701、图11 的处理器1102或图12的信号处理器1202执行。
本申请图6、图8及图21的实施例中的编码方法中，将CRC编码后的比特映射到信息比特时，可以有多种方式。相应的，对于图14的实施例中涉及到的译码方法中对译码结果的处理也不同。信息块与CRC比特映射到信息比特时可以进行一定交织，相对应地，译码时先对SCL的译码结果解交织，然后通过CRC校验进行路径挑选和检错。如图22所示，CRC编码后的比特包括信息块和CRC比特，信息块和CRC比特可以按照以下四种方式排序映射到信息比特的位置上。这里所说的CRC比特，包括前面(i)(ii)(iii)种CRC编码方面中涉及的单一CRC块，CRC片段、额外CRC比特、基础CRC比特。
(1)CRC比特位于信息块之后，如图22(1)所示。
(2)CRC比特位于信息块之前，如图22(2)所示。
(3)CRC比特位于信息块之间，如图22(3)所示。
(4)CRC比特分成多个片段，每个片段位于信息块之间、信息块之前或者信息块之后中的任意位置，如图22(4)所示。
如图11所示，本申请提供了另一种可以实施本申请的编码方法的编码装置1100。该编码装置1100包括：
存储器1101，用于存储程序；
处理器1102，用于执行所述存储器存储的所述程序，当所述程序被执行时，执行图8所示的编码方法。例如，该方法包括：根据极化信道的可靠度排序获取信息比特和冻结比特的位置，所述信息比特对应的极化信道的可靠度高于所述冻结比特对应的极化信道的可靠度，对信息块进行循环冗余校验CRC编码，将CRC编码后的比特映射到所述信息比特，确定所述冻结比特中的至少一个比特作为校验冻结比特，所述校验冻结比特的值由所述校验冻结比特之前的信息比特中符合预设条件的P个信息比特的值确定，P为大于等于1的整数；对所述信息比特、所述校验冻结比特和所述校验冻结比特以外的其他冻结比特进行Polar编码。
由于编码方法在前面的方法实施例中已经介绍过，处理器只是用于根据程序执行该编码方法，因此涉及编码方法的具体描述，可以参见图8以及图8对应实施例相关部分，此处不再赘述。
有关校验冻结比特的确定方式、以及P各信息比特如何选择等内容可以参照前述的编码方法。存储器1101可以是物理上独立的单元，也可以与处理器1102集成在一起。
图11的编码装置还可以进一步包括发送器(图中未示出)，用于发送处理器1102对所述信息比特和校验冻结比特进行Polar编码后得到的编码块。
如图12所示，本申请提供了另一种可以实施本申请的编码方法的编码装置1200。该编码装置1200包括：
至少一个输入端(inPut)1201，用于接收信息块；
信号处理器1202，用于根据极化信道的可靠度排序获取信息比特和冻结比特的位置， 所述信息比特对应的极化信道的可靠度高于所述冻结比特对应的极化信道的可靠度，对信息块进行循环冗余校验CRC编码，将CRC编码后的比特映射到所述信息比特，确定所述冻结比特中的至少一个比特作为校验冻结比特，所述校验冻结比特的值由所述校验冻结比特之前的信息比特中符合预设条件的P个信息比特的值确定，P为大于等于1的整数；对所述信息比特、所述校验冻结比特和所述校验冻结比特以外的其他冻结比特进行Polar编码；
至少一个输出端(outPut)1203，用于输出信号处理器1202得到的编码块。
有关校验冻结比特的确定方式、以及P个信息比特如何选择等内容可以参照前述的编码方法。
可选的，上述信号处理器1202可以是通过硬件实现的，例如，基带处理器，处理电路，编码器，或者编码电路。
由于编码方法在前面的方法实施例中已经介绍过，信号处理器1202只是用于执行该编码方法，因此涉及编码方法的具体描述，可以参见图8以及图8对应实施例相关部分，此处不再赘述。
图12的编码装置还可以进一步包括发送器(图中未示出)，用于发送输出端(outPut)1203输出的编码块。
本申请中的编码装置可以是任何具有无线通信功能的设备，例如接入点、站点、用户设备、基站等。
图13所示的译码装置1300可以用来执行本申请的译码方法。如图14所示，译码过程包括以下过程：
1401、获取待译码比特中信息比特和冻结比特的位置，确定所述冻结比特中的至少一个比特作为校验冻结比特。
获取单元1301根据极化信道的可靠度排序获取信息比特和冻结比特的位置，所述信息比特对应的极化信道的可靠度高于所述冻结比特对应的极化信道的可靠度。具体的，获取单元1301根据极化信道的可靠度排序，从中选择K info+K crc个最可靠的作为信息比特，K info是信息块的大小，K crc是CRC比特的个数。剩余的极化信道作为冻结比特。获取单元1301确定所述冻结比特中的至少一个比特作为校验冻结比特。
1402、采用串行抵消列表SCL译码算法按顺序对所述待译码比特进行译码，输出L条候选路径，其中，各个路径的所述校验冻结比特的值由所述校验冻结比特之前的信息比特中符合预设条件的P个信息比特的值确定，P为大于等于1的整数。关于校验冻结比特的位置、用于确定其值的信息比特以及校验方程的构造与编码端相同。
译码单元1302采用串行抵消列表SCL译码算法按顺序对所述待译码比特进行译码，输出度量值最优的L条候选路径，每条候选路径的译码结果包括信息块和循环冗余校验CRC比特。
在SCL译码过程中，将CRC比特作为信息比特译码，是未知比特，在译码过程中需要进行路径扩展。由于校验冻结比特的值是由其前面的信息比特和校验方程确定的，因此校验冻结比特的译码同原来的冻结比特一样，作为已知比特进行译码，在译码过 程中不进行路径扩展，只是校验冻结比特的值的译码结果用前面已经译码的信息比特和校验方程确定。具体的译码过程参考图2和图3及其相应的描述。
1403、对所述L条候选路径进行CRC校验。
CRC校验单元1303从度量值最优的候选路径开始，依次对L条候选路径进行CRC校验。CRC校验单元1303可以对所有L条候选路径都分别进行CRC校验，得出校验通过或者校验失败的结果。也可以得到第一个CRC校验通过的候选路径后，不再校验剩余的候选路径。
1404、将CRC校验通过的第一个候选路径中的信息块作为译码输出。
输出单元1304选择CRC校验通过的第一个候选路径作为译码结果，其中的信息比特对应的信息块作为本次译码的输出。
图15是SCL译码算法List＝2的示例,在译码过程中保留2个候选路径。通常前面的几个比特是冻结比特，设置为固定的值，如0。因此实际上从第一个信息比特开始译码。图15中，PM值的计算采用公式(1)计算，通过在每次扩展的时候保留PM值最小的路径，后得到如箭头所示的两条候选路径L1和L2。路径L1最终的PM值为0.3，另一条路径L2的PM值最终为0.2。从PM最小(度量值最优)的路径L2先进行CRC校验，若校验通过则选择L2作为译码输出。若L2路径校验不通过，继续校验L1路径，若校验通过，选择L1作为译码输出。若L1和L2均校验未通过，可以选择PM较小的(度量值最优)的L2路径作为译码结果输出。若L1和L2均校验未通过，也可以确认为本次译码失败。
图15中，图中标示的第i个比特是校验冻结比特，两个箭头1501表示该校验冻结比特的值是由第i-3个比特(信息比特)确定。可以看到在译码第i个比特的时候，不需要进行路径扩展，第i个比特的值由该路径中第i-3个比特的值确定，因此路径L1中的校验冻结比特的值是0，L2中的校验冻结比特的值是1。图15和图3的区别在于，第i个比特在图3中对应的是冻结比特，而在图15中对应的是校验冻结比特。图15中，PM值在译码到校验冻结比特的时候，PM值与图3相比发生了变化。具体的，图15中假设L1和L2路径的校验冻结比特的LLR(i)小于0，假设LLR(i)小于0对应的值是1，L1路径中的i比特的译码结果0与LLR(i)的结果不一致，根据公式(1)PM值加|LLR(i)|，假设为0.3。L2路径中，i比特的译码结果1与LLR(i)对应的值一致，根据公式(1)，PM(i)＝PM(i-1)＝0.2。由于校验冻结比特的引入，如果L1前面的译码有误，那么该冻结比特i参考了前面的信息比特i-1的结果也是有误的，这样就会导致i比特的译码结果与LLR(i)对应的值不一致的概率增加，PM(i)就会加上惩罚值|LLR(i)|，导致该路径的PM值加大，在译码过程中该错误路径被删除的概率也加大，因为本例中PM值越小，才是越优的。
图16是本申请的方案与传统的CA-Polar在AWGN信道下的性能对比。在传统的CA-Polar中，除了信息比特外，其余的极化信道均为冻结比特，设置为全0。图16中，本申请的方案则是采用所有冻结比特均为校验冻结比特，且通过选择与校验冻结比特序号模5的值相同的序号的信息比特参与确定校验冻结比特的值。从图16中可以 看出，本申请的技术方案相对传统的CA-Polar有0.2dB到0.3dB之间的性能增益。码率越低，增益越大，这是因为在低码率时，可用作校验冻结比特的极化信道更多，SCL译码过程中正确路径保留下来的概率更高。
如图17所示的译码装置1700也可以用于执行译码方法，该译码装置1700包括：
存储器1701，用于存储程序；
处理器1702，用于执行所述存储器存储的所述程序，当所述程序被执行时，执行图14所示的译码方法。该方法包括：获取待译码比特中信息比特和冻结比特的位置，确定所述冻结比特中的至少一个比特作为校验冻结比特；采用串行抵消列表SCL译码算法按顺序对所述待译码比特进行译码，输出度量值最优的L条候选路径，每条候选路径的译码结果包括信息块和循环冗余校验CRC比特，其中，各个路径中的所述校验冻结比特的值由所述校验冻结比特之前的信息比特中符合预设条件的P个信息比特译码得到的值确定，P为大于等于1的整数；从度量值最优的候选路径开始，对所述L条候选路径进行CRC校验，将CRC校验通过的第一个候选路径中的信息块作为译码输出。
若L条候选路径的CRC校验均未通过，可以选择度量值最优的路径作为译码输出，也可以确认为译码失败。
有关校验冻结比特的确定方式、以及P各信息比特如何选择等内容可以参照前述的编码方法和译码方法的实施例。存储器1701可以是物理上独立的单元，也可以与处理器1702集成在一起。
图17的译码装置还可以进一步包括接收器(图中未示出)，用于接收编码装置发送的编码块，对于译码装置来说，即待译码的比特或待译码的比特序列。
如图18所示，本申请提供了另一种可以实施本申请的编码方法的译码装置1800。该译码装置1800包括：
至少一个输入端(input)1801，用于接收待译码比特信息；
信号处理器1802，用于获取待译码比特中信息比特和冻结比特的位置，确定所述冻结比特中的至少一个比特作为校验冻结比特；采用串行抵消列表SCL译码算法按顺序对所述待译码比特进行译码，输出度量值最优的L条候选路径，每条候选路径的译码结果包括信息块和循环冗余校验CRC比特，其中，各个路径中的所述校验冻结比特的值由所述校验冻结比特之前的信息比特中符合预设条件的P个信息比特译码得到的值确定，P为大于等于1的整数；从度量值最优的候选路径开始，对所述L条候选路径进行CRC校验；
至少一个输出端(output)1803，用于将CRC校验通过的第一个候选路径中的信息块作为译码输出。
有关校验冻结比特的确定方式、以及P个信息比特如何选择等内容可以参照前述的编码方法和译码方法的实施例。
可选的，上述信号处理器1802可以是通过硬件实现的，例如，基带处理器，处理 电路，解码器，或者解码电路。
图18的译码装置还可以进一步包括接收器(图中未示出)，用于接收编码装置发送的编码块，对于译码装置来说，即待译码的比特或待译码的比特序列。
本申请实施例的译码装置可以是任何具有无线通信功能的设备，例如接入点、站点、用户设备、基站等。
本申请实施例所说的串行抵消列表SCL译码算法，包括其他按顺序译码、提供多条候选路径的类似SCL的译码算法或者对SCL译码算法的改进算法。
本申请实施例所说的编码装置或译码装置，在实际使用中可能是分别独立的设备；也可能是集成在一起的设备，用于待发送信息进行编码后发送，或者对接收到的信息进行译码。
本申请实施例描述的各示例的单元及方法过程，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。例如多个单元或组件可以结合或者可以集成到另一个系统。方法中的一些步骤可以忽略，或不执行。此外，各个单元相互之间的耦合或直接耦合或通信连接可以是通过一些接口实现，这些接口可以是电性、机械或其它的形式。
作为分离部件说明的单元可以是或者也可以不是物理上分开的，既可以位于一个地方，也可以分布到多个网络单元上。另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本发明实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者通过所述计算机可读存储介质进行传输。所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心、等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带、U盘、ROM、RAM等)、光介质(例如，CD、DVD等)、或者半导体介质(例如固态硬盘Solid State Disk(SSD))等。

Claims (35)

  1. 一种Polar编码方法，其特征在于，包括：
    根据极化信道的可靠度排序获取信息比特和冻结比特的位置，所述信息比特对应的极化信道的可靠度高于所述冻结比特对应的极化信道的可靠度；
    对信息块进行循环冗余校验CRC编码，将CRC编码后的比特映射到所述信息比特；
    确定所述冻结比特中的至少一个比特作为校验冻结比特，所述校验冻结比特的值由所述校验冻结比特之前的信息比特中符合预设条件的P个信息比特的值确定，P为大于等于1的整数；
    对所述信息比特、所述校验冻结比特和所述校验冻结比特以外的其他冻结比特进行Polar编码。
  2. 根据权利要求1所述的方法，其特征在于，所述P个信息比特的序号与所述校验冻结比特的序号模Q的值相同，Q为大于等于1的整数。
  3. 根据权利要求2所述的方法，其特征在于，所述Q为质数或奇数。
  4. 根据权利要求3所述的方法，其特征在于，所述Q为3、5、7或9。
  5. 根据权利要求1所述的方法，其特征在于，所述符合预设条件的P个信息比特是从所述该校验冻结比特之前的所有信息比特中随机确定的信息比特。
  6. 根据权利要求5所述的方法，其特征在于，对于每一个校验冻结比特，对该校验冻结比特前面的每一个信息比特采用随机种子产生一个随机数，如果该随机数小于预设的门限T，则该信息比特参与确定该校验冻结比特的值。
  7. 根据权利要求6所述的方法，其特征在于，所述随机种子产生0到1之间均匀分布的随机数，T为大于0小于1的值。
  8. 根据权利要求1所述的方法，其特征在于，所述P个信息比特包括：序号与所述校验冻结比特的序号模Q1、模Q2、…、或模Qh的值相同的信息比特，h为大于等于2的整数，Q1、Q2、…、Qh分别为大于等于1且互不相同的整数；或
    所述P个信息比特中的每个信息比特的序号与所述校验冻结比特的差不等于2的整数次幂。。
  9. 根据权利要求1所述的方法，其特征在于，其特征在于，P＝1。
  10. 根据权利要求9所述的方法，其特征在于，所述1个信息比特为距所述校验冻结比特最近的、且所述校验冻结比特的序号与所述1个信息比特的序号的差不等于2的整数次幂。
  11. 根据权利要求1-10任意一项所述的方法，其特征在于，所述编码矩阵中对应P个信息比特中任一信息比特的行向量与编码矩阵中对应所述校验冻结比特的行向量相加得到的向量中1的个数大于编码矩阵中对应所述任一信息比特的行向量的1的个数。
  12. 根据权利要求1-11任意一项所述的方法，其特征在于，对信息块进行CRC编码包括以下中的任意一种：
    对信息块进行CRC编码，得到CRC编码后的比特，所述CRC编码后的比特包括信息块和K CRC个CRC比特，其中，K CRC为预先设置的固定CRC长度；或
    将所述信息块分成多个片段，分别对所述信息块的每个片段进行CRC编码，得到 CRC编码后的比特，所述CRC编码后的比特包括信息块和K CRC个CRC比特，K CRC为预先设置的固定CRC长度或者为固定CRC长度加上额外CRC长度后的长度；或
    对所述信息块进行整体CRC编码，得到CRC编码后的比特，所述CRC编码后的比特包括信息块和(K CRC+K’ CRC)个CRC比特，其中，K CRC为预先设置的固定CRC长度，K’ CRC为额外的CRC长度；或
    对信息块进行第一级CRC编码，得到CRC编码后的比特，所述第一级CRC编码后的比特包括信息块和K CRC个CRC比特，将第一级CRC编码后的比特作为一个整体块，进行第二级CRC编码，得到第二级CRC编码后的比特，所述第二级CRC编码后的比特包括信息块、K CRC个第一级CRC比特和K’ CRC个第二级CRC比特，其中，K CRC为预先设置的固定CRC长度，K’ CRC为额外CRC长度；
    其中，K CRC、K CRC、K’ CRC为大于0的整数。
  13. 根据权利要求1-12任意一项所述的方法，其特征在于，将CRC编码后的比特映射到所述信息比特后，CRC比特与信息块的位置包括以下中的任意一种：
    CRC比特排在信息块之后；或
    CRC比特排在信息块之前；或
    CRC比特排在信息块之间；或
    CRC比特分成多个片段，每个片段位于信息块之间、信息块之前或者信息块之后中的任意位置。
  14. 一种编码装置，其特征在于，包括：
    获取单元，用于根据极化信道的可靠度排序获取信息比特和冻结比特的位置，所述信息比特对应的极化信道的可靠度高于所述冻结比特对应的极化信道的可靠度；
    CRC编码单元，用于对信息块进行循环冗余校验CRC编码，将CRC编码后的比特映射到所述信息比特；
    确定单元，用于确定所述冻结比特中的至少一个比特作为校验冻结比特，所述校验冻结比特的值由所述校验冻结比特之前的信息比特中符合预设条件的P个信息比特的值确定，P为大于等于1的整数；
    Polar编码单元，用于对所述信息比特、所述校验冻结比特和所述校验冻结比特以外的其他冻结比特进行Polar编码。
  15. 根据权利要求14所述的装置，其特征在于，所述P个信息比特的序号是与所述校验冻结比特的序号模Q的值相同，Q为大于等于1的整数。
  16. 根据权利要求15所述的装置，其特征在于，所述Q为质数或奇数。
  17. 根据权利要求16所述的装置，其特征在于，所述Q为3、5、7或9。
  18. 根据权利要求14所述的装置，其特征在于，所述符合预设条件的P个信息比特是从所述该校验冻结比特之前的所有信息比特中随机确定的信息比特。
  19. 根据权利要求18所述的装置，其特征在于，对于每一个校验冻结比特，对该校验冻结比特前面的每一个信息比特采用随机种子产生一个随机数，如果该随机数小于预设的门限T，则该信息比特参与确定该校验冻结比特的值。
  20. 根据权利要求19所述的装置，其特征在于，所述随机种子产生0到1之间均匀分布的随机数，T为大于0小于1的值。
  21. 根据权利要求14所述的装置，其特征在于，所述P个信息比特包括：序号与所述校验冻结比特的序号模Q1、模Q2、…、或模Qh的值相同的信息比特，h为大于等于2的整数，Q1、Q2、…、Qh分别为大于等于1且互不相同的整数；或
    所述P个信息比特中的每个信息比特的序号与所述校验冻结比特的差不等于2的整数次幂。
  22. 根据权利要求14所述的装置，其特征在于，其特征在于，P＝1。
  23. 根据权利要求22所述的装置，其特征在于，其特征在于，所述1个信息比特为距所述校验冻结比特最近的、且所述校验冻结比特的序号与所述1个信息比特的序号的之差不等于2的整数次幂。
  24. 根据权利要求14-23任意一项所述的装置，其特征在于，所述编码矩阵中对应P个信息比特中任一信息比特的行向量与编码矩阵中对应所述校验冻结比特的行向量相加得到的向量中1的个数大于编码矩阵中对应所述任一信息比特的行向量的1的个数。
  25. 根据权利要求14-24任意一项所述的装置，其特征在于，对信息块进行CRC编码包括以下中的任意一种：
    对信息块进行CRC编码，得到CRC编码后的比特，所述CRC编码后的比特包括信息块和K CRC个CRC比特，其中，K CRC为预先设置的固定CRC长度；或
    将所述信息块分成多个片段，分别对所述信息块的每个片段进行CRC编码，得到CRC编码后的比特，所述CRC编码后的比特包括信息块和K CRC个CRC比特，K CRC为预先设置的固定CRC长度或者为固定CRC长度加上额外CRC长度后的长度；或
    对所述信息块进行整体CRC编码，得到CRC编码后的比特，所述CRC编码后的比特包括信息块和(K CRC+K’ CRC)个CRC比特，其中，K CRC为预先设置的固定CRC长度，K’ CRC为额外的CRC长度；或
    对信息块进行第一级CRC编码，得到CRC编码后的比特，所述第一级CRC编码后的比特包括信息块和K CRC个CRC比特，将第一级CRC编码后的比特作为一个整体块，进行第二级CRC编码，得到第二级CRC编码后的比特，所述第二级CRC编码后的比特包括信息块、K CRC个第一级CRC比特和K’ CRC个第二级CRC比特，其中，K CRC为预先设置的固定CRC长度，K’ CRC为额外CRC长度；
    其中，K CRC、K CRC、K’ CRC为大于0的整数。
  26. 根据权利要求14-25任意一项所述的装置，其特征在于，将CRC编码后的比特映射到所述信息比特后，CRC比特与信息块的位置包括以下中的任意一种：
    CRC比特排在信息块之后；或
    CRC比特排在信息块之前；或
    CRC比特排在信息块之间；或
    CRC比特分成多个片段，每个片段位于信息块之间、信息块之前或者信息块之后中的任意位置。
  27. 一种编码装置，其特征在于，包括：
    存储器，用于存储程序；
    处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理 器用于执行权利要求1-13任意一项所述的方法。
  28. 一种编码装置，其特征在于，包括：
    至少一个输入端，用于接收信息块；
    信号处理器，用于执行权利要求1-13任意一项所述的方法；
    至少一个输出端，用于输出信号处理器得到的编码块。
  29. 一种Polar译码方法，其特征在于，包括：
    获取待译码比特中信息比特和冻结比特的位置,确定所述冻结比特中的至少一个比特作为校验冻结比特；
    采用串行抵消列表SCL译码算法按顺序对所述待译码比特进行译码，输出度量值最优的L条候选路径，每条候选路径的译码结果包括信息块和循环冗余校验CRC比特；其中，各个路径中的所述校验冻结比特的值由所述校验冻结比特之前的信息比特中符合预设条件的P个信息比特译码得到的值确定，P为大于等于1的整数；
    从度量值最优的候选路径开始，对所述L条候选路径进行CRC校验，将CRC校验通过的第一个候选路径中的信息块作为译码输出。
  30. 一种译码装置，其特征在于，包括：
    获取单元，用于获取待译码比特中信息比特和冻结比特的位置，确定所述冻结比特中的至少一个比特作为校验冻结比特；
    译码单元，用于采用串行抵消列表SCL译码算法按顺序对所述待译码比特进行译码，输出度量值最优的L条候选路径，每条候选路径的译码结果包括信息块和循环冗余校验CRC比特；其中，各个路径中的所述校验冻结比特的值由所述校验冻结比特之前的信息比特中符合预设条件的P个信息比特译码得到的值确定，P为大于等于1的整数；
    CRC校验单元，用于从度量值最优的候选路径开始，对所述L条候选路径进行CRC校验；
    输出单元，用于将CRC校验通过的第一个候选路径中的信息块作为译码输出。
  31. 一种译码装置，其特征在于，包括：
    存储器，用于存储程序；
    处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于执行权利要求29所述的方法。
  32. 提供一种译码装置，包括：
    至少一个输入端，用于接收待译码比特信息；
    信号处理器，用于执行权利要求29所述的方法；
    至少一个输出端，用于将CRC校验通过的第一个候选路径中的信息块作为译码输出。
  33. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述权利要求1-13任意一项所述的方法或权利要求29所述的方法。
  34. 一种计算机程序产品，其特征在于，当其在计算机上运行时，使得计算机执 行执行上述权利要求1-13任意一项所述的方法或权利要求29所述的方法。
  35. 一种计算机程序，当其在计算机上运行时，使得计算机执行上述权利要求1-13任意一项所述的方法或权利要求29所述的方法。
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