WO2016191996A1 - 极化码的路径合并方法、装置以及译码装置 - Google Patents

极化码的路径合并方法、装置以及译码装置 Download PDF

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Publication number
WO2016191996A1
WO2016191996A1 PCT/CN2015/080448 CN2015080448W WO2016191996A1 WO 2016191996 A1 WO2016191996 A1 WO 2016191996A1 CN 2015080448 W CN2015080448 W CN 2015080448W WO 2016191996 A1 WO2016191996 A1 WO 2016191996A1
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Prior art keywords
paths
bits
reliability
polar code
decoding
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PCT/CN2015/080448
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English (en)
French (fr)
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李斌
沈晖
陈凯
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华为技术有限公司
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Priority to CN201580080360.XA priority Critical patent/CN107636973B/zh
Priority to CN202010036108.1A priority patent/CN111162798B/zh
Priority to PCT/CN2015/080448 priority patent/WO2016191996A1/zh
Publication of WO2016191996A1 publication Critical patent/WO2016191996A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6561—Parallelized implementations

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  • the present invention relates to the field of mobile communication technologies, and in particular, to a path combining method, apparatus, and decoding apparatus for a polarized code.
  • Polarization code is an encoding technology that has received increasing attention in recent years. By constructing a composite channel, the original channel characteristics are changed, so that the capacity of the composite channel is closer to the high and low poles. Due to this characteristic, the polarization code can be adapted to the randomly distributed original channel by a suitable coding design, and achieves good performance and approaches the channel capacity under many different channel implementations. Moreover, it can eliminate decoding by interference, greatly reducing the complexity of the receiver, and is very advantageous for implementation.
  • the decoding of the Polar code can be performed by SC (successive-cancellation)-list (list) decoding.
  • SC-List decoding it is necessary to search for the path with the highest probability from multiple paths.
  • the hardware implementation of such a search process is very complex and resource intensive when the number of decoded bits is large. As such, the encoding ability of the Polar code will not be fully utilized.
  • the embodiment of the invention discloses a path merging method for polarization code decoding, which aims to solve the problem that the number of search paths is large and the search process complexity is high.
  • the embodiment of the present invention discloses a path merging method for the polarization of the Polar code.
  • the code length of the Polar code is N, and the method includes:
  • N is a positive integer power of 2
  • k is a positive integer greater than or equal to 2
  • M is a positive integer multiple of k
  • L is a positive integer.
  • the M+1th to the M+kth bits of the Polar code include w low reliability bits and kw high reliability bits, w
  • the decoded L strips are determined from the 2k ⁇ L stripe paths according to the reliability of the M+1th to the M+thth bits of the Polar code. Survival paths, including:
  • determining the decoded L surviving paths from the 2w ⁇ L extension paths includes:
  • Determining the L paths with the highest probability from the 2w ⁇ L extended paths is the decoded L surviving paths.
  • determining the decoded L-survival path includes:
  • a decoded surviving path is determined according to each of the L surviving paths before the decoding, respectively, as follows:
  • a surviving path is determined from the 2w extension paths.
  • the high reliability bit is the reliability is higher than the threshold a bit
  • the low reliability bit being a bit having a reliability lower than the threshold
  • the threshold being determined according to the following method:
  • the threshold is an average of the reliability of the N bits included in the Polar code.
  • the threshold is the median of the reliability of the N bits included in the Polar code.
  • the high reliability bit is arranged in descending order of reliability Bits located in bits 1 through P, where P is a positive integer less than N.
  • the embodiment of the present invention provides a path merging device for the polarization of the Polar code.
  • the code length of the Polar code is N, and the device includes:
  • An obtaining module configured to acquire L survival paths before decoding determined by decoding the first M bits of the Polar code
  • An expansion module configured to decode the M+1th to the M+thth bits of the Polar code, and obtain 2k ⁇ L extended paths;
  • a merging module configured to determine, according to the reliability of the M+1th to the M+kth bits of the Polar code, the decoded L survival paths from the 2k ⁇ L extension paths;
  • N is a positive integer power of 2
  • k is a positive integer greater than or equal to 2
  • M is a positive integer multiple of k
  • L is a positive integer.
  • the M+1th to the M+kth bits of the Polar code include w low reliability bits and kw high reliability bits, w
  • the merge module is used to:
  • the merging module is used to:
  • Determining the L paths with the highest probability from the 2w ⁇ L extended paths is the decoded L surviving paths.
  • the merging module is configured to determine, according to each of the L surviving paths before the decoding, a decoded surviving path. ,Specifically:
  • a surviving path is determined from the 2w extension paths.
  • the high reliability bit is a bit with a reliability higher than a threshold
  • the low reliability bit is a bit whose reliability is lower than the threshold
  • the threshold is determined according to the following method:
  • the threshold is an average of the reliability of the N bits included in the Polar code.
  • the threshold is the median of the reliability of the N bits included in the Polar code.
  • the high reliability bit is ranked in the first order of reliability as being located in the first Bits to P, where P is a positive integer less than N.
  • the embodiment of the present invention discloses a path merging device for the polarization of the Polar code.
  • the code length of the Polar code is N, and the device includes:
  • An obtaining module configured to acquire L survival paths before decoding determined by decoding the first M bits of the Polar code
  • An expansion module configured to decode the M+1th to the M+thth bits of the Polar code, and obtain 2k ⁇ L extended paths;
  • a merging module configured to determine, according to the reliability of the M+1th to the M+kth bits of the Polar code, the decoded L survival paths from the 2k ⁇ L extension paths;
  • a processing module configured to obtain a decoding result of the Polar code according to the decoded L-survival path
  • N is a positive integer power of 2
  • k is a positive integer greater than or equal to 2
  • M is a positive integer multiple of k
  • L is a positive integer.
  • the M+1th to the M+kth bits of the Polar code include w low reliability bits and kw high reliability bits, w Big For an integer equal to or less than 0 and less than k, the merge module is used to:
  • the merging module is used to:
  • Determining the L paths with the highest probability from the 2w ⁇ L extended paths is the decoded L surviving paths.
  • the merging module is configured to determine, according to each of the L surviving paths before the decoding, a decoded surviving path. ,Specifically:
  • a surviving path is determined from the 2w extension paths.
  • the processing module selects, as the Polar code, a path with the highest probability value among the decoded L surviving paths. The decoding result.
  • the high reliability bit is more reliable than a bit of a threshold
  • the low reliability bit being a bit having a reliability lower than the threshold
  • the threshold being determined according to the following method:
  • the threshold is an average of the reliability of the N bits included in the Polar code.
  • the threshold is the median of the reliability of the N bits included in the Polar code.
  • the high reliability bit is in descending order of reliability Is the bit located at 1st to Pth, where P is a positive integer less than N.
  • the path merging method provided by the embodiment of the present invention reduces the number of determined path searches, can reduce complexity, reduce decoding delay, and improve decoding efficiency.
  • FIG. 1 is a schematic diagram of a wireless communication system according to an embodiment of the present invention.
  • 2 is a schematic diagram of path merging of one type of SC-LIST decoder
  • FIG. 3 is a schematic diagram of another parallel decoding time path combination of an SC-LIST decoder
  • FIG. 4 is a schematic diagram of another parallel decoding time path combination of an SC-LIST decoder
  • FIG. 5 is a schematic flowchart diagram of another path merging method for a polarization code according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of path merging in parallel decoding of a polarization code according to an embodiment of the present invention
  • FIG. 7 is a detailed schematic diagram of path merging in parallel decoding of another polarization code according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of path merging in parallel decoding of a polarization code according to an embodiment of the present invention.
  • FIG. 9 is a detailed schematic diagram of path merging in parallel decoding of another polarization code according to an embodiment of the present invention.
  • FIG. 10 is a detailed schematic diagram of path merging in parallel decoding of another polarization code according to an embodiment of the present invention.
  • FIG. 11 is a detailed schematic diagram of path merging in parallel decoding of another polarization code according to an embodiment of the present invention.
  • FIG. 12 is a detailed schematic diagram of path merging in parallel decoding of another polarization code according to an embodiment of the present invention.
  • FIG. 13 is a schematic block diagram of a path merging apparatus according to an embodiment of the present invention.
  • FIG. 14 is a block diagram of a decoding apparatus according to an embodiment of the present invention.
  • GSM Global System of Mobile Communication
  • GPRS General Packet Radio Service
  • CDMA code division multiple access
  • WCDMA Wideband Code Division Multiple Access
  • LTE Long Term Evolution
  • UE User Equipment
  • CN Core via Radio Access Network
  • the communication may be a user device such as a mobile phone or a computer with a mobile terminal, such as a portable, pocket, handheld, computer built-in or in-vehicle mobile device.
  • the base station may be a base station (BTS, Base Transceiver Station) in GSM or CDMA, or a base station (NodeB) in WCDMA, or an evolved base station (eNB or e-NodeB, evolutional Node B) in LTE.
  • BTS Base Transceiver Station
  • NodeB base station
  • eNB evolved base station
  • e-NodeB evolutional Node B
  • the method, device and terminal device for decoding a polarization code (Polar code) disclosed in the embodiments of the present invention can fully utilize the capability of the Polar code and improve the performance and efficiency of the Polar code.
  • FIG. 1 illustrates a wireless communication system 100 in accordance with various embodiments described herein.
  • System 100 includes a base station 102 that can include multiple antenna groups.
  • one antenna group may include antennas 104 and 106
  • another antenna group may include antennas 108 and 110
  • additional groups may include antennas 112 and 114.
  • Two antennas are shown for each antenna group, however more or fewer antennas may be used for each group.
  • Base station 102 can additionally include a transmitter chain and a receiver chain, as will be understood by those of ordinary skill in the art. They can all include multiple components related to signal transmission and reception, such as processors, modulators, multiplexers, demodulators, demultiplexers or antennas, and the like.
  • Base station 102 can communicate with one or more access terminals, such as access terminal 116 and access terminal 122. It will be appreciated that base station 102 can communicate with any number of access terminals similar to access terminals 116 and 122. Access terminals 116 and 122 can be, for example, cellular telephones, smart phones, portable computers, handheld communication devices, handheld computing devices, satellite radios, global positioning systems, PDAs, or any other suitable device for communicating over wireless communication system 100. . As shown, access terminal 116 is in communication with antennas 112 and 114, with antennas 112 and 114 transmitting information to access terminal 116 over forward link 118 and receiving information from access terminal 116 over reverse link 120.
  • access terminal 122 is in communication with antennas 104 and 106, wherein antennas 104 and 106 transmit information to access terminal 122 over forward link 124 and receive information from access terminal 122 over reverse link 126.
  • FDD Frequency Division Duplex
  • the forward link 118 can utilize a different frequency band than that used by the reverse link 120, and the forward link 124 can utilize the reverse link 126. Different frequency bands used.
  • TDD Time Division Duplex
  • the forward link 118 and the reverse link 120 can use a common frequency band
  • the forward link 124 and the reverse link 126 can use a common frequency band.
  • Each set of antennas and/or regions designed for communication is referred to as a sector of base station 102.
  • the antenna group can be designed to communicate with access terminals in sectors of the coverage area of base station 102.
  • the transmit antennas of base station 102 may utilize beamforming to improve the signal to noise ratio for forward links 118 and 124 of access terminals 116 and 122.
  • the base station 102 transmits to the randomly dispersed access terminals 116 and 122 in the relevant coverage area by the base station as compared to all of the access terminals transmitted by the base station, the mobile devices in the adjacent cells are subject to Less interference.
  • base station 102, access terminal 116, or access terminal 122 may be a transmitting wireless communication device or a receiving wireless communication device.
  • the transmitting wireless communication device can encode the data for transmission.
  • the transmitting wireless communication device can have a certain number of information bits to be transmitted over the channel to the receiving wireless communication device. Such information bits can be included in one or more transport blocks of data.
  • the transmitting wireless communication device can encode each code block using a Polar code encoder to improve the reliability of data transmission, thereby ensuring communication quality.
  • Polar code encoder output (y 1 , y 2 ,...,y N ), where Is a generator matrix, Matrix In the middle K line, B N is a bit reverse order interleaving matrix, Multiply for Cartesian.
  • Polar SC decoders sequentially decode (u 1 , u 2 ,..., u K ), that is, first translate u 1 , then translate u 2 ,..., and finally translate u k .
  • the extended 2L paths are obtained, and then the largest L paths are selected.
  • parallel processing can also be employed, that is, 2 bits, 4 bits or more are processed each time.
  • FIG. 4 is a schematic diagram of path splitting and merging for parallel decoding of 4 bits.
  • FIG. 5 is a schematic flowchart of a path merging method for Polar code decoding according to the present disclosure.
  • the method shown in FIG. 5 can be performed by the path combining means of the Polar code.
  • the path combining means may be located in a receiving device of the Polar code, for example by a processor in the receiving device, or by a dedicated Polar decoder in the receiving device.
  • the code length of the Polar code is N, and N is a positive integer power of 2.
  • the code length of the Polar code refers to the number of bits included in the Polar code.
  • the L survivor path refers to a surviving path reserved after decoding the first M bits of the Polar code.
  • the current decoding bit is expanded to 0 and 1 branches into two extended paths.
  • 2k ⁇ L paths are obtained.
  • the decoding apparatus decodes the M+1th and M+2th bits to obtain 4L extension paths.
  • the decoding apparatus decodes the four bits M+1, M+2, M+3, and M+4 to obtain 16L extension paths.
  • the merging module 330 determines the L paths after decoding, and selects the path with the largest probability value among the L paths as the decoding result of the Polar code.
  • the Polar code bits can be classified into high reliability bits or low reliability bits.
  • the high reliability bit is a bit whose reliability is higher than the threshold, and the low reliability is a bit whose reliability is lower than the threshold.
  • the threshold may be an average of the reliability of the N bits included in the Polar code, or may be a Polar code.
  • the high reliability bits are arranged in descending order of reliability as bits located in bits 1 through P, where P is a positive integer less than N. The L surviving path is used to obtain the decoding result of the Polar code.
  • the step 103 includes:
  • 2 w ⁇ L extension paths are determined from the 2 k ⁇ L extension paths.
  • Decoding the decoded L survival paths from the 2 w ⁇ L extension paths Specifically, the L paths with the highest probability are determined from the 2 w ⁇ L extension paths as the decoded L surviving paths.
  • one decoded surviving path is determined according to each of the surviving paths in the L surviving paths before decoding, as follows:
  • Polar codes based on the reliability of the first through M + 1 M + k bits, determined article 2 w 2 k propagation paths from the path extension bar;
  • a surviving path is determined from the 2 w extension path.
  • the method disclosed in the embodiment of the present invention generates a plurality of extended paths according to the plurality of bits to be decoded, and generates a plurality of extended paths according to the plurality of bits to be decoded, and according to the reliability of the plurality of bits, multiple The extended path is selected in the extended path, and the decoded L-survival path is determined according to the selected extended path, thereby reducing the number of determined path searches, reducing complexity, reducing decoding delay, and improving decoding efficiency.
  • the decoding device in the embodiment of the present invention may be implemented entirely by dedicated hardware, such as a dedicated chip, an integrated circuit, or other firmware; or may be implemented by a general-purpose processor and its instructions, which may be stored in the processor. Or stored in a separate memory. These forms are all within the scope of embodiments of the invention.
  • one surviving path is selected from the four extended paths of each path. Specifically, when both bits are high reliability bits, one path with the highest probability is selected from the four paths as a surviving path.
  • one of the two bits is a high reliability bit and one is a low reliability bit, two paths are selected from the four extended paths, and one path with the highest probability among the two paths is used as a surviving path. Therefore, when the L-survival paths before decoding obtained by decoding the M bits before the Polar code are acquired, L survival paths are output after decoding.
  • Parallel path splitting of (u 4k-3 , u 4k-2 , u 4k-1 , u 4k ) for List decoding is performed to obtain 16L paths. Specifically, using a four-way parallel scheme, each of the L paths expands by 16 paths. According to the reliability of (u 4k-3 , u 4k-2 , u 4k-1 , u 4k ), one of the 16 paths extending from each path survives. When all four bits are low reliability bits, the 16 extended paths extended by each path are reserved, and the largest one of the 16 extended paths is taken as a surviving path.
  • (u 4k-3 , u 4k-2 , u 4k-1 ) is a low reliability information bit
  • u 4k is a high reliability information bit as an example.
  • (u 4k-3 , u 4k-2 ) is a low reliability information bit
  • (u 4k-1 , u 4k ) is a high reliability information bit as an example.
  • u 4k-3 is a low reliability information bit
  • (u 4k-2 , u 4k-1 , u 4k ) is a high reliability information bit as an example.
  • For each value of u 4k-3 one path with the highest probability among the eight combinations of values (u 4k-2 , u 4k-1 , u 4k ) is selected. In this way, two extended paths can be selected from the 16 extended paths, and one of the two extended paths with the highest probability is taken as the surviving path.
  • (u 4k-3 , u 4k-2 , u 4k-1 , u 4k ) are all high reliability information bits as an example for description, and (u 4k-3 , u 4k is selected).
  • -1 , u 4k-1 , u 4k The 16 most probable ones of the 16 combinations of values. In this way, one extended path can be selected from the 16 extended paths as a surviving path.
  • FIG. 13 is a path merging device for a Polar code decoding according to the present invention.
  • the path merging device 300 is configured to perform the above steps 210 to 203.
  • the apparatus 300 includes an acquisition module 310, an expansion module 320, and a merge module 330.
  • the obtaining module 310 is configured to acquire, before the decoding, the L survival paths determined by decoding the first M bits of the Polar code;
  • the expansion module 320 is configured to decode the M+1th to the M+thth bits of the Polar code to obtain 2k ⁇ L extended paths;
  • the merging module 330 is configured to determine, according to the reliability of the M+1th to the M+kth bits of the Polar code, the decoded L survival paths from the 2k ⁇ L extension paths;
  • N is a positive integer power of 2
  • k is a positive integer greater than or equal to 2
  • M is a positive integer multiple of k
  • L is a positive integer.
  • the Polar code bits can be classified into high reliability bits or low reliability bits.
  • the high reliability bit is a bit whose reliability is higher than the threshold, and the low reliability is a bit whose reliability is lower than the threshold.
  • the threshold may be an average of the reliability of the N bits included in the Polar code, or may be a Polar code. The median of the reliability of the included N bits.
  • the high reliability bits are arranged in descending order of reliability as bits located in bits 1 through P, where P is a positive integer less than N.
  • the path merging device 300 may be located in various forms of network devices, such as a macro base station, a micro base station, a relay device, or a user equipment, for implementing path extension and merging.
  • the path merging device 300 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP, Network Processor), etc., or may be a digital signal processor (DSP), dedicated integration.
  • ASIC Application Specific Integrated Circuit
  • FPGA Field-Programmable Gate Array
  • other programmable logic device discrete gate or transistor logic device, discrete hardware component.
  • the obtaining module 310, the expanding module 320, and the merging module 330 may be modules that are independent of each other and may be integrated, and combined as functional components to form a larger-scale circuit.
  • the steps of the method disclosed in the embodiment of the present invention may be directly implemented as a hardware code processor, or may be performed by a combination of hardware and software modules in the code processor.
  • Software module It can be located in a random access memory, a flash memory, a read only memory, a programmable read only memory, or an electrically erasable programmable memory, a register, or the like.
  • the merging module 330 Used for:
  • the decoded L surviving paths are determined from the 2 w ⁇ L extension paths. Specifically, the merging module 330 determines, from the 2 w ⁇ L extension paths, the L paths with the highest probability as the decoded L surviving paths.
  • the merging module 330 is configured to determine one decoded surviving path according to each of the L surviving paths before decoding, specifically:
  • FIG. 14 is a schematic diagram of a Polar code decoding apparatus according to an embodiment of the present invention.
  • the decoding apparatus 400 shown in FIG. 14 includes an acquisition module 410, an expansion module 420, a merging module 430, and a processing module 440.
  • the obtaining module 410 is configured to perform the foregoing step 210
  • the expanding module 420 is configured to perform the foregoing step 220
  • the merging module 430 is configured to perform the foregoing step 230.
  • the obtaining module 410 is configured to acquire L survival paths before decoding determined by decoding the first M bits of the Polar code
  • the expansion module 420 is configured to decode the M+1th to the M+thth bits of the Polar code to obtain 2k ⁇ L extended paths;
  • the merging module 430 is configured to determine, according to the reliability of the M+1th to the M+kth bits of the Polar code, the decoded L survival paths from the 2k ⁇ L extension paths;
  • N is a positive integer power of 2
  • k is a positive integer greater than or equal to 2
  • M is a positive integer multiple of k
  • L is a positive integer.
  • the Polar code bits can be classified into high reliability bits or low reliability bits.
  • the high reliability bit is a bit whose reliability is higher than the threshold, and the low reliability is a bit whose reliability is lower than the threshold.
  • the threshold may be an average of the reliability of the N bits included in the Polar code, or may be a Polar code. The median of the reliability of the included N bits.
  • the high reliability bits are arranged in descending order of reliability as bits located in bits 1 through P, where P is a positive integer less than N.
  • the decoding apparatus 400 may be located in various forms of network equipment such as a macro base station, a micro base station, a relay device, or a user equipment, for implementing path extension and merging.
  • the decoding device 400 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP, Network Processor), etc., and may also be a digital signal processor (DSP), dedicated integration.
  • ASIC Application Specific Integrated Circuit
  • FPGA Field-Programmable Gate Array
  • other programmable logic device discrete gate or transistor logic device, discrete hardware component.
  • the acquisition module 410, the expansion module 420, the merging module 430, and the processing module 440 may be modules that are independent of each other and may be integrated, and combined as functional components to form a larger-scale circuit.
  • the steps of the method disclosed in the embodiment of the present invention may be directly implemented as a hardware code processor, or may be performed by a combination of hardware and software modules in the code processor.
  • the software module can be located in a random access memory, a flash memory, a read only memory, a programmable read only memory, or an electrically erasable programmable memory, a register, or the like.
  • the merging module 430 Used for:
  • the decoded L surviving paths are determined from the 2 w ⁇ L extension paths. Specifically, the merging module 430 determines, from the 2 w ⁇ L extension paths, L paths with the highest probability as the decoded L surviving paths.
  • the merging module 430 is configured to respectively perform each of the L-survival paths before decoding.
  • the surviving path determines a surviving path after decoding, specifically:

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Abstract

本发明实施例公开一种极化Polar码译码的路径合并方法，Polar码的码长为N，方法包括：获取对Polar码前M个比特进行译码所确定的译码前的L条幸存路径；对Polar码第M+1至第M+k个比特进行译码，获取2k×L条扩展路径；根据Polar码第M+1至第M+k个比特的可靠度，从2k×L条扩展路径确定译码后的L条幸存路径；其中，N为2的正整数次幂，k为大于或等于2的正整数，M为k的正整数倍，L为正整数。

Description

极化码的路径合并方法、装置以及译码装置 技术领域
本发明涉及移动通信技术领域，尤其涉及极化码的路径合并方法、装置以及译码装置。
背景技术
在通信系统中，通常采用信道编码提高数据传输的可靠性，以保证通信的质量。极化码(Polar码)是一种近年来日益受到重视的编码技术，它通过构造复合信道，改变原始信道特性，使得复合信道的容量更多地接近高、低两极。由于这种特性，极化码通过合适的编码设计，可以适合随机分布的原始信道，在很多不同的信道实现下，均达到很好的性能，并逼近信道容量。而且，它可以通过干扰消除译码，极大地降低接收机复杂度，非常有利于实现。
Polar码的译码可以用SC(successive-cancellation，连续消除)-List(列表)译码，在SC-List译码时，需要从多条路径中搜索出概率最大的路径。当带译码的数量较多时，如此搜索过程的硬件实现是非常复杂以及耗费资源。如此，将不能充分利用Polar码的编码能力。
发明内容
本发明实施例公开了一种极化码译码的路径合并方法，旨在解决搜索路径数量较多，搜索过程复杂度较高的问题。
第一方面，本发明实施例公开了一种极化Polar码译码的路径合并方法，所述Polar码的码长为N，所述方法包括：
获取对所述Polar码前M个比特进行译码所确定的译码前的L条幸存路径；
对所述Polar码第M+1至第M+k个比特进行译码，获取2k×L条扩展路径；
根据所述Polar码第M+1至第M+k个比特的可靠度，从所述2k×L条扩展路径确定译码后的L条幸存路径；
其中，所述N为2的正整数次幂，k为大于或等于2的正整数，M为k的正整数倍，L为正整数。
在所述第一方面的第一种可能的实施方式中，所述Polar码第M+1至第M+k个比特中包括w个低可靠度的比特和k-w个高可靠度的比特，w为大于或等于0，且小于k的整数，根据所述Polar码第M+1至第M+k个比特的可靠度，从所述2k×L条扩展路径确定所述译码后的L条幸存路径，包括：
根据所述Polar码第M+1至第M+k个比特的可靠度，从所述2k×L条扩展路径确定2w×L条扩展路径；
从所述2w×L条扩展路径中确定所述译码后的L条幸存路径。
在所述第一方面的第二种可能的实施方式中，从所述2w×L条扩展路径中确定所述译码后的L条幸存路径，包括：
从所述2w×L条扩展路径中确定概率最大的L条路径为所述译码后的L条幸存路径。
在所述第一方面的第三种可能的实施方式中，确定所述译码后的L条幸存路径，包括：
分别根据所述译码前的L条幸存路径中的每一条幸存路径，确定1条译码后的幸存路径，方法如下：
对所述Polar码第M+1至第M+k个比特进行译码，获取2k条扩展路径；
根据所述Polar码第M+1至第M+k个比特的可靠度，从所述2k条扩展路径确定2w条扩展路径；
从所述2w条扩展路径中确定1条幸存路径。
结合所述第一方面的第一种至第三种任一种可能的实施方式，在所述第一方面的第四种可能的实施方式中，所述高可靠度比特为可靠度高于阈值的比特，所述低可靠度比特为可靠度低于所述阈值的比特，所述阈值根据如下方法确定：
所述阈值为所述Polar码包括的N个比特的可靠度的平均数；或，
所述阈值为所述Polar码包括的N个比特的可靠度的中位数。
结合所述第一方面的第一种至第三种任一种可能的实施方式，在所述第一方面的第五种可能的实施方式中，所述高可靠度比特为可靠度降序排列为位于第1至P的比特，其中P为小于N的正整数。
第二方面，本发明实施例提出一种极化Polar码译码的路径合并装置，所述Polar码的码长为N，所述装置包括：
获取模块，用于获取对所述Polar码前M个比特进行译码所确定的译码前的L条幸存路径；
扩展模块，用于对所述Polar码第M+1至第M+k个比特进行译码，获取2k×L条扩展路径；
合并模块，用于根据所述Polar码第M+1至第M+k个比特的可靠度，从所述2k×L条扩展路径确定译码后的L条幸存路径；
其中，所述N为2的正整数次幂，k为大于或等于2的正整数，M为k的正整数倍，L为正整数。
在所述第二方面的第一种可能的实施方式中，所述Polar码第M+1至第M+k个比特中包括w个低可靠度的比特和k-w个高可靠度的比特，w为大于或等于0，且小于k的整数，所述合并模块用于：
根据所述Polar码第M+1至第M+k个比特的可靠度，从所述2k×L条扩展路径确定2w×L条扩展路径；
从所述2w×L条扩展路径中确定所述译码后的L条幸存路径。
在所述第二方面的第二种可能的实施方式中，所述合并模块用于：
从所述2w×L条扩展路径中确定概率最大的L条路径为所述译码后的L条幸存路径。
在所述第二方面的第三种可能的实施方式中，所述合并模块用于分别根据所述译码前的L条幸存路径中的每一条幸存路径，确定1条译码后的幸存路径，具体为：
对所述Polar码第M+1至第M+k个比特进行译码，获取2k条扩展路径；
根据所述Polar码第M+1至第M+k个比特的可靠度，从所述2k条扩展路径确定2w条扩展路径；
从所述2w条扩展路径中确定1条幸存路径。
结合所述第二方面的第一种至第三种可能的实施方式，在所述第二方面的第四种可能的实施方式中，所述高可靠度比特为可靠度高于阈值的比特，所述低可靠度比特为可靠度低于所述阈值的比特，所述阈值根据如下方法确定：
所述阈值为所述Polar码包括的N个比特的可靠度的平均数；或，
所述阈值为所述Polar码包括的N个比特的可靠度的中位数。
结合所述第二方面的第一种至第三种可能的实施方式，在所述第二方面的第五种可能的实施方式中，所述高可靠度比特为可靠度降序排列为位于第1至P的比特，其中P为小于N的正整数。
第三方面，本发明实施例公开了一种极化Polar码译码的路径合并装置，所述Polar码的码长为N，所述装置包括：
获取模块，用于获取对所述Polar码前M个比特进行译码所确定的译码前的L条幸存路径；
扩展模块，用于对所述Polar码第M+1至第M+k个比特进行译码，获取2k×L条扩展路径；
合并模块，用于根据所述Polar码第M+1至第M+k个比特的可靠度，从所述2k×L条扩展路径确定译码后的L条幸存路径；
处理模块，用于根据所述译码后的L条幸存路径，得到Polar码的译码结果；
其中，所述N为2的正整数次幂，k为大于或等于2的正整数，M为k的正整数倍，L为正整数。
在所述第三方面的第一种可能的实施方式中，所述Polar码第M+1至第M+k个比特中包括w个低可靠度的比特和k-w个高可靠度的比特，w为大 于或等于0，且小于k的整数，所述合并模块用于：
根据所述Polar码第M+1至第M+k个比特的可靠度，从所述2k×L条扩展路径确定2w×L条扩展路径；
从所述2w×L条扩展路径中确定所述译码后的L条幸存路径。
在所述第三方面的第二种可能的实施方式中，所述合并模块用于：
从所述2w×L条扩展路径中确定概率最大的L条路径为所述译码后的L条幸存路径。
在所述第三方面的第三种可能的实施方式中，所述合并模块用于分别根据所述译码前的L条幸存路径中的每一条幸存路径，确定1条译码后的幸存路径，具体为：
对所述Polar码第M+1至第M+k个比特进行译码，获取2k条扩展路径；
根据所述Polar码第M+1至第M+k个比特的可靠度，从所述2k条扩展路径确定2w条扩展路径；
从所述2w条扩展路径中确定1条幸存路径。
在所述第三方面的第四种可能的实施方式中，当M+k＝N时，所述处理模块选取所述译码后的L条幸存路径中概率值最大的路径作为所述Polar码的译码结果。
结合所述第三方面的第一种至第四种中任一种可能的实施方式，在所述第三方面的第五种可能的实施方式中，所述高可靠度比特为可靠度高于阈值的比特，所述低可靠度比特为可靠度低于所述阈值的比特，所述阈值根据如下方法确定：
所述阈值为所述Polar码包括的N个比特的可靠度的平均数；或，
所述阈值为所述Polar码包括的N个比特的可靠度的中位数。
结合所述第三方面的第一种至第四种中任一种可能的实施方式，在所述第三方面的第六种可能的实施方式中，所述高可靠度比特为可靠度降序排列为位于第1至P的比特，其中P为小于N的正整数。
基于以上技术方案，本发明实施例提供的路径合并方法，减少确定路径搜索的数量，能够降低复杂度，减少译码延迟，提高译码效率。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例的无线通信系统示意图；
图2是SC-LIST译码器的一种的路径合并的示意图；
图3是SC-LIST译码器的另一种并行译码时路径合并的示意图；
图4是SC-LIST译码器的另一种并行译码时路径合并的示意图；
图5是本发明实施例的另一种极化码的路径合并方法的流程示意图；
图6是本发明实施例的一种极化码的并行译码时路径合并的示意图；
图7是本发明实施例的另一种极化码的并行译码时路径合并的详细示意图；
图8是本发明实施例的一种极化码的并行译码时路径合并的示意图；
图9是本发明实施例的另一种极化码的并行译码时路径合并的详细示意图；
图10是本发明实施例的另一种极化码的并行译码时路径合并的详细示意图；
图11是本发明实施例的另一种极化码的并行译码时路径合并的详细示意图；
图12是本发明实施例的另一种极化码的并行译码时路径合并的详细示意图；
图13是本发明实施例的一种路径合并装置的模块示意图；
图14是本发明实施例的一种译码装置的模块示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明的技术方案，可以应用于各种通信系统，例如：全球移动通讯系统(GSM，Global System of Mobile communication)，通用分组无线业务(GPRS，General Packet Radio Service)系统，码分多址(CDMA，Code Division Multiple Access)系统，宽带码分多址(WCDMA，Wideband Code Division Multiple Access Wireless)系统，长期演进(LTE，Long Term Evolution)系统，以及后续演进发展的各类无线通信系统，包括但不限于第五代移动通信系统(5G，5th Generation)等。
用户设备(UE，User Equipment)，也可称之为移动终端(Mobile Terminal)、移动用户设备等，可以经无线接入网(RAN，Radio Access Network)与一个或多个核心网(CN，Core Network)进行通信，用户设备可以是如移动电话或具有移动终端的计算机，例如，便携式、袖珍式、手持式、计算机内置的或者车载的移动装置。
基站，可以是GSM或CDMA中的基站(BTS，Base Transceiver Station)，也可以是WCDMA中的基站(NodeB)，还可以是LTE中的演进型基站(eNB或e-NodeB，evolutional Node B)，以及后续演进系统中实现类似功能的网络设备，本发明并不限定。需要注意的是，根据实际网络部署需要，对网络设备的形态进行相应的改变，如采用分布式基站等方式，亦在本发明的保护范围之内。
本发明实施例公开的极化码(Polar码)的译码方法、装置和终端设备，能够充分利用Polar码的能力，提高Polar码的性能和效率。
图1示出了根据本文所述的各个实施例的无线通信系统100。系统100包括基站102，后者可包括多个天线组。例如，一个天线组可包括天线104和106，另一个天线组可包括天线108和110，附加组可包括天线112和114。对于每个天线组示出了2个天线，然而可对于每个组使用更多或更少的天线。基站102可附加地包括发射机链和接收机链，本领域普通技术人员可以理解， 它们均可包括与信号发送和接收相关的多个部件，例如处理器、调制器、复用器、解调器、解复用器或天线等。
基站102可以与一个或多个接入终端通信，例如，接入终端116和接入终端122。可以理解，基站102可以与类似于接入终端116和122的任意数目的接入终端进行通信。接入终端116和122可以是例如蜂窝电话、智能电话、便携式电脑、手持通信设备、手持计算设备、卫星无线电装置、全球定位系统、PDA或用于在无线通信系统100上通信的任意其它适合设备。如图所示，接入终端116与天线112和114通信，其中天线112和114通过前向链路118向接入终端116发送信息，并通过反向链路120从接入终端116接收信息。此外，接入终端122与天线104和106通信，其中天线104和106通过前向链路124向接入终端122发送信息，并通过反向链路126从接入终端122接收信息。在频分双工(FDD，Frequency Division Duplex)系统中，例如，前向链路118可利用与反向链路120所使用的不同频带，前向链路124可利用与反向链路126所使用的不同频带。此外，在时分双工(TDD，Time Division Duplex)系统中，前向链路118和反向链路120可使用共同频带，前向链路124和反向链路126可使用共同频带。
被设计用于通信的每组天线和/或区域称为基站102的扇区。例如，可将天线组设计为与基站102覆盖区域的扇区中的接入终端通信。在通过前向链路118和124的通信中，基站102的发射天线可利用波束成形来改善针对接入终端116和122的前向链路118和124的信噪比。此外，与基站通过单个天线向它所有的接入终端发送相比，在基站102利用波束成形向相关覆盖区域中随机分散的接入终端116和122发送时，相邻小区中的移动设备会受到较少的干扰。
在给定时间，基站102、接入终端116或接入终端122可以是发送无线通信装置或接收无线通信装置。当发送数据时，发送无线通信装置可对数据进行编码以用于传输。具体地，发送无线通信装置可具有要通过信道发送至接收无线通信装置的一定数目的信息比特。这种信息比特可包含在数据的一个或多个传输块中。此外，发送无线通信装置可使用Polar码编码器来对每个代码块编码，以提高数据传输的可靠性，进而保证通信质量。
以下，对Polar码译码原理进行简单地介绍。
Polar码编码器输出(y1,y2,...,yN),其中
Figure PCTCN2015080448-appb-000001
是生成矩阵，
Figure PCTCN2015080448-appb-000002
为矩阵
Figure PCTCN2015080448-appb-000003
中K行，BN为比特反序交织矩阵，
Figure PCTCN2015080448-appb-000004
Figure PCTCN2015080448-appb-000005
Figure PCTCN2015080448-appb-000006
为笛卡尔乘。
Polar的SC译码器对(u1,u2,...,uK)进行顺序译码，即先译u1，然后译u2，…，最后译uk。
请参照图2，Polar的SC-LIST译码器跟踪并保留L条路径，对每一条路径计算当前译码比特uk的二种可能性uk＝0和uk＝1的路径概率，这样得到了扩展的2L条路径，然后选取其中最大的L条路径。
为了提高译码的速度和吞吐率，也可以采用并行处理，即每次处理2个比特、4个比特或者更多比特。
请参照图3，为对2个比特进行并行译码的路径分裂与合并示意图。具体地，根据每一条路径获取当前译码的二个比特(u2k-1,u2k)的4种可能性:(u2k-1＝0,u2k＝0)，(u2k-1＝0,u2k＝1)，(u2k-1＝1,u2k＝0)和(u2k-1＝1,u2k＝1)的路径概率，这样得到了4L扩展条路径，然后选取其中概率最大的L条路径。
请参照图4，为对4个比特进行并行译码的路径分裂与合并示意图。具体地，根据每一条路径获取当前译码的四个比特(u4k-3,u4k-2,u4k-1,u4k)的16种可能性:(u4k-3＝0,u4k-2＝0,u4k-1＝0,u4k＝0)，(u4k-3＝0,u4k-2＝0,u4k-1＝0,u4k＝1)，…，(u4k-3＝1,u4k-2＝1,u4k-1＝1,u4k＝1)的路径概率，这样得到了扩展的16L条路径，然后选取其中概率最大的L条路径。
图5是本发明公开的一种Polar码译码的路径合并方法的示意性流程图。图5所示的方法可以由Polar码的路径合并装置执行。该路径合并装置可以位于Polar码的接收设备中，例如由接收设备中的处理器实现，或者由接收设备中的专用Polar译码器实现。
201，获取对Polar码前M个比特进行译码所确定的译码前的L条幸存路径，M和L为正整数。
该Polar码的码长为N，N为2的正整数次幂。Polar码的码长是指Polar码所包含的比特数。该L条幸存路径是指对Polar码前M个比特进行译码后所保留的幸存路径。
202，对Polar码第M+1至第M+k个比特进行译码，获取2k×L条扩展 路径，其中k为大于或者等于2的正整数，M为k的正整数倍。
具体地，在以前的译码路径的基础上根据当前译码比特扩展为0和1分支为两条扩展路径。当并行地对第M+1至第M+k个比特进行译码，获取2k×L条路径。例如，当k＝2时，译码装置对第M+1以及第M+2两个比特进行译码，获取4L条扩展路径。当k＝4时，译码装置对第M+1、M+2、M+3以及M+4四个比特进行译码，获取16L条扩展路径。
203，根据Polar码第M+1至第M+k个比特的可靠度，从所述2k×L条扩展路径确定译码后的L条幸存路径。当M+k＝N时，合并模块330确定译码后的L条路径，选取该L条路径中概率值最大的路径作为Polar码的译码结果。
根据Polar码比特的可靠度，可以将Polar码比特区分为高可靠度比特或者低可靠度比特。其中，高可靠度比特为可靠度高于阈值的比特，低可靠度为可靠度低于阈值的比特，该阈值可以为Polar码包括的N个比特的可靠度的平均数，或者可以为Polar码包括的N个比特的可靠度的中位数。可选地，在其他的实施方式中，高可靠度比特为可靠度降序排列为位于第1至P的比特，其中P为小于N的正整数。该L条幸存路径，用于获取Polar码的译码结果。
当第M+1至第M+k个比特中包括w个低可靠度的比特和k-w个高可靠度的比特时，其中w为大于或等于0且小于k的整数，步骤103包括：
根据Polar码第M+1至第M+k个比特的可靠度，从所述2k×L条扩展路径确定2w×L条扩展路径。
从所述2w×L条扩展路径中确定所述译码后的L条幸存路径。具体地，从所述2w×L条扩展路径中确定概率最大的L条路径为所述译码后的L条幸存路径。
具体地，分别根据译码前的L条幸存路径中的每一条幸存路径，确定1条译码后的幸存路径，方法如下：
对所述Polar码第M+1至第M+k个比特进行译码，获取2k条扩展路径；
根据所述Polar码第M+1至第M+k个比特的可靠度，从所述2k条扩展路径确定2w条扩展路径；
从所述2w条扩展路径中确定1条幸存路径。
本实施例中，仅为了描述方便，采用了如前所述的数学表达方式，不应构成对本发明保护范围的限制。
本发明实施例所公开的方法将译码前所确定的L条幸存路径，根据待译码的多个比特进行并行译码产生多个扩展路径，并根据多个比特的可靠度，从多个扩展路径中选取相应地扩展路径，并根据选取的扩展路径确定译码后的L条幸存路径，从而减少确定路径搜索的数量，能够降低复杂度，减少译码延迟，提高译码效率。
应注意，本发明实施例中的译码装置可以是完全由专用硬件实现，例如专用的芯片、集成电路或其他固件；也可以由通用处理器及其指令实现，该指令可以存储于处理器中或者存储于独立的存储器中。这些形式均落入本发明实施例的范围内。
下面结合不同的实施例，更加详细的描述本发明实施例的路径合并方法。
请参照图6，为当k＝2时，对待译码的两个比特(u2k-1,u2k)的扩展路径进行路径合并的流程示意图。
对(u2k-1,u2k)进行List译码的并行路径分裂，获得4L条路径。根据待译码的两个比特的可靠度情况，从每一条路径的4条扩展路径中选取1条幸存路径。具体地，当两个比特均为高可靠度比特时，从4条路径中选取概率最大的1条路径作为幸存路径。当两个比特中一个为高可靠度比特，一个为低可靠度比特时，从4条扩展路径中选取2条路径，将2条路径中概率最大的1条路径作为幸存路径。从而，当获取到对Polar码前M个比特进行译码所确定的译码前的L条幸存路径时，译码后将输出L条幸存路径。
示例性地，请参照图7，以u2k-1为低可靠度比特，u2k为高可靠度比特为例，对从4条扩展路径中选取2条路径具体为：选定u2k-1＝0时输出的2条扩展路径中概率值最大的1条路径，以及选定u2k＝1时输出的2条扩展路径中概率值最大的1条路径。
请参照图8，当k＝4时，对待译码的四个比特(u4k-3,u4k-2,u4k-1,u4k)的扩展路径进行路径合并的流程示意图。
对(u4k-3,u4k-2,u4k-1,u4k)进行List译码的并行路径分裂，获得16L条路径。具体地，采用四路并行方案，L条路径中每一条路径扩展出16条路径。根据(u4k-3,u4k-2,u4k-1,u4k)的可靠度情况，从每一条路径扩展的16条路径中1条幸存路径。当四个比特均为低可靠度比特时，保留每条路径扩展出的16条扩展路径，将16条扩展路径中最大的1条作为幸存路径。当四个比特中包括3个低可靠度比特和1个高可靠度比特时，从16条扩展路径中选取8条路径，将8条路径中概率最大的1条路径作为幸存路径。当四个比特中包括2个低可靠度比特和2个高可靠度比特时，从16条扩展路径中选取4条路径，将4条路径中概率最大的1条路径作为幸存路径。当四个比特中包括1个低可靠度比特和3个高可靠度比特时，从16条扩展路径中选取2条路径，将2条路径中概率最大的1条路径作为幸存路径。当四个比特均为高可靠度比特时，从16条路径中选取1条路径作为幸存路径。从而，当获取到对Polar码前M个比特进行译码所确定的译码前的L条幸存路径时，译码后将输出L条幸存路径。
示例性地，请参照图9，以(u4k-3,u4k-2,u4k-1)为低可靠度信息比特，u4k为高可靠度信息比特为例进行说明。对(u4k-3,u4k-2,u4k-1)的每一种取值组合，选取u4k＝0或者u4k＝1时概率值最大的1条扩展路径。如此，可以从16条扩展路径中选取8条扩展路径，将8条扩展路径中概率最大的1条路径作为幸存路径。
示例性地，请参照图10，以(u4k-3,u4k-2)为低可靠度信息比特，(u4k-1,u4k)为高可靠度信息比特为例进行说明。对(u4k-3,u4k-2)的每一种取值组合，选取(u4k-1,u4k)的四种取值组合中概率最大的1条路径。如此，可以从16条扩展路径中选取4条扩展路径，将4条扩展路径中概率最大的1条路径作为幸存路径。
示例性地，请参照图11，以u4k-3为低可靠度信息比特，(u4k-2,u4k-1,u4k)为高可靠度的信息比特为例进行说明。对u4k-3的每一种取值，选取(u4k-2,u4k-1,u4k)的八种取值组合中概率最大的1条路径。如此，可以从16条扩展路径中选取2条扩展路径，将2条扩展路径中概率最大的1条路径作为幸存路径。
示例性地，请参照图12，以(u4k-3,u4k-2,u4k-1,u4k)均为高可靠度信息比特为例进行说明，选取(u4k-3,u4k-2,u4k-1,u4k)的16种取值组合中概率最大的1条扩展路 径。如此，可以从16条扩展路径中选取1条扩展路径作为幸存路径。
图13是本发明公开的一种Polar码译码的路径合并装置，路径合并装置300用于执行上述步骤210至203。如图13所示，装置300包括获取模块310、扩展模块320和合并模块330。
获取模块310，用于获取对Polar码前M个比特进行译码所确定的译码前的L条幸存路径；
扩展模块320，用于对Polar码第M+1至第M+k个比特进行译码，获取2k×L条扩展路径；
合并模块330，用于根据Polar码第M+1至第M+k个比特的可靠度，从2k×L条扩展路径确定译码后的L条幸存路径；
其中，N为2的正整数次幂，k为大于或等于2的正整数，M为k的正整数倍，L为正整数。
根据Polar码比特的可靠度，可以将Polar码比特区分为高可靠度比特或者低可靠度比特。其中，高可靠度比特为可靠度高于阈值的比特，低可靠度为可靠度低于阈值的比特，该阈值可以为Polar码包括的N个比特的可靠度的平均数，或者可以为Polar码包括的N个比特的可靠度的中位数。可选地，在其他的实施方式中，高可靠度比特为可靠度降序排列为位于第1至P的比特，其中P为小于N的正整数。
应理解，在具体的应用中，路径合并装置300可以位于宏基站、微基站、中继设备或用户设备等各种形态的网络设备中，用于实现路径扩展与合并。路径合并装置300可以是通用处理器，包括中央处理器(CPU，Central Processing Unit)、网络处理器(NP，Network Processor)等；还可以是数字信号处理器(DSP，Digital Signal Processor)、专用集成电路(ASIC，Application Specific Integrated Circuit)、现场可编程门阵列(FPGA，Field－Programmable Gate Array)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。获取模块310、扩展模块320和合并模块330可以是相互独立而分别存在的模块，也可以集成在一起，作为功能组件合并构成更大规模的电路。结合本发明实施例所公开的方法的步骤可以直接体现为硬件编码处理器执行完成，或者用编码处理器中的硬件及软件模块组合执行完成。软件模块 可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等存储介质中。
当Polar码第M+1至第M+k个比特中包括w个低可靠度的比特和k-w个高可靠度的比特时，其中w为大于或等于0，且小于k的整数，合并模块330用于：
根据Polar码第M+1至第M+k个比特的可靠度，从2k×L条扩展路径确定2w×L条扩展路径；
从2w×L条扩展路径中确定译码后的L条幸存路径。具体地，合并模块330从所述2w×L条扩展路径中确定概率最大的L条路径为所述译码后的L条幸存路径。
具体地，合并模块330用于分别根据译码前的L条幸存路径中的每一条幸存路径，确定1条译码后的幸存路径，具体为：
对Polar码第M+1至第M+k个比特进行译码，获取2k条扩展路径；
根据Polar码第M+1至第M+k个比特的可靠度，从2k条扩展路径确定2w条扩展路径；
从2w条扩展路径中确定1条幸存路径。
图14是本发明实施例公开的一种Polar码译码装置的示意图。图14所示的译码装置400包括获取模块410、扩展模块420、合并模块430和处理模块440。其中，获取模块410用于执行上述步骤210，扩展模块420用于执行上述步骤220，合并模块430用于执行上述步骤230。
获取模块410，用于获取对Polar码前M个比特进行译码所确定的译码前的L条幸存路径；
扩展模块420，用于对Polar码第M+1至第M+k个比特进行译码，获取2k×L条扩展路径；
合并模块430，用于根据Polar码第M+1至第M+k个比特的可靠度，从2k×L条扩展路径确定译码后的L条幸存路径；
处理模块440，用于根据译码后的L条幸存路径，得到Polar码的译码结果。具体地，当M+k＝N时，合并模块330确定译码后的L条路径，处理模块340选取该L条幸存路径中概率值最大的路径作为Polar码的译码结果。
其中，N为2的正整数次幂，k为大于或等于2的正整数，M为k的正整数倍，L为正整数。
根据Polar码比特的可靠度，可以将Polar码比特区分为高可靠度比特或者低可靠度比特。其中，高可靠度比特为可靠度高于阈值的比特，低可靠度为可靠度低于阈值的比特，该阈值可以为Polar码包括的N个比特的可靠度的平均数，或者可以为Polar码包括的N个比特的可靠度的中位数。可选地，在其他的实施方式中，高可靠度比特为可靠度降序排列为位于第1至P的比特，其中P为小于N的正整数。
应理解，在具体的应用中，译码装置400可以位于宏基站、微基站、中继设备或用户设备等各种形态的网络设备中，用于实现路径扩展与合并。译码装置400可以是通用处理器，包括中央处理器(CPU，Central Processing Unit)、网络处理器(NP，Network Processor)等；还可以是数字信号处理器(DSP，Digital Signal Processor)、专用集成电路(ASIC，Application Specific Integrated Circuit)、现场可编程门阵列(FPGA，Field－Programmable Gate Array)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。获取模块410、扩展模块420、合并模块430和处理模块440可以是相互独立而分别存在的模块，也可以集成在一起，作为功能组件合并构成更大规模的电路。结合本发明实施例所公开的方法的步骤可以直接体现为硬件编码处理器执行完成，或者用编码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等存储介质中。
当Polar码第M+1至第M+k个比特中包括w个低可靠度的比特和k-w个高可靠度的比特时，其中w为大于或等于0，且小于k的整数，合并模块430用于：
根据Polar码第M+1至第M+k个比特的可靠度，从2k×L条扩展路径确定2w×L条扩展路径；
从2w×L条扩展路径中确定译码后的L条幸存路径。具体地，合并模块430从所述2w×L条扩展路径中确定概率最大的L条路径为所述译码后的L条幸存路径。
具体地，合并模块430用于分别根据译码前的L条幸存路径中的每一条 幸存路径，确定1条译码后的幸存路径，具体为：
对Polar码第M+1至第M+k个比特进行译码，获取2k条扩展路径；
根据Polar码第M+1至第M+k个比特的可靠度，从2k条扩展路径确定2w条扩展路径；
从2w条扩展路径中确定1条幸存路径。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到本发明可借助软件加必需的通用硬件的方式来实现。基于这样的理解，本发明的技术方案中的全部或部分步骤是可以通过程序来指令相关的硬件来完成，所述的程序可以存储于一计算机可读取存储介质中，该程序在执行时，包括如上述方法实施例的步骤。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可以轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以权利要求的保护范围为准。

Claims (19)

  1. 一种极化Polar码译码的路径合并方法，所述Polar码的码长为N，其特征在于，所述方法包括：
    获取对所述Polar码前M个比特进行译码所确定的译码前的L条幸存路径；
    对所述Polar码第M+1至第M+k个比特进行译码，获取2k×L条扩展路径；
    根据所述Polar码第M+1至第M+k个比特的可靠度，从所述2k×L条扩展路径确定译码后的L条幸存路径；
    其中，所述N为2的正整数次幂，k为大于或等于2的正整数，M为k的正整数倍，L为正整数。
  2. 根据权利要求1所述的方法，其特征在于，所述Polar码第M+1至第M+k个比特中包括w个低可靠度的比特和k-w个高可靠度的比特，w为大于或等于0，且小于k的整数，根据所述Polar码第M+1至第M+k个比特的可靠度，从所述2k×L条扩展路径确定所述译码后的L条幸存路径，包括：
    根据所述Polar码第M+1至第M+k个比特的可靠度，从所述2k×L条扩展路径确定2w×L条扩展路径；
    从所述2w×L条扩展路径中确定所述译码后的L条幸存路径。
  3. 根据权利要求2所述的方法，其特征在于，从所述2w×L条扩展路径中确定所述译码后的L条幸存路径，包括：
    从所述2w×L条扩展路径中确定概率最大的L条路径为所述译码后的L条幸存路径。
  4. 根据权利要求2所述的方法，其特征在于，确定所述译码后的L条幸存路径，包括：
    分别根据所述译码前的L条幸存路径中的每一条幸存路径，确定1条译码后的幸存路径，方法如下：
    对所述Polar码第M+1至第M+k个比特进行译码，获取2k条扩展路径；
    根据所述Polar码第M+1至第M+k个比特的可靠度，从所述2k条扩展路径确定2w条扩展路径；
    从所述2w条扩展路径中确定1条幸存路径。
  5. 根据权利要求2-4所述的任一种方法，其特征在于，所述高可靠度 比特为可靠度高于阈值的比特，所述低可靠度比特为可靠度低于所述阈值的比特，所述阈值根据如下方法确定：
    所述阈值为所述Polar码包括的N个比特的可靠度的平均数；或，
    所述阈值为所述Polar码包括的N个比特的可靠度的中位数。
  6. 根据权利要求2-4所述的任一种方法，其特征在于，所述高可靠度比特为可靠度降序排列为位于第1至P的比特，其中P为小于N的正整数。
  7. 一种极化Polar码译码的路径合并装置，所述Polar码的码长为N，其特征在于，所述装置包括：
    获取模块，用于获取对所述Polar码前M个比特进行译码所确定的译码前的L条幸存路径；
    扩展模块，用于对所述Polar码第M+1至第M+k个比特进行译码，获取2k×L条扩展路径；
    合并模块，用于根据所述Polar码第M+1至第M+k个比特的可靠度，从所述2k×L条扩展路径确定译码后的L条幸存路径；
    其中，所述N为2的正整数次幂，k为大于或等于2的正整数，M为k的正整数倍，L为正整数。
  8. 根据权利要求7所述的装置，其特征在于，所述Polar码第M+1至第M+k个比特中包括w个低可靠度的比特和k-w个高可靠度的比特，w为大于或等于0，且小于k的整数，所述合并模块用于：
    根据所述Polar码第M+1至第M+k个比特的可靠度，从所述2k×L条扩展路径确定2w×L条扩展路径；
    从所述2w×L条扩展路径中确定所述译码后的L条幸存路径。
  9. 根据权利要求8所述的装置，其特征在于，所述合并模块用于：
    从所述2w×L条扩展路径中确定概率最大的L条路径为所述译码后的L条幸存路径。
  10. 根据权利要求8所述的装置，其特征在于，所述合并模块用于分别根据所述译码前的L条幸存路径中的每一条幸存路径，确定1条译码后的幸存路径，具体为：
    对所述Polar码第M+1至第M+k个比特进行译码，获取2k条扩展路径；
    根据所述Polar码第M+1至第M+k个比特的可靠度，从所述2k条扩展路径确定2w条扩展路径；
    从所述2w条扩展路径中确定1条幸存路径。
  11. 根据权利要求8-10所述的任一种装置，其特征在于，所述高可靠度比特为可靠度高于阈值的比特，所述低可靠度比特为可靠度低于所述阈值的比特，所述阈值根据如下方法确定：
    所述阈值为所述Polar码包括的N个比特的可靠度的平均数；或，
    所述阈值为所述Polar码包括的N个比特的可靠度的中位数。
  12. 根据权利要求8-10所述的任一种装置，其特征在于，所述高可靠度比特为可靠度降序排列为位于第1至P的比特，其中P为小于N的正整数。
  13. 一种极化Polar码译码的路径合并装置，所述Polar码的码长为N，其特征在于，所述装置包括：
    获取模块，用于获取对所述Polar码前M个比特进行译码所确定的译码前的L条幸存路径；
    扩展模块，用于对所述Polar码第M+1至第M+k个比特进行译码，获取2k×L条扩展路径；
    合并模块，用于根据所述Polar码第M+1至第M+k个比特的可靠度，从所述2k×L条扩展路径确定译码后的L条幸存路径；
    处理模块，用于根据所述译码后的L条幸存路径，得到Polar码的译码结果；
    其中，所述N为2的正整数次幂，k为大于或等于2的正整数，M为k的正整数倍，L为正整数。
  14. 根据权利要求13所述的装置，其特征在于，所述Polar码第M+1至第M+k个比特中包括w个低可靠度的比特和k-w个高可靠度的比特，w为大于或等于0，且小于k的整数，所述合并模块用于：
    根据所述Polar码第M+1至第M+k个比特的可靠度，从所述2k×L条 扩展路径确定2w×L条扩展路径；
    从所述2w×L条扩展路径中确定所述译码后的L条幸存路径。
  15. 根据权利要求14所述的装置，其特征在于，所述合并模块用于：
    从所述2w×L条扩展路径中确定概率最大的L条路径为所述译码后的L条幸存路径。
  16. 根据权利要求14所述的装置，其特征在于，所述合并模块用于分别根据所述译码前的L条幸存路径中的每一条幸存路径，确定1条译码后的幸存路径，具体为：
    对所述Polar码第M+1至第M+k个比特进行译码，获取2k条扩展路径；
    根据所述Polar码第M+1至第M+k个比特的可靠度，从所述2k条扩展路径确定2w条扩展路径；
    从所述2w条扩展路径中确定1条幸存路径。
  17. 根据权利要求13所述的装置，其特征在于，当M+k＝N时，所述处理模块选取所述译码后的L条幸存路径中概率值最大的路径作为所述Polar码的译码结果。
  18. 根据权利要求14-17所述的任一种装置，其特征在于，所述高可靠度比特为可靠度高于阈值的比特，所述低可靠度比特为可靠度低于所述阈值的比特，所述阈值根据如下方法确定：
    所述阈值为所述Polar码包括的N个比特的可靠度的平均数；或，
    所述阈值为所述Polar码包括的N个比特的可靠度的中位数。
  19. 根据权利要求14-17所述的任一种装置，其特征在于，所述高可靠度比特为可靠度降序排列为位于第1至P的比特，其中P为小于N的正整数。
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