WO2018157717A1 - 一种极化码译码方法及装置 - Google Patents

一种极化码译码方法及装置 Download PDF

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Publication number
WO2018157717A1
WO2018157717A1 PCT/CN2018/075771 CN2018075771W WO2018157717A1 WO 2018157717 A1 WO2018157717 A1 WO 2018157717A1 CN 2018075771 W CN2018075771 W CN 2018075771W WO 2018157717 A1 WO2018157717 A1 WO 2018157717A1
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Prior art keywords
sequence
path
check
check sequence
decoding
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PCT/CN2018/075771
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English (en)
French (fr)
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王加庆
孙韶辉
潘学明
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电信科学技术研究院有限公司
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Publication of WO2018157717A1 publication Critical patent/WO2018157717A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0047—Decoding adapted to other signal detection operation

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a polarization code decoding method and apparatus.
  • the 4G the 4 th Generation mobile communication technology, the fourth generation mobile communication technology
  • the future fifth-generation mobile communications technology 5G 5 th Generation, fifth generation
  • 5G eMBB Enhanced Mobile Broad Band
  • Polar Codes are a new type of coding that can achieve binary symmetric channel capacity and have excellent decoding performance.
  • the polarization code encoding and decoding method in the prior art includes a CRC (Cyclic Redundancy Check)-assisted polarization code encoding code and a PC (Parity Check)-assisted polarization code encoding code.
  • 1 is a schematic diagram of a CRC-assisted polarization code encoding and decoding code in the prior art.
  • the CRC-assisted polarization code encoding and decoding process includes: first encoding an information sequence to be encoded by a CRC encoder to generate a corresponding CRC sequence, and then The information sequence and the CRC sequence are sent to the Polar encoder, encoded, modulated by the modulator, and then transmitted to the receiving end through the channel.
  • the bit stream demodulated by the demodulator is translated by the Polar-CRC joint decoder during decoding.
  • the code is mainly a CRC-assisted Successive Cancellation List (SCL) decoding algorithm.
  • SCL Successive Cancellation List
  • the PC-assisted polarization code encoding and decoding process includes: first encoding an information sequence to be encoded by a CRC encoder to generate a corresponding CRC sequence, and then The information sequence and the CRC sequence are sent to the PC-Polar encoder, encoded and modulated by the modulator, and then transmitted to the receiving end through the channel; when decoding, the bit stream demodulated by the modulator is decoded by the Polar decoder.
  • the PC decoder-assisted SCL decoding algorithm is mainly used.
  • the Polar decoder When the decoding result of the final decoding is selected in the decoding, the Polar decoder first restores the candidate codeword to a candidate information sequence containing the PC, and all candidate information sequences are used. The PC decoding process is performed, and the candidate information sequence decoded by the PC and having the highest reliability is used as the final decoding result.
  • BLER Block Error Rate
  • metric another important performance indicator of the control channel performance evaluation standard
  • the low false alarm rate is beneficial to reduce the uplink collision probability of the UE (User Equipment), reduce the power consumption of the UE, and improve the system performance.
  • the embodiment of the present application provides a method and a device for decoding a polarization code to provide a new polarization decoding solution.
  • the embodiment of the present application discloses a polarization code decoding method, where the method includes:
  • the target decoding path is determined according to the information sequence in each path in the SCL decoding, and the first check sequence and the second check sequence in each path.
  • the determining, according to the information sequence in each path in the SCL decoding, and the first check sequence and the second check sequence in each path, determining the target decoding path includes:
  • the target decoding path is determined according to the first check sequence and the second check sequence in each candidate path.
  • the determining, according to the information sequence in each path in the SCL decoding, and the first check sequence and the second check sequence in each path, determining the target decoding path includes:
  • the target decoding path is determined according to the information sequence in each candidate path and the determined first check sequence.
  • the first check sequence is any one of a cyclic redundancy check CRC sequence, a hash hash sequence, and a random sequence
  • the second check sequence is a CRC sequence, a hash sequence, and a parity check. Any of a PC sequence and a random sequence.
  • the second check sequence is a CRC sequence, a hash sequence, and a random sequence.
  • determining, according to the information sequence in each path in the SCL decoding, and the first check sequence and the second check sequence in each path, the target decoding path includes:
  • the second predetermined number of paths to be decoded are preset as the target decoding path.
  • the second check sequence is a CRC sequence, a hash sequence, and a random sequence.
  • determining, according to the information sequence in each path in the SCL decoding, and the first check sequence and the second check sequence in each path, the target decoding path includes:
  • the second predetermined number of paths to be decoded are preset as the target decoding path.
  • the first check sequence is any one of a cyclic redundancy check CRC sequence, a hash hash sequence, and a random sequence
  • the second check sequence is a parity check PC sequence
  • the second number of candidate paths serve as target decoding paths.
  • the method before the determining the target decoding path according to the first check sequence and the second check sequence in each candidate path, the method further includes:
  • the second check sequence is updated by an algorithm corresponding to the sender, wherein the algorithm corresponding to the sender includes at least one of an exclusive OR processing algorithm, an interleaving algorithm, and an algorithm for updating a set bit.
  • the updating by using an algorithm corresponding to the sending end, updating the first check sequence, and/or updating the second check sequence by using an algorithm corresponding to the sending end includes:
  • the first check sequence and/or the second check sequence are updated using a scrambling sequence corresponding to the sender.
  • the method further includes:
  • Decoding results are determined based on the first check sequence and/or the second check sequence.
  • the embodiment of the present application discloses a polarization code decoding device, where the device includes:
  • a polarization code Polar decoder configured to perform continuous deletion list SCL decoding on the sequence encoded by the received polarization code
  • a check sequence decoder configured to determine a target decoding path according to the information sequence in each path in the SCL decoding, and the first check sequence and the second check sequence in each path.
  • the check sequence decoder is configured to determine a candidate sequence in the candidate candidate sequence for the candidate sequence in the candidate sequence, and determine a first check sequence of the candidate path. And a second check sequence; determining a target decoding path according to the first check sequence and the second check sequence in each candidate path.
  • the check sequence decoder is specifically configured to determine a candidate path according to the information sequence of each path in the SCL decoding and the determined second check sequence; according to the information in each candidate path The sequence and the determined first check sequence determine a target decoding path.
  • the check sequence decoder is specifically configured to determine a first matching degree of the first sequence in each candidate path and the corresponding first check sequence, according to the first matching degree from high to low. Sorting each candidate path sequentially, selecting a preset first number of candidate paths as the to-be-decoded path; determining a second sequence in each of the to-be-decoded paths and a second of the corresponding second check sequence Matching degree, each of the to-be-decoded paths is sorted in descending order of the second matching degree, and the preset second predetermined number of to-be-decoded paths are selected as the target decoding path, wherein the first The sequence is any one of a cyclic redundancy check CRC sequence, a hash hash sequence, and a random sequence, and the second sequence is any one of a CRC sequence, a hash sequence, and a random sequence.
  • the check sequence decoder is specifically configured to determine a second matching degree of the second sequence in each candidate path and the corresponding second check sequence, according to the second matching degree from high to low. Sorting each candidate path sequentially, selecting a preset first number of candidate paths as the to-be-decoded path; determining the first sequence in each of the to-be-decoded paths and the first of the corresponding first check sequence Matching degree, each of the to-be-decoded paths is sorted according to the first matching degree from high to low, and the preset second predetermined number of to-be-decoded paths are selected as the target decoding path, wherein the first The sequence is any one of a cyclic redundancy check CRC sequence, a hash hash sequence, and a random sequence, and the second sequence is any one of a CRC sequence, a hash sequence, and a random sequence.
  • the check sequence decoder is specifically configured to determine a first matching degree of the first sequence in each candidate path and the corresponding first check sequence, according to the first matching degree from high to low. Sorting each candidate path sequentially, and selecting a preset second predetermined number of candidate paths as a target decoding path, wherein the first check sequence is a cyclic redundancy check CRC sequence, a hash hash sequence, and Any one of random sequences, the second check sequence being any one of a CRC sequence, a hash sequence, and a random sequence.
  • the device further includes:
  • an update module configured to update the first check sequence by using an algorithm corresponding to the sending end; and/or update the second check sequence by using an algorithm corresponding to the sending end, where the sending end
  • the corresponding algorithm includes at least one of an exclusive OR processing algorithm, an interleaving algorithm, and an algorithm for updating a set bit.
  • the updating module is specifically configured to update the first check sequence and/or the second check sequence by using a scrambling sequence corresponding to the sending end.
  • the check sequence decoder is further configured to determine a decoding result according to the first check sequence and/or the second check sequence.
  • a memory for storing program instructions
  • a processor configured to invoke a program instruction stored in the memory, and execute according to the obtained program:
  • the target decoding path is determined according to the information sequence in each path in the SCL decoding, and the first check sequence and the second check sequence in each path.
  • Another embodiment of the present application provides a computer storage medium storing computer executable instructions for causing the computer to perform any of the methods described above.
  • the embodiment of the present application discloses a method and a device for decoding a polarization code.
  • the method includes: performing a continuous deletion list SCL decoding on a sequence encoded by a received polarization code; and performing each path according to SCL decoding.
  • the information sequence, and the first check sequence and the second check sequence in each path determine the target decoding path.
  • the path selection is performed according to the first check sequence and the second check sequence, thereby reducing the false alarm rate and improving the performance of the system.
  • FIG. 1 is a schematic diagram of a CRC-assisted polarization code encoding code in the prior art
  • FIG. 2 is a schematic diagram of a PC-assisted polarization code encoding code in the prior art
  • FIG. 3 is a schematic diagram of a polarization code decoding process according to an embodiment of the present application.
  • FIG. 4A is a schematic diagram of a polarization code encoding process according to an embodiment of the present application.
  • FIG. 4B is a schematic diagram of a polarization code encoding process according to an embodiment of the present application.
  • FIG. 5A is a schematic diagram of a polarization code encoding process according to an embodiment of the present application.
  • FIG. 5B is a schematic diagram of a polarization code encoding process according to an embodiment of the present application.
  • FIG. 6 is a structural diagram of a polarization code encoding apparatus according to an embodiment of the present application.
  • FIG. 7 is a structural diagram of another apparatus for encoding a polarization code according to an embodiment of the present application.
  • a method for decoding a polarization code includes: performing continuous deletion list SCL decoding on a sequence encoded by a received polarization code; and performing an information sequence in each path according to SCL decoding, and A first check sequence and a second check sequence in each path determine a target decoding path.
  • the method for decoding a polarization code provided by the embodiment of the present application is applied to a receiving end, and the receiving end may be a base station or a UE.
  • the selection is performed according to two sequences, thereby reducing the false alarm rate and improving the performance of the system.
  • the target decoding is determined according to the information sequence in each path in the SCL decoding, and the first check sequence and the second check sequence in each path.
  • the path includes:
  • the target decoding path is determined according to the first check sequence and the second check sequence in each candidate path.
  • the first check sequence is any one of a cyclic redundancy check CRC sequence, a hash hash sequence, and a random sequence
  • the second check sequence is any one of a CRC sequence, a hash sequence, and a random sequence.
  • FIG. 3 is a schematic diagram of a process of decoding a polarization code according to an embodiment of the present application, where the process includes the following steps:
  • S301 Perform continuous deletion list SCL decoding on the sequence encoded by the received polarization code.
  • the coded coded sequence is subjected to rate matching processing and modulation, and then transmitted.
  • the receiving end needs demodulation and de-rate matching processing after receiving the codeword, and then determines the received codeword.
  • the rate matching sequence used may preferably be obtained by using a Gaussian method or other rate matching sequences that are insensitive to a Signal Noise Ratio (SNR).
  • SNR Signal Noise Ratio
  • a plurality of candidate paths are reserved according to a preset number, and each candidate path includes a corresponding candidate sequence.
  • S302 Determine a sequence of information in the candidate sequence for the candidate sequence in the plurality of candidate paths reserved for SCL decoding, and determine a first check sequence and a second check sequence of the candidate path.
  • the result of the determined decoding is more accurate, and in the process of determining the information sequence, the first sequence and the second sequence in the candidate sequence, Determining according to an encoding manner corresponding to the transmitting end, that is, determining a sequence of information, a first sequence, and a second sequence in the candidate sequence, and determining the information sequence, the first sequence, and the second when encoding with the transmitting terminal polarization code
  • the sequence is the same process.
  • the transmitting end maps the information sequence, the first sequence and the second sequence to the subchannels with different bit channel capacities, and implements the information sequence, the first sequence and the second sequence and the bit channel mapping, and the rest
  • the position corresponding to the subchannel is used as the freezing position 0, and then the polarization code is encoded.
  • the specific information is transmitted after the specific mapping is known.
  • the receiving end determines the information sequence, the first sequence, and the second sequence in the candidate sequence, the information sequence, the first sequence, and the second sequence are determined in the candidate sequence according to a mapping method corresponding to the transmitting end.
  • the receiving end also knows in advance that there is a mapping method of the transmitting end, that is, what information is mapped on which subchannel is known by the receiving end, so the receiving end can determine the information sequence, the first sequence, and the candidate path after decoding.
  • the second sequence is a mapping method of the transmitting end, that is, what information is mapped on which subchannel is known by the receiving end, so the receiving end can determine the information sequence, the first sequence, and the candidate path after decoding.
  • the second sequence is a mapping method of the transmitting end, that is, what information is mapped on which subchannel is known by the receiving end
  • the process of determining a plurality of candidate paths reserved by the SCL decoding in the receiving end includes: when starting decoding, the number of paths is 1, and each time a bit is decoded, the number of paths is doubled, when the number of paths is greater than a set number, Determining the probability of the path according to the probability of the bit decoded in each path, selecting a set number of paths with a higher probability as the candidate path, performing decoding of the next bit, and after decoding, determining for the next bit Whether the number of paths corresponding to the decoding result of one bit is greater than the set number, and if so, repeating the above process until the last bit is successfully decoded, and the final candidate path is selected.
  • the SCL decoding stores a preset number, which may be, for example, 4.
  • the first sequence generation algorithm corresponding to the sender is determined, that is, the process of determining the first check sequence is generated by the sender.
  • the process of the first sequence is the same.
  • it is determined according to a second sequence generation algorithm corresponding to the sender that is, the process of determining the second check sequence is the same as the process of generating the second sequence by the sender.
  • the receiving end stores a first sequence generating algorithm and a second sequence generating algorithm corresponding to the sending end. For each candidate path, the receiving end determines the first check sequence according to the attribute information of the information sequence in the candidate path and the first sequence generation algorithm corresponding to the sending end, and according to the attribute information of the information sequence in the candidate path and The second sequence generation algorithm corresponding to the sender determines the second check sequence.
  • the attribute information of the information sequence may be the length of the information sequence, the content of the information sequence, or the length and content of the information sequence.
  • the content of the information sequence may be the entire content of the information sequence or part of the information sequence.
  • the first check sequence and the second check sequence corresponding to the first sequence and the second sequence may be reconstructed in the foregoing manner.
  • the first sequence or the second sequence may be directly used as the first check sequence or the second check sequence.
  • the first sequence is a CRC sequence
  • the first sequence can be used as the first check CRC sequence.
  • S303 Determine a target decoding path according to the first check sequence and the second check sequence in each candidate path.
  • the target decoding path may be determined according to the first check sequence and the second check sequence in each candidate path.
  • the first matching degree according to the first sequence and the first check sequence, and the second sequence may be The second matching degree of the second check sequence determines the total matching degree, and each candidate path is sorted according to the total matching degree from high to low, and the preset number of candidate paths ranked first is selected as the target translation.
  • the code path thereby selecting a path by the first check sequence and the second check sequence.
  • the information sequence and the first sequence or the second sequence may be input to the CRC decoder according to the decoder.
  • Output determining a first matching degree of each candidate path, for example, determining the first matching degree according to a ratio of the number of zero bits to the total number of bits, and then determining the second sequence or the first sequence, Correlating with the second matching degree of the corresponding second check sequence or the first check sequence, determining the total matching degree, sorting each candidate path according to the order of total matching degree from high to low, and selecting the top ranking
  • a predetermined number of candidate paths are used as target decoding paths, thereby selecting paths by the first check sequence and the second check sequence.
  • the information sequence and the first sequence are input to a CRC decoder, and the first matching degree of each candidate path is determined according to the output of the decoder.
  • the first matching degree may be determined according to the ratio of the number of zero bits to the total number of bits
  • the second matching degree of the HASH sequence and the corresponding second check sequence is determined, and the total matching degree is determined, according to The total matching degree is in descending order, and a predetermined number of candidate paths ranked first are selected as the target decoding path.
  • the path selection is performed according to the first check sequence and the second check sequence, thereby reducing the false alarm rate and improving the performance of the system.
  • the first sequence may be a CRC sequence, may be a hash sequence, or may be a random sequence.
  • the second sequence may be a CRC sequence, and may be a hash sequence or a random sequence.
  • the first sequence and the second sequence may be the same or different.
  • the receiving end determines the first check sequence according to the attribute information of the information sequence and the first sequence generation algorithm corresponding to the sending end, and determines the first according to the attribute information of the information sequence and the second sequence generating algorithm corresponding to the sending end. Second check sequence.
  • the receiving end determines the check sequence according to a sequence generation algorithm corresponding to the sender. Specifically include:
  • the receiving end may generate a check sequence according to the content of the information sequence and the CRC processing algorithm corresponding to the sender.
  • the receiving end may generate a check sequence according to the content of the information sequence and the hash function corresponding to the sender.
  • the receiving end may generate a check sequence according to the length of the information sequence and a random function corresponding to the sender.
  • the process of generating the check sequence may be used when generating the first check sequence, or when generating the second check sequence, or when the first check sequence and the second check sequence are generated.
  • the receiving end When the receiving end generates the check sequence according to the content of the information sequence and the CRC processing algorithm corresponding to the sending end, the receiving end may first generate an initial calibration according to the attribute information of the information sequence and the initial processing algorithm corresponding to the sending end. And verifying the sequence, and generating a check sequence according to the content of the information sequence, the initial check sequence, and a CRC processing algorithm corresponding to the transmitting end.
  • the initial processing algorithm may be a CRC algorithm, and may be a hash function or a random function.
  • the receiving end When the receiving end generates the check sequence according to the content of the information sequence and the hash function corresponding to the sending end, the receiving end may first generate an initial check according to the attribute information of the information sequence and the initial processing algorithm corresponding to the sending end. The sequence further generates a check sequence according to the content of the information sequence, the initial check sequence, and a hash function corresponding to the sender.
  • the initial processing algorithm may be a CRC algorithm, and may be a hash function or a random function.
  • the receiving end When the receiving end generates the check sequence according to the content of the information sequence and the hash function corresponding to the sending end, the receiving end may acquire at least one subsequence in the information sequence, and send and send according to the at least one subsequence.
  • the Hash function corresponding to the end determines the Hash sequence corresponding to the information sequence, and uses the Hash sequence as the generated check sequence.
  • the process of generating the check sequence may be used when generating the first check sequence, or when generating the second check sequence, or when the first check sequence and the second check sequence are generated.
  • the sending end if the sending end generates the second sequence according to the first sequence, the attribute information of the information sequence, and the preset second sequence generating algorithm, the receiving end generates the second school.
  • the sequence is verified, it is also generated according to the first check sequence, the attribute information of the information sequence, and the second sequence generation algorithm corresponding to the transmitting end.
  • the first check sequence and the second check sequence may be simultaneously performed. Path Selection. In order to reduce the complexity of the check, it is also possible to first filter the path to be decoded with one check sequence, and then determine the target decoding path by another check sequence.
  • the second sequence is a CRC sequence, a hash sequence, and a random sequence.
  • determining, according to the first sequence, the second sequence, the corresponding first check sequence, and the second check sequence, the target decoding path includes: determining each candidate path Selecting a first matching degree of the first sequence and the corresponding first check sequence, sorting each candidate path according to a first matching degree from highest to lowest, and selecting a preset first number of candidates before sorting The path is used as a path to be decoded; determining a second matching degree of the second sequence and the corresponding second check sequence in each path to be coded, and each path to be decoded is in descending order according to the second matching degree Sorting is performed to select a preset second number of to-be-decoded paths to be the target decoding path.
  • the first end and the second quantity are pre-stored in the receiving end, and the target decoding path is determined according to the first sequence, the second sequence, the corresponding first check sequence, and the second check sequence.
  • the first matching degree of the first sequence in each candidate path and the corresponding first check sequence may be determined first, and each candidate path is sorted according to the first matching degree in descending order, at most Among the candidate paths, the first number of candidate paths ranked first is selected as the path to be decoded.
  • a second matching degree of the second sequence and the second check sequence in each path to be decoded and sorting each path to be decoded according to the second matching degree in descending order, in the A second number of to-be-decoded paths that are ranked first are selected as the target decoding path among the first number of paths to be decoded.
  • the first quantity is greater than the second quantity, or the first quantity is equal to the second quantity.
  • the first number can be determined according to the same number of bits corresponding to the first sequence and the first check sequence, and the total number of bits of the first sequence.
  • the matching degree; the second matching degree can also be determined according to the manner. For example, the total bit is 8, and if the information of 7 bits is the same, the matching degree is 7/8.
  • the first sequence is a CRC sequence
  • the second sequence is a hash sequence as an example.
  • FIG. 4A is a schematic diagram of a polarization code encoding process according to an embodiment of the present disclosure.
  • a transmitting end first sends a sequence of information to be encoded to a CRC encoder, that is, a CRC processing algorithm is used for the information sequence to be encoded.
  • a CRC sequence is generated, which is the first sequence.
  • the preferred length of the CRC sequence is between 10 bits and 20 bits, and other lengths are not excluded.
  • the first sequence that is, the CRC sequence is combined with the information sequence to be encoded, and then sent to the hash state generator, that is, the hash sequence is obtained by using the hash function to obtain the hash sequence, and the hash sequence is used as the first Two sequences.
  • the length of the hash sequence is between 1 bit and 10 bits, although other lengths are not excluded.
  • the information sequence to be encoded is serially cascaded with the first sequence and the second sequence, and respectively mapped to subchannels having different bit channel capacities, thereby realizing information sequence, first sequence and second sequence and bit channel mapping, and the remaining subchannels are correspondingly
  • the position is frozen as position 0 and then sent to the polar encoder for encoding.
  • the length of the Polar mother code must be an integer power of 2, and the length of the output codeword may be arbitrary, so a rate matching operation is required, that is, a shortening or puncturing operation is performed.
  • the rate matching sequence corresponding to the rate matching operation can be obtained by a Gaussian approximation method, or another rate matching sequence that is insensitive to SNR, and the polar encoder outputs a sequence after rate matching.
  • the encoded sequence of the polar encoder is modulated by the modulator and transmitted to the receiving end through the channel.
  • FIG. 4B is a schematic diagram of a polarization code decoding process according to an embodiment of the present application.
  • the information sequence is firstly subjected to a CRC processing algorithm corresponding to the transmitting end to generate a first check sequence, and the sequence after combining the first check sequence and the information sequence is used.
  • the hash function corresponding to the sender generates a second check sequence.
  • the second sequence that is, the second matching degree of the hash sequence and the second check sequence
  • the second number of target decoding paths with the second higher matching degree are selected in the first number M of the to-be-decoded paths.
  • the determining, according to the first check sequence and the second check sequence in the candidate path, the target decoding path includes:
  • the second predetermined number of paths to be decoded are preset as the target decoding path.
  • the first end and the second quantity are pre-stored in the receiving end, and when the target decoding path is determined according to the first sequence, the second sequence, and the corresponding first check sequence and the second check sequence, a second matching degree of the second sequence in each candidate path and the corresponding second check sequence, each candidate path is sorted according to the second matching degree in descending order, and the sorting is selected among the plurality of candidate paths
  • the first number of candidate paths are used as the path to be decoded.
  • a second number of to-be-decoded paths that are ranked first are selected as the target decoding path among the first number of paths to be decoded.
  • the first quantity is greater than the second quantity, or the first quantity is equal to the second quantity.
  • the first sequence is a CRC sequence
  • the second sequence is a hash sequence as an example.
  • the polarization code encoding process is the same as the encoding process described above with reference to FIG. 4A, and will not be described again herein.
  • the decoding process is shown in FIG. 4B.
  • the receiving end after receiving the codeword sent by the transmitting end, the receiving end needs to send the codeword to the demodulator for demodulation, and performs de-rate matching for modulation.
  • the receiving end performs path selection, another case is: first, the information sequence is subjected to a CRC processing algorithm corresponding to the transmitting end to generate a first check sequence, and the sequence after combining the first check sequence and the information sequence is adopted.
  • a hash function corresponding to the sender generates a second check sequence.
  • M is the first quantity.
  • the second sequence that is, the first matching degree of the CRC sequence and the first check sequence
  • the second number of target decoding paths with the first matching degree are selected in the first number M of the to-be-decoded paths.
  • the second matching degree of the second sequence that is, the hash sequence and the corresponding second check sequence, can be selected to select four second matching degrees.
  • the path to be decoded is sent to the first sequence, the CRC sequence. Then, using the first matching degree of the CRC sequence and the first check sequence, the two to-be-decoded paths with the first matching degree are selected as the target decoding path among the four to-be-decoded paths.
  • the method further includes: before determining the target decoding path according to the first check sequence and the second check sequence in each candidate path, the method further includes:
  • the second check sequence is updated by using an algorithm corresponding to the sender, where the algorithm corresponding to the sender includes at least one of an exclusive OR processing algorithm, an interleaving algorithm, and an algorithm for updating a set bit.
  • the transmitting end when the transmitting end performs polarization code encoding, the first sequence and/or the second sequence may be updated.
  • the receiving end is based on the Before determining the target decoding path, the first sequence, the second sequence, and the corresponding first check sequence and the second check sequence in the candidate path may also use an algorithm corresponding to the sending end to the first check sequence. Performing an update; and/or updating the second check sequence by using an algorithm corresponding to the sender, where the algorithm corresponding to the sender includes an XOR processing algorithm, an interleaving algorithm, and an algorithm for updating a set bit At least one of them.
  • the receiving end may update the first check sequence by using only an algorithm corresponding to the sending end. If the sending end updates the second sequence by using only a preset algorithm, the receiving end may update the second check sequence by using only an algorithm corresponding to the sending end. If the sending end updates the first sequence and the second sequence by using a preset algorithm, the receiving end performs the first check sequence and the second check sequence by using an algorithm corresponding to the sending end. Update.
  • Updating the first check sequence by using an algorithm corresponding to the sending end, and/or updating the second check sequence by using an algorithm corresponding to the sending end includes:
  • the first check sequence and/or the second check sequence are updated using a scrambling sequence corresponding to the sender.
  • the transmitting end updates the first sequence and/or updates the second sequence by using a preset algorithm
  • the first sequence and/or the second sequence are updated by using a scrambling sequence.
  • the receiving end makes the determined decoding result more accurate in order to make the obtained first check sequence and/or the second check sequence more accurate, and updates the first check sequence by using an algorithm corresponding to the sending end and/or Or, when the second check sequence is updated by using an algorithm corresponding to the sender, the first check sequence and/or the second check sequence need to be updated by using a scrambling sequence corresponding to the sender.
  • the receiver uses and transmits The 8-bit UEID corresponding to the end is scrambled with the 8-bit second check sequence, that is, the hash sequence.
  • the number 8 is only one column when the length of the UEID is not greater than the hash sequence. If the length of the UEID is greater than the hash sequence and greater than the second sequence, that is, the CRC sequence, the transmitting end divides the UEID into two segments according to a preset method and respectively respectively.
  • the second sequence CRC sequence of the hash sequence is scrambled. For example, the first segment of the UEID is equal to the hash sequence. The first segment scrambles the hash sequence, and the remaining bits of the UEID are used as the second segment to scramble the CRC.
  • the receiving end divides the UEID corresponding to the sending end into two segments according to the method corresponding to the sending end, and respectively scrambles with the first check sequence, that is, the hash sequence and the second check sequence, that is, the CRC check sequence, such as the first segment of the UEID. It is equal to the first check sequence, that is, the hash sequence.
  • the first segment scrambles the first check sequence, that is, the hash sequence, and the remaining bits of the UEID are used as the second segment to scramble the second check sequence, that is, the CRC check.
  • the same processing as DCI can be performed for the uplink information (UPI) in the uplink control channel.
  • UCI uplink information
  • the method further includes:
  • Decoding results are determined based on the first check sequence and/or the second check sequence.
  • the first sequence may be a CRC sequence, may be a hash sequence, or may be a random sequence.
  • the second sequence is a CRC sequence, which may be a hash sequence, and may be a PC sequence or a random sequence.
  • the first sequence and the second sequence may be the same or different.
  • the receiving end may be according to each Whether the first sequence in the candidate path is identical to the corresponding first check sequence and the second sequence and the corresponding second check sequence, and determines a decoding result if the first sequence and the first check sequence in the candidate path The same, and the second sequence is the same as the second check sequence, and the information sequence on the candidate path is the decoding result. If at least one of the first sequence and the second sequence is not identical, the decoding fails.
  • the receiving end may determine whether the decoding result is the same according to whether the first sequence in each candidate path is the same as the corresponding first check sequence, if the first sequence and the first sequence in the candidate path If the check sequence is the same, the candidate path can be used as the decoding result output path, and the information sequence on the candidate path is the decoding result.
  • FIG. 4B A schematic diagram of a polarization code decoding process as shown in FIG. 4B, because only the first sequence is identical to the first check sequence, and the second sequence is identical to the second check sequence, the target decoding path decoding result is considered Correct, otherwise the decoding result is wrong.
  • the decoding path generally contains a polar code that can decode the correct target decoding path. Determining, for each path to be decoded, whether the first sequence in the to-be-decoded path is the same as the corresponding first check sequence, so that the target decoding path with the same first sequence and the first check sequence is selected as the polar code The decoding result is output. Obviously, this decoding algorithm has better performance. At the same time, since the two sequences are required to satisfy the verification relationship, it is considered correct, so the false alarm performance of the system is improved.
  • the CRC bit overhead can also be reduced, but the operation is also performed. Reduced system complexity.
  • the information sequence in each path according to the SCL decoding, and the first check in each path, when one of the sequences is a PC sequence when the polarization code is encoded determines the target decoding path including:
  • the target decoding path is determined according to the information sequence in each candidate path and the determined first check sequence.
  • a plurality of candidate paths are reserved according to a preset number.
  • the reserved candidate path is through the PC sequence, so When the target decoding path is selected, it is only necessary to select a sequence other than the PC and then select it.
  • the second sequence in the sequence is used as the PC sequence. Therefore, when performing the target decoding path selection, the same first sequence as the transmitting end can be reconstructed, so that the determined decoding result is more accurate. .
  • the process of determining the information sequence and the first sequence in the candidate sequence it is determined according to the coding manner corresponding to the transmitting end, that is, the process of determining the information sequence and the first sequence in the candidate sequence, and the polarization code of the transmitting end is required.
  • the process of determining the sequence of information is the same as the process of the first sequence.
  • the first sequence generation algorithm corresponding to the sender is determined, that is, the process of determining the first check sequence is generated by the sender.
  • the process of the first sequence is the same.
  • the attribute information of the information sequence may be the length of the information sequence, may be the content of the information sequence, or may be the length and content of the information sequence.
  • the content of the information sequence may be the entire content of the information sequence or part of the information sequence.
  • the first sequence may be a CRC sequence, may be a hash sequence, or may be a random sequence.
  • the first check sequence corresponding to the first sequence may be reconstructed in the manner described in the foregoing embodiment, but in order to further improve the efficiency of path selection, The first sequence is taken as the first check sequence.
  • the translation according to SCL The sequence of information in each path in the code, and the first check sequence and the second check sequence in each path, determine the target decoding path including:
  • the second number of candidate paths serve as target decoding paths.
  • the first matching degree of the first sequence and the first check sequence may be determined as the total matching degree, and the total matching degree is high.
  • each candidate path is sorted, and a predetermined number of candidate paths ranked first are selected as the target decoding path, thereby selecting the path by the first check sequence.
  • the information sequence and the first sequence may be input to the CRC decoder, and each candidate path is determined according to the output of the decoder.
  • the first matching degree may be determined according to a ratio of the number of zero bits to the total number of bits, and the first matching degree is determined as the total matching degree, and the total matching degree is high. In the lowest order, each candidate path is sorted, and a predetermined number of candidate paths ranked first are selected as the target decoding path, thereby selecting the path by the first check sequence.
  • the receiving end pre-stores a second quantity.
  • the second sequence is a PC sequence
  • the target decoding path according to the first check sequence it may be determined in each candidate path.
  • the second number of candidate paths serve as target decoding paths.
  • the first sequence may be a CRC sequence, may be a hash sequence, or may be a random sequence.
  • the first sequence is a CRC sequence
  • the second sequence is a PC sequence as an example.
  • FIG. 5A is a schematic diagram of a polarization code encoding process according to an embodiment of the present application.
  • a transmitting end first sends a sequence of information to be encoded to a CRC encoder, that is, a CRC processing algorithm is used for the information sequence to be encoded.
  • a CRC sequence is generated, which is the first sequence.
  • the CRC processing algorithm is a first sequence generation algorithm.
  • the preferred length of the CRC sequence is between 16 bits and 20 bits, and other lengths are not excluded.
  • the first sequence that is, the CRC sequence is combined with the information sequence to be encoded, and then sent to the PC sequence generator, that is, the sequence of the information sequence to be encoded and the sequence of the first sequence is combined by a PC processing algorithm to obtain a PC sequence, and the PC sequence is used as a PC sequence.
  • the second sequence is a second sequence generation algorithm.
  • the information sequence to be encoded is serially cascaded with the first sequence and the second sequence, and respectively mapped to subchannels having different bit channel capacities, thereby realizing information sequence, first sequence and second sequence and bit channel mapping, and the remaining subchannels are correspondingly
  • the position is frozen as position 0 and then sent to the polar code encoder for encoding.
  • the length of the Polar mother code must be an integer power of 2, and the length of the output codeword may be arbitrary, so a rate matching operation and a shortening or puncturing operation are required.
  • the rate matching sequence corresponding to the rate matching operation may preferably be obtained by a Gaussian approximation method, or another rate matching sequence that is insensitive to SNR, and the polar encoder outputs a code sequence after rate matching.
  • the encoded sequence of the polar encoder is modulated by the modulator and transmitted to the receiving end through the channel.
  • FIG. 5B is a schematic diagram of a polarization code decoding process according to an embodiment of the present invention.
  • the receiving end When performing path selection, the receiving end generates a first check sequence according to the information sequence and a first sequence generation algorithm corresponding to the sending end, and uses the first sequence, that is, the first match of the CRC sequence and the first check sequence. Degree, a second number M of target decoding paths are selected in the N candidate paths. Assuming that the second number M is 1, one candidate path with a higher first matching degree is selected among the N candidate paths as the target decoding path.
  • the minimum number of CRC bits used is limited by the list size of SCL decoding.
  • the false alarm performance requirement of the LTE control channel is used.
  • the list size is L
  • log2(L) CRCs on the basis of the original 16-bit CRC, but this greatly limits the decoding capability of the receiving end.
  • the control signaling is short, a larger list size decoding than 8 can achieve better performance, and at the same time, due to the control information bit length. Small, low complexity is easy to accept, but using a larger list size than 8 can cause false alarm performance to fail.
  • the advantage also ensures false alarm performance.
  • the length of the PC sequence can be reduced to further improve system performance.
  • the decoding result may also be determined according to the first check sequence, that is, the first check sequence may be used to detect an error.
  • the receiving end may determine whether the decoding result is the same according to whether the first sequence in each candidate path is the same as the corresponding first check sequence, if the first sequence and the first sequence in the candidate path If the check sequence is the same, the candidate path can be used as the decoding result output path, and the information sequence on the candidate path is the decoding result.
  • the first check sequence may be updated by using an algorithm corresponding to the sending end, where the algorithm corresponding to the sending end includes XOR processing. At least one of an algorithm, an interleaving algorithm, and an algorithm for updating a set bit.
  • updating the first check sequence by using an algorithm corresponding to the sending end includes: updating the first check sequence by using a scrambling sequence corresponding to the sending end. The process of the scrambling is the same as that in the above embodiment, and the process is not described in the embodiment of the present application.
  • FIG. 6 is a device for decoding a polarization code according to an embodiment of the present disclosure, where the device includes:
  • Polar decoder 61 configured to perform continuous deletion list SCL decoding on the sequence encoded by the received polarization code
  • the check sequence decoder 62 is configured to determine a target decoding path according to the information sequence in each path in the SCL decoding, and the first check sequence and the second check sequence in each path.
  • the check sequence decoder 62 is configured to determine a candidate sequence in the candidate sequence for the candidate sequence in the candidate candidate sequence for SCL decoding, and determine a first check sequence and a second of the candidate path. a check sequence; determining a target decoding path according to the first check sequence and the second check sequence in each candidate path
  • the check sequence decoder 62 is specifically configured to determine a candidate path according to the information sequence of each path in the SCL decoding and the determined second check sequence; according to the information sequence and determination in each candidate path
  • the first check sequence is output to determine the target decoding path.
  • the check sequence decoder 62 is specifically configured to determine a first matching degree of the first sequence in each candidate path and the corresponding first check sequence, in order from highest to lowest according to the first matching degree. Sorting the candidate paths, selecting a preset first number of candidate paths as the to-be-decoded path; determining a second matching degree of the second sequence and the corresponding second check sequence in each of the to-be-decoded paths, Sorting each path to be decoded according to a second matching degree from high to low, and selecting a preset second predetermined number of paths to be decoded as a target decoding path, wherein the first sequence is a loop Redundantly verifying any one of a CRC sequence, a hash hash sequence, and a random sequence, the second sequence being any one of a CRC sequence, a hash sequence, and a random sequence.
  • the check sequence decoder 62 is specifically configured to determine a second matching degree of the second sequence in each candidate path and the corresponding second check sequence, in descending order of the second matching degree. Sorting the candidate paths, selecting a preset first number of candidate paths as the to-be-decoded path; determining a first matching degree of the first sequence and the corresponding first check sequence in each of the to-be-decoded paths, Sorting each path to be decoded according to a first matching degree from high to low, and selecting a preset second predetermined number of paths to be decoded as a target decoding path, wherein the first sequence is a loop Redundantly verifying any one of a CRC sequence, a hash hash sequence, and a random sequence, the second sequence being any one of a CRC sequence, a hash sequence, and a random sequence.
  • the check sequence decoder 62 is specifically configured to determine a first matching degree of the first sequence in each candidate path and the corresponding first check sequence, in order from highest to lowest according to the first matching degree.
  • the candidate paths are sorted, and the preset second predetermined number of candidate paths are selected as the target decoding path, wherein the first check sequence is a cyclic redundancy check CRC sequence, a hash hash sequence, and a random sequence.
  • the second check sequence is any one of a CRC sequence, a hash sequence, and a random sequence.
  • the device also includes:
  • an update module configured to update the first check sequence by using an algorithm corresponding to the sending end; and/or update the second check sequence by using an algorithm corresponding to the sending end, where the sending end
  • the corresponding algorithm includes at least one of an exclusive OR processing algorithm, an interleaving algorithm, and an algorithm for updating a set bit.
  • the updating module is specifically configured to update the first check sequence and/or the second check sequence by using a scrambling sequence corresponding to the sending end.
  • the check sequence decoder 62 is further configured to determine a decoding result according to the first check sequence and/or the second check sequence.
  • An embodiment of the present application provides another polarization code decoding apparatus, where the apparatus includes:
  • a PC polarization code Polar decoder configured to perform continuous deletion list SCL decoding on the sequence encoded by the received polarization code; wherein the sequence is encoded by a parity PC polarization code encoding manner;
  • a check sequence decoder determining a sequence of information in the candidate sequence for the candidate sequence in the plurality of candidate paths reserved by the SCL decoding, and determining a first check sequence of the candidate path; according to each candidate path
  • the first check sequence determines the target decoding path.
  • the check sequence decoder is specifically configured to determine a first matching degree of the first sequence in each candidate path and the corresponding first check sequence, and each of the first matching degrees is in descending order
  • the candidate paths are sorted, and the preset second number of candidate paths are sorted as the target decoding path.
  • the device also includes:
  • An update module configured to update the first check sequence by using an algorithm corresponding to the sending end, where the algorithm corresponding to the sending end includes an XOR processing algorithm, an interleaving algorithm, and an algorithm for updating a set bit At least one.
  • the update module is specifically configured to update the first check sequence by using a scrambling sequence corresponding to the sending end.
  • another polarization code decoding apparatus provided by an embodiment of the present application includes:
  • a memory 520 configured to store program instructions
  • the processor 500 is configured to invoke a program instruction stored in the memory, and execute according to the obtained program:
  • the target decoding path is determined according to the information sequence in each path in the SCL decoding, and the first check sequence and the second check sequence in each path.
  • the determining, according to the information sequence in each path in the SCL decoding, and the first check sequence and the second check sequence in each path, determining the target decoding path includes:
  • the target decoding path is determined according to the first check sequence and the second check sequence in each candidate path.
  • the determining, according to the information sequence in each path in the SCL decoding, and the first check sequence and the second check sequence in each path, determining the target decoding path includes:
  • the target decoding path is determined according to the information sequence in each candidate path and the determined first check sequence.
  • the first check sequence is any one of a cyclic redundancy check CRC sequence, a hash hash sequence, and a random sequence
  • the second check sequence is a CRC sequence, a hash sequence, and a parity check. Any of a PC sequence and a random sequence.
  • the second check sequence is a CRC sequence, a hash sequence, and a random sequence.
  • determining, according to the information sequence in each path in the SCL decoding, and the first check sequence and the second check sequence in each path, the target decoding path includes:
  • the second predetermined number of paths to be decoded are preset as the target decoding path.
  • the second check sequence is a CRC sequence, a hash sequence, and a random sequence.
  • determining, according to the information sequence in each path in the SCL decoding, and the first check sequence and the second check sequence in each path, the target decoding path includes:
  • the second predetermined number of paths to be decoded are preset as the target decoding path.
  • the first check sequence is any one of a cyclic redundancy check CRC sequence, a hash hash sequence, and a random sequence
  • the second check sequence is a parity check PC sequence
  • the second number of candidate paths serve as target decoding paths.
  • the processor before determining the target decoding path according to the first check sequence and the second check sequence in each candidate path, the processor is further configured to:
  • the second check sequence is updated by using an algorithm corresponding to the sender, where the algorithm corresponding to the sender includes at least one of an exclusive OR processing algorithm, an interleaving algorithm, and an algorithm for updating a set bit.
  • the updating by using an algorithm corresponding to the sending end, updating the first check sequence, and/or updating the second check sequence by using an algorithm corresponding to the sending end includes:
  • the first check sequence and/or the second check sequence are updated using a scrambling sequence corresponding to the sender.
  • the processor is further configured to:
  • Decoding results are determined based on the first check sequence and/or the second check sequence.
  • the transceiver 510 is configured to receive and transmit data under the control of the processor 500.
  • transceiver 510 is optional and is not necessarily a device.
  • the bus architecture may include any number of interconnected buses and bridges, specifically linked by one or more processors represented by processor 500 and various circuits of memory represented by memory 520.
  • the bus architecture can also link various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and, therefore, will not be further described herein.
  • the bus interface provides an interface.
  • Transceiver 510 can be a plurality of components, including a transmitter and a transceiver, providing means for communicating with various other devices on a transmission medium.
  • the processor 500 is responsible for managing the bus architecture and general processing, and the memory 520 can store data used by the processor 500 when performing operations.
  • the processor 500 can be a central buried device (CPU), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or a complex programmable logic device (Complex Programmable Logic Device). , CPLD).
  • CPU central buried device
  • ASIC application specific integrated circuit
  • FPGA field-programmable gate array
  • CPLD complex programmable logic device
  • Another embodiment of the present application provides a computer storage medium storing computer executable instructions for causing the computer to execute any of the above methods in the embodiments of the present application.
  • the computer storage medium can be any available media or data storage device accessible by a computer, including but not limited to magnetic storage (eg, floppy disk, hard disk, magnetic tape, magneto-optical disk (MO), etc.), optical storage (eg, CD, DVD, BD, HVD, etc.), and semiconductor memories (for example, ROM, EPROM, EEPROM, non-volatile memory (NAND FLASH), solid-state hard disk (SSD)).
  • magnetic storage eg, floppy disk, hard disk, magnetic tape, magneto-optical disk (MO), etc.
  • optical storage eg, CD, DVD, BD, HVD, etc.
  • semiconductor memories for example, ROM, EPROM, EEPROM, non-volatile memory (NAND FLASH), solid-state hard disk (SSD)).
  • the embodiment of the present application discloses a method and an apparatus for decoding a polarization code, where the method includes: performing continuous deletion list SCL decoding on a sequence encoded by a received polarization code; and decoding according to SCL.
  • the path selection is performed according to the first check sequence and the second check sequence, thereby reducing the false alarm rate and improving the performance of the system.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

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Abstract

一种极化码译码方法及装置，所述方法包括：对接收到的极化码编码后的序列进行连续删除列表SCL译码（S301）；根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径（S303）。所述方法根据第一校验序列和第二校验序列进行路径选择，降低了虚警率，提高了系统的性能。

Description

一种极化码译码方法及装置
本申请要求在2017年3月1日提交中国专利局、申请号为201710118514.0、发明名称为“一种极化码译码方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及通信技术领域，特别涉及一种极化码译码方法及装置。
背景技术
目前，随着4G(the 4 th Generation mobile communication technology，第四代移动通信技术)进入规模商用阶段，面向未来的第五代移动通信技术5G(5 th Generation，第五代)已成为全球研发的热点。确定统一的5G概念，制定全球统一的5G标准，已经成为业界的共同呼声。作为5G的eMBB(Enhanced Mobile Broad Band，增强移动宽带)场景控制信道编码方案的极化码(Polar Codes)，是一种可以达到二进制对称信道容量的新型编码方式，且具有优异的译码性能。
现有技术中的极化码编译码方式包括CRC(Cyclic Redundancy Check，循环冗余校验)辅助的极化码编译码和PC(Parity Check，奇偶校验)辅助的极化码编译码。图1为现有技术中CRC辅助的极化码编译码的示意图，CRC辅助的极化码编译码过程包括：将待编码的信息序列首先经过CRC编码器编码，生成对应的CRC序列，再将信息序列和CRC序列一起送入Polar编码器，编码后经过调制器调制，再通过信道发送给接收端；译码时针对解调器解调后的比特流采用Polar-CRC联合译码器进行译码，主要是采用CRC辅助的连续删除列表(Successive Cancellation List，SCL)译码算法，在译码中选择最终译码的译码结果时，Polar-CRC联合译码器先将所有候选码字还原成含有CRC的候选信息序列，对所有候选信息序列做CRC译码处理，将通过CRC译码并且可靠度最高的候选信息序列作为最终的译码结果。
图2为现有技术中PC辅助的极化码编译码的示意图，PC辅助的极化码编译码过程包括：将待编码的信息序列首先经过CRC编码器编码，生成对应的CRC序列，再将信息序列和CRC序列一起送入PC-Polar编码器，编码后通过调制器调制，再通过信道发送给接收端；译码时针对调制器解调后的比特流采用Polar译码器进行译码，主要是采用PC辅助的SCL译码算法，在译码中选择最终译码的译码结果时，Polar译码器先将所述候选码字还原成含有PC的候选信息序列，对所有候选信息序列做PC译码处理，将通过PC译码并且可靠度最高的候选信息序列作为最终的译码结果。
控制信道的性能评估标准(metric)除了块出错率(Block Error Rate，BLER)以外，另一个重要的性能指标为虚警率(false alarm rates)。虚警率的计算方法有多种定义，常用的两种计算方法为：虚警率＝错误且通过CRC校验的帧数/总的传输帧数，或者虚警率＝错误且通过CRC校验的帧数/总的出错帧数。低的虚警率有利于降低UE(User Equipment，用户终端设备)上行碰撞概率，降低UE功耗，提高系统性能。
为了提高Polar译码的性能，一般采用SCL的列表译码(list decoding)算法。对于CRC辅助的极化码译码(aided polar codes)，由于译码时利用附加的CRC比特进行list decoding译码的路径选择，会导致虚警率的提高。如果虚警率P fa,path由N个CRC比特决定的虚警率，当采用列表大小(list size)为L的CRC辅助译码算法时，在最差的情况下，L条候选路径都需要用CRC进行校验选择，这就导致虚警率变为P fa,block＝1-(1-P fa,path) L，且随着L的增大而增大，其中，P fa,path为虚警率。
对于PC-polar来说最后附加的N个比特只用于检测错误(error detection)并不用于路径选择，故虚警率不会变差，但PC-polar需要较多的校验比特开销，才能保证虚警率的需求，因此该方法将导致BLER性能变差。对hash polar来说，虽然在信息比特比较短时明显优于PC-polar，但是要想采用较大的list size译码，如L＝32，哈希hash序列的开销也要相应增加。
发明内容
本申请实施例提供了一种极化码译码方法及装置，用以提供一种新的极化译码方案。
为达到上述目的，本申请实施例公开了一种极化码译码方法，所述方法包括：
对接收到的极化码编码后的序列进行连续删除列表SCL译码；
根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径。
可选地，所述根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径包括：
针对SCL译码保留的多条候选路径中的候选序列，确定该候选序列中的信息序列，并确定该候选路径的第一校验序列和第二校验序列；
根据每条候选路径中的第一校验序列和第二校验序列，确定目标译码路径。
可选地，所述根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径包括：
根据SCL译码中的每条路径的信息序列及确定出的第二校验序列，确定候选路径；
根据每条候选路径中的信息序列及确定出的第一校验序列，确定目标译码路径。
可选地，所述第一校验序列为循环冗余校验CRC序列、哈希hash序列和随机序列中的任意一种，所述第二校验序列为CRC序列、hash序列、奇偶校验PC序列和随机序列中的任意一种。
可选地，当所述第一校验序列为循环冗余校验CRC序列、哈希hash序列和随机序列中的任意一种，所述第二校验序列为CRC序列、hash序列和随机序列中的任意一种时，所述根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径包括：
确定每条候选路径中的第一序列与对应的第一校验序列的第一匹配度，按照第一匹配度由高至低的顺序对每条候选路径进行排序，选择排序在前的预设第一数量的候选路径作为待译码路径；
确定每条待译码路径中第二序列与对应的第二校验序列的第二匹配度，按照第二匹配度由高至低的顺序对每条待译码路径进行排序，选择排序在前的预设第二数量的待译码路径作为目标译码路径。
可选地，当所述第一校验序列为循环冗余校验CRC序列、哈希hash序列和随机序列中的任意一种，所述第二校验序列为CRC序列、hash序列和随机序列中的任意一种时，所述根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径包括：
确定每条候选路径中的第二序列与对应的第二校验序列的第二匹配度，按照第二匹配度由高至低的顺序对每条候选路径进行排序，选择排序在前的预设第一数量的候选路径作为待译码路径；
确定每条待译码路径中第一序列与对应的第一校验序列的第一匹配度，按照第一匹配度由高至低的顺序对每条待译码路径进行排序，选择排序在前的预设第二数量的待译码路径作为目标译码路径。
可选地，当所述第一校验序列为循环冗余校验CRC序列、哈希hash序列和随机序列中的任意一种，所述第二校验序列为奇偶校验PC序列时，所述根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径包括：
确定每条候选路径中的第一序列与对应的第一校验序列的第一匹配度，按照第一匹配度由高至低的顺序对每条候选路径进行排序，选择排序在前的预设第二数量的候选路径作为目标译码路径。
可选地，所述根据每条候选路径中的第一校验序列和第二校验序列，确定目标译码路径之前，所述方法还包括：
采用与发送端对应的算法对所述第一校验序列进行更新；和/或
采用与发送端对应的算法对所述第二校验序列进行更新，其中所述与发送端对应的算 法包括异或处理算法、交织算法和更新设定比特位的算法中的至少一种。
可选地，所述采用与发送端对应的算法对所述第一校验序列进行更新和/或采用与发送端对应的算法对所述第二校验序列进行更新包括：
采用与发送端对应的加扰序列对第一校验序列和/或第二校验序列进行更新。
可选地，所述方法还包括：
根据所述第一校验序列和\或第二校验序列，确定译码结果。
本申请实施例公开了一种极化码译码装置，所述装置包括：
极化码Polar译码器，用于对接收到的极化码编码后的序列进行连续删除列表SCL译码；
校验序列译码器，用于根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径。
可选地，所述校验序列译码器，用于针对SCL译码保留的多条候选路径中的候选序列，确定该候选序列中的信息序列，并确定该候选路径的第一校验序列和第二校验序列；根据每条候选路径中的第一校验序列和第二校验序列，确定目标译码路径。
可选地，所述校验序列译码器，具体用于根据SCL译码中的每条路径的信息序列及确定出的第二校验序列，确定候选路径；根据每条候选路径中的信息序列及确定出的第一校验序列，确定目标译码路径。
可选地，所述校验序列译码器，具体用于确定每条候选路径中的第一序列与对应的第一校验序列的第一匹配度，按照第一匹配度由高至低的顺序对每条候选路径进行排序，选择排序在前的预设第一数量的候选路径作为待译码路径；确定每条待译码路径中第二序列与对应的第二校验序列的第二匹配度，按照第二匹配度由高至低的顺序对每条待译码路径进行排序，选择排序在前的预设第二数量的待译码路径作为目标译码路径，其中所述第一序列为循环冗余校验CRC序列、哈希hash序列和随机序列中的任意一种，所述第二序列为CRC序列、hash序列和随机序列中的任意一种。
可选地，所述校验序列译码器，具体用于确定每条候选路径中的第二序列与对应的第二校验序列的第二匹配度，按照第二匹配度由高至低的顺序对每条候选路径进行排序，选择排序在前的预设第一数量的候选路径作为待译码路径；确定每条待译码路径中第一序列与对应的第一校验序列的第一匹配度，按照第一匹配度由高至低的顺序对每条待译码路径进行排序，选择排序在前的预设第二数量的待译码路径作为目标译码路径，其中所述第一序列为循环冗余校验CRC序列、哈希hash序列和随机序列中的任意一种，所述第二序列为CRC序列、hash序列和随机序列中的任意一种。
可选地，所述校验序列译码器，具体用于确定每条候选路径中的第一序列与对应的第一校验序列的第一匹配度，按照第一匹配度由高至低的顺序对每条候选路径进行排序，选 择排序在前的预设第二数量的候选路径作为目标译码路径，其中所述第一校验序列为循环冗余校验CRC序列、哈希hash序列和随机序列中的任意一种，所述第二校验序列为CRC序列、hash序列和随机序列中的任意一种。
可选地，所述装置还包括：
更新模块，用于采用与发送端对应的算法对所述第一校验序列进行更新；和/或采用与发送端对应的算法对所述第二校验序列进行更新，其中所述与发送端对应的算法包括异或处理算法、交织算法和更新设定比特位的算法中的至少一种。
可选地，所述更新模块，具体用于采用与发送端对应的加扰序列对第一校验序列和/或第二校验序列进行更新。
可选地，所述校验序列译码器，还用于根据所述第一校验序列和\或第二校验序列，确定译码结果。
本申请实施例提供的另一种极化码译码装置，包括：
存储器，用于存储程序指令；
处理器，用于调用所述存储器中存储的程序指令，按照获得的程序执行：
对接收到的极化码编码后的序列进行连续删除列表SCL译码；
根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径。
本申请另一实施例提供了一种计算机存储介质，所述计算机存储介质存储有计算机可执行指令，所述计算机可执行指令用于使所述计算机执行上述任一种方法。
本申请实施例公开了一种极化码译码方法及装置，所述方法包括：对接收到的极化码编码后的序列进行连续删除列表SCL译码；根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径。由于在本申请实施例中，根据第一校验序列和第二校验序列，进行路径选择，从而降低了虚警率，提高了系统的性能。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中CRC辅助的极化码编译码的示意图；
图2为现有技术中PC辅助的极化码编译码的示意图；
图3为本申请实施例提供一种极化码译码过程示意图；
图4A为本申请实施例提供一种极化码编码过程示意图；
图4B为本申请实施例提供一种极化码编码过程示意图；
图5A为本申请实施例提供一种极化码编码过程示意图；
图5B为本申请实施例提供一种极化码编码过程示意图；
图6为本申请实施例提供一种极化码编码装置结构图；
图7为本申请实施例提供另一种极化码编码装置结构图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本申请实施例提供的一种极化码译码方法，包括：对接收到的极化码编码后的序列进行连续删除列表SCL译码；根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径。
本申请实施例提供的极化码译码方法应用于接收端，所述接收端可以是基站，也可以是UE。
具体的，在本申请实施例中，在进行译码路径选择时，根据两个序列进行选择，从而降低了虚警率，提高了系统的性能。
实施例1：
为了有效的提高系统的性能，在本申请实施例中所述根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径包括：
针对SCL译码保留的多条候选路径中的候选序列，确定该候选序列中的信息序列，并确定该候选路径的第一校验序列和第二校验序列；
根据每条候选路径中的第一校验序列和第二校验序列，确定目标译码路径。
所述第一校验序列为循环冗余校验CRC序列、哈希hash序列和随机序列中的任意一种，所述第二校验序列为CRC序列、hash序列和随机序列中的任意一种。
图3为本申请实施例提供一种极化码译码过程示意图，该过程包括以下步骤：
S301：对接收到的极化码编码后的序列进行连续删除列表SCL译码。
通常情况下，极化码编码后的序列会做速率匹配(rate matching)处理和调制，再进行发送，接收端在接收到码字后需要解调和解速率匹配处理后，确定接收到的码字对应的极化码编码后的序列。在进行解速率匹配时，所采用的rate matching序列较佳的可以利用高斯方法获得，或者采用对信噪比(Signal Noise Ratio，SNR)不敏感的其他rate matching 序列。接收端的解速率方法与发送端的速率匹配方法是相对应的。
所述对接收到的极化码编码后的序列进行SCL译码的过程属于现有技术，在本申请实施例中对该过程不做赘述。
所述极化码编码后的序列经过SCL译码后，会根据预先设定的数量，保留多条候选路径，每条候选路径中包括对应的候选序列。
S302：针对SCL译码保留的多条候选路径中的候选序列，确定候选序列中的信息序列，并确定该候选路径的第一校验序列和第二校验序列。
为了能够重构出与发送端相同的第一序列和第二序列，使确定的译码的结果的更加准确，在确定候选序列中的信息序列、第一序列和第二序列的过程中，需要根据与发送端对应的编码方式来确定，即确定候选序列中的信息序列、第一序列和第二序列的过程，需要与发送端极化码编码时，确定信息序列、第一序列和第二序列的过程相同。
发送端在进行极化码编码时，将信息序列、第一序列和第二序列分别映射到比特信道容量不同的子信道上，实现信息序列、第一序列和第二序列与比特信道映射，其余子信道对应的位置作为冻结位置0，然后进行极化码编码，具体的映射后在哪个子信道上映射了什么信息发送端已知。则接收端在候选序列中确定信息序列、第一序列和第二序列时，需要根据与发送端对应的映射方法，在候选序列中确定出信息序列、第一序列和第二序列。具体的，接收端也预先获知有发送端映射方法，即接收端已知在哪个子信道上映射了什么信息，因此接收端在译码后的候选路径中可以确定出信息序列、第一序列和第二序列。
接收端中在确定SCL译码保留的多条候选路径的过程包括：开始译码时，路径数是1，每译码出一个比特位，路径数加倍，当路径数大于设定的数量时，根据每条路径中译出的比特位的概率确定路径的概率，选择概率较高的设定数量的路径作为候选路径，进行下一比特位的译码，并在译码后，判断针对该下一比特位的译码结果对应的路径数量是否大于设定的数量，如果是，重复上述过程，直到最后一个比特位译码成功，并选择出最终的候选路径。一般的，SCL译码中保存有预先设定的数量，例如可以是4。
同理，为了使得译码的结果更加准确，在确定第一校验序列的过程中，根据与发送端对应的第一序列生成算法来确定，即确定第一校验序列的过程与发送端生成第一序列的过程相同。在确定第二校验序列的过程中，根据与发送端对应的第二序列生成算法来确定的，即确定第二校验序列的过程与发送端生成第二序列的过程相同。
具体的可以是接收端保存有与发送端对应的第一序列生成算法和第二序列生成算法。针对每条候选路径，接收端根据该候选路径中信息序列的属性信息及与发送端对应的第一序列生成算法，确定第一校验序列，并根据该候选路径中信息序列的属性信息及与发送端对应的第二序列生成算法，确定第二校验序列。
信息序列的属性信息可以是信息序列的长度，可以是信息序列的内容，也可以是信息 序列的长度和内容。所述信息序列的内容可以是信息序列的全部内容，也可以是信息序列的部分内容。
或者，在本申请实施例中，如果第一序列或第二序列为CRC序列，可以采用上述方式重构出与第一序列和第二序列对应的第一校验序列和第二校验序列，但为了进一步提高路径选择的效率，可以直接将第一序列或第二序列作为第一校验序列或第二校验序列。例如第一序列为CRC序列，则可以将第一序列作为第一校验CRC序列。
S303：根据每条候选路径中的第一校验序列和第二校验序列，确定目标译码路径。
在确定出每条候选路径中的第一校验序列和第二校验序列后，可以根据每条候选路径中的第一校验序列和第二校验序列，确定目标译码路径。
在根据每条候选路径中的第一校验序列和第二校验序列，确定目标译码路径时，可以是根据第一序列与第一校验序列的第一匹配度，以及第二序列与第二校验序列的第二匹配度，确定出总匹配度，按照总匹配度由高至低的顺序，将每条候选路径进行排序，选择排序靠前的预设数量的候选路径作为目标译码路径，从而通过第一校验序列和第二校验序列选择路径。
如果第一序列或第二序列为CRC校验序列，则在进行目标译码路径选择时，还可以是将信息序列和第一序列或第二序列输入到CRC译码器中，根据译码器的输出，确定每条候选路径的第一匹配度，例如可以根据为零的比特位的数量与总的比特位数量的比值，确定该第一匹配度，然后确定第二序列或第一序列，与对应的第二校验序列或第一校验序列的第二匹配度，确定出总匹配度，按照总匹配度由高至低的顺序，将每条候选路径进行排序，选择排序靠前的预设数量的候选路径作为目标译码路径，从而通过第一校验序列和第二校验序列选择路径。例如第一序列为CRC序列，第二序列为HASH序列时，则将信息序列和第一序列输入到CRC译码器中，根据译码器的输出，确定每条候选路径的第一匹配度，例如可以根据为零的比特位的数量与总的比特位数量的比值，确定该第一匹配度，确定HASH序列与对应的第二校验序列的第二匹配度，确定出总匹配度，按照总匹配度由高至低的顺序，选择排序靠前的预设数量的候选路径作为目标译码路径。
由于在本申请实施例中，根据第一校验序列和第二校验序列，进行路径选择，从而降低了虚警率，提高了系统的性能。
实施例2：
所述第一序列可以是CRC序列、可以是hash序列，也可以是随机序列。所述第二序列可以是CRC序列，可以是hash序列，也可以是随机序列。第一序列和第二序列可以相同，也可以不同。
接收端根据所述信息序列的属性信息及与发送端对应的第一序列生成算法，确定第一校验序列，并根据信息序列的属性信息及与发送端对应的第二序列生成算法，确定第二校 验序列。
在生成第一校验序列和第二校验序列时，接收端根据与发送端对应的序列生成算法来确定校验序列。具体包括：
如果与发送端对应的序列生成算法为CRC处理算法，接收端可以根据所述信息序列的内容及与发送端对应的CRC处理算法，生成校验序列。
如果与发送端对应的序列生成算法为Hash函数，接收端可以根据所述信息序列的内容及与发送端对应的Hash函数，生成校验序列。
如果与发送端对应的序列生成算法为随机函数，接收端可以根据所述信息序列的长度及与发送端对应的随机函数，生成校验序列。
上述生成校验序列的过程可以在生成第一校验序列时使用，也可以是在生成第二校验序列时使用，也可以在生成第一校验序列和第二校验序列时同时使用。
接收端在根据所述信息序列的内容及与发送端对应的CRC处理算法，生成校验序列时，可以是先根据所述信息序列的属性信息及与发送端对应的初始处理算法，生成初始校验序列，再根据所述信息序列的内容、所述初始校验序列及与发送端对应的CRC处理算法，生成校验序列。其中该初始处理算法可以是CRC算法，可以是Hash函数，还可以是随机函数。
接收端在根据所述信息序列的内容及与发送端对应的Hash函数，生成校验序列时，可以是先根据所述信息序列的属性信息及与发送端对应的初始处理算法，生成初始校验序列，再根据所述信息序列的内容、所述初始校验序列及与发送端对应的Hash函数，生成校验序列。其中该初始处理算法可以是CRC算法，可以是Hash函数，还可以是随机函数。
接收端在根据所述信息序列的内容及与发送端对应的Hash函数，生成校验序列包括时，可以是在所述信息序列中获取至少一个子序列，根据所述至少一个子序列及与发送端对应的Hash函数，确定所述信息序列对应的Hash序列，将所述Hash序列作为生成的校验序列。
上述生成校验序列的过程可以在生成第一校验序列时使用，也可以是在生成第二校验序列时使用，也可以在生成第一校验序列和第二校验序列时同时使用。
具体的，在本申请实施例中如果发送端在生成第二序列时，是根据第一序列、信息序列的属性信息及预设的第二序列生成算法生成的，则接收端在生成第二校验序列时，也根据第一校验序列、信息序列的属性信息及与发送端对应的第二序列生成算法生成。
确定了第一校验序列和第二校验序列后，在根据第一校验序列和第二校验序列确定目标译码路径时，可以是第一校验序列与第二校验序列同时进行路径选择。为了减小校验时的复杂度，也可以是先用一个校验序列筛选出待译码路径，再通过另一个校验序列确定目标译码路径。
在上述各实施例的基础上，在本申请实施例中，当所述第一序列为CRC序列、hash序列和随机序列中的任意一种，所述第二序列为CRC序列、hash序列和随机序列中的任意一种时，所述根据该候选路径中的第一序列、第二序列与对应的第一校验序列、第二校验序列，确定目标译码路径包括：确定每条候选路径中的第一序列与对应的第一校验序列的第一匹配度，按照第一匹配度由高至低的顺序对每条候选路径进行排序，选择排序在前的预设第一数量的候选路径作为待译码路径；确定每条待译码路径中第二序列与对应的第二校验序列的第二匹配度，按照第二匹配度由高至低的顺序对每条待译码路径进行排序，选择排序在前的预设第二数量的待译码路径作为目标译码路径。
在本申请实施例中，接收端中预先保存有第一数量和第二数量，在根据第一序列、第二序列与对应的第一校验序列、第二校验序列，确定目标译码路径时，可以是先确定每条候选路径中的第一序列与对应的第一校验序列的第一匹配度，根据第一匹配度由高至低的顺序对每条候选路径进行排序，在多条候选路径中选择排序靠前的第一数量的候选路径作为待译码路径。然后再确定每条待译码路径中的第二序列与第二校验序列的第二匹配度，根据第二匹配度由高至低的顺序对每条待译码路径进行排序，在所述第一数量的待译码路径中选择排序靠前的第二数量的待译码路径作为目标译码路径。第一数量大于第二数量，或者第一数量等于第二数量。
因为第一序列和第一校验序列的长度相同，因此根据第一序列和第一校验序列对应的比特位的信息相同的数量，及第一序列的总的比特位数量，可以确定第一匹配度；同理第二匹配度也可以根据该方式确定。例如总的比特位为8，如果有7个比特位的信息都对应相同，则匹配度为7/8。
以第一序列为CRC序列，第二序列为hash序列为例进行说明。
图4A为本申请实施例提供一种极化码编码过程示意图，发送端在进行极化码编码时，首先将待编码的信息序列送入CRC编码器，即对待编码的信息序列采用CRC处理算法生成CRC序列，所述CRC序列作为第一序列。较佳的CRC序列的长度位于10比特-20比特之间，并不排除其他长度。将第一序列即CRC序列与待编码信息序列进行组合之后送入hash状态生成器，即对待编码的信息序列和第一序列组合后的序列采用hash函数，得到hash序列，所述hash序列作为第二序列。较佳的，该hash序列的长度位于1比特-10比特之间，当然并不排除其他长度。将待编码的信息序列与第一序列与第二序列串行级联，分别映射到比特信道容量不同的子信道，实现信息序列、第一序列与第二序列与比特信道映射，其余子信道对应的位置作为冻结位置0，然后一起送入polar编码器，进行编码。
具体的映射后在哪个子信道上映射了什么信息发送端已知。Polar母码的长度一定是2的整数次幂，而输出码字的长度可能是任意的，故需要rate matching操作，即执行减缩(shortening)或者打孔(puncturing)操作。rate matching操作对应的rate matching序列较 佳的可以利用高斯近似方法获得，或者采用对SNR不敏感的其他rate matching序列，polar编码器输出的是rate matching后的序列。polar编码器编码后的序列通过调制器调制，就可以通过信道发送给接收端了。
图4B为本申请实施例提供一种极化码译码过程示意图，由图4B可以看出，接收端在接收到发送端发送的码字后，需要将该码字送入解调器解调，并进行解速率匹配，针对调制器解调后的比特流采用Polar-hash联合译码器进行译码，主要采用SCL译码。若采用SCL译码的list size为L时，保留了N＝2 L条候选路径，得到N条候选路径中的N个候选序列，所述候选序列包括信息序列，第一序列和第二序列。
接收端在进行路径选择时，一种情况为，首先将信息序列采用与发送端对应的CRC处理算法，生成第一校验序列，将第一校验序列与信息序列进行组合之后的序列采用与发送端对应的hash函数，生成第二校验序列。利用每条候选路径中第一序列即CRC序列与第一检验序列的第一匹配度，从N条候选路径中选择第一匹配度较高的M(M<N)条待译码路径，其中M为第一数量。然后利用第二序列即hash序列与第二校验序列的第二匹配度，在第一数量M条待译码路径选择第二匹配度较高的第二数量的目标译码路径。这样带来的好处在于，由于hash序列的校验比CRC序列校验的复杂度更高，直接先利用CRC序列选择待译码路径，将第一数量M值降到较小，有利于降低hash序列校验过程的复杂度。
另一种情况为：所述根据该候选路径中第一校验序列和第二校验序列，确定目标译码路径包括：
确定每条候选路径中的第二序列与对应的第二校验序列的第二匹配度，按照第二匹配度由高至低的顺序对每条候选路径进行排序，选择排序在前的预设第一数量的候选路径作为待译码路径；
确定每条待译码路径中第一序列与对应的第一校验序列的第一匹配度，按照第一匹配度由高至低的顺序对每条待译码路径进行排序，选择排序在前的预设第二数量的待译码路径作为目标译码路径。
接收端中预先保存有第一数量和第二数量，在根据第一序列、第二序列与对应的第一校验序列、第二校验序列，确定目标译码路径时，可以是，先确定每条候选路径中的第二序列与对应的第二校验序列的第二匹配度，根据第二匹配度由高至低的顺序对每条候选路径进行排序，在多条候选路径中选择排序靠前的第一数量的候选路径作为待译码路径。然后再确定每条待译码路径中的第一序列与第一校验序列的第一匹配度，根据第一匹配度由高至低的顺序对每条待译码路径进行排序，在所述第一数量的待译码路径中选择排序靠前的第二数量的待译码路径作为目标译码路径。第一数量大于第二数量，或者第一数量等于第二数量。
还是以第一序列为CRC序列，第二序列为hash序列为例进行说明。
极化码编码过程与上述图4A描述的编码过程相同，在此不再进行赘述。译码过程如图4B所示，由图4B可以看出，接收端在接收到发送端发送的码字后，需要将该码字送入解调器解调，并进行解速率匹配，针对调制器解调后的比特流采用Polar-hash联合译码器进行译码，主要采用SCL译码。若采用SCL译码的list size为L时，保留了N＝2 L条候选路径，得到N条候选路径中的N个候选序列，所述候选序列包括信息序列，第一序列和第二序列。
接收端在进行路径选择时，另一种情况为：首先将信息序列采用与发送端对应的CRC处理算法，生成第一校验序列，将第一校验序列与信息序列进行组合之后的序列采用与发送端对应的hash函数，生成第二校验序列。利用每条候选路径中第二序列即hash序列与第二检验序列的第二匹配度，从N条候选路径中选择第二匹配度较高的M(M<N)条待译码路径，其中M为第一数量。然后利用第一序列即CRC序列与第一校验序列的第一匹配度，在第一数量M条待译码路径选择第一匹配度较高的第二数量的目标译码路径。
假定N＝8，第一数量M＝4，第二数量为2，可以用第二序列即hash序列与对应的第二校验序列的第二匹配度，选择4条第二匹配度较高的待译码路径，送给第一序列即CRC序列。然后利用CRC序列与第一校验序列的第一匹配度，在这4条待译码路径中选择第一匹配度较高的2条待译码路径作为目标译码路径。
实施例3：
所述根据每条候选路径中的第一校验序列和第二校验序列，确定目标译码路径之前，所述方法还包括：
采用与发送端对应的算法对所述第一校验序列进行更新；和/或
采用与发送端对应的算法对所述第二校验序列进行更新，其中所述与发送端对应的算法包括异或处理算法、交织算法和更新设定比特位的算法中的至少一种。
一般发送端在进行极化码编码时，可能还会对第一序列和/或第二序列进行更新，为了能够重构出与发送端相同的第一序列和第二序列，接收端在根据该候选路径中的第一序列、第二序列与对应的第一校验序列和第二校验序列，确定目标译码路径之前，也可以采用与发送端对应的算法对所述第一校验序列进行更新；和/或采用与发送端对应的算法对所述第二校验序列进行更新，其中所述与发送端对应的算法包括异或处理算法、交织算法和更新设定比特位的算法中的至少一种。
如果发送端只采用预设的算法对所述第一序列进行更新，则接收端可以是只采用与发送端对应的算法对所述第一校验序列进行更新。如果发送端只采用预设的算法对所述第二序列进行更新，则接收端可以是只采用与发送端对应的算法对所述第二校验序列进行更新。如果发送端采用预设的算法对所述第一序列和所述第二序列均进行更新，则接收端采 用与发送端对应的算法对所述第一校验序列和第二校验序列均进行更新。
所述采用与发送端对应的算法对所述第一校验序列进行更新和/或采用与发送端对应的算法对所述第二校验序列进行更新包括：
采用与发送端对应的加扰序列对第一校验序列和/或第二校验序列进行更新。
由于发送端在采用预设的算法对所述第一序列进行更新和/或第二序列进行更新时，会采用加扰序列对第一序列和/或第二序列进行更新。接收端为了使得到的第一校验序列和/或第二校验序列更加准确，使确定的译码的结果更加准确，在采用与发送端对应的算法对第一校验序列进行更新和/或采用与发送端对应的算法对第二校验序列进行更新时，需要采用与发送端对应的加扰序列对第一校验序列和/或第二校验序列进行更新。
由于是两个校验序列，当发送端只对一个序列进行加扰时，例如对第一序列hash序列加扰，采用8比特的UEID与8比特的hash序列加扰，则接收端采用与发送端对应的8比特的UEID与8比特的第二校验序列即hash序列加扰。
当然数字8只是UEID长度不大于hash序列时的一个列子，如果UEID的长度大于hash序列，也大于第二序列即CRC序列，发送端将UEID按照预设的方法分成两段分别与第一序列即hash序列个第二序列CRC序列加扰，如UEID的第一段与hash序列等长，该第一段对hash序列加扰，UEID剩余的比特作为第二段对CRC加扰。
则接收端将与发送端对应的UEID按照与发送端对应的方法分成两段分别与第一校验序列即hash序列和第二校验序列即CRC校验序列加扰，如UEID的第一段与第一校验序列即hash序列等长，该第一段对第一校验序列即hash序列加扰，UEID剩余的比特作为第二段对第二校验序列即CRC校验加扰。
对于上行控制信道中的上行链路信息(UP link Information，UCI)可以进行与DCI相同的处理。
实施例4：
在上述各实施例的基础上，在本申请实施例中，所述方法还包括：
根据所述第一校验序列和\或第二校验序列，确定译码结果。
在本申请实施例中，第一序列可以是CRC序列、可以是hash序列，也可以是随机序列。所述第二序列为CRC序列，可以是hash序列，可以是PC序列，也可以是随机序列。第一序列和第二序列可以相同，也可以是不同。
当所述第一序列为CRC序列、hash序列和随机序列中的任意一种，所述第二序列为CRC序列、hash序列、和随机序列中的任意一种时，接收端可以是根据每条候选路径中的第一序列与对应的第一校验序列以及第二序列与对应的第二校验序列是否相同，确定译码结果，如果该候选路径中的第一序列与第一校验序列相同，并且第二序列与第二校验序列 也相同，该候选路径上的信息序列即为译码结果。如果第一序列与第二序列中至少有一个不相同，则译码失败。
当第二序列为PC序列时，接收端可以是根据每条候选路径中的第一序列与对应的第一校验序列是否相同，确定译码结果，如果该候选路径中的第一序列与第一校验序列相同，则可以将该候选路径作为译码结果输出路径，该候选路径上的信息序列即为译码结果。
如图4B所示的极化码译码过程示意图，因为只有当第一序列与第一校验序列相同，并且第二序列与第二校验序列相同，则认为该目标译码路径译码结果正确，否则判断译码结果错误。
当第二序列为hash序列，第一序列为CRC序列时，因为hash序列的校验较复杂，根据第二序列与第二校验序列的第二匹配度选择后的第一数量为M的待译码路径里面一般包含polar码能够译码正确的目标译码路径。针对每条待译码路径，判断该待译码路径中第一序列与对应的第一校验序列是否相同，从而选出第一序列与第一校验序列相同的目标译码路径作为polar码的译码结果输出，显然这种译码算法具有更好的性能，同时由于需要两个序列都要满足校验关系才认为正确，故提高了系统的false alarm性能。
在先根据第一序列与第一校验序列的第一匹配度选择M条待译码路径，再根据第二序列与第二校验序列的第二匹配度选择目标译码路径时，一种特例，当M＝1时，只利用第一序列即简单的CRC序列与对应的第一校验序列的第一匹配度，选择出1条待译码路径，该待译码路径为第一匹配度最高的候选路径，最有可能是译码输出路径。再利用第二序列与第二校验序列是否相同，确定最终的译码输出路径，由于还是两个序列都满足校验才判断为译码正确，故同样可以降低CRC比特开销，但是这种操作降低了系统复杂度。
实施例5：
当极化码编码时其中一个序列为PC序列时，为了进行路径选择，在本申请实施例中，所述根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径包括：
根据SCL译码中的每条路径的信息序列及确定出的第二校验序列，确定候选路径；
根据每条候选路径中的信息序列及确定出的第一校验序列，确定目标译码路径。
所述极化码编码后的序列经过SCL译码后，会根据预先设定的数量，保留多条候选路径，当该序列中包含PC序列时，保留的候选路径是通过PC序列的，因此在进行目标译码路径选择时，只需要采用除PC之外的序列再进行选择即可。
为了简单，将该序列中的第二序列作为PC序列，因此具体在进行目标译码路径选择时，可以能够重构出与发送端相同的第一序列，使确定的译码的结果的更加准确。在确定候选序列中的信息序列、第一序列的过程中，需要根据与发送端对应的编码方式来确定，即确定候选序列中的信息序列、第一序列的过程，需要与发送端极化码编码时，确定信息 序列和第一序列的过程相同。
同理，为了使得译码的结果更加准确，在确定第一校验序列的过程中，根据与发送端对应的第一序列生成算法来确定，即确定第一校验序列的过程与发送端生成第一序列的过程相同。
信息序列的属性信息可以是信息序列的长度，可以是信息序列的内容，也可以是信息序列的长度和内容。所述信息序列的内容可以是信息序列的全部内容，也可以是信息序列的部分内容。
其中，该第一序列可以是CRC序列、可以是hash序列，也可以是随机序列。
在本申请实施例中，如果第一序列为CRC序列，可以采用上述实施例中描述的方式重构出与第一序列对应的第一校验序列，但为了进一步提高路径选择的效率，可以直接将第一序列作为第一校验序列。
当所述第一校验序列为循环冗余校验CRC序列、哈希hash序列和随机序列中的任意一种，所述第二校验序列为奇偶校验PC序列时，所述根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径包括：
确定每条候选路径中的第一序列与对应的第一校验序列的第一匹配度，按照第一匹配度由高至低的顺序对每条候选路径进行排序，选择排序在前的预设第二数量的候选路径作为目标译码路径。
在根据每条候选路径中的第一校验序列，确定目标译码路径时，可以是将第一序列与第一校验序列的第一匹配度确定为总匹配度，按照总匹配度由高至低的顺序，将每条候选路径进行排序，选择排序靠前的预设数量的候选路径作为目标译码路径，从而通过第一校验序列选择路径。
如果第一序列为CRC校验序列，则在进行目标译码路径选择时，还可以是将信息序列和第一序列输入到CRC译码器中，根据译码器的输出，确定每条候选路径的第一匹配度，例如可以根据为零的比特位的数量与总的比特位数量的比值，确定该第一匹配度，将该第一匹配度确定为总匹配度，按照总匹配度由高至低的顺序，将每条候选路径进行排序，选择排序靠前的预设数量的候选路径作为目标译码路径，从而通过第一校验序列选择路径。
在本申请实施例中，接收端预先保存有第二数量，当第二序列为PC序列时，在根据第一校验序列，确定目标译码路径时，可以是，确定每条候选路径中的第一序列与对应的第一校验序列的第一匹配度，将第一匹配度由高至低进行排序，也就是对每条候选路径进行排序，在多条候选路径中选择排序靠前的第二数量的候选路径作为目标译码路径。第一序列可以是CRC序列、可以是hash序列，也可以是随机序列。
以第一序列为CRC序列，第二序列为PC序列为例进行说明。
图5A为本申请实施例提供一种极化码编码过程示意图，发送端在进行极化码编码时，首先将待编码的信息序列送入CRC编码器，即对待编码的信息序列采用CRC处理算法生成CRC序列，所述CRC序列作为第一序列。CRC处理算法为第一序列生成算法。较佳的CRC序列的长度位于16比特-20比特之间，并不排除其他长度。将第一序列即CRC序列与待编码信息序列进行组合之后送入PC序列生成器，即对待编码的信息序列和第一序列组合后的序列采用PC处理算法，得到PC序列，所述PC序列作为第二序列。PC处理算法为第二序列生成算法。将待编码的信息序列与第一序列与第二序列串行级联，分别映射到比特信道容量不同的子信道，实现信息序列、第一序列与第二序列与比特信道映射，其余子信道对应的位置作为冻结位置0，然后一起送入polar码编码器，进行编码。
具体的映射后在哪个子信道上映射了什么信息发送端已知。Polar母码的长度一定是2的整数次幂，而输出码字的长度可能是任意的，故需要rate matching操作及执行shortening或者puncturing操作。rate matching操作对应的rate matching序列较佳的可以利用高斯近似方法获得，或者采用对SNR不敏感的其他rate matching序列，polar编码器输出的是rate matching后的编码序列。polar编码器编码后的序列通过调制器调制，就可以通过信道发送给接收端了。
图5B为本申请实施例提供一种极化码译码过程示意图，由图5B可以看出，接收端在接收到发送端发送的码字后，需要将该码字送入解调器解调，并进行解速率匹配，针对调制器解调后的比特流采用PC-Polar译码器进行译码时，主要采用PC辅助的SCL译码算法。若采用SCL译码的list size为L时，保留了N＝2 L条候选路径，则得到N条候选路径中的N个候选序列，所述候选序列包括信息序列，第一序列和第二序列。接收端在进行路径选择时，根据所述信息序列，及与发送端对应的第一序列生成算法，生成第一校验序列，利用第一序列即CRC序列与第一校验序列的第一匹配度，在N条候选路径选择第二数量M的目标译码路径。假设第二数量M为1，则在N条候选路径中选择第一匹配度较高的1条候选路径作为目标译码路径。
注意到，CRC辅助译码为了维持false alarm性能，所采用的最小CRC比特数受限于SCL译码的list size，以LTE控制信道的false alarm性能要求为例，如采用list size为L，就要在原16比特CRC基础上增加log2(L)个CRC，但这大大限制了接收端的解码能力。以L＝8为例，附加CRC个数为3共19个比特CRC，当控制信令较短时，采用比8更大的list size译码能够取得更好的性能，同时由于控制信息比特长度小，复杂度低很容易被接受，但是采用比8更大的list size会导致false alarm性能无法满足要求。本方案中无论采用多大的list size进行polar译码首先根据PC序列选择路径，只保留M条路径让CRC参与路径选择，其中，M＝4或M＝2，既可以发挥CRC译码性能好的优点还可以确保false alarm性能，对于PC-polar来说由于CRC也参与了路径选择，完全可以降低PC序列的长度来进一 步提高系统性能。
其中，在本申请实施例中，还可以根据所述第一校验序列确定译码结果，即该第一校验序列可以用于检测错误。
当第二序列为PC序列时，接收端可以是根据每条候选路径中的第一序列与对应的第一校验序列是否相同，确定译码结果，如果该候选路径中的第一序列与第一校验序列相同，则可以将该候选路径作为译码结果输出路径，该候选路径上的信息序列即为译码结果。
另外，在本申请实施例中，当生成了第一序列后，也可以采用与发送端对应的算法对所述第一校验序列进行更新，其中所述与发送端对应的算法包括异或处理算法、交织算法和更新设定比特位的算法中的至少一种。具体的采用与发送端对应的算法对所述第一校验序列进行更新包括：采用与发送端对应的加扰序列对第一校验序列进行更新。该加扰的过程与上述实施例中相同，在本申请实施例中对该过程不进行赘述。
图6为本申请实施例提供的一种极化码译码装置，所述装置包括：
极化码Polar译码器61，用于对接收到的极化码编码后的序列进行连续删除列表SCL译码；
校验序列译码器62，用于根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径。
所述校验序列译码器62，用于针对SCL译码保留的多条候选路径中的候选序列，确定该候选序列中的信息序列，并确定该候选路径的第一校验序列和第二校验序列；根据每条候选路径中的第一校验序列和第二校验序列，确定目标译码路径
所述校验序列译码器62，具体用于根据SCL译码中的每条路径的信息序列及确定出的第二校验序列，确定候选路径；根据每条候选路径中的信息序列及确定出的第一校验序列，确定目标译码路径.
所述校验序列译码器62，具体用于确定每条候选路径中的第一序列与对应的第一校验序列的第一匹配度，按照第一匹配度由高至低的顺序对每条候选路径进行排序，选择排序在前的预设第一数量的候选路径作为待译码路径；确定每条待译码路径中第二序列与对应的第二校验序列的第二匹配度，按照第二匹配度由高至低的顺序对每条待译码路径进行排序，选择排序在前的预设第二数量的待译码路径作为目标译码路径，其中所述第一序列为循环冗余校验CRC序列、哈希hash序列和随机序列中的任意一种，所述第二序列为CRC序列、hash序列和随机序列中的任意一种。
所述校验序列译码器62，具体用于确定每条候选路径中的第二序列与对应的第二校验序列的第二匹配度，按照第二匹配度由高至低的顺序对每条候选路径进行排序，选择排序在前的预设第一数量的候选路径作为待译码路径；确定每条待译码路径中第一序列与对应的第一校验序列的第一匹配度，按照第一匹配度由高至低的顺序对每条待译码路径进行排 序，选择排序在前的预设第二数量的待译码路径作为目标译码路径，其中所述第一序列为循环冗余校验CRC序列、哈希hash序列和随机序列中的任意一种，所述第二序列为CRC序列、hash序列和随机序列中的任意一种。
所述校验序列译码器62，具体用于确定每条候选路径中的第一序列与对应的第一校验序列的第一匹配度，按照第一匹配度由高至低的顺序对每条候选路径进行排序，选择排序在前的预设第二数量的候选路径作为目标译码路径，其中所述第一校验序列为循环冗余校验CRC序列、哈希hash序列和随机序列中的任意一种，所述第二校验序列为CRC序列、hash序列和随机序列中的任意一种。
所述装置还包括：
更新模块，用于采用与发送端对应的算法对所述第一校验序列进行更新；和/或采用与发送端对应的算法对所述第二校验序列进行更新，其中所述与发送端对应的算法包括异或处理算法、交织算法和更新设定比特位的算法中的至少一种。
所述更新模块，具体用于采用与发送端对应的加扰序列对第一校验序列和/或第二校验序列进行更新。
所述校验序列译码器62，还用于根据所述第一校验序列和\或第二校验序列，确定译码结果。
本申请实施例提供了另一种极化码译码装置，所述装置包括：
PC极化码Polar译码器，用于对接收到的极化码编码后的序列进行连续删除列表SCL译码；其中所述序列采用奇偶校验PC极化码编码方式编码；
校验序列译码器，针对SCL译码保留的多条候选路径中的候选序列，确定该候选序列中的信息序列，并确定该候选路径的第一校验序列；根据每条候选路径中的第一校验序列，确定目标译码路径。
所述校验序列译码器，具体用于确定每条候选路径中的第一序列与对应的第一校验序列的第一匹配度，按照第一匹配度由高至低的顺序对每条候选路径进行排序，选择排序在前的预设第二数量的候选路径作为目标译码路径。
所述装置还包括：
更新模块，用于采用与发送端对应的算法对所述第一校验序列进行更新，其中所述与发送端对应的算法包括异或处理算法、交织算法和更新设定比特位的算法中的至少一种。
所述更新模块，具体用于采用与发送端对应的加扰序列对第一校验序列进行更新。
参见图7，本申请实施例提供的另一种极化码译码装置，包括：
存储器520，用于存储程序指令；
处理器500，用于调用所述存储器中存储的程序指令，按照获得的程序执行：
对接收到的极化码编码后的序列进行连续删除列表SCL译码；
根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径。
可选地，所述根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径包括：
针对SCL译码保留的多条候选路径中的候选序列，确定该候选序列中的信息序列，并确定该候选路径的第一校验序列和第二校验序列；
根据每条候选路径中的第一校验序列和第二校验序列，确定目标译码路径。
可选地，所述根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径包括：
根据SCL译码中的每条路径的信息序列及确定出的第二校验序列，确定候选路径；
根据每条候选路径中的信息序列及确定出的第一校验序列，确定目标译码路径。
可选地，所述第一校验序列为循环冗余校验CRC序列、哈希hash序列和随机序列中的任意一种，所述第二校验序列为CRC序列、hash序列、奇偶校验PC序列和随机序列中的任意一种。
可选地，当所述第一校验序列为循环冗余校验CRC序列、哈希hash序列和随机序列中的任意一种，所述第二校验序列为CRC序列、hash序列和随机序列中的任意一种时，所述根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径包括：
确定每条候选路径中的第一序列与对应的第一校验序列的第一匹配度，按照第一匹配度由高至低的顺序对每条候选路径进行排序，选择排序在前的预设第一数量的候选路径作为待译码路径；
确定每条待译码路径中第二序列与对应的第二校验序列的第二匹配度，按照第二匹配度由高至低的顺序对每条待译码路径进行排序，选择排序在前的预设第二数量的待译码路径作为目标译码路径。
可选地，当所述第一校验序列为循环冗余校验CRC序列、哈希hash序列和随机序列中的任意一种，所述第二校验序列为CRC序列、hash序列和随机序列中的任意一种时，所述根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径包括：
确定每条候选路径中的第二序列与对应的第二校验序列的第二匹配度，按照第二匹配度由高至低的顺序对每条候选路径进行排序，选择排序在前的预设第一数量的候选路径作为待译码路径；
确定每条待译码路径中第一序列与对应的第一校验序列的第一匹配度，按照第一匹配度由高至低的顺序对每条待译码路径进行排序，选择排序在前的预设第二数量的待译码路径作为目标译码路径。
可选地，当所述第一校验序列为循环冗余校验CRC序列、哈希hash序列和随机序列中的任意一种，所述第二校验序列为奇偶校验PC序列时，所述根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径包括：
确定每条候选路径中的第一序列与对应的第一校验序列的第一匹配度，按照第一匹配度由高至低的顺序对每条候选路径进行排序，选择排序在前的预设第二数量的候选路径作为目标译码路径。
可选地，所述根据每条候选路径中的第一校验序列和第二校验序列，确定目标译码路径之前，所述处理器还用于：
采用与发送端对应的算法对所述第一校验序列进行更新；和/或
采用与发送端对应的算法对所述第二校验序列进行更新，其中所述与发送端对应的算法包括异或处理算法、交织算法和更新设定比特位的算法中的至少一种。
可选地，所述采用与发送端对应的算法对所述第一校验序列进行更新和/或采用与发送端对应的算法对所述第二校验序列进行更新包括：
采用与发送端对应的加扰序列对第一校验序列和/或第二校验序列进行更新。
可选地，所述处理器还用于：
根据所述第一校验序列和\或第二校验序列，确定译码结果。
收发机510，用于在处理器500的控制下接收和发送数据。
需要说明的是，收发机510是可选的，不是必须要有的器件。
其中，在图7中，总线架构可以包括任意数量的互联的总线和桥，具体由处理器500代表的一个或多个处理器和存储器520代表的存储器的各种电路链接在一起。总线架构还可以将诸如外围设备、稳压器和功率管理电路等之类的各种其他电路链接在一起，这些都是本领域所公知的，因此，本文不再对其进行进一步描述。总线接口提供接口。收发机510可以是多个元件，即包括发送机和收发机，提供用于在传输介质上与各种其他装置通信的单元。处理器500负责管理总线架构和通常的处理，存储器520可以存储处理器500在执行操作时所使用的数据。
处理器500可以是中央处埋器(CPU)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现场可编程门阵列(Field－Programmable Gate Array，FPGA)或复杂可编程逻辑器件(Complex Programmable Logic Device，CPLD)。
本申请另一实施例提供了一种计算机存储介质，所述计算机存储介质存储有计算机可执行指令，所述计算机可执行指令用于使所述计算机执行本申请实施例上述任一种方法。
所述计算机存储介质可以是计算机能够存取的任何可用介质或数据存储设备，包括但不限于磁性存储器(例如软盘、硬盘、磁带、磁光盘(MO)等)、光学存储器(例如CD、DVD、BD、HVD等)、以及半导体存储器(例如ROM、EPROM、EEPROM、非易失性存储器(NAND FLASH)、固态硬盘(SSD))等。
综上所述，本申请实施例公开了一种极化码译码方法及装置，所述方法包括：对接收到的极化码编码后的序列进行连续删除列表SCL译码；根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径。由于在本申请实施例中，根据第一校验序列和第二校验序列，进行路径选择，从而降低了虚警率，提高了系统的性能。
对于系统/装置实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者一个操作与另一个实体或者另一个操作区分开来，而不一定要求或者暗示这些实体或者操作之间存在任何这种实际的关系或者顺序。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个 方框或多个方框中指定的功能的步骤。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的精神和范围。这样，倘若本申请实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (21)

  1. 一种极化码译码方法，其特征在于，所述方法包括：
    对接收到的极化码编码后的序列进行连续删除列表SCL译码；
    根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径。
  2. 如权利要求1所述的方法，其特征在于，所述根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径包括：
    针对SCL译码保留的多条候选路径中的候选序列，确定该候选序列中的信息序列，并确定该候选路径的第一校验序列和第二校验序列；
    根据每条候选路径中的第一校验序列和第二校验序列，确定目标译码路径。
  3. 如权利要求1所述的方法，其特征在于，所述根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径包括：
    根据SCL译码中的每条路径的信息序列及确定出的第二校验序列，确定候选路径；
    根据每条候选路径中的信息序列及确定出的第一校验序列，确定目标译码路径。
  4. 如权利要求1-3任一项所述的方法，其特征在于，所述第一校验序列为循环冗余校验CRC序列、哈希hash序列和随机序列中的任意一种，所述第二校验序列为CRC序列、hash序列、奇偶校验PC序列和随机序列中的任意一种。
  5. 如权利要求4所述的方法，其特征在于，当所述第一校验序列为循环冗余校验CRC序列、哈希hash序列和随机序列中的任意一种，所述第二校验序列为CRC序列、hash序列和随机序列中的任意一种时，所述根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径包括：
    确定每条候选路径中的第一序列与对应的第一校验序列的第一匹配度，按照第一匹配度由高至低的顺序对每条候选路径进行排序，选择排序在前的预设第一数量的候选路径作为待译码路径；
    确定每条待译码路径中第二序列与对应的第二校验序列的第二匹配度，按照第二匹配度由高至低的顺序对每条待译码路径进行排序，选择排序在前的预设第二数量的待译码路径作为目标译码路径。
  6. 如权利要求4所述的方法，其特征在于，当所述第一校验序列为循环冗余校验CRC序列、哈希hash序列和随机序列中的任意一种，所述第二校验序列为CRC序列、hash序列和随机序列中的任意一种时，所述根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径包括：
    确定每条候选路径中的第二序列与对应的第二校验序列的第二匹配度，按照第二匹配度由高至低的顺序对每条候选路径进行排序，选择排序在前的预设第一数量的候选路径作为待译码路径；
    确定每条待译码路径中第一序列与对应的第一校验序列的第一匹配度，按照第一匹配度由高至低的顺序对每条待译码路径进行排序，选择排序在前的预设第二数量的待译码路径作为目标译码路径。
  7. 如权利要求4所述的方法，其特征在于，当所述第一校验序列为循环冗余校验CRC序列、哈希hash序列和随机序列中的任意一种，所述第二校验序列为奇偶校验PC序列时，所述根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径包括：
    确定每条候选路径中的第一序列与对应的第一校验序列的第一匹配度，按照第一匹配度由高至低的顺序对每条候选路径进行排序，选择排序在前的预设第二数量的候选路径作为目标译码路径。
  8. 如权利要求1所述的方法，其特征在于，所述根据每条候选路径中的第一校验序列和第二校验序列，确定目标译码路径之前，所述方法还包括：
    采用与发送端对应的算法对所述第一校验序列进行更新；和/或
    采用与发送端对应的算法对所述第二校验序列进行更新，其中所述与发送端对应的算法包括异或处理算法、交织算法和更新设定比特位的算法中的至少一种。
  9. 如权利要求8所述的方法，其特征在于，所述采用与发送端对应的算法对所述第一校验序列进行更新和/或采用与发送端对应的算法对所述第二校验序列进行更新包括：
    采用与发送端对应的加扰序列对第一校验序列和/或第二校验序列进行更新。
  10. 如权利要求1所述的方法，其特征在于，所述方法还包括：
    根据所述第一校验序列和\或第二校验序列，确定译码结果。
  11. 一种极化码译码装置，其特征在于，所述装置包括：
    极化码Polar译码器，用于对接收到的极化码编码后的序列进行连续删除列表SCL译码；
    校验序列译码器，用于根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径。
  12. 如权利要求11所述的装置，其特征在于，所述校验序列译码器，用于针对SCL译码保留的多条候选路径中的候选序列，确定该候选序列中的信息序列，并确定该候选路径的第一校验序列和第二校验序列；根据每条候选路径中的第一校验序列和第二校验序列，确定目标译码路径。
  13. 如权利要求11所述的装置，其特征在于，所述校验序列译码器，具体用于根据 SCL译码中的每条路径的信息序列及确定出的第二校验序列，确定候选路径；根据每条候选路径中的信息序列及确定出的第一校验序列，确定目标译码路径。
  14. 如权利要求12所述的装置，其特征在于，所述校验序列译码器，具体用于确定每条候选路径中的第一序列与对应的第一校验序列的第一匹配度，按照第一匹配度由高至低的顺序对每条候选路径进行排序，选择排序在前的预设第一数量的候选路径作为待译码路径；确定每条待译码路径中第二序列与对应的第二校验序列的第二匹配度，按照第二匹配度由高至低的顺序对每条待译码路径进行排序，选择排序在前的预设第二数量的待译码路径作为目标译码路径，其中所述第一序列为循环冗余校验CRC序列、哈希hash序列和随机序列中的任意一种，所述第二序列为CRC序列、hash序列和随机序列中的任意一种。
  15. 如权利要求12所述的装置，其特征在于，所述校验序列译码器，具体用于确定每条候选路径中的第二序列与对应的第二校验序列的第二匹配度，按照第二匹配度由高至低的顺序对每条候选路径进行排序，选择排序在前的预设第一数量的候选路径作为待译码路径；确定每条待译码路径中第一序列与对应的第一校验序列的第一匹配度，按照第一匹配度由高至低的顺序对每条待译码路径进行排序，选择排序在前的预设第二数量的待译码路径作为目标译码路径，其中所述第一序列为循环冗余校验CRC序列、哈希hash序列和随机序列中的任意一种，所述第二序列为CRC序列、hash序列和随机序列中的任意一种。
  16. 如权利要求13所述的装置，其特征在于，所述校验序列译码器，具体用于确定每条候选路径中的第一序列与对应的第一校验序列的第一匹配度，按照第一匹配度由高至低的顺序对每条候选路径进行排序，选择排序在前的预设第二数量的候选路径作为目标译码路径，其中所述第一校验序列为循环冗余校验CRC序列、哈希hash序列和随机序列中的任意一种，所述第二校验序列为CRC序列、hash序列和随机序列中的任意一种。
  17. 如权利要求11所述的装置，其特征在于，所述装置还包括：
    更新模块，用于采用与发送端对应的算法对所述第一校验序列进行更新；和/或采用与发送端对应的算法对所述第二校验序列进行更新，其中所述与发送端对应的算法包括异或处理算法、交织算法和更新设定比特位的算法中的至少一种。
  18. 如权利要求17所述的装置，其特征在于，所述更新模块，具体用于采用与发送端对应的加扰序列对第一校验序列和/或第二校验序列进行更新。
  19. 如权利要求11所述的装置，其特征在于，所述校验序列译码器，还用于根据所述第一校验序列和\或第二校验序列，确定译码结果。
  20. 一种极化码译码装置，其特征在于，所述装置包括：
    存储器，用于存储程序指令；
    处理器，用于调用所述存储器中存储的程序指令，按照获得的程序执行：
    对接收到的极化码编码后的序列进行连续删除列表SCL译码；
    根据SCL译码中每条路径中的信息序列，及每条路径中第一校验序列和第二校验序列，确定目标译码路径。
  21. 一种计算机存储介质，其特征在于，所述计算机存储介质存储有计算机可执行指令，所述计算机可执行指令用于使所述计算机执行权利要求1至10任一项所述的方法。
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