CN112567659A - Scl并行译码方法、装置及设备 - Google Patents
Scl并行译码方法、装置及设备 Download PDFInfo
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- CN112567659A CN112567659A CN201880096570.1A CN201880096570A CN112567659A CN 112567659 A CN112567659 A CN 112567659A CN 201880096570 A CN201880096570 A CN 201880096570A CN 112567659 A CN112567659 A CN 112567659A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/3966—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes based on architectures providing a highly parallelized implementation, e.g. based on systolic arrays
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/3905—Maximum a posteriori probability [MAP] decoding or approximations thereof based on trellis or lattice decoding, e.g. forward-backward algorithm, log-MAP decoding, max-log-MAP decoding
- H03M13/3927—Log-Likelihood Ratio [LLR] computation by combination of forward and backward metrics into LLRs
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/43—Majority logic or threshold decoding
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/45—Soft decoding, i.e. using symbol reliability information
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6561—Parallelized implementations
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0052—Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computing Systems (AREA)
- Error Detection And Correction (AREA)
Abstract
一种SCL并行译码方法、装置及设备,该方法包括:接收到的数据对应P组待译码比特,获取第i‑1组待译码比特的L1个第一译码路径,i为整数,P为大于1的整数,1<i≤P,L1为正整数(S401);对每一个第一译码路径分别确定L3个第三译码路径,第i组待译码比特中信息比特的个数为n,n为大于或等于1的正整数,L3为正整数(S402),L3<2n;在L1×L3个第三个译码路径中确定第i组待译码比特的至少一个保留译码路径,至少一个保留译码路径包括第i组待译码比特的译码结果(S403)。所述方法提高了SCL并行译码的效率。
Description
PCT国内申请,说明书已公开。
Claims (26)
- PCT国内申请,权利要求书已公开。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2018/103293 WO2020042089A1 (zh) | 2018-08-30 | 2018-08-30 | Scl并行译码方法、装置及设备 |
Publications (1)
Publication Number | Publication Date |
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CN112567659A true CN112567659A (zh) | 2021-03-26 |
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ID=69643362
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN201880096570.1A Pending CN112567659A (zh) | 2018-08-30 | 2018-08-30 | Scl并行译码方法、装置及设备 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20210184701A1 (zh) |
EP (1) | EP3840260A4 (zh) |
CN (1) | CN112567659A (zh) |
WO (1) | WO2020042089A1 (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111200439B (zh) * | 2018-11-16 | 2022-05-06 | 华为技术有限公司 | 译码方法、装置及设备 |
CN113949485B (zh) * | 2021-08-31 | 2022-11-15 | 北京大学 | 一种区分噪声帧和极化码字帧的阈值盲检方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106877884A (zh) * | 2017-02-01 | 2017-06-20 | 东南大学 | 一种减少译码路径分裂的极化码译码方法 |
CN107534448A (zh) * | 2015-04-30 | 2018-01-02 | 华为技术有限公司 | 极化码的译码器和译码方法 |
CN108347302A (zh) * | 2017-01-25 | 2018-07-31 | 华为技术有限公司 | 一种编译码方法和终端 |
CN108462558A (zh) * | 2018-03-01 | 2018-08-28 | 西安电子科技大学 | 一种极化码scl译码方法、装置及电子设备 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9176927B2 (en) * | 2011-11-08 | 2015-11-03 | The Royal Institution For The Advancement Of Learning/Mcgill University | Methods and systems for decoding polar codes |
CN104124979B (zh) * | 2013-04-27 | 2018-04-17 | 华为技术有限公司 | 极性码的译码方法和译码装置 |
CN106487479B (zh) * | 2016-09-27 | 2019-04-16 | 清华大学深圳研究生院 | 一种基于多位判决的极化码译码方法 |
US10615825B2 (en) * | 2017-05-05 | 2020-04-07 | Qualcomm Incorporated | Early-termination techniques for polar list decoders |
CN107896137B (zh) * | 2017-11-03 | 2020-10-27 | 东南大学 | 一种适用于极化码译码路径分裂的排序方法 |
CN108063649B (zh) * | 2017-12-14 | 2020-10-02 | 东南大学 | 一种低时延低复杂度的极化码译码方法 |
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2018
- 2018-08-30 CN CN201880096570.1A patent/CN112567659A/zh active Pending
- 2018-08-30 EP EP18931878.5A patent/EP3840260A4/en not_active Withdrawn
- 2018-08-30 WO PCT/CN2018/103293 patent/WO2020042089A1/zh unknown
-
2021
- 2021-02-26 US US17/186,781 patent/US20210184701A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107534448A (zh) * | 2015-04-30 | 2018-01-02 | 华为技术有限公司 | 极化码的译码器和译码方法 |
CN108347302A (zh) * | 2017-01-25 | 2018-07-31 | 华为技术有限公司 | 一种编译码方法和终端 |
CN106877884A (zh) * | 2017-02-01 | 2017-06-20 | 东南大学 | 一种减少译码路径分裂的极化码译码方法 |
CN108462558A (zh) * | 2018-03-01 | 2018-08-28 | 西安电子科技大学 | 一种极化码scl译码方法、装置及电子设备 |
Non-Patent Citations (1)
Title |
---|
CHENRONG XIONG: "Symbol-Decision Successive Cancellation List Decoder for Polar Codes", 《IEEE TRANSACTIONS ON SIGNAL PROCESSING》 * |
Also Published As
Publication number | Publication date |
---|---|
WO2020042089A1 (zh) | 2020-03-05 |
US20210184701A1 (en) | 2021-06-17 |
EP3840260A1 (en) | 2021-06-23 |
EP3840260A4 (en) | 2021-08-04 |
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Application publication date: 20210326 |